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110 Commits
Author SHA1 Message Date
CTCaer 502a0ff21a soc: tegra: introduce reboot2payload
Some Tegra124 and Tegra21x boards have open-source
bootloaders injected via RCM rather than onboard. These
boards need special reboot handling, which we call
`Reboot2Payload`.

Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Ezekiel Bethel <zek@9net.org>
2026-10-13 16:51:00 -05:00
tmakin 9359ba377c soc: tegra: add support for brom cmds
Tegra bootrom can signal PMIC and other onboard devices to handle
early-boot configuration. Downstream L4T kernel has long supported
this functionality, where commands are specified via device-tree and
can be hooked for power/reset events.

Based on:
- https://gitlab.com/nvidia/nv-tegra/linux-3.10/-/commit/4ac6f24c8988ef8f6d8100f9dceede5a3ff4a2d3
- https://gitlab.com/nvidia/nv-tegra/linux-4.4/-/commit/5ba61fa064fdd66c8e84592e721a5ac0fa78ed6e
- https://github.com/CTCaer/switch-l4t-kernel-4.9/commit/b4f03b6ab671597971bd9fc41482c0b52eb64bfd

Co-developed-by: Laxman Dewangan <ldewangan@nvidia.com>
Co-developed-by: CTCaer <ctcaer@gmail.com>
2026-10-13 16:40:44 -05:00
tmakin 63f7efc319 soc: tegra: add t21x panic handler 2026-10-12 16:50:55 -05:00
tmakin 08bd2cf2fd stmfts: update touch handling 2026-10-10 11:18:03 -05:00
tmakin 3e090e8a5a panel-nx: add drm orientation 2026-10-10 11:18:02 -05:00
Billy Laws 2aa5b04a01 [SQUASH] input: misc: Add support for max77620's onoff block
input: misc: Max77620 ON/OFF Block change to button press to key_sleep for linux.

input: misc: max77620-onoff: Ignore button release interrupt if the accompanying press was reported to userspace

Caused some userspaces to shutdown after wakeup from lp0 sleep if the
button was pressed during sleep and not released till after waking.

max77620-onoff: Refactor driver

- Add `maxim,onoff-keycode` under `onoff` child node to select custom ON/OFF button key code.
- Fix button stack at resume.

max77620-onoff: Correct regmap

max77620-onoff: correct irq priority and names

max77620-onoff: clear pending irq on probe

Change-Id: I033bd7a26a4e59b2508e90b4d9e42d2d52e5c17e
2026-10-10 11:17:17 -05:00
tmakin 5c7245e156 stmfts: support FTM4 chips
Some FingerTipS chips use FTM4 variants like Ftm4cd60d

Based loosely on
https://github.com/android-linux-stable/bluecross/blob/android-msm-bluecross-4.9/drivers/input/touchscreen/stm/ftm4_ts.c
and
https://github.com/CTCaer/switch-l4t-kernel-4.9/blob/linux-dev/drivers/input/touchscreen/stm/ftm4_ts.c

Assisted-by: Grok:grok-4.6
2026-10-07 10:26:55 -05:00
Petr Hodina 823de1bf0a arm64: dts: qcom: sdm845-google: Add STM FTS touchscreen support
Basic touchscreen connected to second i2c bus.

Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
2026-10-06 19:01:54 -05:00
David Heidelberg 9261922c66 Input: stmfts - support FTS5
The FTS support SLPI and AP mode, introduce mode-switch GPIO to switch
between those two. Currently we can handle only full power AP mode, so we
just keep the AP on.

Useful for devices like Pixel 3 (blueline), Pixel 4a (sunfish),
Xiaomi Mi 8 (dipper), and many others.

Based on work of Petr Hodina <petr.hodina@protonmail.com>

Signed-off-by: David Heidelberg <david@ixit.cz>
2026-10-06 19:01:54 -05:00
David Heidelberg 6c42b74e14 dt-bindings: input: touchscreen: st,stmfts: Introduce STM FTS5
Introduce more recent STM FTS5 touchscreen support.

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
2026-10-06 19:01:54 -05:00
David Heidelberg cd75bcb1f9 dt-bindings: input: touchscreen: st,stmfts: Improve example
The touchscreen-size-{x,y} is exact number, the -1 deduction is done on
driver side.

Example now use interrupts-extended and size obviously not deducted by
one.

Signed-off-by: David Heidelberg <david@ixit.cz>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
2026-10-06 19:01:43 -05:00
David Heidelberg 36fa0b8913 Input: stmfts - wait for controller ready after reset
After releasing the reset line stmfts_reset() sleeps a fixed 50 ms and
stmfts_power_on() another 50 ms before the first I2C access.  That is
enough for a warm reset, but when both supplies were really cut during
system suspend the controller boots from cold and can need longer.  If
it does, the first read fails, stmfts_resume() returns an error and the
touchscreen is left powered off with its interrupt disabled.

The controller posts a controller ready event once it has booted, and
the event parser already completes cmd_done on it.  Enable the interrupt
right after releasing reset and wait for that event instead of sleeping,
giving the controller 300 ms, the total budget the vendor driver allows.
Boards without a reset line keep the old timing.

Usually phones such as Pixel 4a and Xiaomi Mi 8 needs longer delay, so
without this change touchscreen stops working.

Fixes: 8a1f9de80e45 ("Input: stmfts - add optional reset GPIO support")
Cc: stable@vger.kernel.org
Co-developed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
2026-10-06 19:01:43 -05:00
Uwe Kleine-König (The Capable Hub) dcea3dc03a Input: Use named initializers for arrays of i2c_device_data
While being less compact, using named initializers allows to more easily
see which members of the structs are assigned which value without having
to lookup the declaration of the struct. And it's also more robust
against changes to the struct definition.

The mentioned robustness is relevant for a planned change to struct
i2c_device_id that replaces .driver_data by an anonymous union.

This patch doesn't modify the compiled arrays, only their representation
in source form benefits. The former was confirmed with x86 and arm64
builds.

Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
Link: https://patch.msgid.link/20260515164848.497608-2-u.kleine-koenig@baylibre.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 19:01:38 -05:00
Dmitry Torokhov dd36ee6907 Input: stmfts - fix formatting issues
Fix a few formatting issues reported by checkpatch.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 19:01:38 -05:00
Petr Hodina cdd38f1012 Input: stmfts - add optional reset GPIO support
Add support for an optional "reset-gpios" property. If present, the
driver drives the reset line high at probe time and releases it during
power-on, after the regulators have been enabled.

Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-8-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 19:01:38 -05:00
Petr Hodina f70d95850e Input: stmfts - use client to make future code cleaner
Make code cleaner, compiler will optimize it away anyway.

Preparation for FTM5 support, where more steps are needed.

Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-6-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 19:01:38 -05:00
David Heidelberg 4f8d7f167d Input: stmfts - disable regulators and disable irq when power on fails
We must power off regulators and ensure that IRQ is disabled when
failing at power on phase. Create stmfts_configure function to limit
use of goto.

Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-5-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 18:55:01 -05:00
David Heidelberg 965c9d231b Input: stmfts - abstract reading information from the firmware
Improves readability and makes splitting power on function in following
commit easier.

Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-4-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 18:55:01 -05:00
David Heidelberg 2fcfbdae10 Input: stmfts - switch to devm_regulator_bulk_get_const
Switch to devm_regulator_bulk_get_const() to stop setting the supplies
list in probe(), and move the regulator_bulk_data struct in static const.

Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-3-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 18:55:01 -05:00
David Heidelberg d3fd5a30ad Input: stmfts - use dev struct directly
Makes the code better readable and noticably shorter.

Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-2-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 18:55:01 -05:00
David Heidelberg 91275a8004 Input: stmfts - fix the MODULE_LICENSE() string
Replace the bogus "GPL v2" with "GPL" as MODULE_LICNSE() string. The
value does not declare the module's exact license, but only lets the
module loader test whether the module is Free Software or not.

See commit bf7fbeeae6 ("module: Cure the MODULE_LICENSE "GPL" vs.
"GPL v2" bogosity") in the details of the issue. The fix is to use
"GPL" for all modules under any variant of the GPL.

Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://patch.msgid.link/20260409-stmfts5-v4-1-64fe62027db5@ixit.cz
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-10-06 18:55:01 -05:00
tmakin 670265a2ca bm92t: gork assisted minor rework 2026-10-06 01:09:58 -05:00
tmakin 05fe91af04 xudc: hax for testing 2026-10-06 01:09:58 -05:00
tmakin d0828055d5 [UPSTREAM] usb: gadget: tegra-xudc: Fix CNT65 configuration
https://lore.kernel.org/linux-tegra/20260921-tegra-usb-v1-5-74a925a35d82@nvidia.com/
2026-10-06 01:09:58 -05:00
tmakin 3690f129b6 xusb: t210: support utmi pad biasing
Based on t186 driver and downstream:
https://gitlab.com/nvidia/nv-tegra/linux-4.9/-/commit/8d05313ac9fd54a2fc373a0e789390dfa0607726
2026-10-06 01:09:57 -05:00
tmakin a21e956221 gki hax 2026-10-06 01:09:57 -05:00
Bibhay Ranjan 47101f1600 pinctrl: t210b01: Add SDMMC2 pinmux support
Add sdmmc2 pinmux support inorder to use
SDMMC2 controller on t210b01 platforms.

Bug 200360711

Change-Id: Ie2d3a20d10325d42dc5dbf601c9da747ff0caa66
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593367
Reviewed-on: https://git-master.nvidia.com/r/1648549
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2026-10-06 01:09:57 -05:00
tmakin 79d808ff03 xusb: tegra210: add needed reg for b01 2026-10-06 01:09:57 -05:00
Peter De Schrijver e6ea914769 clk: tegra: dfll: fix use of tune values
There was some confusion on the use of the tune values. They were
defined in 2 different structs, but only initialzed in one of them.
Remove most of the references in struct tegra_dfll_soc_data and adjust
the code accordingly. Only tune_high_min_millivolts is left, because
this can be adjusted using debugfs. Hence copy the initial value from
the cvb table at boot.
2026-10-06 01:09:57 -05:00
Peter De Schrijver a5aef46a18 clk: tegra: apply regulator align to Vmin
Apply regulator alignment when using Vmin to determine the lowest possible
rate generated by the DFLL.

Change-Id: I169528614871733e4a7568f3ec740079b0e9d097
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584439
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2026-10-06 01:09:56 -05:00
tmakin b54d304a10 soc/tegra: fuse: print speedo IDs on info 2026-10-06 01:09:56 -05:00
tmakin e04cc94e55 drm/tegra: dsi: detect possible_crtcs
Other platforms allow dsi across multiple heads, but some have
one or more heads disabled. This results in a mismatch between
possible_crtcs and the real crtc mask. Apply the same
`tegra_output_find_possible_crtcs` function to DSI to properly
detect.
2026-10-06 01:09:56 -05:00
Alex Frid 407b8ee51b soc: tegra: Add support for DFLL Vmin CVB
Added Vmin coefficients to CPU DFLL CVB table, and updated Vmin
calculations during OPP table build accordingly. Changed build function
signature to return final Vmin.

Bug 1906940

Change-Id: I6e19266f865e9a3dda21c9e0f7178feece055ddf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565468
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
2026-10-06 01:09:56 -05:00
Alex Frid 972c60c721 clk: soc: tegra: Add DFLL tune high margin voltage
Added DFLL tune high margin voltage entry in CVB table. This allows to
replace current fixed margin defined as number of DFLL voltage steps
with per-table/per-chip margin in millivolts, and convert it to steps
during DFLL initialization.

Bug 1967884

Change-Id: I56268ae2faf9cc633b9f988cacbfd0ea3ba77ff3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576307
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2026-10-06 01:09:56 -05:00
Alex Frid 77412a8302 clk: soc: tegra: Add DFLL tune1_high parameter
Added support for DFLL tune1_high parameter

Bug 1967884

Change-Id: I0140724a22c43a3b05d39735b7a7faebd4be2908
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577129
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2026-10-06 01:09:56 -05:00
tmakin bafa332c10 clk: tegra: add locking support to DFLL
Based on part of https://gitlab.com/nvidia/nv-tegra/linux-4.9/-/commit/4f0b1e6e76f7b0ff8d028c66d34da9f37ca39233
2026-10-06 01:09:56 -05:00
Alex Frid 9642e53c2c clk: soc: tegra: Rename DFLL tune1 to tune1_low
Renamed DFLL tune1 to tune1_low to be consistent with
tune0_low/tune0_high naming convention.

Bug 1967884

Change-Id: If23170305143b05c2918e04691c73fe13b777272
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576306
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2026-10-06 01:09:55 -05:00
Vince Hsu c01ca7c586 clk: tegra: add DFLL dynamic tuning support
This patch is heavily based on the DFLL driver which is
written by Paul Walmsley and used by Tegra124 Chrome
projects currently.

The DFLL output can be fine tuned by the tuning parameters
depending on the voltage threshold. Both of the tuning
parameters and voltage threshold are specified by the
chip characterization. This patch introduces a tuning
timer which controls/monitors the tuning status. When
the DFLL is in open loop, only the tune low parameter
can be used. Once the DFLL enters the close loop, we
can switch to the tune high state if the output voltage
goes higher than the predefined threshold.

Added support for PWM regulator based DFLL.

Bug 200262988

Change-Id: I5ed51fbbf4b18cbd8cced5ab27848817201d8b39
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565464
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
2026-10-06 01:09:55 -05:00
tmakin 55d991543c gpio: tegra: deprecate static allocation 2026-10-06 01:09:55 -05:00
tmakin d5c4098152 tegra210b01: use tegra210b01 pinctrl 2026-10-06 01:09:55 -05:00
Laxman Dewangan 35e22c8e05 pinctrl: tegra210: Add support for LPDR bit
Tegra SOC Tegra210b01 have the support for LPDR configuration
via DT property "nvidia,lpdr".

Add support for configuring this property.

bug 200302268

Change-Id: I314af7f5094de6097f3c5944b28ad91ca61b1fdd
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1469552
Reviewed-on: https://git-master.nvidia.com/r/1557094
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-06 01:09:55 -05:00
Maulik Shah e2e53ae79a gpio: Use IRQ trigger mask helpers
Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded
trigger type combinations in irqchip callbacks.

No functional change intended.

Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20260802-b4b4-irq-trigger-mask-gpio-v1-1-948973636c84@oss.qualcomm.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-10-06 01:09:55 -05:00
Runyu Xiao e4c7dc6b80 gpio: tegra: do not call pinctrl for GPIO direction
tegra_gpio_direction_input() and tegra_gpio_direction_output() already
program the GPIO controller direction registers directly. The additional
pinctrl_gpio_direction_input/output() calls do not add a Tegra pinctrl
operation, because the Tegra pinmux ops provide GPIO request/free
handling but no gpio_set_direction hook.

The extra call still enters the pinctrl core and takes pctldev->mutex.
Shared GPIO users can call the direction path while holding their
per-line spinlock, so this otherwise redundant pinctrl direction call can
sleep in an atomic context.

This was found by our static analysis tool and then confirmed by manual
review of tegra_gpio_probe(), the Tegra GPIO direction callbacks and the
Tegra pinctrl ops. The reviewed path has a default non-sleeping
struct gpio_chip while the direction callback still enters the pinctrl
mutex path.

A directed runtime validation kept the same non-sleeping chip registration
and drove:

  gpio_shared_proxy_direction_output()
  gpiod_direction_output_raw_commit()
  tegra_gpio_direction_output()
  pinctrl_gpio_direction_output()

Lockdep reported a sleep-in-atomic warning with the shared GPIO spinlock
held and pinctrl_get_device_gpio_range() plus tegra_gpio_direction_output()
on the stack.

Do not mark the whole chip as can_sleep to paper over this: can_sleep
describes whether get()/set() may sleep, and Tegra value access is MMIO.
Remove the redundant pinctrl direction calls and keep pinctrl involvement
in the existing request/free path.

Fixes: 11da905412 ("gpio: tegra: Fix offset of pinctrl calls")
Cc: stable@vger.kernel.org
Signed-off-by: Runyu Xiao <runyu.xiao@seu.edu.cn>
Link: https://patch.msgid.link/20260619152439.1239561-1-runyu.xiao@seu.edu.cn
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-10-06 01:09:54 -05:00
tmakin adc3327467 bm92t: convert to typec fwk
note: ai
2026-10-06 01:09:54 -05:00
tmakin b7b1575ade bm92t fix 2026-10-06 01:09:54 -05:00
tmakin 2fa462786f bm92t: err change 2026-10-06 01:09:53 -05:00
tmakin c1199061b4 power: bq24190: add get_current_limit 2026-10-06 01:09:53 -05:00
tmakin 7390834040 pci: tegra: update lanes if dt incorrect 2026-10-06 01:09:53 -05:00
tmakin f3c7a9908f sor: allow selection of alt sor1 tuning 2026-10-06 01:09:53 -05:00
Alexandre Hamamdjian db5460d78a dt-bindings: usb: add Rohm BM92TXX Type-C controller
Add the device-tree binding documentation for the Rohm BM92TXX family
of USB Type-C and Power Delivery controllers. The device is controlled
over I2C and signals state changes through a dedicated interrupt line.

Document the rohm,* properties consumed by the driver: the optional
VCONN-enable GPIO, the DisplayPort alternate-mode toggles
(rohm,dp-disable, rohm,dp-alerts-enable, rohm,dp-signal-toggle-on-resume,
rohm,dp-lanes), the suspend/dock tunables (rohm,led-static-on-suspend,
rohm,dock-power-limit-disable) and the four
rohm,pd-{5,9,12,15}v-current-limit-ma per-PDO charging current limits.
A graph port is required to link the controller to a USB role switch
consumer.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
2026-10-05 12:47:16 -05:00
CTCaer 90b5a2e220 usb: typec: bm92txx: add Rohm BM92TXX support
Add a driver for the Rohm Semiconductor BM92TXX family of USB Type-C
and Power Delivery controllers. The IC integrates an MCU that runs the
PD state machine; the host configures it and observes status over I2C
and reacts to a level-triggered ALERT interrupt.

The driver exposes the controller through extcon and a USB role switch,
manages the VBUS sink, optional VBUS source and battery-charger
regulators along with the VCONN-enable GPIO, and applies per-PDO
charging current limits (5 V, 9 V, 12 V, 15 V) sourced from device
tree. DisplayPort alternate-mode handling and dock LED behaviour are
configurable through rohm,* properties so the same driver can serve
boards that wire the part up differently. A debugfs interface under
bm92txx/ is provided for register dumps and low-level command access
when CONFIG_DEBUG_FS is enabled.

Signed-off-by: CTCaer <ctcaer@gmail.com>
Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
2026-10-05 12:47:15 -05:00
azkali 5451612c9c regulator: fan52555: add support for fan53528 fan 2026-10-05 12:47:15 -05:00
tmakin f15bdd8f1f t210: assign better mmc clocks 2026-10-05 12:47:15 -05:00
tmakin a434425e73 clk changes, test later 2026-10-05 12:47:15 -05:00
Laxman Dewangan 66a1caddd5 NVIDIA: SAUCE: platform: tegra: Add tegra prod as built-in driver
BugLink: https://bugs.launchpad.net/bugs/2080908

This is an integration squash change of below commits.

 - [INTG: NV INTERNAL] platform: tegra: Add tegra prod as built-in
 - [INTG: NV INTERNAL] platform: tegra: Add tegra prod framework
 - [INTG: NV INTERNAL] platform: tegra: Add support for mask with 1s
 - [INTG: NV INTERNAL] platform: tegra_prod: Use kmemleak_not_leak for allocated memory
 - [INTG: NV INTERNAL] platform: tegra_prod: Fix prod setting parsing for package/board
 - [INTG: NV INTERNAL] platform: tegra_prod: Use proper variable name
 - [INTG: NV INTERNAL] platform: tegra_prod: Use for_each_available_child_of_node()
 - [INTG: NV INTERNAL] platform: tegra: move struct tegra_prod_list to private
 - [INTG: NV INTERNAL] platform: tegra_prod: Add APIs to managed allocation of prod_list
 - [INTG: NV INTERNAL] platform: tegra_prod: Remove unused APIs from public header
 - [INTG: NV INTERNAL] platform: tegra_prod: Get rid of tegra_prod_release()
 - [INTG: NV INTERNAL] platform: tegra_prod: Add support for nested prod nodes
 - [INTG: NV INTERNAL] platform: tegra_prod: Add devm_tegra_prod_get_from_node()
 - [INTG: NV INTERNAL] platform: tegra_prod: use devm_ for allocation
 - [INTG: NV INTERNAL] platform: tegra_prod: Do not use kmemleak_not_leak()
 - [INTG: NV INTERNAL] platform: tegra: Add support to find prod setting
 - [INTG: NV INTERNAL] platform: tegra: APIs to set prod based on name/index/offset/mask
 - [INTG: NV INTERNAL] prod: Add support for masked write in partially prod config
 - [INTG: NV INTERNAL] platform: tegra_prod: Use strcasecmp() for prod name
 - [INTG: NV INTERNAL] prod: set prod-settings mask to 1-style default
 - [INTG: NV INTERNAL] platform: tegra_prod: add support to avoid multiple configruation
 - soc: tegra: Add prod configuration parser
 - prod: remove package and board specific prod node
 - platform: tegra: Add config for next generation tegra prod
 - tegra-prod: Add legacy and next gen prod based on config
 - tegra-prod: Fix missing last entry
 - tegra-prod: Fix null pointer error
 - tegra-prod: Fix null pointer error
 - tegra: prod: remove new prod settings support

http://nvbugs/4165866
http://nvbugs/200416207
http://nvbugs/1758682
http://nvbugs/1745386
http://nvbugs/1768583
http://nvbugs/200217343
http://nvbugs/200215286
http://nvbugs/1807581
http://nvbugs/1865456
http://nvbugs/4097475
http://nvbugs/3389584
http://nvbugs/4638219
http://nvbugs/4283554
http://nvbugs/4765671
http://nvbugs/4754882

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
2026-10-05 12:47:14 -05:00
tmakin 037b91b974 clk: tegra210: update pll_c4 parameters 2026-10-05 12:47:14 -05:00
tmakin 6a2d2c6887 ftm4: compile fixes 2026-10-05 12:47:13 -05:00
Alvin Park 4c4e537de4 serial: tegra: clear tx_in_progress in flush func
Cleared tx_in_progress when tegra_uart_flush_buffer is called.
If tegra_uart_flush_buffer is called before complete to transmit
through DMA, next transmit could not be started because
tx_in_progress is not cleared.

Bug 3098159

Change-Id: I4b6b001314479313d7854d04a10d8394357a37cf
Signed-off-by: Alvin Park <apark@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.9/+/2405363
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Hardik T Shah <hardikts@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Signed-off-by: CTCaer <ctcaer@gmail.com>
2026-10-05 12:47:13 -05:00
azkali 18abb022ab touchscreen: stm: forward port ftm4 touchscreen driver from L4T 2026-10-05 12:47:12 -05:00
tmakin 61eb99267d dts: misc updates 2026-10-05 12:47:12 -05:00
tmakin 64754792ed memory: tegra: populate dt subnodes
Tegra210b01 uses tegra186-emc driver as emc clock is controlled by BPMP.
However, this driver expects emc as subnode of mc. Adjust Tegra30 mc
probe routine to populate subnodes.
2026-10-05 12:47:11 -05:00
Vidya Sagar fac12575c4 PCI: tegra: add PCI_REASSIGN_ALL_BUS flag
adds PCI_REASSIGN_ALL_BUS pci flag so as to enable
re-assigning bus numbers (if there is any bridge device added
recently) during rescan.

Bug 200192107

Change-Id: Iffc02827a75dcb82f5e02b69e96e65b38a0b7cd6
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/1144609
(cherry picked from commit 26464cda2eff345548e3271f26b00ddcd79d9264)
Reviewed-on: http://git-master/r/1176833
(cherry picked from commit bf21f6959bbecc70b4dce07329e0deea32b41b67)
Reviewed-on: http://git-master/r/1141937
(cherry picked from commit 284d2e97ce311771808d8dbd75c861a95c16d031)
Reviewed-on: http://git-master/r/1210983
(cherry picked from commit ef83e7563eb0ce4dad493abba2c92d20a67f41ac)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2371135
(cherry picked from commit a43acb68398f7fd6208988684698b49962b3c6f9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407883
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:11 -05:00
Manikanta Maddireddy 587dd0e9fc PCI: tegra: Add DT support to disable CLKREQ# control on PLLE
Sometimes CLKREQ# pin connection might be missing on a platform. Add DT
support to disable CLKREQ# control on PLLE in driver. Platform device tree
can use this DT property to disable CLKREQ# control on PLLE. In kernel-5.9,
upstream device tree property "supports-clkreq" is used in place of
kernel-4.14 custom device tree property "nvidia,disable-clock-request".

bug 200420606

Change-Id: I6ac44bd99d090e158fa10e5e9b62d63e52563c8c
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786551
(cherry picked from commit 6870a94b48a4bbbe9df607802c7f7c1f61806b7b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407880
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:11 -05:00
Manikanta Maddireddy 37c5760c35 PCI: tegra: aspm DT support
Squashed below k414 commits into single change.

PCI: tegra: Add DT support to disable per state aspm

Kernel config option provides choice to disable L0s & L1 or L1 substates
combinedly. Add DT support to disable each aspm state individually.

bug 200420606

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786548
(cherry picked from commit f3c5bcdc3ab8cadd3d24ea4d1a8e0aba7beea751)

PCI: tegra: Fix ASPM DT property parsing code

DT property "nvidia,disable-aspm-states" is part of PCIe port node.
Use correct of_node pointer to parse this property.

bug 200434876

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2383766
(cherry picked from commit 8dd957e9ecf29da4ba94471e3d74b2aef98a0643)

Change-Id: Iee1f573a103c0045d4f8f6606db13b47575b8cb9
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2408709
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2026-10-05 12:47:10 -05:00
Manikanta Maddireddy 15edaf962d PCI: tegra: Bypass CLKREQ# control over PLLE
When PCIe link is L2 CLKREQ# will be floating and this might interfere
with PLL power down. Bypass CLKREQ# control over PLLE when link is in L2.

bug 1356695
bug 200420606

Change-Id: I361db03df5f9a1a8d38bd9fb816d17fc4c64a9fc
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786565
(cherry picked from commit 69e79f42f65df70b0c76e62200aca40ed3972e3b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407877
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:10 -05:00
Manikanta Maddireddy 415f474a30 PCI: tegra: Fix incorrect CLKREQ and PLLE programming
CLKREQ_EN bit should be cleared to control REFCLK through CLKREQ# pin.
Enable PCIE2PLLE bit to control PLLE through clock clamp signal.
Program PADS2PLLE and PCIE2PLLE bits only if Tegra PCIe supports L1SS.

bug 200420606

Change-Id: I04cacf64fce8eed0f17bb632457ffcc9f052819d
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786550
(cherry picked from commit e71a64e47225b848c9b8a1d33e8c80a7bdb9d3cc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407876
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:10 -05:00
Vidya Sagar f5817e0969 PCI: tegra: Fixups to avoid unnecessary wakeup from ASPM-L1.2
sets CLKREQ asserted delay to a higher value to avoid
unnecessary wake up from L1.2.ENTRY state for Tegra210

bug 200420606

Change-Id: Iec2564bfd434897f0e50cd3f0ad6bc76aacc12e8
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786545
(cherry picked from commit d7785c1e6c98e33a85ba9487d3be6ab7e518a285)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407875
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:10 -05:00
Vidya Sagar e8cabae6ec PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States
Programs Port Common_Mode_Restore_Time and Port T_POWER_ON values
(from the L1 PM Substates Capabilities Register, PCIe 4.0r0.9, sec 7.8.3.2)
to get them reflected in ASPM-L1 Sub-States capability registers.
Also adjusts internal counter values according to 19.2 MHz clk_m value.

bug 200420606

Change-Id: Ie139255e522e4476fdfbe64aa6250d0293b7ae89
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786544
(cherry picked from commit 9ac6211e1a99583618945c86748214ccc33de463)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407874
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:09 -05:00
Manikanta Maddireddy d936e3daaf PCI: tegra: Configure L1 power save parameters
Programmed bits of register RP_VEND_XP_PAD_PWRDN are defined as follows,

L1(bit[0]):
 This bit, when set, causes the analog pads to power down when we're in L1.
 When clear, the LTSSM still enters L1 as required, but the analog pads
 are left at full power.
DYNAMIC(bit[1]):
 This bit, when set, causes unused analog pads to power down after
 "Dynamic Link Width Re-negotiation" takes place.  When clear, all analog
 pads remain powered up, even those that are no longer being used after
 "Dynamic Link Width Re-negotiation" down-sizes the link.
DISABLED(bit[2]):
 This bit, when set, causes the analog pads to power down when we're in the
 DISABLED_DOWN state. When clear, the LTSSM still enters DISBLED_DOWN as
 required, but the analog pads are left at full power.
L1_CLKREQ(bit[15]):
 This bit, when set, causes the analog pads to power down to
 SLEEP_MODE_L1_REQ when clkreq signal is deasserted in L1.
 (NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1 needs to be set in order to power
 down pad in L1.)  Also, when clkreq is asserted in L1, ltssm will exit L1
 immediately. When clear, the clkreq signal doesn't affect the power
 management.
SLEEP_MODE_L1(bits[4:3]):
 It defines the 2-bit sleep-mode coding in the pad when LTSSM is in the L1
 state or DISABLED state.
SLEEP_MODE_DYNAMIC(bits[6:5]):
 It defines the 2-bit sleep-mode coding in the pad when the lane shut down
 due to dynamic link downsizing.
SLEEP_MODE_L1_CLKREQ(bits[17:16]):
 It defines the 2-bit sleep-mode coding when clkreq is deasserted in L1.
The 2-bit sleep-mode encoding is defined as:
 - L0 (0x0): Normal power-up mode
 - L1 (0x1): L1 power-down mode; Tx common mode on, Rx e-idle detect on
 - L1P (0x2): L1 power-down mode; Tx common mode off, Rx e-idle detect on
 - L1PP (0x3): L1 power-down mode; Tx common mode off, Rx e-idle detect off

bug 200420606

Change-Id: I74aa9c1460d882084b1ecccb9c0168dd667c9d84
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786547
(cherry picked from commit d7899c186f89ecf503812003b743adbae07c4cbe)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407873
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:09 -05:00
Vidya Sagar f14a1b1af6 PCI: tegra: Advertise ASPM L1 PM support
Enables advertisement of ASPM-L1 support in capability
registers of applicable Tegra chips

bug 200420606

Change-Id: Ie5dbb3a262ca1c0c9cc59c91a8710bf6bd6a6900
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786543
(cherry picked from commit 7eedf2a02489b529374bc1ca95234be1f02b9119)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407872
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:09 -05:00
Manikanta Maddireddy 05e87bf9ef PCI: tegra: Convert WRAP transactions to increment burst
AFI module doesn't support WRAP transactions in Tegra. WRAP instructions
from CPU targeting PCIe BAR memory can cause data corruption. This can
happen if PCIe memory is marked as normal cacheable or GRE device.
Program mselect register to convert WRAP transactions to increment burst
for slave PCIe.

bug 200353330
bug 200420606

Change-Id: I867da85eb63332708bc294238e30ad99a71f345d
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786561
(cherry picked from commit b345cfae7b7633a3a52e0f2a659baf44feee1466)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407869
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:08 -05:00
Manikanta Maddireddy 2cdbb848ac PCI: tegra: Access endpoint config only if PCIe link is up
Few endpoints like Wi-Fi supports power on/off and to leverage that
root port must support hot-plug and hot-unplug. Tegra PCIe doesn't
support hot-plug and hot-unplug, however it supports endpoint power
on/off feature as follows,
 - Power off sequence:
   - Transition of PCIe link to L2
   - Power off endpoint
   - Leave root port in power up state with the link in L2
 - Power on sequence:
   - Power on endpoint
   - Apply hot reset to get PCIe link up

PCIe client driver stops accessing PCIe endpoint config and BAR registers
after endpoint is powered off. However, software applications like x11
server or lspci can access endpoint config registers in which case
host controller raises "response decoding" errors. To avoid this scenario,
add PCIe link up check in config read and write callback functions before
accessing endpoint config registers.

Change-Id: I47653cb0b580c2b764cb0ad9c42deeb9c8823c58
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2371131
(cherry picked from commit be664bfdd901138222a8ea8bb17160a2fa9de04a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407866
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2026-10-05 12:47:08 -05:00
tmakin 7b74031652 [WAR] core: don't loop 2026-10-05 12:47:08 -05:00
tmakin a0b78d8bb6 memory: tegra186-emc: support t210b01
Tegra210b01 uses Tegra186 style emc management, as in it is
offloaded to BPMP. This driver already implements this, so no
reason to shoehorn in elsewhere.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:08 -05:00
tmakin 41c7e5b923 tegra210b01: do not enable venc
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:08 -05:00
tmakin 3414bc92e8 tegra-drm: add t210b01 dsi support
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:08 -05:00
tmakin d39948ba5f enable max77812
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:07 -05:00
tmakin 1af6832aa1 panel-nx: match jdi panel driver style
squash later
2026-10-05 12:47:07 -05:00
azkali 9f99fb469d panel: dsi-nx: Add dsi-nx panel driver
dsi-nx is a new blanket driver for panels on the Nintendo Switch.
The Switch boots Linux via the "hekate" custom bootloader, which
performs panel initialization and passes panel info to kernel.

This driver is based on panel-jdi-lpm062m326a by SwitchR.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:07 -05:00
Laxman Dewangan 9652725d15 regulator: core: add API to get min/max voltage for rails
Add API to get min/max rail voltage configured from platform for
given rails. This will help to set the pad voltage based on platform
specific power tree.

bug 200083043

Change-Id: I054734ca2a25b5c830525e27ab22e43534f67351
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/712001
(cherry picked from commit c0d1de0da091132d037e1bb32f2ee09b5c00369b)
Reviewed-on: http://git-master/r/1119836
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:07 -05:00
Alex Frid b1f8d8dc78 clk: Add parent change notifications
Added parent change notifications to be used when drivers behavior
depends on physical nature of the parent, not just clock rate it
supplies (e.g., selection of Tegra DFLL as CPU clock source changes
mechanism of voltage control even if the clock rate stays the same
as on PLL).

Bug 200269751

Change-Id: I617c94927ef437caf240efd91497b49ad6f5c39d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573111
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:07 -05:00
Alex Frid e7c5dae9a0 clk: tegra: Add subtree change notifications
Added PRE_SUBTREE_CHANGE and POST_SUBTREE_CHANGE that called before
and after rate change is propagated down the sub-tree rooted in clk.
This would allow children to be aware that next set rate operation
is triggered by downward rate propagation, rather than direct set rate
on a child clock.

Bug 200267979

Change-Id: I6f2acbeca7cead0ecd385dcb2e58ced32448e998
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
(cherry picked from commit 62f0d763fcb6c9d5bd9a373d22d802503ab0fdc5)
Reviewed-on: https://git-master.nvidia.com/r/1558143
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:06 -05:00
tmakin 093f3edc50 arm64: t210b01: enable max77812
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:06 -05:00
tmakin c97121ef23 arm64: t210b01: add max77620 support
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:06 -05:00
tmakin 86b5a9c905 arm64: t210: add initial support for nx
The Nintendo Switch is a video game console based on the
Tegra X1 (T210) and X1+ (T210B01).

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
2026-10-05 12:47:04 -05:00
Aaron Kling 2cab2ab41f ANDROID: GKI: Export Nvidia dts'
Change-Id: I6e882d22300339288fa4f40d07faf0d4e9f413b0
2026-10-05 12:47:04 -05:00
Keir Fraser 40474da663 Revert "Revert "ANDROID: Support CONFIG_CMDLINE_EXTEND""
This reverts commit 68cf9989a1 and
reinstates long-standing Android command-line parsing behaviour with
CONFIG_CMDLINE_EXTEND.

Bug: 357781595
Bug: 120440972
Bug: 278749606
Signed-off-by: Keir Fraser <keirf@google.com>
Change-Id: Iac374066a980d38a1dadf1fa13fff16f48bd44c5
2026-10-05 12:47:03 -05:00
Aaron Kling 0490038044 arm64: tegra: Add support for NVIDIA Shield TV 2019
Add initial device-tree support for NVIDIA Shield TV 2019 (a.k.a Sif)
based on the Tegra210B01 SoC with 2 GiB of LPDDR4 RAM.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:02 -05:00
Aaron Kling f8401a72d8 arm64: tegra: Enable HDA controller on P2894
The HDA controller can be used for audio playback over HDMI.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:02 -05:00
Aaron Kling fa3635b142 arm64: tegra: Enable HDMI on P2894
Add regulators and enable the host1x nodes necessary to attain video
output via hdmi.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:01 -05:00
Aaron Kling 7fc6394176 arm64: tegra: Enable DFLL clock on P2894
Add pinmux for PWM-based DFLL support.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:01 -05:00
Aaron Kling 156132864e arm64: tegra: Enable PWM fan on P2894
This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devices are similar, so using the same configuration.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:01 -05:00
Aaron Kling 523114b93c arm64: tegra: Add Wifi node for Tegra210B01 P2894
The Tegra210B01 p2894 product has a BCM4356 module with wifi on pcie.
Enable the pcie port it is plugged into add a node for the wifi card,
and add a gpio-hog to enable power to the card. Attempts to tie the gpio
to power sequencing has not worked.

Change-Id: I7236fa1a3eabeb7fbb5b94af05f951b922955a38
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:00 -05:00
Aaron Kling 0fd3f43820 arm64: tegra: Add Wifi node for Tegra210 P2894
The Tegra210 p2894 product has a BCM4354 module with wifi on sdio.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:47:00 -05:00
Aaron Kling d56c180dba arm64: tegra: Wire up Bluetooth for P2894
The p2894 product contains a BCM4354 module with bluetooth on uart.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:59 -05:00
Aaron Kling 1789b75e32 arm64: tegra: Enable PCIe Ethernet on P2894
The P2894 product has a Realtek r6168 PCIe ethernet adapter. Enable the
pcie port the adapter is attached to.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:59 -05:00
Aaron Kling 1df0cc2a82 arm64: tegra: Enable XUSB controller on P2894
Enable the XUSB controller on P2894. One of the USB 3.0 lanes goes to a
switchable USB-A port, while the second USB 3.0 lane supports the normal
USB-A port.

The padctl layout is different between the Tegra210 and Tegra210B01
variants. The latter is overridden in the device specific dts.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:58 -05:00
Aaron Kling 34e509d5e5 arm64: tegra: Enable gpu on P2894
This adds the gpu regulator and enables the gpu node.

Change-Id: I7d9580967edf9af4c31d500608f880eeb9d1e0b5
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:58 -05:00
Aaron Kling 3d913d9051 arm64: tegra: Add support for NVIDIA Shield TV Pro 2019
Add initial device-tree support for NVIDIA Shield TV Pro 2019 (a.k.a
MDarcy) based up the Tegra210B01 SoC with 3 GiB of LPDDR4 RAM.

This device is very similar to the Tegra210 p2894 device, so this shares
the p2894 dtsi with a few overrides to the pinmux and power tree.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:58 -05:00
Aaron Kling f06e70573e arm64: tegra: tegra210-p2894: Move arch dtsi include
In preparation for support of the Tegra210B01 p2894 variant, move the
arch dtsi include to the Tegra210 revision specific dts. This will allow
the p2894 dtsi to be shared across archs, as the variants share a
majority of the hardware design.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:57 -05:00
Aaron Kling 62729c112f arm64: tegra: Add Tegra210B01 support
Also known as Tegra X1+, the Tegra210B01 has higher CPU and GPU clocks
than the original Tegra210.

Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This is derived from the Tegra210 dtsi, as they
share a lot.

Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:57 -05:00
Aaron Kling 9bbaf832bb arm64: tegra: Add BPMP node for Tegra210
The Tegra210 soc supports bpmp offload for power management among other
things. This was considered insecure partway through the soc's lifecycle
and support was removed in the bootloader. However, Tegra210B01 returned
to using the bpmp. Plus old bootloaders on the original Tegra210 still
work with the existing driver. So add the node to the common Tegra210
soc dtsi, but disabled by default.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:56 -05:00
tmakin c7465408be mmc: sdhci-tegra: add support for Tegra210B01
Tegra210B01 is basically the same as Tegra210 but uses different tap
delays.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:56 -05:00
tmakin 08c08b7b32 pci: tegra: add t210b01 support
This commit also fixes configuration checks

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:56 -05:00
Aaron Kling 9e79aefb8f usb: gadget: tegra-xudc: Add Tegra210B01 Support
It doesn't need some of the workarounds that the original Tegra210 does.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:54 -05:00
Aaron Kling 10fc7db687 usb: xhci: tegra: Add Tegra210B01 support
This uses a different firmware, but is otherwise compatible with
Tegra210.

Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:54 -05:00
Aaron Kling 935ca443cb phy: tegra: xusb: Add Tegra201B01 Support
This covers a few differences:
* Lanes compared to the original Tegra210
* The soc has a different clock driver and thus callbacks
* The soc has an extra clock for uphy management

Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Change-Id: I455358267b3a700461caa8f9f9963d33596dd189
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:54 -05:00
tmakin 5c743de761 memory: tegra: populate dt subnodes
Tegra210b01 uses tegra186-emc driver as emc clock is controlled by BPMP.
However, this driver expects emc as subnode of mc. Adjust Tegra30 mc
probe routine to populate subnodes.
2026-10-05 12:46:53 -05:00
Alexandre Hamamdjian 0df5550822 soc/tegra: pmc: Add Tegra210B01 support
The PMC in Tegra210B01 is very similar to the one in the original
Tegra210, but has a few powergate differences. Specifically sata and ve2
are removed.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:51 -05:00
tmakin a797a11437 nouveau: add gm20b c1 variant for t210b01
This is a revision of the GM20B chipset with some minor changes.
- Support new ID for b01 variant
- Support C1 PLL revision
- Differentiate DVFS parameters between B1 (t210) and C1 (t210b01)
- Add pstates for t210b01 (start with NA table for now)

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
2026-10-05 12:46:49 -05:00
12 changed files with 74 additions and 877 deletions

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-1
View File
@@ -506,7 +506,6 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = {
{ 0x6606, "BCM4345C5" }, /* 003.006.006 */
{ 0x230f, "BCM4356A2" }, /* 001.003.015 */
{ 0x2310, "BCM4343A2" }, /* 001.003.016 */
{ 0x2409, "BCM4356A3" }, /* 001.004.009 */
{ 0x220e, "BCM20702A1" }, /* 001.002.014 */
{ 0x420d, "BCM4349B1" }, /* 002.002.013 */
{ 0x420e, "BCM4349B1" }, /* 002.002.014 */
+19 -60
View File
@@ -13,7 +13,6 @@
#include <linux/pm.h>
#include <linux/semaphore.h>
#include <linux/sched/clock.h>
#include <linux/syscore_ops.h>
#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>
@@ -344,12 +343,28 @@ static ssize_t tegra_bpmp_channel_write(struct tegra_bpmp_channel *channel,
static int __maybe_unused tegra_bpmp_resume(struct device *dev);
static int __tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
struct tegra_bpmp_channel *channel = bpmp->tx_channel;
struct tegra_bpmp_channel *channel;
int err;
if (WARN_ON(!irqs_disabled()))
return -EPERM;
if (!tegra_bpmp_message_valid(msg))
return -EINVAL;
if (bpmp->suspended) {
/* Reset BPMP IPC channels during resume based on flags passed */
if (msg->flags & TEGRA_BPMP_MESSAGE_RESET)
tegra_bpmp_resume(bpmp->dev);
else
return -EAGAIN;
}
channel = bpmp->tx_channel;
spin_lock(&bpmp->atomic_tx_lock);
err = tegra_bpmp_channel_write(channel, msg->mrq, MSG_ACK,
@@ -372,26 +387,6 @@ static int __tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
return __tegra_bpmp_channel_read(channel, msg->rx.data, msg->rx.size,
&msg->rx.ret);
}
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg)
{
if (WARN_ON(!irqs_disabled()))
return -EPERM;
if (!tegra_bpmp_message_valid(msg))
return -EINVAL;
if (bpmp->suspended) {
/* Reset BPMP IPC channels during resume based on flags passed */
if (msg->flags & TEGRA_BPMP_MESSAGE_RESET)
tegra_bpmp_resume(bpmp->dev);
else
return -EAGAIN;
}
return __tegra_bpmp_transfer_atomic(bpmp, msg);
}
EXPORT_SYMBOL_GPL(tegra_bpmp_transfer_atomic);
int tegra_bpmp_transfer(struct tegra_bpmp *bpmp,
@@ -738,37 +733,6 @@ void tegra_bpmp_handle_rx(struct tegra_bpmp *bpmp)
spin_unlock(&bpmp->lock);
}
#define MRQ_T210_ENABLE_SUSPEND 17
#define TEGRA210_BPMP_PM_SC7 23
static int tegra210_bpmp_syscore_suspend(void *data)
{
struct tegra_bpmp *bpmp = data;
__le32 req[2] = { cpu_to_le32(TEGRA210_BPMP_PM_SC7), 0 };
struct tegra_bpmp_message msg = {
.mrq = MRQ_T210_ENABLE_SUSPEND,
.tx = {
.data = req,
.size = sizeof(req),
},
};
int err;
err = __tegra_bpmp_transfer_atomic(bpmp, &msg);
if (err < 0)
dev_err(bpmp->dev, "failed to enable SC7: %d\n", err);
return 0;
}
static const struct syscore_ops tegra210_bpmp_syscore_ops = {
.suspend = tegra210_bpmp_syscore_suspend,
};
static struct syscore tegra210_bpmp_syscore = {
.ops = &tegra210_bpmp_syscore_ops,
};
static int tegra_bpmp_probe(struct platform_device *pdev)
{
struct tegra_bpmp *bpmp;
@@ -867,11 +831,6 @@ static int tegra_bpmp_probe(struct platform_device *pdev)
if (err < 0)
dev_err(&pdev->dev, "debugfs initialization failed: %d\n", err);
if (of_device_is_compatible(pdev->dev.of_node, "nvidia,tegra210-bpmp")) {
tegra210_bpmp_syscore.data = bpmp;
register_syscore(&tegra210_bpmp_syscore);
}
return 0;
free_mrq:
+18 -103
View File
@@ -53,10 +53,6 @@
#define DCS_CONTROL_DISPLAY_DIMMING_CTRL ((u8)BIT(3))
#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL ((u8)BIT(5))
#define DCS_SM_BRIGHTNESS_MAX 2047
#define DCS_SM_DUTY_MAX 255
#define DCS_SM_DUTY_DEFAULT 150
/* OLED Panels color mode */
#define DCS_SM_COLOR_MODE_SATURATED ((u8)0x00) /* Disabled. Similar to vivid but over-saturated. Wide gamut? */
#define DCS_SM_COLOR_MODE_WASHED ((u8)0x45)
@@ -114,7 +110,6 @@ struct nx_panel {
bool prepared;
bool enabled;
bool dcs_backlight;
const struct drm_display_mode *mode;
enum drm_panel_orientation orientation;
@@ -136,7 +131,6 @@ struct init_cmd init_cmds_default[] = {
0xFF,
20,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd init_cmds_PANEL_JDI_XXX062M[] = {
@@ -199,41 +193,35 @@ struct init_cmd suspend_cmds_PANEL_JDI_XXX062M[] = {
};
struct init_cmd init_cmds_PANEL_SAM_AMS699VC01[] = {
{ MIPI_DCS_EXIT_SLEEP_MODE, 0, { 0x00 } },
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
180,
},
// Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20).
{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE, 1, { DCS_SM_COLOR_MODE_BASIC } },
{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE, 2, { 0x23, 0x0 } },
// Enable backlight and smooth PWM.
{ MIPI_DCS_WRITE_CONTROL_DISPLAY, 1, { DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL } },
{ MIPI_DCS_WRITE_CONTROL_DISPLAY, 2, { 0x28, 0x0 } },
// Unlock Level 2 registers.
{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0x5A, 0x5A } },
{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0x5A, 0x5A, 0x0, 0x0 } },
// Set registers offset and set PWM transition to 6 frames (100ms).
{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET, 1, { 0x07 } },
{ MIPI_DCS_PRIV_SM_SET_ELVSS, 1, { 0x06 } },
{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET, 2, { 0x07, 0x0 } },
{ MIPI_DCS_PRIV_SM_SET_ELVSS, 2, { 0x06, 0x0 } },
// Relock Level 2 registers.
{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0xA5, 0xA5 } },
{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0xA5, 0xA5, 0x0, 0x0 } },
// MIPI_DCS_SET_BRIGHTNESS 0000: 0%. 07FF: 100%.
{ MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 2, { 0x00, 0x00 } },
// MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%.
{ 0x03, 7, { 0x00, 0x00, 0x51, 0x0, 0x0, 0x0, 0x0 } },
{
0xFF,
5,
},
{ MIPI_DCS_SET_DISPLAY_ON, 0, { 0x00 } },
{
0xFF,
20,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd init_cmds_PANEL_AUO_A062TAN01[] = {
@@ -248,7 +236,6 @@ struct init_cmd init_cmds_PANEL_AUO_A062TAN01[] = {
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x11, 0x71, 0x09, 0x32, 0x14 } },
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_AUO_A062TAN01[] = {
@@ -265,7 +252,6 @@ struct init_cmd suspend_cmds_PANEL_AUO_A062TAN01[] = {
0xFF,
50,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_AUO_A055TAN01[] = {
@@ -288,7 +274,6 @@ struct init_cmd suspend_cmds_PANEL_AUO_A055TAN01[] = {
0xFF,
50,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd init_cmds_PANEL_INL_P062CCA_AZ1[] = {
@@ -304,7 +289,6 @@ struct init_cmd init_cmds_PANEL_INL_P062CCA_AZ1[] = {
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x15, 0x75, 0x09, 0x32, 0x14 } },
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_INL_2J055IA_27A[] = {
@@ -327,7 +311,6 @@ struct init_cmd suspend_cmds_PANEL_INL_2J055IA_27A[] = {
0xFF,
50,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_SHP_LQ055T1SW10[] = {
@@ -350,21 +333,18 @@ struct init_cmd suspend_cmds_PANEL_SHP_LQ055T1SW10[] = {
0xFF,
50,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_SAM_AMS699VC01[] = {
{ MIPI_DCS_SET_DISPLAY_OFF, 0, { 0x00 } },
{
0xFF,
100,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 0, { 0x00 } },
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
120,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
static inline struct nx_panel *to_nx_panel(struct drm_panel *panel)
@@ -372,43 +352,23 @@ static inline struct nx_panel *to_nx_panel(struct drm_panel *panel)
return container_of(panel, struct nx_panel, base);
}
static u16 nx_dcs_brightness(struct backlight_device *bl)
{
if (backlight_is_blank(bl))
return 0;
if (bl->props.brightness >= DCS_SM_DUTY_MAX)
return DCS_SM_BRIGHTNESS_MAX;
return max(bl->props.brightness, 1) *
(DCS_SM_BRIGHTNESS_MAX / DCS_SM_DUTY_MAX);
}
static void nx_panel_detect(struct nx_panel *nx)
{
u8 id[3] = { 0 };
int ret;
nx->init_cmds = NULL;
nx->suspend_cmds = NULL;
nx->display_id = 0;
memset(&(nx->display_id), 0, sizeof(nx->display_id));
ret = mipi_dsi_dcs_read(nx->dsi, MIPI_DCS_GET_DISPLAY_ID,
id, sizeof(id));
&(nx->display_id), sizeof(nx->display_id));
if (ret < 0) {
dev_err(&nx->dsi->dev, "failed to read panel ID: %d\n", ret);
} else {
nx->display_id = (id[2] << 8) | id[0];
dev_info_once(&nx->dsi->dev, "display ID[%d]: %02x %02x %02x\n",
ret, id[0], id[1], id[2]);
dev_info(&nx->dsi->dev, "display ID[%d]: %04x\n",
ret, nx->display_id);
}
if ((nx->display_id & 0xFF) == PANEL_JDI_XXX062M)
nx->display_id = PANEL_JDI_XXX062M;
if (of_machine_is_compatible("nintendo,aula"))
nx->display_id = PANEL_SAM_AMS699VC01;
dev_info(&nx->dsi->dev,
"setting init sequence for ID %04x\n", nx->display_id);
@@ -533,21 +493,6 @@ static int nx_panel_init(struct nx_panel *nx)
return ret;
}
if (nx->dcs_backlight) {
u8 mode;
ret = mipi_dsi_dcs_set_display_brightness_large(dsi,
nx_dcs_brightness(nx->backlight));
if (ret < 0) {
dev_err(dev, "failed to set brightness: %d\n", ret);
return ret;
}
ret = mipi_dsi_dcs_get_power_mode(dsi, &mode);
if (ret < 0)
dev_warn(dev, "failed to read power mode: %d\n", ret);
}
return 0;
}
@@ -574,9 +519,6 @@ static int nx_panel_disable(struct drm_panel *panel)
backlight_disable(nx->backlight);
if (nx->dcs_backlight)
mipi_dsi_dcs_set_display_off(nx->dsi);
nx->enabled = false;
return 0;
@@ -665,7 +607,7 @@ static const struct drm_display_mode default_mode = {
.htotal = 720 + 136 + 72 + 72,
.vdisplay = 1280,
.vsync_start = 1280 + 10,
.vsync_end = 1280 + 10 + 1,
.vsync_end = 1280 + 10 + 2,
.vtotal = 1280 + 10 + 1 + 9,
.flags = 0,
};
@@ -692,6 +634,8 @@ static int nx_panel_get_modes(struct drm_panel *panel,
connector->display_info.height_mm = 137;
connector->display_info.bpc = 8;
drm_connector_set_panel_orientation(connector, nx->orientation);
return 1;
}
@@ -711,21 +655,6 @@ static const struct drm_panel_funcs nx_panel_funcs = {
.get_orientation = nx_panel_get_orientation,
};
static int nx_dcs_backlight_update_status(struct backlight_device *bl)
{
struct nx_panel *nx = bl_get_data(bl);
if (!nx->prepared)
return 0;
return mipi_dsi_dcs_set_display_brightness_large(nx->dsi,
nx_dcs_brightness(bl));
}
static const struct backlight_ops nx_dcs_backlight_ops = {
.update_status = nx_dcs_backlight_update_status,
};
static int nx_panel_add(struct nx_panel *nx)
{
struct device *dev = &nx->dsi->dev;
@@ -760,20 +689,6 @@ static int nx_panel_add(struct nx_panel *nx)
if (!nx->backlight)
return -EPROBE_DEFER;
} else {
struct backlight_properties props = {
.type = BACKLIGHT_RAW,
.brightness = DCS_SM_DUTY_DEFAULT,
.max_brightness = DCS_SM_DUTY_MAX,
};
nx->backlight = devm_backlight_device_register(dev, "backlight", dev, nx,
&nx_dcs_backlight_ops,
&props);
if (IS_ERR(nx->backlight))
return PTR_ERR(nx->backlight);
nx->dcs_backlight = true;
}
ret = of_drm_get_panel_orientation(dev->of_node, &nx->orientation);
@@ -795,7 +710,7 @@ static void nx_panel_del(struct nx_panel *nx)
if (nx->base.dev)
drm_panel_remove(&nx->base);
if (nx->backlight && !nx->dcs_backlight)
if (nx->backlight)
put_device(&nx->backlight->dev);
}
+6 -45
View File
@@ -25,7 +25,6 @@
#include <drm/drm_panel.h>
#include <drm/drm_print.h>
#include <drm/drm_simple_kms_helper.h>
#include <drm/drm_vblank.h>
#include "dc.h"
#include "drm.h"
@@ -1075,9 +1074,6 @@ static int tegra_dsi_init(struct host1x_client *client)
&tegra_dsi_connector_helper_funcs);
dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
drm_connector_set_orientation_from_panel(
&dsi->output.connector, dsi->output.panel);
drm_simple_encoder_init(drm, &dsi->output.encoder,
DRM_MODE_ENCODER_DSI);
drm_encoder_helper_add(&dsi->output.encoder,
@@ -1346,39 +1342,6 @@ static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
}
}
static ssize_t tegra_dsi_video_transfer(struct tegra_dsi *dsi,
const struct mipi_dsi_packet *packet)
{
const u8 *header = packet->header;
u32 host_control, value;
host_control = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_TX_TRIG_SOL |
DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
value = DSI_VIDEO_MODE_CMD_PKT_ENABLE | DSI_VIDEO_MODE_LINE_TYPE(4);
tegra_dsi_writel(dsi, value, DSI_VIDEO_MODE_CONTROL);
value = header[2] << 16 | header[1] << 8 | header[0];
tegra_dsi_writel(dsi, value, DSI_WR_DATA);
if (packet->payload_length > 0)
tegra_dsi_writesl(dsi, DSI_WR_DATA, packet->payload,
packet->payload_length);
if (dsi->output.encoder.crtc) {
drm_crtc_wait_one_vblank(dsi->output.encoder.crtc);
drm_crtc_wait_one_vblank(dsi->output.encoder.crtc);
}
tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
tegra_dsi_writel(dsi, host_control, DSI_HOST_CONTROL);
return packet->size;
}
static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
const struct mipi_dsi_msg *msg)
{
@@ -1399,16 +1362,14 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
if (packet.size > dsi->video_fifo_depth * 4)
return -ENOSPC;
if (tegra_dsi_readl(dsi, DSI_CONTROL) & DSI_CONTROL_VIDEO_ENABLE) {
if (msg->rx_buf && msg->rx_len > 0)
return -EBUSY;
return tegra_dsi_video_transfer(dsi, &packet);
/* reset underflow/overflow flags */
value = tegra_dsi_readl(dsi, DSI_STATUS);
if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
value = DSI_HOST_CONTROL_FIFO_RESET;
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
usleep_range(10, 20);
}
tegra_dsi_writel(dsi, DSI_HOST_CONTROL_FIFO_RESET, DSI_HOST_CONTROL);
usleep_range(10, 20);
value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
value |= DSI_POWER_CONTROL_ENABLE;
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
-2
View File
@@ -102,8 +102,6 @@
#define DSI_PAD_CONTROL_CD 0x4c
#define DSI_PAD_CD_STATUS 0x4d
#define DSI_VIDEO_MODE_CONTROL 0x4e
#define DSI_VIDEO_MODE_CMD_PKT_ENABLE (1 << 0)
#define DSI_VIDEO_MODE_LINE_TYPE(x) (((x) & 0x7) << 1)
#define DSI_PAD_CONTROL_1 0x4f
#define DSI_PAD_CONTROL_2 0x50
#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
-10
View File
@@ -135,16 +135,6 @@ config AS73211
This driver can also be built as a module. If so, the module
will be called as73211.
config BH1730
tristate "ROHM BH1730 ambient light sensor"
depends on I2C
help
Say Y here to build support for the ROHM BH1730FVC ambient light
sensor.
To compile this driver as a module, choose M here: the module will
be called bh1730.
config BH1745
tristate "ROHM BH1745 colour sensor"
depends on I2C
-1
View File
@@ -15,7 +15,6 @@ obj-$(CONFIG_APDS9300) += apds9300.o
obj-$(CONFIG_APDS9306) += apds9306.o
obj-$(CONFIG_APDS9960) += apds9960.o
obj-$(CONFIG_AS73211) += as73211.o
obj-$(CONFIG_BH1730) += bh1730.o
obj-$(CONFIG_BH1745) += bh1745.o
obj-$(CONFIG_BH1750) += bh1750.o
obj-$(CONFIG_BH1780) += bh1780.o
-575
View File
@@ -1,575 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ROHM BH1730 ambient light sensor driver
*
* Copyright (c) 2021 CTCaer <ctcaer@gmail.com>
*
* Based on previous iio BH1730FVC drivers from:
* Copyright (c) 2018 Google, Inc.
* Author: Pierre Bourdon <delroth@google.com>
*
* Copyright (C) 2012 Samsung Electronics. All rights reserved.
* Author: Won Huh <won.huh@samsung.com>
*
* Data sheets:
* http://www.rohm.com/web/global/datasheet/BH1730FVC/bh1730fvc-e
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm.h>
#include <linux/regulator/consumer.h>
#define BH1730_NAME "bh1730fvc"
#define BH1730_CMD_BIT BIT(7)
#define BH1730_REG_CONTROL 0x00
#define BH1730_REG_TIMING 0x01
#define BH1730_REG_GAIN 0x07
#define BH1730_REG_DATA0LOW 0x14
#define BH1730_REG_DATA1LOW 0x16
#define BH1730_CONTROL_POWER BIT(0)
#define BH1730_CONTROL_ADC_EN BIT(1)
#define BH1730_ADC_CALC_DELAY_US 2000 /* BH1730_INTERNAL_CLOCK_MS * 714 */
#define BH1730_ITIME_TO_US 2700 /* BH1730_INTERNAL_CLOCK_MS * 964 */
#define BH1730_DEFAULT_INTEG_CYCLE 38
#define BH1730_DEFAULT_ITIME_MS 100
#define BH1730_POWER_ON_DELAY_US 10000
#define BH1730_MAX_MEASURED_LUX 100000
enum bh1730_gain {
BH1730_GAIN_1X = 0,
BH1730_GAIN_2X,
BH1730_GAIN_64X,
BH1730_GAIN_128X,
};
struct gain_coeff_t {
u32 cl;
u32 fl;
};
struct opt_win_coeff_t {
u32 rc;
u32 cv;
u32 ci;
};
struct lux_cal_data_t {
const struct gain_coeff_t *gain_coeff;
const struct opt_win_coeff_t *opt_win_coeff;
u32 opt_win_coeff_count;
u32 itime_cycle;
u32 mul;
};
/*
* No optical window or optical window that has flat transmittance
* from visible light to infrared light.
*/
static const struct opt_win_coeff_t def_lux_coeff[] = {
{ 260, 1290, 2733 },
{ 550, 795, 859 },
{ 1090, 510, 345 },
{ 2130, 276, 130 }
};
static const struct gain_coeff_t def_gain_coeff[] = {
{ 3000, -1 }, /* 1x */
{ 2000, 9800 }, /* 2x */
{ 15, 60000 }, /* 64x */
{ 0, 1300 } /* 128x */
};
static const struct lux_cal_data_t def_lux_data = {
.gain_coeff = def_gain_coeff,
.opt_win_coeff = def_lux_coeff,
.opt_win_coeff_count = ARRAY_SIZE(def_lux_coeff),
.itime_cycle = BH1730_DEFAULT_INTEG_CYCLE,
.mul = 1000
};
struct bh1730_data {
struct i2c_client *client;
struct lux_cal_data_t cal;
struct regulator *reg_vdd;
struct regulator *reg_vid;
enum bh1730_gain gain;
bool powered;
u32 itime_us;
u32 tmt_us;
};
static int bh1730_read_word(struct bh1730_data *bh1730, u8 reg)
{
int ret = i2c_smbus_read_word_data(bh1730->client,
BH1730_CMD_BIT | reg);
if (ret < 0)
dev_err(&bh1730->client->dev,
"i2c read failed error %d, register %01x\n",
ret, reg);
return ret;
}
static int bh1730_write(struct bh1730_data *bh1730, u8 reg, u8 val)
{
int ret = i2c_smbus_write_byte_data(bh1730->client,
BH1730_CMD_BIT | reg,
val);
if (ret < 0)
dev_err(&bh1730->client->dev,
"i2c write failed error %d, register %01x\n",
ret, reg);
return ret;
}
static int bh1730_gain_multiplier(struct bh1730_data *bh1730)
{
switch (bh1730->gain) {
case BH1730_GAIN_1X:
return 1;
case BH1730_GAIN_2X:
return 2;
case BH1730_GAIN_64X:
return 64;
case BH1730_GAIN_128X:
return 128;
}
dev_warn(&bh1730->client->dev,
"invalid gain multiplier settings: %d\n", bh1730->gain);
bh1730->gain = BH1730_GAIN_1X;
return 1;
}
static int bh1730_set_gain(struct bh1730_data *bh1730, enum bh1730_gain gain)
{
int ret = bh1730_write(bh1730, BH1730_REG_GAIN, gain);
if (ret < 0)
return ret;
bh1730->gain = gain;
return 0;
}
static int bh1730_set_integration_time_cycle(struct bh1730_data *bh1730,
u32 cycle)
{
int ret, itime;
itime = 256 - cycle;
/* ITIME == 0 is reserved for manual integration mode. */
if (itime <= 0 || itime > 255) {
dev_warn(&bh1730->client->dev,
"integration time out of range: %d cycles\n", cycle);
return -ERANGE;
}
ret = bh1730_write(bh1730, BH1730_REG_TIMING, itime);
if (ret < 0)
return ret;
bh1730->itime_us = BH1730_ITIME_TO_US * cycle;
bh1730->tmt_us = bh1730->itime_us + BH1730_ADC_CALC_DELAY_US;
return 0;
}
static int bh1730_adjust_gain(struct bh1730_data *bh1730)
{
int visible, ir, highest, gain, ret;
visible = bh1730_read_word(bh1730, BH1730_REG_DATA0LOW);
if (visible < 0)
return visible;
ir = bh1730_read_word(bh1730, BH1730_REG_DATA1LOW);
if (ir < 0)
return ir;
highest = max(visible, ir);
/* Adjust gain based on sensitivity calibration */
gain = bh1730->gain;
if (highest > bh1730->cal.gain_coeff[gain].fl &&
gain != BH1730_GAIN_1X) {
gain--; /* Decrease sensitivity */
} else if (highest < bh1730->cal.gain_coeff[gain].cl &&
gain != BH1730_GAIN_128X) {
gain++; /* Increase sensitivity */
}
if (gain != bh1730->gain) {
ret = bh1730_set_gain(bh1730, gain);
if (ret < 0)
return ret;
fsleep(bh1730->tmt_us);
}
return 0;
}
static int bh1730_get_lux(struct bh1730_data *bh1730)
{
const struct opt_win_coeff_t *opt_win_coeff;
int i, visible, ir;
u64 lux = 0;
visible = bh1730_read_word(bh1730, BH1730_REG_DATA0LOW);
/* If visible is 0, skip calculations */
if (visible <= 0)
return visible;
ir = bh1730_read_word(bh1730, BH1730_REG_DATA1LOW);
if (ir < 0)
return ir;
/* Calibrate based on optical window */
for (i = 0; i < bh1730->cal.opt_win_coeff_count; i++) {
opt_win_coeff = &bh1730->cal.opt_win_coeff[i];
if (1000 * ir / visible < opt_win_coeff->rc) {
lux = ((u64)opt_win_coeff->cv * visible) -
(opt_win_coeff->ci * ir);
break;
}
}
/* Calculate lux */
lux *= BH1730_DEFAULT_ITIME_MS;
lux = div_u64(lux, bh1730_gain_multiplier(bh1730) * bh1730->itime_us);
lux = div_u64(lux * bh1730->cal.mul, 1000);
if (lux > BH1730_MAX_MEASURED_LUX)
lux = BH1730_MAX_MEASURED_LUX;
return (int)lux;
}
static int bh1730_power_ctrl(struct bh1730_data *bh1730, bool enable)
{
struct device *dev = &bh1730->client->dev;
int ret;
if (bh1730->powered == enable)
return 0;
if (enable) {
ret = regulator_enable(bh1730->reg_vdd);
if (ret) {
dev_err(dev, "failed to enable vdd: %d\n", ret);
return ret;
}
ret = regulator_enable(bh1730->reg_vid);
if (ret) {
dev_err(dev, "failed to enable vid: %d\n", ret);
regulator_disable(bh1730->reg_vdd);
return ret;
}
fsleep(BH1730_POWER_ON_DELAY_US);
} else {
regulator_disable(bh1730->reg_vid);
regulator_disable(bh1730->reg_vdd);
}
bh1730->powered = enable;
return 0;
}
static int bh1730_power_on(struct bh1730_data *bh1730)
{
int ret = bh1730_power_ctrl(bh1730, true);
if (ret < 0)
return ret;
return bh1730_write(bh1730, BH1730_REG_CONTROL,
BH1730_CONTROL_POWER | BH1730_CONTROL_ADC_EN);
}
static int bh1730_init_config(struct bh1730_data *bh1730)
{
int ret;
ret = bh1730_set_gain(bh1730, BH1730_GAIN_64X);
if (ret < 0)
return ret;
return bh1730_set_integration_time_cycle(bh1730,
bh1730->cal.itime_cycle);
}
static int bh1730_power_off(struct bh1730_data *bh1730)
{
int ret = bh1730_write(bh1730, BH1730_REG_CONTROL, 0);
if (ret < 0)
return ret;
return bh1730_power_ctrl(bh1730, false);
}
static int bh1730_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct bh1730_data *bh1730 = iio_priv(indio_dev);
int data_reg, ret;
ret = bh1730_adjust_gain(bh1730);
if (ret < 0)
return ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
ret = bh1730_get_lux(bh1730);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_RAW:
switch (chan->channel2) {
case IIO_MOD_LIGHT_CLEAR:
data_reg = BH1730_REG_DATA0LOW;
break;
case IIO_MOD_LIGHT_IR:
data_reg = BH1730_REG_DATA1LOW;
break;
default:
return -EINVAL;
}
ret = bh1730_read_word(bh1730, data_reg);
if (ret < 0)
return ret;
ret = ret * 1000 / bh1730_gain_multiplier(bh1730);
*val = ret / 1000;
*val2 = (ret % 1000) * 1000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = bh1730->itime_us;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int bh1730_parse_dt(struct bh1730_data *bh1730)
{
struct device *dev = &bh1730->client->dev;
struct device_node *dn = dev->of_node;
u32 *opt_win_coeff = NULL;
u32 *gain_coeff = NULL;
int opt_win_coeff_count, gain_coeff_count;
u32 cycle = 0, mul = 0;
bh1730->cal = def_lux_data;
bh1730->reg_vdd = devm_regulator_get(dev, "als-vdd");
if (IS_ERR(bh1730->reg_vdd))
return dev_err_probe(dev, PTR_ERR(bh1730->reg_vdd),
"failed to get als-vdd\n");
bh1730->reg_vid = devm_regulator_get(dev, "als-vid");
if (IS_ERR(bh1730->reg_vid))
return dev_err_probe(dev, PTR_ERR(bh1730->reg_vid),
"failed to get als-vid\n");
if (!dn)
goto out;
/* Get calibration */
if (of_property_read_u32(dn, "rohm,integration-cycle", &cycle) ||
of_property_read_u32(dn, "rohm,lux-multiplier", &mul) ||
!cycle || !mul)
goto out;
/* Get optical window coefficients */
opt_win_coeff_count = of_property_count_u32_elems(dn, "rohm,opt-win-coeff");
if (opt_win_coeff_count > 0 &&
!(opt_win_coeff_count % (sizeof(struct opt_win_coeff_t) / sizeof(u32)))) {
opt_win_coeff = devm_kcalloc(dev, opt_win_coeff_count,
sizeof(u32), GFP_KERNEL);
if (!opt_win_coeff)
return -ENOMEM;
if (of_property_read_u32_array(dn, "rohm,opt-win-coeff",
opt_win_coeff, opt_win_coeff_count))
goto out;
}
/* Get gain sensitivity coefficients, 2 for each gain supported */
gain_coeff_count = of_property_count_u32_elems(dn, "rohm,gain-coeff");
if (gain_coeff_count == 8) {
gain_coeff = devm_kcalloc(dev, gain_coeff_count,
sizeof(u32), GFP_KERNEL);
if (!gain_coeff)
return -ENOMEM;
if (of_property_read_u32_array(dn, "rohm,gain-coeff",
gain_coeff, gain_coeff_count))
goto out;
}
if (opt_win_coeff) {
bh1730->cal.opt_win_coeff =
(const struct opt_win_coeff_t *)opt_win_coeff;
bh1730->cal.opt_win_coeff_count = opt_win_coeff_count /
(sizeof(struct opt_win_coeff_t) / sizeof(u32));
}
if (gain_coeff)
bh1730->cal.gain_coeff = (const struct gain_coeff_t *)gain_coeff;
bh1730->cal.itime_cycle = cycle;
bh1730->cal.mul = mul;
return 0;
out:
dev_info(dev, "using default calibration\n");
return 0;
}
static const struct iio_info bh1730_info = {
.read_raw = bh1730_read_raw,
};
static const struct iio_chan_spec bh1730_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_INT_TIME),
},
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_CLEAR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
};
static void bh1730_power_off_action(void *data)
{
bh1730_power_off(data);
}
static int bh1730_probe(struct i2c_client *client)
{
struct bh1730_data *bh1730;
struct iio_dev *indio_dev;
int ret;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WORD_DATA))
return -EOPNOTSUPP;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*bh1730));
if (!indio_dev)
return -ENOMEM;
bh1730 = iio_priv(indio_dev);
bh1730->client = client;
i2c_set_clientdata(client, indio_dev);
ret = bh1730_parse_dt(bh1730);
if (ret < 0)
return ret;
ret = bh1730_power_on(bh1730);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev, bh1730_power_off_action,
bh1730);
if (ret)
return ret;
ret = bh1730_init_config(bh1730);
if (ret < 0)
return ret;
indio_dev->info = &bh1730_info;
indio_dev->name = "bh1730";
indio_dev->channels = bh1730_channels;
indio_dev->num_channels = ARRAY_SIZE(bh1730_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int bh1730_suspend(struct device *dev)
{
struct bh1730_data *bh1730 = iio_priv(dev_get_drvdata(dev));
return bh1730_power_off(bh1730);
}
static int bh1730_resume(struct device *dev)
{
struct bh1730_data *bh1730 = iio_priv(dev_get_drvdata(dev));
int ret;
ret = bh1730_power_on(bh1730);
if (ret < 0)
return ret;
return bh1730_init_config(bh1730);
}
static DEFINE_SIMPLE_DEV_PM_OPS(bh1730_pm_ops, bh1730_suspend, bh1730_resume);
static const struct i2c_device_id bh1730_i2c_device_id[] = {
{ BH1730_NAME },
{ }
};
MODULE_DEVICE_TABLE(i2c, bh1730_i2c_device_id);
static const struct of_device_id of_bh1730_match[] = {
{ .compatible = "rohm,bh1730fvc" },
{ }
};
MODULE_DEVICE_TABLE(of, of_bh1730_match);
static struct i2c_driver bh1730_driver = {
.probe = bh1730_probe,
.driver = {
.name = BH1730_NAME,
.of_match_table = of_bh1730_match,
.pm = pm_sleep_ptr(&bh1730_pm_ops),
},
.id_table = bh1730_i2c_device_id,
};
module_i2c_driver(bh1730_driver);
MODULE_AUTHOR("CTCaer <ctcaer@gmail.com>");
MODULE_DESCRIPTION("ROHM BH1730FVC driver");
MODULE_LICENSE("GPL");
+16 -64
View File
@@ -221,8 +221,6 @@
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL8(x) (0x47c + (x) * 0x40)
#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(x) (0x464 + (x) * 0x40)
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ BIT(0)
#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD BIT(1)
@@ -432,20 +430,6 @@ static struct init_data tegra210b01_usb3_pll_g1_init_data[] = {
{.cfg_addr = 0x1E, .cfg_wdata = 0x0017},
};
static struct init_data tegra210b01_usb3_lane_init_data[] = {
{.cfg_addr = 0x1, .cfg_wdata = 0x0002},
{.cfg_addr = 0x4, .cfg_wdata = 0x0032},
{.cfg_addr = 0x7, .cfg_wdata = 0x0022},
{.cfg_addr = 0x35, .cfg_wdata = 0x2587},
{.cfg_addr = 0x49, .cfg_wdata = 0x0FC7},
{.cfg_addr = 0x52, .cfg_wdata = 0x0001},
{.cfg_addr = 0x53, .cfg_wdata = 0x3C0F},
{.cfg_addr = 0x56, .cfg_wdata = 0xC00F},
{.cfg_addr = 0x5D, .cfg_wdata = 0xFF07},
{.cfg_addr = 0x5E, .cfg_wdata = 0x141A},
{.cfg_addr = 0x97, .cfg_wdata = 0x0080},
};
struct tegra210_xusb_fuse_calibration {
u32 hs_curr_level[4];
u32 hs_term_range_adj;
@@ -546,31 +530,6 @@ static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
return -EINVAL;
}
static void tegra210b01_usb3_lane_init(struct tegra_xusb_padctl *padctl)
{
struct tegra_xusb_lane *lane;
unsigned int i, j;
u32 value;
for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
if (!padctl->pcie->lanes[i])
continue;
lane = phy_get_drvdata(padctl->pcie->lanes[i]);
if (!tegra_xusb_lane_check(lane, "usb3-ss"))
continue;
for (j = 0; j < ARRAY_SIZE(tegra210b01_usb3_lane_init_data); j++) {
value = CFG_ADDR(tegra210b01_usb3_lane_init_data[j].cfg_addr);
value |= CFG_WDATA(tegra210b01_usb3_lane_init_data[j].cfg_wdata);
value |= CFG_RESET;
value |= CFG_WS;
padctl_writel(padctl, value,
XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL8(lane->index));
}
}
}
/* must be called under padctl->lock */
static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
{
@@ -611,24 +570,22 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
padctl_writel(padctl, value,
XUSB_PADCTL_UPHY_PLL_S0_CTL10);
}
tegra210b01_usb3_lane_init(padctl);
} else {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
}
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
@@ -2210,10 +2167,7 @@ static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
if (submode == USB_ROLE_HOST) {
tegra210_xusb_padctl_id_override(padctl, true);
if (!port->supply_enabled) {
err = regulator_enable(port->supply);
port->supply_enabled = !err;
}
err = regulator_enable(port->supply);
} else if (submode == USB_ROLE_DEVICE) {
tegra210_xusb_padctl_vbus_override(padctl, true);
} else if (submode == USB_ROLE_NONE) {
@@ -2222,10 +2176,8 @@ static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
* USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
* be enabled.
*/
if (port->supply_enabled) {
if (regulator_is_enabled(port->supply))
regulator_disable(port->supply);
port->supply_enabled = false;
}
tegra210_xusb_padctl_id_override(padctl, false);
tegra210_xusb_padctl_vbus_override(padctl, false);
-1
View File
@@ -314,7 +314,6 @@ struct tegra_xusb_usb2_port {
struct tegra_xusb_port base;
struct regulator *supply;
bool supply_enabled;
enum usb_dr_mode mode;
bool internal;
int usb3_port_fake;
+6 -4
View File
@@ -466,7 +466,8 @@ struct tegra_pmc_soc {
bool has_usb_sleepwalk;
bool supports_core_domain;
bool has_single_mmio_aperture;
bool has_panic_notifier;
bool cboot_panic_notifier;
};
/**
@@ -1365,6 +1366,7 @@ static int tegra_pmc_panic_handler(struct notifier_block *this,
unsigned long action, void *data)
{
tegra_pmc_writel(pmc, KERNEL_PANIC_MAGIC, PMC_SCRATCH37);
return NOTIFY_DONE;
}
@@ -3565,7 +3567,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
}
}
if (pmc->soc->has_panic_notifier) {
if (pmc->soc->cboot_panic_notifier) {
pmc->panic_notifier.notifier_call = tegra_pmc_panic_handler;
pmc->panic_notifier.priority = INT_MAX-1;
@@ -4402,7 +4404,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.has_blink_output = true,
.has_usb_sleepwalk = true,
.has_single_mmio_aperture = true,
.has_panic_notifier = true,
.cboot_panic_notifier = true,
.has_bootrom_command = true,
};
@@ -4465,7 +4467,7 @@ static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
.has_blink_output = true,
.has_usb_sleepwalk = true,
.has_single_mmio_aperture = true,
.has_panic_notifier = true,
.cboot_panic_notifier = true,
.has_bootrom_command = true,
};
+9 -11
View File
@@ -961,9 +961,7 @@ static void bm92t_port_set_init_state(struct work_struct *work)
"port is set to init state\n");
msleep(100); /* Wait a bit */
disable_irq(info->i2c_client->irq);
if (!queue_work(info->event_wq, &info->work))
enable_irq(info->i2c_client->irq);
queue_work(info->event_wq, &info->work);
}
static bool bm92t_check_pdo(struct bm92t_info *info)
@@ -1885,8 +1883,6 @@ ret:
bm92t_read_reg(info, UNKOWN_1C_REG, (void *)&dp, sizeof(dp));
bm92t_read_reg(info, UNKOWN_1D_REG, (void *)&dp, sizeof(dp));
}
enable_irq(info->i2c_client->irq);
}
static irqreturn_t bm92t_interrupt_handler(int irq, void *handle)
@@ -1894,8 +1890,7 @@ static irqreturn_t bm92t_interrupt_handler(int irq, void *handle)
struct bm92t_info *info = handle;
disable_irq_nosync(info->i2c_client->irq);
if (!queue_work(info->event_wq, &info->work))
enable_irq(info->i2c_client->irq);
queue_work(info->event_wq, &info->work);
return IRQ_HANDLED;
}
@@ -2151,7 +2146,7 @@ static ssize_t bm92t_cmd_write(struct file *file,
ret = kstrtouint(buf, 0, &val);
if (!ret) {
if (ret == 1) {
cmd = val;
bm92t_send_cmd(info, &cmd);
} else {
@@ -2183,7 +2178,7 @@ static ssize_t bm92t_usbhub_dp_sleep_write(struct file *file,
ret = kstrtouint(buf, 0, &val);
if (!ret) {
if (ret == 1) {
bm92t_usbhub_dp_sleep(info, val ? true : false);
} else {
dev_err(&info->i2c_client->dev, "Syntax is: 0 or number\n");
@@ -2522,8 +2517,11 @@ static int bm92t_probe(struct i2c_client *client)
if (client->irq > 0) {
/*
* Level-triggered (active-low) IRQ wired to BM92T36 ALERT.
* The IRQ stays disabled while the event work runs i2c reads
* and is re-enabled once the controller's status is cleared.
* Use a threaded handler with IRQF_ONESHOT so the line is
* masked while bm92t_interrupt_handler runs i2c reads, then
* re-enabled after the work clears the controller's status.
* Without IRQF_ONESHOT this would re-enter immediately on
* the still-asserted line and "irq nobody cared" disable it.
*/
if (request_threaded_irq(client->irq, NULL,
bm92t_interrupt_handler,