clk: soc: tegra: Add DFLL tune1_high parameter

Added support for DFLL tune1_high parameter

Bug 1967884

Change-Id: I0140724a22c43a3b05d39735b7a7faebd4be2908
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577129
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

drivers/clk/tegra/clk-dfll.c

@@ -552,10 +552,21 @@ static void dfll_tune_low(struct tegra_dfll *td)
  */
 static void dfll_tune_high(struct tegra_dfll *td)
 {
+	u32 tune0_high;
+	u32 tune1_high;
+
 	td->tune_range = DFLL_TUNE_HIGH;
 
-	dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_high, DFLL_TUNE0);
-	dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1_low, DFLL_TUNE1);
+	tune0_high = td->soc->cvb->cpu_dfll_data.tune0_high;
+	if (!tune0_high)
+		tune0_high = td->soc->cvb->cpu_dfll_data.tune0_low;
+	dfll_writel(td, tune0_high, DFLL_TUNE0);
+
+	tune1_high = td->soc->cvb->cpu_dfll_data.tune1_high;
+	if (!tune1_high)
+		tune1_high = td->soc->cvb->cpu_dfll_data.tune1_low;
+	dfll_writel(td, tune1_high, DFLL_TUNE1);
+
 	dfll_wmb(td);
 
 	if (td->soc->set_clock_trimmers_high)

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

@@ -683,6 +683,7 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
 		.cpu_dfll_data = {
 			.tune0_low = 0x0000ffcf,
 			.tune1_low = 0x012207ff,
+			.tune1_high = 0x03FFF7FF,
 			.tune_high_min_millivolts = 850,
 		}
 	},

drivers/clk/tegra/cvb.h

@@ -32,6 +32,7 @@ struct cvb_cpu_dfll_data {
 	u32 tune0_low;
 	u32 tune0_high;
 	u32 tune1_low;
+	u32 tune1_high;
 	unsigned int tune_high_min_millivolts;
 };