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thermal: intel: intel_tcc_cooling: Use a model-specific bitmask for TCC offset

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BugLink: https://bugs.launchpad.net/bugs/2103427

The TCC offset field in the register MSR_TEMPERATURE_TARGET is not
architectural. The TCC library provides a model-specific bitmask. Use it to
determine the maximum TCC offset.

Suggested-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Link: https://patch.msgid.link/20240614211606.5896-3-ricardo.neri-calderon@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit be6bfb29c55e48567983e24aba7b6bf9a66a45ab)
Signed-off-by: Thibault Ferrante <thibault.ferrante@canonical.com>
Acked-by: Andrei Gherzan <andrei.gherzan@canonical.com>
Acked-by: Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>
Signed-off-by: Mehmet Basaran <mehmet.basaran@canonical.com>
This commit is contained in:
Ricardo Neri
2025-03-17 16:52:06 +01:00
committed by Mehmet Basaran
parent 51938a0f5f
commit f98fb0e2a8
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/thermal/intel/intel_tcc_cooling.c
+1 -1
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@@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev;
static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long
*state)
{
*state = 0x3f;
*state = intel_tcc_get_offset_mask();
return 0;
}