From f98fb0e2a88c607a9c7b4a7cd1fc8c69c028128d Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Mon, 17 Mar 2025 16:52:06 +0100 Subject: [PATCH] thermal: intel: intel_tcc_cooling: Use a model-specific bitmask for TCC offset BugLink: https://bugs.launchpad.net/bugs/2103427 The TCC offset field in the register MSR_TEMPERATURE_TARGET is not architectural. The TCC library provides a model-specific bitmask. Use it to determine the maximum TCC offset. Suggested-by: Zhang Rui Reviewed-by: Zhang Rui Signed-off-by: Ricardo Neri Link: https://patch.msgid.link/20240614211606.5896-3-ricardo.neri-calderon@linux.intel.com Signed-off-by: Rafael J. Wysocki (cherry picked from commit be6bfb29c55e48567983e24aba7b6bf9a66a45ab) Signed-off-by: Thibault Ferrante Acked-by: Andrei Gherzan Acked-by: Massimiliano Pellizzer Signed-off-by: Mehmet Basaran --- drivers/thermal/intel/intel_tcc_cooling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 6c392147e6d1..5bfc2b515c78 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = 0x3f; + *state = intel_tcc_get_offset_mask(); return 0; }