PCI: tegra194: Set EP alignment restriction for inbound ATU

BugLink: https://bugs.launchpad.net/bugs/2083196

[ Upstream commit d19a86d584e04191cdab7ced24d7ed791075697a ]

Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction
for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the
Tegra194 PCIe driver.

Fixes: c57247f940 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Link: https://lore.kernel.org/linux-pci/20240508092207.337063-1-jonathanh@nvidia.com
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Portia Stephens <portia.stephens@canonical.com>
Signed-off-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>

This commit is contained in:

Jon Hunter

2024-05-08 10:22:07 +01:00

committed by

Mehmet Basaran

parent 7ea4d9ade5

commit 6bbd103a61

1 changed files with 1 additions and 0 deletions

									
										drivers/pci/controller/dwc/pcie-tegra194.c
									
		+1
		
												View File
												
				@@ -2010,6 +2010,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {

					.reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5,

					.bar_fixed_64bit = 1 << BAR_0,

					.bar_fixed_size[0] = SZ_1M,

					.align = SZ_64K,

				};

				static const struct pci_epc_features*