From 6bbd103a610449418aeaaa2b130314c288f07867 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 8 May 2024 10:22:07 +0100 Subject: [PATCH] PCI: tegra194: Set EP alignment restriction for inbound ATU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BugLink: https://bugs.launchpad.net/bugs/2083196 [ Upstream commit d19a86d584e04191cdab7ced24d7ed791075697a ] Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the Tegra194 PCIe driver. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Suggested-by: Manikanta Maddireddy Link: https://lore.kernel.org/linux-pci/20240508092207.337063-1-jonathanh@nvidia.com Signed-off-by: Jon Hunter Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Niklas Cassel Signed-off-by: Sasha Levin Signed-off-by: Portia Stephens Signed-off-by: Roxana Nicolescu --- drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 2349e284f6e8..f82b32a308ed 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2010,6 +2010,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = { .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5, .bar_fixed_64bit = 1 << BAR_0, .bar_fixed_size[0] = SZ_1M, + .align = SZ_64K, }; static const struct pci_epc_features*