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NVIDIA: SAUCE: cpufreq: tegra194: disable irqs for freq read

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Disabling interrupts for the duration of the cpu frequency read. This
prevents another task from hijacking the CPU and causing issues with our
read-back methodology.
Bug is observing errors compared to the NAFLL's PTO counter for cpufreq
readback. Readback is consistently lower than expected.
Suspecting that a spurious task/interrupt is interrupt the MRS
instructions and causing refclk to be measured across a longer interval
than coreclk.

http://nvbugs/4934006

Signed-off-by: Ishan Shah <ishah@nvidia.com>

Reviewed-by: Nathan Hartman <nhartman@nvidia.com>
Reviewed-by: Ishan Shah <ishah@nvidia.com>
Tested-by: Ishan Shah <ishah@nvidia.com>
Reviewed-by: Mirko Andjic <mandjic@nvidia.com>
Signed-off-by: Vishwaroop A <va@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Ishan Shah
2024-12-06 18:05:35 +00:00
committed by Noah Wager
parent ad49a6af18
commit 638d0d1c0e
1 changed files with 8 additions and 0 deletions
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drivers/cpufreq/tegra194-cpufreq.c
+8
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@@ -256,6 +256,13 @@ static void tegra264_read_counters(struct tegra_cpu_ctr *c)
u32 delta_refcnt;
int cnt = 0;
/**
* Bug 4934006 observes that we under-read the CPU Frequency compared
* to our clock-source HW counters. Disabling IRQs to avoid preemption
* and make this a critical section.
*/
local_irq_disable();
/* SYS_AMEVCNTR0_CORE_EL0 and SYS_AMEVCNTR0_CORE_EL1 */
asm volatile("mrs %0, S3_3_C13_C4_0" : "=r" (c->last_coreclk_cnt) : );
asm volatile("mrs %0, S3_3_C13_C4_1" : "=r" (c->last_refclk_cnt) : );
@@ -279,6 +286,7 @@ static void tegra264_read_counters(struct tegra_cpu_ctr *c)
break;
}
} while (delta_refcnt < data->soc->refclk_delta_min);
local_irq_enable();
}
static struct tegra_cpufreq_ops tegra264_cpufreq_ops = {