From 638d0d1c0ee78dc70f100c074f1a5ffde37c32f9 Mon Sep 17 00:00:00 2001 From: Ishan Shah Date: Fri, 6 Dec 2024 18:05:35 +0000 Subject: [PATCH] NVIDIA: SAUCE: cpufreq: tegra194: disable irqs for freq read Disabling interrupts for the duration of the cpu frequency read. This prevents another task from hijacking the CPU and causing issues with our read-back methodology. Bug is observing errors compared to the NAFLL's PTO counter for cpufreq readback. Readback is consistently lower than expected. Suspecting that a spurious task/interrupt is interrupt the MRS instructions and causing refclk to be measured across a longer interval than coreclk. http://nvbugs/4934006 Signed-off-by: Ishan Shah Reviewed-by: Nathan Hartman Reviewed-by: Ishan Shah Tested-by: Ishan Shah Reviewed-by: Mirko Andjic Signed-off-by: Vishwaroop A Acked-by: Noah Wager Acked-by: Jacob Martin Signed-off-by: Noah Wager --- drivers/cpufreq/tegra194-cpufreq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index 32a7a327f53a..0a87f28897d1 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -256,6 +256,13 @@ static void tegra264_read_counters(struct tegra_cpu_ctr *c) u32 delta_refcnt; int cnt = 0; + /** + * Bug 4934006 observes that we under-read the CPU Frequency compared + * to our clock-source HW counters. Disabling IRQs to avoid preemption + * and make this a critical section. + */ + + local_irq_disable(); /* SYS_AMEVCNTR0_CORE_EL0 and SYS_AMEVCNTR0_CORE_EL1 */ asm volatile("mrs %0, S3_3_C13_C4_0" : "=r" (c->last_coreclk_cnt) : ); asm volatile("mrs %0, S3_3_C13_C4_1" : "=r" (c->last_refclk_cnt) : ); @@ -279,6 +286,7 @@ static void tegra264_read_counters(struct tegra_cpu_ctr *c) break; } } while (delta_refcnt < data->soc->refclk_delta_min); + local_irq_enable(); } static struct tegra_cpufreq_ops tegra264_cpufreq_ops = {