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NVIDIA: SAUCE: memory: Add support for T264 mc-err

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Add support for mc-err logging for T264 in upstream mc driver.
- Add mc-error handling flow for MCF, HUB, HUBC, SBS and MC Channel.
- Each of these components have different interrupt lines for mc-err.
- Register interrupt handlers for interrupts from these different MSS
components.
- Introduce new SOC specific fields in tegra_mc_soc.

http://nvbugs/4655916

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Ketan Patil
2024-06-18 06:13:47 +00:00
committed by Noah Wager
parent 4c428a18bf
commit 4ef740cae9
12 changed files with 1148 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/memory/tegra/mc.c
+82 -34
View File
@@ -56,6 +56,24 @@ static const struct of_device_id tegra_mc_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
const struct tegra_mc_regs tegra20_mc_regs = {
.mc_err_status_reg = 0x08,
.mc_err_add_reg = 0x0c,
.mc_err_add_hi_reg = 0x11fc,
.mc_err_vpr_status_reg = 0x654,
.mc_err_vpr_add_reg = 0x658,
.mc_err_sec_status_reg = 0x67c,
.mc_err_sec_add_reg = 0x680,
.mc_err_mts_status_reg = 0x9b0,
.mc_err_mts_add_reg = 0x9b4,
.mc_err_gen_co_status_reg = 0xc00,
.mc_err_gen_co_add_reg = 0xc04,
.mc_err_route_status_reg = 0x9c0,
.mc_err_route_add_reg = 0x9c4,
.mc_addr_hi_mask = 0x3,
.mc_err_status_type_mask = (0x7 << 28),
};
static void tegra_mc_devm_action_put_device(void *data)
{
struct tegra_mc *mc = data;
@@ -537,9 +555,12 @@ int tegra30_mc_probe(struct tegra_mc *mc)
return 0;
}
static irq_handler_t tegra30_mc_irq_handlers = tegra30_mc_handle_irq;
const struct tegra_mc_ops tegra30_mc_ops = {
.probe = tegra30_mc_probe,
.handle_irq = tegra30_mc_handle_irq,
.handle_irq = &tegra30_mc_irq_handlers,
.num_interrupts = 1,
};
#endif
@@ -589,7 +610,7 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
return IRQ_NONE;
for_each_set_bit(bit, &status, 32) {
const char *error = tegra_mc_status_names[bit] ?: "unknown";
const char *error = tegra20_mc_status_names[bit] ?: "unknown";
const char *client = "unknown", *desc;
const char *direction, *secure;
u32 status_reg, addr_reg;
@@ -605,37 +626,37 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
switch (intmask) {
case MC_INT_DECERR_VPR:
status_reg = MC_ERR_VPR_STATUS;
addr_reg = MC_ERR_VPR_ADR;
status_reg = mc->soc->mc_regs->mc_err_vpr_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_vpr_add_reg;
break;
case MC_INT_SECERR_SEC:
status_reg = MC_ERR_SEC_STATUS;
addr_reg = MC_ERR_SEC_ADR;
status_reg = mc->soc->mc_regs->mc_err_sec_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_sec_add_reg;
break;
case MC_INT_DECERR_MTS:
status_reg = MC_ERR_MTS_STATUS;
addr_reg = MC_ERR_MTS_ADR;
status_reg = mc->soc->mc_regs->mc_err_mts_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_mts_add_reg;
break;
case MC_INT_DECERR_GENERALIZED_CARVEOUT:
status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
status_reg = mc->soc->mc_regs->mc_err_gen_co_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_gen_co_add_reg;
break;
case MC_INT_DECERR_ROUTE_SANITY:
status_reg = MC_ERR_ROUTE_SANITY_STATUS;
addr_reg = MC_ERR_ROUTE_SANITY_ADR;
status_reg = mc->soc->mc_regs->mc_err_route_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_route_add_reg;
break;
default:
status_reg = MC_ERR_STATUS;
addr_reg = MC_ERR_ADR;
status_reg = mc->soc->mc_regs->mc_err_status_reg;
addr_reg = mc->soc->mc_regs->mc_err_add_reg;
#ifdef CONFIG_PHYS_ADDR_T_64BIT
if (mc->soc->has_addr_hi_reg)
addr_hi_reg = MC_ERR_ADR_HI;
addr_hi_reg = mc->soc->mc_regs->mc_err_add_hi_reg;
#endif
break;
}
@@ -654,7 +675,7 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
addr = mc_readl(mc, addr_hi_reg);
} else {
addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
MC_ERR_STATUS_ADR_HI_MASK);
mc->soc->mc_regs->mc_addr_hi_mask);
}
addr <<= 32;
}
@@ -679,11 +700,11 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
}
}
type = (value & MC_ERR_STATUS_TYPE_MASK) >>
type = (value & mc->soc->mc_regs->mc_err_status_type_mask) >>
MC_ERR_STATUS_TYPE_SHIFT;
desc = tegra_mc_error_names[type];
desc = tegra20_mc_error_names[type];
switch (value & MC_ERR_STATUS_TYPE_MASK) {
switch (value & mc->soc->mc_regs->mc_err_status_type_mask) {
case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
perm[0] = ' ';
perm[1] = '[';
@@ -736,7 +757,7 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
return IRQ_HANDLED;
}
const char *const tegra_mc_status_names[32] = {
const char *const tegra20_mc_status_names[32] = {
[ 1] = "External interrupt",
[ 6] = "EMEM address decode error",
[ 7] = "GART page fault",
@@ -751,7 +772,7 @@ const char *const tegra_mc_status_names[32] = {
[20] = "Route Sanity error",
};
const char *const tegra_mc_error_names[8] = {
const char *const tegra20_mc_error_names[8] = {
[2] = "EMEM decode error",
[3] = "TrustZone violation",
[4] = "Carveout violation",
@@ -946,25 +967,52 @@ static int tegra_mc_probe(struct platform_device *pdev)
tegra_mc_num_channel_enabled(mc);
if (mc->soc->ops && mc->soc->ops->handle_irq) {
mc->irq = platform_get_irq(pdev, 0);
if (mc->irq < 0)
return mc->irq;
WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
for (int i = 0; i < mc->soc->ops->num_interrupts; i++) {
int irq;
irq = platform_get_irq(pdev, i);
if (irq < 0)
return irq;
err = devm_request_irq(&pdev->dev, irq, mc->soc->ops->handle_irq[i], 0,
dev_name(&pdev->dev), mc);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq,
err);
return err;
}
}
}
if (mc->soc->has_chiplet_arch) {
unsigned long intstat;
/* Unmask MCF interrupts */
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->mcf_intmask, MCF_INTMASK_0);
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->mcf_intmask, MCF_INTPRIORITY_0);
/* Unmask HUB and HUBC interrupts */
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->hub_intmask, MSS_HUB_INTRMASK_0);
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->hub_intmask,
MSS_HUB_INTRPRIORITY_0);
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->hubc_intmask,
MSS_HUB_HUBC_INTMASK_0);
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->hubc_intmask,
MSS_HUB_HUBC_INTPRIORITY_0);
/* Unmask SBS interrupts */
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->sbs_intmask, MSS_SBS_INTMASK_0);
/* Unmask MC channel interrupt */
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->mc_ch_intmask, MC_CH_INTMASK_0);
} else {
if (mc->soc->num_channels)
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
MC_INTMASK);
MC_INTMASK);
else
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0,
dev_name(&pdev->dev), mc);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
err);
return err;
}
}
if (mc->soc->reset_ops) {
drivers/memory/tegra/mc.h
+98 -40
View File
@@ -13,15 +13,23 @@
#include <soc/tegra/mc.h>
#define MC_INTSTATUS 0x00
#define MC_INT_INVALID_GART_PAGE BIT(7)
#define MC_INT_INVALID_SMMU_PAGE BIT(10)
#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11)
#define MC_ERR_ROUTE_SANITY_SEC BIT(13)
#define MC_INTMASK 0x04
#define MC_ERR_STATUS 0x08
#define MC_ERR_ADR 0x0c
#define MC_GART_ERROR_REQ 0x30
#define MC_EMEM_ADR_CFG 0x54
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
#define MC_SECURITY_VIOLATION_STATUS 0x74
#define MC_EMEM_ARB_CFG 0x90
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
#define MC_EMEM_ARB_TIMING_RCD 0x98
#define MC_EMEM_ARB_TIMING_RP 0x9c
#define MC_EMEM_ARB_TIMING_RC 0xa0
@@ -43,57 +51,103 @@
#define MC_EMEM_ARB_OVERRIDE 0xe8
#define MC_TIMING_CONTROL_DBG 0xf8
#define MC_TIMING_CONTROL 0xfc
#define MC_ERR_VPR_STATUS 0x654
#define MC_ERR_VPR_ADR 0x658
#define MC_ERR_SEC_STATUS 0x67c
#define MC_ERR_SEC_ADR 0x680
#define MC_ERR_MTS_STATUS 0x9b0
#define MC_ERR_MTS_ADR 0x9b4
#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0
#define MC_ERR_ROUTE_SANITY_ADR 0x9c4
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
#define T264_MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0x8870
#define MC_GLOBAL_INTSTATUS 0xf24
#define MC_ERR_ADR_HI 0x11fc
#define MC_TIMING_UPDATE BIT(0)
#define MC_INT_DECERR_ROUTE_SANITY BIT(20)
#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)
#define MC_INT_DECERR_MTS BIT(16)
#define MC_INT_SECERR_SEC BIT(13)
#define MC_INT_DECERR_VPR BIT(12)
#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11)
#define MC_INT_INVALID_SMMU_PAGE BIT(10)
#define MC_INT_ARBITRATION_EMEM BIT(9)
#define MC_INT_SECURITY_VIOLATION BIT(8)
#define MC_INT_INVALID_GART_PAGE BIT(7)
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
#define MC_GLOBAL_INTSTATUS 0xf24
/* Registers for MSS HUB */
#define MSS_HUB_GLOBAL_INTSTATUS_0 0x6000
#define MSS_HUBC_INTR BIT(0)
#define MSS_HUB_HUBC_INTSTATUS_0 0x6008
#define MSS_HUB_INTRSTATUS_0 0x600c
#define MSS_HUB_HUBC_INTMASK_0 0x6010
#define MSS_HUB_HUBC_SCRUB_DONE_INTMASK BIT(0)
#define MSS_HUB_HUBC_INTPRIORITY_0 0x6014
#define MSS_HUB_INTRMASK_0 0x6018
#define MSS_HUB_COALESCER_ERR_INTMASK BIT(0)
#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK BIT(1)
#define MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK BIT(2)
#define MSS_HUB_MSI_ERR_INTMASK BIT(3)
#define MSS_HUB_POISON_RSP_INTMASK BIT(4)
#define MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK BIT(5)
#define MSS_HUB_RESERVED_PA_ERR_INTMASK BIT(6)
#define MSS_HUB_INTRPRIORITY_0 0x601c
#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0 0x6020
#define MSS_HUB_MSI_ERR_STATUS_0 0x6024
#define MSS_HUB_POISON_RSP_STATUS_0 0x6028
#define MSS_HUB_COALESCE_ERR_STATUS_0 0x60e0
#define MSS_HUB_COALESCE_ERR_ADR_HI_0 0x60e4
#define MSS_HUB_COALESCE_ERR_ADR_0 0x60e8
#define MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0 0x638c
#define MSS_HUB_RESERVED_PA_ERR_STATUS_0 0x6390
#define MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0 0x63b0
/* Registers for MC Channel */
#define MC_CH_INTSTATUS_0 0x82d4
#define MC_CH_INTMASK_0 0x82d8
#define WCAM_ERR_INTMASK BIT(19)
#define T264_MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0x8870
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0 0xbc74
/* Registers for MCF */
#define MCF_COMMON_INTSTATUS0_0_0 0xce04
#define MCF_INTSTATUS_0 0xce2c
#define MC_INT_DECERR_EMEM BIT(6)
#define MC_INT_SECURITY_VIOLATION BIT(8)
#define MC_INT_DECERR_VPR BIT(12)
#define MC_INT_SECERR_SEC BIT(13)
#define MC_INT_DECERR_MTS BIT(16)
#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)
#define MC_INT_DECERR_ROUTE_SANITY BIT(20)
#define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI BIT(21)
#define MCF_INTMASK_0 0xce30
#define MCF_INTPRIORITY_0 0xce34
/* Registers for SBS */
#define MSS_SBS_INTSTATUS_0 0xec08
#define MSS_SBS_INTMASK_0 0xec0c
#define MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK BIT(0)
#define MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK BIT(1)
#define MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK BIT(2)
/*Bit field of MC_ERR_ROUTE_SANITY_STATUS_0 register */
#define MC_ERR_ROUTE_SANITY_RW BIT(12)
/*Bit field of MC_ERR_STATUS_0 register */
#define MC_ERR_STATUS_RW BIT(16)
#define MC_ERR_STATUS_SECURITY BIT(17)
#define MC_ERR_STATUS_NONSECURE BIT(25)
#define MC_ERR_STATUS_WRITABLE BIT(26)
#define MC_ERR_STATUS_READABLE BIT(27)
#define MC_ERR_STATUS_ADR_HI_MASK_GSC 0xffff
#define MC_ERR_STATUS_ADR_HI_SHIFT_GSC 16
#define MC_ERR_STATUS_ADR_HI_SHIFT_RT 15
#define MC_ERR_STATUS_TYPE_SHIFT 28
#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
#define MC_ERR_STATUS_TYPE_MASK (0x7 << 28)
#define MC_ERR_STATUS_READABLE BIT(27)
#define MC_ERR_STATUS_WRITABLE BIT(26)
#define MC_ERR_STATUS_NONSECURE BIT(25)
#define MC_ERR_STATUS_TYPE_MASK_RT (0xf << 28)
#define MC_ERR_STATUS_TYPE_SHIFT_RT 28
#define MC_ERR_STATUS_ADR_HI_SHIFT 20
#define MC_ERR_STATUS_ADR_HI_MASK 0x3
#define MC_ERR_STATUS_SECURITY BIT(17)
#define MC_ERR_STATUS_RW BIT(16)
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
#define ERR_GENERALIZED_APERTURE_ID_SHIFT 0
#define ERR_GENERALIZED_APERTURE_ID_MASK 0x1F
#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT 5
#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK 0x1F
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
#define MC_TIMING_UPDATE BIT(0)
#define MC_BROADCAST_CHANNEL ~0
static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents)
@@ -207,8 +261,12 @@ extern const struct tegra_mc_ops tegra264_mc_ops;
#endif
irqreturn_t tegra30_mc_handle_irq(int irq, void *data);
extern const char * const tegra_mc_status_names[32];
extern const char * const tegra_mc_error_names[8];
extern const char * const tegra20_mc_status_names[32];
extern const char * const tegra20_mc_error_names[8];
int tegra186_mc_probe(struct tegra_mc *mc);
int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev);
int tegra186_mc_resume(struct tegra_mc *mc);
void tegra186_mc_remove(struct tegra_mc *mc);
/*
* These IDs are for internal use of Tegra ICC drivers. The ID numbers are
drivers/memory/tegra/tegra114.c
+2
View File
@@ -1114,4 +1114,6 @@ const struct tegra_mc_soc tegra114_mc_soc = {
.resets = tegra114_mc_resets,
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
.ops = &tegra30_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
drivers/memory/tegra/tegra124.c
+4
View File
@@ -1275,6 +1275,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
.ops = &tegra30_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
@@ -1307,5 +1309,7 @@ const struct tegra_mc_soc tegra132_mc_soc = {
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
.ops = &tegra30_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
drivers/memory/tegra/tegra186.c
+10 -12
View File
@@ -24,7 +24,7 @@
#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
static int tegra186_mc_probe(struct tegra_mc *mc)
int tegra186_mc_probe(struct tegra_mc *mc)
{
struct platform_device *pdev = to_platform_device(mc->dev);
struct resource *res;
@@ -74,7 +74,7 @@ populate:
return 0;
}
static void tegra186_mc_remove(struct tegra_mc *mc)
void tegra186_mc_remove(struct tegra_mc *mc)
{
of_platform_depopulate(mc->dev);
}
@@ -122,7 +122,7 @@ static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
}
#endif
static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
#if IS_ENABLED(CONFIG_IOMMU_API)
struct of_phandle_args args;
@@ -157,7 +157,7 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
return 0;
}
static int tegra186_mc_resume(struct tegra_mc *mc)
int tegra186_mc_resume(struct tegra_mc *mc)
{
#if IS_ENABLED(CONFIG_IOMMU_API)
unsigned int i;
@@ -172,19 +172,15 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
return 0;
}
static irq_handler_t tegra186_mc_irq_handlers = tegra30_mc_handle_irq;
const struct tegra_mc_ops tegra186_mc_ops = {
.probe = tegra186_mc_probe,
.remove = tegra186_mc_remove,
.resume = tegra186_mc_resume,
.probe_device = tegra186_mc_probe_device,
.handle_irq = tegra30_mc_handle_irq,
};
const struct tegra_mc_ops tegra264_mc_ops = {
.probe = tegra186_mc_probe,
.remove = tegra186_mc_remove,
.probe_device = tegra186_mc_probe_device,
.handle_irq = &tegra186_mc_irq_handlers,
.resume = tegra186_mc_resume,
.num_interrupts = 1,
};
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
@@ -925,5 +921,7 @@ const struct tegra_mc_soc tegra186_mc_soc = {
.ops = &tegra186_mc_ops,
.ch_intmask = 0x0000000f,
.global_intstatus_channel_shift = 0,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
#endif
drivers/memory/tegra/tegra194.c
+2
View File
@@ -1359,4 +1359,6 @@ const struct tegra_mc_soc tegra194_mc_soc = {
.icc_ops = &tegra_mc_icc_ops,
.ch_intmask = 0x00000f00,
.global_intstatus_channel_shift = 8,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
drivers/memory/tegra/tegra20.c
+7 -4
View File
@@ -700,7 +700,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
return IRQ_NONE;
for_each_set_bit(bit, &status, 32) {
const char *error = tegra_mc_status_names[bit];
const char *error = tegra20_mc_status_names[bit];
const char *direction = "read", *secure = "";
const char *client, *desc;
phys_addr_t addr;
@@ -713,7 +713,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
value = mc_readl(mc, reg);
id = value & mc->soc->client_id_mask;
desc = tegra_mc_error_names[2];
desc = tegra20_mc_error_names[2];
if (value & BIT(31))
direction = "write";
@@ -724,7 +724,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
value = mc_readl(mc, reg);
id = (value >> 1) & mc->soc->client_id_mask;
desc = tegra_mc_error_names[2];
desc = tegra20_mc_error_names[2];
if (value & BIT(0))
direction = "write";
@@ -736,7 +736,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
id = value & mc->soc->client_id_mask;
type = (value & BIT(30)) ? 4 : 3;
desc = tegra_mc_error_names[type];
desc = tegra20_mc_error_names[type];
secure = "secure ";
if (value & BIT(31))
@@ -764,6 +764,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
static const struct tegra_mc_ops tegra20_mc_ops = {
.probe = tegra20_mc_probe,
.handle_irq = tegra20_mc_handle_irq,
.num_interrupts = 1,
};
const struct tegra_mc_soc tegra20_mc_soc = {
@@ -778,4 +779,6 @@ const struct tegra_mc_soc tegra20_mc_soc = {
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
.icc_ops = &tegra20_mc_icc_ops,
.ops = &tegra20_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
drivers/memory/tegra/tegra210.c
+2
View File
@@ -1287,4 +1287,6 @@ const struct tegra_mc_soc tegra210_mc_soc = {
.resets = tegra210_mc_resets,
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
.ops = &tegra30_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
drivers/memory/tegra/tegra234.c
+2
View File
@@ -1153,4 +1153,6 @@ const struct tegra_mc_soc tegra234_mc_soc = {
* supported.
*/
.num_carveouts = 32,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
drivers/memory/tegra/tegra264.c
+908 -37
View File
File diff suppressed because it is too large Load Diff
drivers/memory/tegra/tegra30.c
+2
View File
@@ -1400,4 +1400,6 @@ const struct tegra_mc_soc tegra30_mc_soc = {
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
.icc_ops = &tegra30_mc_icc_ops,
.ops = &tegra30_mc_ops,
.has_chiplet_arch = false,
.mc_regs = &tegra20_mc_regs,
};
include/soc/tegra/mc.h
+29 -2
View File
@@ -14,6 +14,7 @@
#include <linux/reset-controller.h>
#include <linux/types.h>
#include <linux/tegra-icc.h>
#include <linux/interrupt.h>
struct clk;
struct device;
@@ -163,8 +164,27 @@ struct tegra_mc_ops {
int (*probe)(struct tegra_mc *mc);
void (*remove)(struct tegra_mc *mc);
int (*resume)(struct tegra_mc *mc);
irqreturn_t (*handle_irq)(int irq, void *data);
irq_handler_t *handle_irq;
int (*probe_device)(struct tegra_mc *mc, struct device *dev);
unsigned int num_interrupts;
};
struct tegra_mc_regs {
unsigned int mc_err_status_reg;
unsigned int mc_err_add_reg;
unsigned int mc_err_add_hi_reg;
unsigned int mc_err_vpr_status_reg;
unsigned int mc_err_vpr_add_reg;
unsigned int mc_err_sec_status_reg;
unsigned int mc_err_sec_add_reg;
unsigned int mc_err_mts_status_reg;
unsigned int mc_err_mts_add_reg;
unsigned int mc_err_gen_co_status_reg;
unsigned int mc_err_gen_co_add_reg;
unsigned int mc_err_route_status_reg;
unsigned int mc_err_route_add_reg;
unsigned int mc_addr_hi_mask;
unsigned int mc_err_status_type_mask;
};
struct tegra_mc_soc {
@@ -196,6 +216,13 @@ struct tegra_mc_soc {
const struct tegra_mc_icc_ops *icc_ops;
const struct tegra_mc_ops *ops;
bool has_chiplet_arch;
u32 mcf_intmask;
u32 hub_intmask;
u32 hubc_intmask;
u32 sbs_intmask;
u32 mc_ch_intmask;
const struct tegra_mc_regs *mc_regs;
};
struct tegra_mc {
@@ -206,7 +233,6 @@ struct tegra_mc {
void __iomem *bcast_ch_regs;
void __iomem **ch_regs;
struct clk *clk;
int irq;
const struct tegra_mc_soc *soc;
unsigned long tick;
@@ -256,4 +282,5 @@ tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
}
#endif
extern const struct tegra_mc_regs tegra20_mc_regs;
#endif /* __SOC_TEGRA_MC_H__ */