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NVIDIA: SAUCE: memory: tegra: Fix channel enable register

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Offset of MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0 has changed for T264.
Add macro for it and save it in MC SOC struct.
Use that offset for getting number of channels enabled.

http://nvbugs/4478451

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Ashish Mhetre
2024-06-04 06:53:36 +00:00
committed by Noah Wager
parent 361e5229ed
commit 4c428a18bf
7 changed files with 13 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/memory/tegra/mc.c
+7 -2
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@@ -888,8 +888,13 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
unsigned int i;
u32 value;
value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE);
if (value <= 0) {
if(mc->soc->cfg_channel_enable) {
value = mc_ch_readl(mc, 0, mc->soc->cfg_channel_enable);
if (value <= 0) {
mc->num_channels = mc->soc->num_channels;
return;
}
} else {
mc->num_channels = mc->soc->num_channels;
return;
}
drivers/memory/tegra/mc.h
+1
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@@ -54,6 +54,7 @@
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
#define T264_MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0x8870
#define MC_GLOBAL_INTSTATUS 0xf24
#define MC_ERR_ADR_HI 0x11fc
drivers/memory/tegra/tegra186.c
+1
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@@ -917,6 +917,7 @@ const struct tegra_mc_soc tegra186_mc_soc = {
.clients = tegra186_mc_clients,
.num_address_bits = 40,
.num_channels = 4,
.cfg_channel_enable = MC_EMEM_ADR_CFG_CHANNEL_ENABLE,
.client_id_mask = 0xff,
.intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
drivers/memory/tegra/tegra194.c
+1
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@@ -1348,6 +1348,7 @@ const struct tegra_mc_soc tegra194_mc_soc = {
.clients = tegra194_mc_clients,
.num_address_bits = 40,
.num_channels = 16,
.cfg_channel_enable = MC_EMEM_ADR_CFG_CHANNEL_ENABLE,
.client_id_mask = 0xff,
.intmask = MC_INT_DECERR_ROUTE_SANITY |
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
drivers/memory/tegra/tegra234.c
+1
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@@ -1137,6 +1137,7 @@ const struct tegra_mc_soc tegra234_mc_soc = {
.clients = tegra234_mc_clients,
.num_address_bits = 40,
.num_channels = 16,
.cfg_channel_enable = MC_EMEM_ADR_CFG_CHANNEL_ENABLE,
.client_id_mask = 0x1ff,
.intmask = MC_INT_DECERR_ROUTE_SANITY |
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
drivers/memory/tegra/tegra264.c
+1
View File
@@ -301,6 +301,7 @@ const struct tegra_mc_soc tegra264_mc_soc = {
.clients = tegra264_mc_clients,
.num_address_bits = 40,
.num_channels = 16,
.cfg_channel_enable = T264_MC_EMEM_ADR_CFG_CHANNEL_ENABLE,
.client_id_mask = 0x1ff,
.intmask = MC_INT_DECERR_ROUTE_SANITY |
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
include/soc/tegra/mc.h
+1
View File
@@ -181,6 +181,7 @@ struct tegra_mc_soc {
u16 client_id_mask;
u8 num_channels;
const u32 cfg_channel_enable;
const struct tegra_smmu_soc *smmu;