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NVIDIA: SAUCE: perf: smmuv3: Read ceid-override from DT

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BugLink: https://bugs.launchpad.net/bugs/2080908

A custom DT property ceid-override has been added to override value of
SMMU_PMCG_CEID register for TBUs, as this register has not been
implemented by HW team in T264. Add support in ARM SMMUv3 PMU driver to
read this property from device tree instead of reading the register.

http://nvbugs/4270693

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Bodla Rakesh Babu <rbodla@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Ketan Patil
2024-03-25 08:27:31 +00:00
committed by Noah Wager
parent e4f0889f97
commit 41610f4718
1 changed files with 9 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/perf/arm_smmuv3_pmu.c
+9 -3
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@@ -849,7 +849,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
struct smmu_pmu *smmu_pmu;
struct resource *res_0;
u32 cfgr, reg_size;
u64 ceid_64[2];
u64 ceid_64[2], ceid;
int irq, err;
char *name;
struct device *dev = &pdev->dev;
@@ -895,8 +895,14 @@ static int smmu_pmu_probe(struct platform_device *pdev)
if (irq > 0)
smmu_pmu->irq = irq;
ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
if (!of_property_read_u64(dev->of_node, "ceid0-override", &ceid)) {
ceid_64[0] = ceid;
ceid_64[1] = 0;
} else {
ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
}
bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
SMMU_PMCG_ARCH_MAX_EVENTS);