NVIDIA: SAUCE: memory: tegra: Disable mc-err handling in upstream

In t264, the mc-err handling flow is pretty different than t234 and
older chips. The new flow has been added in downstream mc-err driver for
t264. Hence it is needed to use downstream irq handler code for t264 mc-
err. Do not specify irq handler for t264 in upstream mc driver, so that
it can use the downstream mc-err handling code.
Later on, we need to move downstream mc-err code into upstream mc
driver and upstream it.

http://nvbugs/4345191

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Signed-off-by: Bodla Rakesh Babu <rbodla@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Ketan Patil
2024-06-13 10:10:22 +00:00
committed by Noah Wager
parent b107c2588b
commit 3bea329573
3 changed files with 13 additions and 3 deletions
+5 -2
View File
@@ -197,11 +197,14 @@ extern const struct tegra_mc_ops tegra30_mc_ops;
#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
defined(CONFIG_ARCH_TEGRA_194_SOC) || \
defined(CONFIG_ARCH_TEGRA_234_SOC) || \
defined(CONFIG_ARCH_TEGRA_264_SOC)
defined(CONFIG_ARCH_TEGRA_234_SOC)
extern const struct tegra_mc_ops tegra186_mc_ops;
#endif
#if defined(CONFIG_ARCH_TEGRA_264_SOC)
extern const struct tegra_mc_ops tegra264_mc_ops;
#endif
irqreturn_t tegra30_mc_handle_irq(int irq, void *data);
extern const char * const tegra_mc_status_names[32];
extern const char * const tegra_mc_error_names[8];
+7
View File
@@ -180,6 +180,13 @@ const struct tegra_mc_ops tegra186_mc_ops = {
.handle_irq = tegra30_mc_handle_irq,
};
const struct tegra_mc_ops tegra264_mc_ops = {
.probe = tegra186_mc_probe,
.remove = tegra186_mc_remove,
.probe_device = tegra186_mc_probe_device,
.resume = tegra186_mc_resume,
};
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct tegra_mc_client tegra186_mc_clients[] = {
{
+1 -1
View File
@@ -287,7 +287,7 @@ const struct tegra_mc_soc tegra264_mc_soc = {
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.has_addr_hi_reg = true,
.ops = &tegra186_mc_ops,
.ops = &tegra264_mc_ops,
.icc_ops = &tegra264_mc_icc_ops,
.ch_intmask = 0x0000ff00,
.global_intstatus_channel_shift = 8,