riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

BugLink: https://bugs.launchpad.net/bugs/2086138

[ Upstream commit 61f2e8a3a94175dbbaad6a54f381b2a505324610 ]

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
250/333/500/1000MHz in fact.

The PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d6d6 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[koichiroden: adjusted for the older kernel without jh7110-common.dtsi]
Signed-off-by: Koichiro Den <koichiro.den@canonical.com>
Signed-off-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>

This commit is contained in:

Xingyu Wu

2024-08-26 16:04:30 +08:00

committed by

Mehmet Basaran

parent a36121d985

commit 17787d4089

1 changed files with 6 additions and 0 deletions

									
										arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
									
		+6
		
												View File
												
				@@ -316,6 +316,12 @@

					};

				};

				&syscrg {

					assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,

							  <&pllclk JH7110_PLLCLK_PLL0_OUT>;

					assigned-clock-rates = <500000000>, <1500000000>;

				};

				&sysgpio {

					i2c0_pins: i2c0-0 {

						i2c-pins {