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5
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 tmakin
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744b0c1bec | ||
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tmakin
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18bb34db4c | ||
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tmakin
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a98ccc64ac | ||
 Aaron Kling
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3c056c0f25 | ||
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Aaron Kling
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6f1524c5ac |
No files matched your search
Vendored
+3
@@ -0,0 +1,3 @@
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{
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"makefile.configureOnOpen": true
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}
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@@ -6,6 +6,10 @@ dtb-y :=
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dtbo-y :=
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makefile-path := t21x/nx
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dtb-y += tegra210-odin.dtb
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dtb-y += tegra210b01-fric.dtb
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dtb-y += tegra210b01-odin.dtb
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dtb-y += tegra210b01-vali.dtb
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ifneq ($(dtb-y),)
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dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
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+1007
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/*
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* Copyright (c) 2019-2020, Billy Laws <blaws05@gmail.com>
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* Copyright (c) 2019-2022, CTCaer <ctcaer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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/ {
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host1x@50000000 {
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sor@54580000 {
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prod-settings {
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#prod-cells = <3>;
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prod_list_hdmi_board = "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m",
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"prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m";
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prod_c_hdmi_54m_75m {
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board {
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prod = <
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0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1
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0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
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// 27:24=ICHPMP 0x1
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0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
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// 12:09=TMDS_TERMADJ 0x9
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// 23:20=LOADADJ 0x3
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0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8
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0x00000138 0xffffffff 0x29292929 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
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// 31:24=LANE3_DP_LANE3 0x29
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// 23:16=LANE2_DP_LANE0 0x29
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// 15:08=LANE1_DP_LANE1 0x29
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// 07:00=LANE0_DP_LANE2 0x29
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0x00000148 0xffffffff 0x00000000 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
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// 31:24=LANE3_DP_LANE3 0x00
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// 23:16=LANE2_DP_LANE0 0x00
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// 15:08=LANE1_DP_LANE1 0x00
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// 07:00=LANE0_DP_LANE2 0x00
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0x00000170 0x0040ff00 0x00404000 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
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// 22:22=TX_PU 0x1
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// 15:08=TX_PU_VALUE 0x40
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>;
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};
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};
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prod_c_hdmi_75m_150m {
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board {
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prod = <
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0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0
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0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
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// 27:24=ICHPMP 0x1
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0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
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// 12:09=TMDS_TERMADJ 0x9
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// 23:20=LOADADJ 0x3
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0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8
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0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
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// 31:24=LANE3_DP_LANE3 0x30
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// 23:16=LANE2_DP_LANE0 0x37
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// 15:08=LANE1_DP_LANE1 0x37
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// 07:00=LANE0_DP_LANE2 0x37
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0x00000148 0xffffffff 0x01020202 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
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// 31:24=LANE3_DP_LANE3 0x01
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// 23:16=LANE2_DP_LANE0 0x02
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// 15:08=LANE1_DP_LANE1 0x02
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// 07:00=LANE0_DP_LANE2 0x02
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0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
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// 22:22=TX_PU 0x1
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// 15:08=TX_PU_VALUE 0x66
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>;
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};
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};
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prod_c_hdmi_150m_300m {
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board {
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prod = <
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0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0
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0x0000005c 0x0f000700 0x06000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
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// 27:24=ICHPMP 0x6
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0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
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// 12:09=TMDS_TERMADJ 0x9
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// 23:20=LOADADJ 0x3
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0x00000068 0x0f000000 0x0F000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xF
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0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
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// 31:24=LANE3_DP_LANE3 0x30
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// 23:16=LANE2_DP_LANE0 0x37
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// 15:08=LANE1_DP_LANE1 0x37
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// 07:00=LANE0_DP_LANE2 0x37
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0x00000148 0xffffffff 0x103E3E3E // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
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// 31:24=LANE3_DP_LANE3 0x10
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// 23:16=LANE2_DP_LANE0 0x3E
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// 15:08=LANE1_DP_LANE1 0x3E
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// 07:00=LANE0_DP_LANE2 0x3E
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0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
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// 22:22=TX_PU 0x1
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// 15:08=TX_PU_VALUE 0x66
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>;
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};
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};
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prod_c_hdmi_300m_600m {
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board {
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prod = <
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0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1
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0x0000005c 0x0f000700 0x0A000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
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// 27:24=ICHPMP 0xA
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0x00000060 0x00f01f00 0x00301700 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
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// 12:09=TMDS_TERMADJ 0xB
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// 23:20=LOADADJ 0x3
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0x00000068 0x0f000000 0x0E000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xE
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0x00000138 0xffffffff 0x353E3E3E // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
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// 31:24=LANE3_DP_LANE3 0x35
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// 23:16=LANE2_DP_LANE0 0x3E
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// 15:08=LANE1_DP_LANE1 0x3E
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// 07:00=LANE0_DP_LANE2 0x3E
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0x00000148 0xffffffff 0x023F3F3F // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
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// 31:24=LANE3_DP_LANE3 0x02
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// 23:16=LANE2_DP_LANE0 0x3F
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// 15:08=LANE1_DP_LANE1 0x3F
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// 07:00=LANE0_DP_LANE2 0x3F
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0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
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// 22:22=TX_PU 0x1
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// 15:08=TX_PU_VALUE 0x66
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>;
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};
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};
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};
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};
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};
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};
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+2256
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "tegra210b01-nx.dtsi"
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/ {
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model = "Nintendo Switch (OLED model)";
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compatible = "nvidia,fric", "nintendo,aula", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
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};
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+2560
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "tegra210b01-nx.dtsi"
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/ {
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model = "Nintendo Switch (2019)";
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compatible = "nvidia,modin", "nvidia,odin", "nintendo,iowa", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
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};
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Reference in new issue
Block a user