tmakin/tegra-dts-t21x-nx
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tmakin committed 2026-07-29 00:48:45 -05:00
1 parent a98ccc64ac
commit 18bb34db4c
5 files changed
+3154 -335
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tegra210-nx.dtsi
+44 -38
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@@ -11,6 +11,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210.dtsi"
#include "tegra210-prods.dtsi"
/ {
aliases {
@@ -274,29 +275,18 @@
};
/* Fixed regulators */
ts_dvdd: ts_dvdd {
battery_reg: regulator@0 {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "ts_dvdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-enable-ramp-delay = <10000>;
};
battery_reg: vdd-ac-bat {
compatible = "regulator-fixed";
status = "okay";
reg = <0>;
regulator-name = "vdd-ac-bat";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: vdd-3v3 {
vdd_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vdd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -320,22 +310,21 @@
vin-supply = <&max77620_ldo0>;
};
lcd_bl_en: lcd-bl-en {
lcd_bl_en: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
status = "okay"; /* Only enabled on Odin/Modin/Vali */
regulator-name = "lcd-bl-en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
regulator-boot-on; /* Must be set for seamless display */
enable-active-high;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
en_vdd_sd: en-vdd-sd {
en_vdd_sd: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "en-vdd-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -359,8 +348,10 @@
};
/* LCD Power Enable -5V. Rohm BD8316GWL. */
v_navdd_5v0: v-navdd-5v0 {
v_navdd_5v0: regulator@8 {
compatible = "regulator-fixed";
reg = <8>;
status = "okay"; /* Only enabled on Odin/Modin/Vali*/
regulator-name = "v_navdd_5v0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -371,8 +362,9 @@
};
/* Joycon/Fan power (battery). Maxim MAX8969EWL53+. */
v_vdd50_a: v-vdd50-a {
v_vdd50_a: regulator@9 {
compatible = "regulator-fixed";
reg = <9>;
regulator-name = "v_vdd50_a";
regulator-min-microvolt = <5300000>;
regulator-max-microvolt = <5300000>;
@@ -381,8 +373,10 @@
};
/* Joycon/Fan power (usb). DC0 on Odin. Maxim MAX8969EWL53+ on Modin. */
v_vdd50_b: v-vdd50-b {
v_vdd50_b: regulator@0xa {
compatible = "regulator-fixed";
reg = <10>;
status = "okay"; /* Only enabled on Odin/Modin */
regulator-name = "v_vdd50_b";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -390,8 +384,10 @@
enable-active-high;
};
v_vdd5v3: v-vdd5v3 {
/* VBUS power */
v_vdd5v3: regulator@0xb {
compatible = "regulator-fixed";
reg = <11>;
status = "okay"; /* Only enabled on Modin/Vali/Fric */
regulator-name = "v_vdd5v3";
regulator-min-microvolt = <5300000>;
@@ -401,8 +397,10 @@
regulator-enable-ramp-delay = <10000>;
};
vdd3v3_gc: vdd3v3-gc {
vdd3v3_gc: regulator@0xc {
compatible = "regulator-fixed";
status = "disabled"; /* Only on Odin */
reg = <12>;
regulator-name = "vdd3v3_gc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -413,34 +411,42 @@
vin-supply = <&vdd_3v3>;
};
/* TI TCR2EE48 4.8V */
en_vdd_jcl_chgr: left-joycon-charger {
vdd_wlreg_on: regulator@0xd {
compatible = "regulator-fixed";
reg = <13>;
regulator-name = "vdd-wlreg_on";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(H, 1) 0>;
regulator-boot-on;
regulator-always-on;
enable-active-high;
};
/* TI TCR2EE48 4.8V */
en_vdd_jcl_chgr: regulator@0xe {
compatible = "regulator-fixed";
reg = <14>;
status = "okay";
regulator-name = "left-joycon-charger";
regulator-name = "left-jc-reg";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
gpio = <&gpio TEGRA_GPIO(CC, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&v_vdd50_a>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* TI TCR2EE48 4.8V */
en_vdd_jcr_chgr: right-joycon-charger {
en_vdd_jcr_chgr: regulator@0xf {
compatible = "regulator-fixed";
reg = <15>;
status = "okay";
regulator-name = "right-joycon-charger";
regulator-name = "right-jc-reg";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&v_vdd50_a>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* SDMMC4 for EMMC */
@@ -488,7 +494,7 @@
mmc@700b0000 {
status = "okay";
bus-width = <4>;
max-frequency = <200000000>;
//max-frequency = <200000000>;
cap-sd-highspeed;
sd-uhs-sdr12;
tegra210-odin-prods.dtsi
+131
View File
@@ -0,0 +1,131 @@
/*
* Copyright (c) 2019-2020, Billy Laws <blaws05@gmail.com>
* Copyright (c) 2019-2022, CTCaer <ctcaer@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/ {
host1x@50000000 {
sor@54580000 {
prod-settings {
#prod-cells = <3>;
prod_list_hdmi_board = "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m",
"prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m";
prod_c_hdmi_54m_75m {
board {
prod = <
0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1
0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
// 27:24=ICHPMP 0x1
0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
// 12:09=TMDS_TERMADJ 0x9
// 23:20=LOADADJ 0x3
0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8
0x00000138 0xffffffff 0x29292929 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
// 31:24=LANE3_DP_LANE3 0x29
// 23:16=LANE2_DP_LANE0 0x29
// 15:08=LANE1_DP_LANE1 0x29
// 07:00=LANE0_DP_LANE2 0x29
0x00000148 0xffffffff 0x00000000 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
// 31:24=LANE3_DP_LANE3 0x00
// 23:16=LANE2_DP_LANE0 0x00
// 15:08=LANE1_DP_LANE1 0x00
// 07:00=LANE0_DP_LANE2 0x00
0x00000170 0x0040ff00 0x00404000 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
// 22:22=TX_PU 0x1
// 15:08=TX_PU_VALUE 0x40
>;
};
};
prod_c_hdmi_75m_150m {
board {
prod = <
0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0
0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
// 27:24=ICHPMP 0x1
0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
// 12:09=TMDS_TERMADJ 0x9
// 23:20=LOADADJ 0x3
0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8
0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
// 31:24=LANE3_DP_LANE3 0x30
// 23:16=LANE2_DP_LANE0 0x37
// 15:08=LANE1_DP_LANE1 0x37
// 07:00=LANE0_DP_LANE2 0x37
0x00000148 0xffffffff 0x01020202 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
// 31:24=LANE3_DP_LANE3 0x01
// 23:16=LANE2_DP_LANE0 0x02
// 15:08=LANE1_DP_LANE1 0x02
// 07:00=LANE0_DP_LANE2 0x02
0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
// 22:22=TX_PU 0x1
// 15:08=TX_PU_VALUE 0x66
>;
};
};
prod_c_hdmi_150m_300m {
board {
prod = <
0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0
0x0000005c 0x0f000700 0x06000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
// 27:24=ICHPMP 0x6
0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
// 12:09=TMDS_TERMADJ 0x9
// 23:20=LOADADJ 0x3
0x00000068 0x0f000000 0x0F000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xF
0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
// 31:24=LANE3_DP_LANE3 0x30
// 23:16=LANE2_DP_LANE0 0x37
// 15:08=LANE1_DP_LANE1 0x37
// 07:00=LANE0_DP_LANE2 0x37
0x00000148 0xffffffff 0x103E3E3E // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
// 31:24=LANE3_DP_LANE3 0x10
// 23:16=LANE2_DP_LANE0 0x3E
// 15:08=LANE1_DP_LANE1 0x3E
// 07:00=LANE0_DP_LANE2 0x3E
0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
// 22:22=TX_PU 0x1
// 15:08=TX_PU_VALUE 0x66
>;
};
};
prod_c_hdmi_300m_600m {
board {
prod = <
0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1
0x0000005c 0x0f000700 0x0A000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3
// 27:24=ICHPMP 0xA
0x00000060 0x00f01f00 0x00301700 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1
// 12:09=TMDS_TERMADJ 0xB
// 23:20=LOADADJ 0x3
0x00000068 0x0f000000 0x0E000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xE
0x00000138 0xffffffff 0x353E3E3E // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
// 31:24=LANE3_DP_LANE3 0x35
// 23:16=LANE2_DP_LANE0 0x3E
// 15:08=LANE1_DP_LANE1 0x3E
// 07:00=LANE0_DP_LANE2 0x3E
0x00000148 0xffffffff 0x023F3F3F // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
// 31:24=LANE3_DP_LANE3 0x02
// 23:16=LANE2_DP_LANE0 0x3F
// 15:08=LANE1_DP_LANE1 0x3F
// 07:00=LANE0_DP_LANE2 0x3F
0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0
// 22:22=TX_PU 0x1
// 15:08=TX_PU_VALUE 0x66
>;
};
};
};
};
};
};
tegra210-odin.dts
+5 -2
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@@ -2,6 +2,7 @@
/dts-v1/;
#include "tegra210-nx.dtsi"
#include "tegra210-odin-prods.dtsi"
/ {
model = "Nintendo Switch (2017)";
@@ -52,9 +53,11 @@
phy-names = "pcie-0";
status = "okay";
wifi { /* PCIE-0 (Port 1) */
wifi@1 { /* PCIE-0 (Port 1) */
status = "okay";
compatible = "brcm,bcm4356-fmac";
brcm,reset_on_wake;
reg = <1>;
reset-gpios = <TEGRA_GPIO(H, 1) GPIO_ACTIVE_LOW>;
};
};
};
tegra210b01-nx.dtsi
+1496 -281
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tegra210b01-vali.dts
+1478 -14
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