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Author SHA1 Message Date
Thomas Makin
1529c65700 xusb: bulk commit to split 2025-11-11 15:25:56 +00:00
Thomas Makin
d33417366f defconfig: updates 2025-11-11 15:24:14 +00:00
Thomas Makin
a1929690c5 dts: misc updates 2025-11-11 15:24:14 +00:00
Thomas Makin
50119fb291 phy: xusb-tegra210: use same supplies for b01 2025-11-11 15:24:14 +00:00
Thomas Makin
f615fff570 memory: tegra: populate dt subnodes 
Tegra210b01 uses tegra186-emc driver as emc clock is controlled by BPMP.
However, this driver expects emc as subnode of mc. Adjust Tegra30 mc
probe routine to populate subnodes.
 2025-11-11 15:24:13 +00:00
Thomas Makin
36202b6dc2 clk: tegra210b01: add plle 2025-11-11 15:15:10 +00:00
Rohith Seelaboyina
6c5e31fc75 phy: tegra: xusb: Add T210B01 support 
- Add T210b01 soc data for xusb_padctl driver
- Add uphy_management clock support
- Add PLL defaults programming

Bug 200340262

Change-Id: Ie5a685a49542221142a0a8e31e5a9ebb729a3035
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584421
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2025-11-11 15:15:10 +00:00
Thomas Makin
b33310ac0b pci: tegra: fix link_up invocation 2025-11-11 15:15:10 +00:00
Vidya Sagar
d1351e804e PCI: tegra: add PCI_REASSIGN_ALL_BUS flag 
adds PCI_REASSIGN_ALL_BUS pci flag so as to enable
re-assigning bus numbers (if there is any bridge device added
recently) during rescan.

Bug 200192107

Change-Id: Iffc02827a75dcb82f5e02b69e96e65b38a0b7cd6
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/1144609
(cherry picked from commit 26464cda2eff345548e3271f26b00ddcd79d9264)
Reviewed-on: http://git-master/r/1176833
(cherry picked from commit bf21f6959bbecc70b4dce07329e0deea32b41b67)
Reviewed-on: http://git-master/r/1141937
(cherry picked from commit 284d2e97ce311771808d8dbd75c861a95c16d031)
Reviewed-on: http://git-master/r/1210983
(cherry picked from commit ef83e7563eb0ce4dad493abba2c92d20a67f41ac)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2371135
(cherry picked from commit a43acb68398f7fd6208988684698b49962b3c6f9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407883
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Manikanta Maddireddy
3ac7bfa0f3 PCI: tegra: Add DT support to disable CLKREQ# control on PLLE 
Sometimes CLKREQ# pin connection might be missing on a platform. Add DT
support to disable CLKREQ# control on PLLE in driver. Platform device tree
can use this DT property to disable CLKREQ# control on PLLE. In kernel-5.9,
upstream device tree property "supports-clkreq" is used in place of
kernel-4.14 custom device tree property "nvidia,disable-clock-request".

bug 200420606

Change-Id: I6ac44bd99d090e158fa10e5e9b62d63e52563c8c
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786551
(cherry picked from commit 6870a94b48a4bbbe9df607802c7f7c1f61806b7b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407880
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Manikanta Maddireddy
f6a8256ac3 PCI: tegra: aspm DT support 
Squashed below k414 commits into single change.

PCI: tegra: Add DT support to disable per state aspm

Kernel config option provides choice to disable L0s & L1 or L1 substates
combinedly. Add DT support to disable each aspm state individually.

bug 200420606

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786548
(cherry picked from commit f3c5bcdc3ab8cadd3d24ea4d1a8e0aba7beea751)

PCI: tegra: Fix ASPM DT property parsing code

DT property "nvidia,disable-aspm-states" is part of PCIe port node.
Use correct of_node pointer to parse this property.

bug 200434876

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2383766
(cherry picked from commit 8dd957e9ecf29da4ba94471e3d74b2aef98a0643)

Change-Id: Iee1f573a103c0045d4f8f6606db13b47575b8cb9
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2408709
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-11-11 15:15:10 +00:00
Manikanta Maddireddy
3a39898f0d PCI: tegra: Bypass CLKREQ# control over PLLE 
When PCIe link is L2 CLKREQ# will be floating and this might interfere
with PLL power down. Bypass CLKREQ# control over PLLE when link is in L2.

bug 1356695
bug 200420606

Change-Id: I361db03df5f9a1a8d38bd9fb816d17fc4c64a9fc
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786565
(cherry picked from commit 69e79f42f65df70b0c76e62200aca40ed3972e3b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407877
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Manikanta Maddireddy
e3a136b7a7 PCI: tegra: Fix incorrect CLKREQ and PLLE programming 
CLKREQ_EN bit should be cleared to control REFCLK through CLKREQ# pin.
Enable PCIE2PLLE bit to control PLLE through clock clamp signal.
Program PADS2PLLE and PCIE2PLLE bits only if Tegra PCIe supports L1SS.

bug 200420606

Change-Id: I04cacf64fce8eed0f17bb632457ffcc9f052819d
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786550
(cherry picked from commit e71a64e47225b848c9b8a1d33e8c80a7bdb9d3cc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407876
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Vidya Sagar
00f1cf7c84 PCI: tegra: Fixups to avoid unnecessary wakeup from ASPM-L1.2 
sets CLKREQ asserted delay to a higher value to avoid
unnecessary wake up from L1.2.ENTRY state for Tegra210

bug 200420606

Change-Id: Iec2564bfd434897f0e50cd3f0ad6bc76aacc12e8
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786545
(cherry picked from commit d7785c1e6c98e33a85ba9487d3be6ab7e518a285)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407875
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Vidya Sagar
b011642f03 PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States 
Programs Port Common_Mode_Restore_Time and Port T_POWER_ON values
(from the L1 PM Substates Capabilities Register, PCIe 4.0r0.9, sec 7.8.3.2)
to get them reflected in ASPM-L1 Sub-States capability registers.
Also adjusts internal counter values according to 19.2 MHz clk_m value.

bug 200420606

Change-Id: Ie139255e522e4476fdfbe64aa6250d0293b7ae89
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786544
(cherry picked from commit 9ac6211e1a99583618945c86748214ccc33de463)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407874
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Manikanta Maddireddy
2b7a4256cc PCI: tegra: Configure L1 power save parameters 
Programmed bits of register RP_VEND_XP_PAD_PWRDN are defined as follows,

L1(bit[0]):
 This bit, when set, causes the analog pads to power down when we're in L1.
 When clear, the LTSSM still enters L1 as required, but the analog pads
 are left at full power.
DYNAMIC(bit[1]):
 This bit, when set, causes unused analog pads to power down after
 "Dynamic Link Width Re-negotiation" takes place.  When clear, all analog
 pads remain powered up, even those that are no longer being used after
 "Dynamic Link Width Re-negotiation" down-sizes the link.
DISABLED(bit[2]):
 This bit, when set, causes the analog pads to power down when we're in the
 DISABLED_DOWN state. When clear, the LTSSM still enters DISBLED_DOWN as
 required, but the analog pads are left at full power.
L1_CLKREQ(bit[15]):
 This bit, when set, causes the analog pads to power down to
 SLEEP_MODE_L1_REQ when clkreq signal is deasserted in L1.
 (NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1 needs to be set in order to power
 down pad in L1.)  Also, when clkreq is asserted in L1, ltssm will exit L1
 immediately. When clear, the clkreq signal doesn't affect the power
 management.
SLEEP_MODE_L1(bits[4:3]):
 It defines the 2-bit sleep-mode coding in the pad when LTSSM is in the L1
 state or DISABLED state.
SLEEP_MODE_DYNAMIC(bits[6:5]):
 It defines the 2-bit sleep-mode coding in the pad when the lane shut down
 due to dynamic link downsizing.
SLEEP_MODE_L1_CLKREQ(bits[17:16]):
 It defines the 2-bit sleep-mode coding when clkreq is deasserted in L1.
The 2-bit sleep-mode encoding is defined as:
 - L0 (0x0): Normal power-up mode
 - L1 (0x1): L1 power-down mode; Tx common mode on, Rx e-idle detect on
 - L1P (0x2): L1 power-down mode; Tx common mode off, Rx e-idle detect on
 - L1PP (0x3): L1 power-down mode; Tx common mode off, Rx e-idle detect off

bug 200420606

Change-Id: I74aa9c1460d882084b1ecccb9c0168dd667c9d84
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786547
(cherry picked from commit d7899c186f89ecf503812003b743adbae07c4cbe)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407873
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:10 +00:00
Vidya Sagar
dd0f08b513 PCI: tegra: Advertise ASPM L1 PM support 
Enables advertisement of ASPM-L1 support in capability
registers of applicable Tegra chips

bug 200420606

Change-Id: Ie5dbb3a262ca1c0c9cc59c91a8710bf6bd6a6900
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786543
(cherry picked from commit 7eedf2a02489b529374bc1ca95234be1f02b9119)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407872
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:09 +00:00
Manikanta Maddireddy
8e42e98420 PCI: tegra: Convert WRAP transactions to increment burst 
AFI module doesn't support WRAP transactions in Tegra. WRAP instructions
from CPU targeting PCIe BAR memory can cause data corruption. This can
happen if PCIe memory is marked as normal cacheable or GRE device.
Program mselect register to convert WRAP transactions to increment burst
for slave PCIe.

bug 200353330
bug 200420606

Change-Id: I867da85eb63332708bc294238e30ad99a71f345d
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786561
(cherry picked from commit b345cfae7b7633a3a52e0f2a659baf44feee1466)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407869
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:09 +00:00
Manikanta Maddireddy
44c081db2a PCI: tegra: Access endpoint config only if PCIe link is up 
Few endpoints like Wi-Fi supports power on/off and to leverage that
root port must support hot-plug and hot-unplug. Tegra PCIe doesn't
support hot-plug and hot-unplug, however it supports endpoint power
on/off feature as follows,
 - Power off sequence:
   - Transition of PCIe link to L2
   - Power off endpoint
   - Leave root port in power up state with the link in L2
 - Power on sequence:
   - Power on endpoint
   - Apply hot reset to get PCIe link up

PCIe client driver stops accessing PCIe endpoint config and BAR registers
after endpoint is powered off. However, software applications like x11
server or lspci can access endpoint config registers in which case
host controller raises "response decoding" errors. To avoid this scenario,
add PCIe link up check in config read and write callback functions before
accessing endpoint config registers.

Change-Id: I47653cb0b580c2b764cb0ad9c42deeb9c8823c58
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2371131
(cherry picked from commit be664bfdd901138222a8ea8bb17160a2fa9de04a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407866
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:09 +00:00
Manikanta Maddireddy
3db69fdfe2 PCI: tegra: Add PCIe support for tegra210b01 chip 
bug 200420606

Change-Id: I943e4ad90915332fbecc3ed9cb368d3f549925a6
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786562
(cherry picked from commit ef7328abda206df3b00364eeaeecc20103896326)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407885
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2025-11-11 15:15:09 +00:00
Thomas Makin
a248214f65 t210b01: sdmmc pinmuxing 2025-11-11 15:15:09 +00:00
Thomas Makin
6c26ccf6d2 tegra210b01: use bpmp for emc 
Make use of the existing tegra186-emc driver to handle emc
clocking and scaling via BPMP API instead of in kernel.

Downstream uses tables from emc and overrides the clock.
 2025-11-11 15:15:09 +00:00
Thomas Makin
94681aeae8 [WAR] core: don't loop 2025-11-11 15:15:09 +00:00
Thomas Makin
6f1f1abf26 [DEBUG] emc logging 2025-11-11 15:15:09 +00:00
Thomas Makin
6d44dc2607 typec: introduce bm92txx driver 
TODO: fix commit
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:09 +00:00
Thomas Makin
b6b5a56f88 memory: tegra186-emc: support t210b01 
Tegra210b01 uses Tegra186 style emc management, as in it is
offloaded to BPMP. This driver already implements this, so no
reason to shoehorn in elsewhere.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:09 +00:00
Thomas Makin
c6ca332037 nouveau: add tegra210b01 support 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:09 +00:00
Thomas Makin
963c5f5011 tegra210b01: do not enable venc 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:09 +00:00
Thomas Makin
0c1e29cf14 tegra-drm: add t210b01 dsi support 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Thomas Makin
0bb8fa8047 enable max77812 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
azkali
b9ed6706e1 panel: dsi-nx: Add dsi-nx panel driver 
dsi-nx is a new blanket driver for panels on the Nintendo Switch.
The Switch boots Linux via the "hekate" custom bootloader, which
performs panel initialization and passes panel info to kernel.

This driver is based on panel-jdi-lpm062m326a by SwitchR.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Thomas Makin
f005bd8b44 t210: add core dvfs floor/cap 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Thomas Makin
c818120483 tegra: dfll: forward-port 4.9 dfll 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Laxman Dewangan
77f7f06729 regulator: core: add API to get min/max voltage for rails 
Add API to get min/max rail voltage configured from platform for
given rails. This will help to set the pad voltage based on platform
specific power tree.

bug 200083043

Change-Id: I054734ca2a25b5c830525e27ab22e43534f67351
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/712001
(cherry picked from commit c0d1de0da091132d037e1bb32f2ee09b5c00369b)
Reviewed-on: http://git-master/r/1119836
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Alex Frid
4ba2917a97 clk: Add parent change notifications 
Added parent change notifications to be used when drivers behavior
depends on physical nature of the parent, not just clock rate it
supplies (e.g., selection of Tegra DFLL as CPU clock source changes
mechanism of voltage control even if the clock rate stays the same
as on PLL).

Bug 200269751

Change-Id: I617c94927ef437caf240efd91497b49ad6f5c39d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573111
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Alex Frid
13c3818949 clk: tegra: Add subtree change notifications 
Added PRE_SUBTREE_CHANGE and POST_SUBTREE_CHANGE that called before
and after rate change is propagated down the sub-tree rooted in clk.
This would allow children to be aware that next set rate operation
is triggered by downward rate propagation, rather than direct set rate
on a child clock.

Bug 200267979

Change-Id: I6f2acbeca7cead0ecd385dcb2e58ced32448e998
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
(cherry picked from commit 62f0d763fcb6c9d5bd9a373d22d802503ab0fdc5)
Reviewed-on: https://git-master.nvidia.com/r/1558143
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Thomas Makin
eeb92feb05 tegra: dfll: use tune1_low 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Jon Hunter
9448b31662 soc/tegra: update sppedo and chip rev handling 
- Make revisions consistent
- Enable T210B01 support
- Update speedo structs

soc/tegra: fuse: Add support for retrieving IDDQ information

Add helpers functions for retrieving IDDQ information which is used
by SYSEDP.

Bug 1811732

Change-Id: I889afecebc9b6d7c2085a528f5dfb58a095165ff
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: http://git-master/r/1255677

Conflicts:
	include/linux/tegra-fuse.h

soc: tegra: Don't confuse chip / speedo revisions

During T210 DVFS initialization SoC chip revision was incorrectly used
instead of speedo fuse revision to limit core maximum voltage. Fixed it
in this commit.

Bug 200269751
Bug 200277489

Change-Id: Ifadabb1840039f407d2abfd8b9a8782b865b5a13
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1302687
Reviewed-on: https://git-master.nvidia.com/r/1563340
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

soc: tegra: Fix for Automotive speedo/process ids

This fixes to derive correct speedo/process ids for
automotive skus(0x17 and 0x23).

Also display the sku info in hexadecimal format.

Bug 200258423

Change-Id: Ifab5f957983494fcffeb253f7fdda6b6062c56c5
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576315
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>

soc: fuse: Introduce T210b01 speedo IDs

Introduce T210b01 speedo ID initialization by implementing:

- Parse T210b01 speedo fuses programming revision from spare fuses
- T210b01 binning thresholds
- Detection of T210b01 SKUs

Bug 1906940

Change-Id: If7d168434c12b5e92250be608f9736fc80cc2886
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576317
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

soc/tegra: fuse: update speedo IDs for Tegra210

Bug 200255986

[ There's a merge conflict during the cherry-pick from Kernel 4.4
  to 4.9 becauase a later patch got merged first -- Nicolin ]

Change-Id: Iacf188f4cccea03d3a82f7ad18455c18681c506d
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: http://git-master/r/1262213
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 98a6b47e55b1e5754490420c1ca379793e3569d2)
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578888
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

soc: tegra: Update T210 sku info

- Populated sku info ucm field, and selected DVFS ids appropriately
- Made "a02" DVFS ids selection forward looking
  (applied to all A02+ revisions)
- Applied vcm31_sku to a02 parts (was a01 only), but limit it to
  0x17 sku fuses (was applied to 0x07 and 0x13 as well)
- Made always on personality a must for sku 0x8F

Bug 200269751

Change-Id: I85cbe2f1621c271640643aa2d203b9dac5b8c992
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1307422
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 9ffc1f1cc2cb588f440640921f77223a6baee280)
Reviewed-on: https://git-master.nvidia.com/r/1578889
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>

soc: tegra: Add support for T210 sku 0x1F

Bug 2059069

Change-Id: I7d20b6f1b889a18f23ae2fe6662d7b08e950154e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669017
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

clk: soc: tegra: Add support for T210b01 sku 0x87

Bug 2075533

Change-Id: I07433bd7139a5c845065a9a1d46f5f6e9559fbb5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669169
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

soc: tegra: Add usage mode UCM field to sku info

Bug 200269751
Bug 200277498
Bug 200340064

Change-Id: I8044b350587e2298ec1b705dd01fec5fc6d83379
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1307421
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563330
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

soc/tegra: add support for getting b01 rev

soc/tegra: adjust revision handling for t210 skus

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Alex Frid
b8a786039a clk: soc: tegra: Rename DFLL tune1 to tune1_low 
Renamed DFLL tune1 to tune1_low to be consistent with
tune0_low/tune0_high naming convention.

Bug 1967884

Change-Id: If23170305143b05c2918e04691c73fe13b777272
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576306
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:08 +00:00
Thomas Makin
7530eba983 arm64: t210b01: enable max77812 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:07 +00:00
Thomas Makin
19be22ef9a arm64: t210b01: add max77620 support 
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:07 +00:00
Thomas Makin
0ac6a10eaa arm64: t210: add initial support for nx 
The Nintendo Switch is a video game console based on the
Tegra X1 (T210) and X1+ (T210B01).

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:07 +00:00
Aaron Kling
40380c8c38 clk: tegra: dfll: add CVB tables for Tegra210B01 
To generate OPP tables for the soc

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:07 +00:00
Aaron Kling
31ecc0af39 drm/tegra: Create switch class for primary hdmi 
Change-Id: I353b1c5ad98bcd69b4827b0c74327511b4d8222d
 2025-11-11 15:15:07 +00:00
Faith Ekstrand
9f565ad57c nouveau: Use WC maps instead of uncached 2025-11-11 15:15:07 +00:00
kuyo chang
eb74f85a1f sched/deadline: Fix RT task potential starvation when expiry time passed 
[Symptom]
The fair server mechanism, which is intended to prevent fair starvation
when higher-priority tasks monopolize the CPU.
Specifically, RT tasks on the runqueue may not be scheduled as expected.

[Analysis]
---------
The log "sched: DL replenish lagged too much" triggered.

By memory dump of dl_server:
--------------
    curr = 0xFFFFFF80D6A0AC00 (
      dl_server = 0xFFFFFF83CD5B1470(
        dl_runtime = 0x02FAF080,
        dl_deadline = 0x3B9ACA00,
        dl_period = 0x3B9ACA00,
        dl_bw = 0xCCCC,
        dl_density = 0xCCCC,
        runtime = 0x02FAF080,
        deadline = 0x0000082031EB0E80,
        flags = 0x0,
        dl_throttled = 0x0,
        dl_yielded = 0x0,
        dl_non_contending = 0x0,
        dl_overrun = 0x0,
        dl_server = 0x1,
        dl_server_active = 0x1,
        dl_defer = 0x1,
        dl_defer_armed = 0x0,
        dl_defer_running = 0x1,
        dl_timer = (
          node = (
            expires = 0x000008199756E700),
          _softexpires = 0x000008199756E700,
          function = 0xFFFFFFDB9AF44D30 = dl_task_timer,
          base = 0xFFFFFF83CD5A12C0,
          state = 0x0,
          is_rel = 0x0,
          is_soft = 0x0,
    clock_update_flags = 0x4,
    clock = 0x000008204A496900,

- The timer expiration time (rq->curr->dl_server->dl_timer->expires)
  is already in the past, indicating the timer has expired.
- The timer state (rq->curr->dl_server->dl_timer->state) is 0.

[Suspected Root Cause]
--------------------
The relevant code flow in the throttle path of
update_curr_dl_se() as follows:

dequeue_dl_entity(dl_se, 0);                // the DL entity is dequeued

if (unlikely(is_dl_boosted(dl_se) || !start_dl_timer(dl_se))) {
    if (dl_server(dl_se))                   // timer registration fails
        enqueue_dl_entity(dl_se, ENQUEUE_REPLENISH);//enqueue immediately
    ...
}

The failure of `start_dl_timer` is caused by attempting to register a
timer with an expiration time that is already in the past. When this
situation persists, the code repeatedly re-enqueues the DL entity
without properly replenishing or restarting the timer, resulting in RT
task may not be scheduled as expected.

[Proposed Solution]:
------------------
Instead of immediately re-enqueuing the DL entity on timer registration
failure, this change ensures the DL entity is properly replenished and
the timer is restarted, preventing RT potential starvation.

Signed-off-by: kuyo chang <kuyo.chang@mediatek.com>
Closes: https://lore.kernel.org/CAMuHMdXn4z1pioTtBGMfQM0jsLviqS2jwysaWXpoLxWYoGa82w@mail.gmail.com
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2025-11-11 15:15:07 +00:00
Aaron Kling
8cf759f651 HACK: HID: usbhid: schedule a hid_reset() for -75 irq_in 
Copied from nvidia's downstream 3.10 kernel

Change-Id: Ifd017363927d249637444d1874aa0f680a48acc4
 2025-11-11 15:15:07 +00:00
Dmitry Osipenko
b39c839c7f partitions: Support NVIDIA Tegra Partition Table 
All NVIDIA Tegra devices use a special partition table format for the
internal storage partitioning.  Most of Tegra devices have GPT partition
in addition to TegraPT, but some older Android consumer-grade devices do
not or GPT is placed in a wrong sector, and thus, the TegraPT is needed
in order to support these devices properly by the upstream kernel. This
patch adds support for NVIDIA Tegra Partition Table format that is used
at least by all NVIDIA Tegra20 and Tegra30 devices.

Tested-by: Nils Östlund <nils@naltan.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
 2025-11-11 15:15:07 +00:00
Dmitry Osipenko
fa5772ad55 mmc: Support non-standard gpt_sector cmdline parameter 
Add support for the gpt_sector cmdline parameter which will be used
for looking up GPT entry on internal eMMC storage of NVIDIA Tegra20+
devices. This parameter is used by a stock downstream bootloader of
Android devices.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
 2025-11-11 15:15:07 +00:00
Aaron Kling
abeb79e303 ARM: tegra: Use io memcpy to write to iram 
Kasan crashes the kernel trying to check boundaries when using the
normal memcpy.

Change-Id: I093741be1ff73e3d5cefc41eeab719bb67b4c3d0
 2025-11-11 15:15:07 +00:00
Vishwaroop A
234fadb4f4 drivers: spi: add support for prod framework 
Add support for prod framework in spi core

Change-Id: Iaa70f8b3bb3efb3a3b13aa7f2d43562b9fff9e51
Signed-off-by: Vishwaroop A <va@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Abhilash G <abhilashg@nvidia.com>
 2025-11-11 15:15:07 +00:00
Shardar Shariff Md
201b0a8131 i2c: core: skip prod-settings node during i2c device registration 
skip prod-settings node during i2c device registration as
prod-settings is not i2c device

Change-Id: Iaeff454cf17ffd68a7273aeb8afcce6e2c8894c6
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Abhilash G <abhilashg@nvidia.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
06ba67e49f Revert "fbdev: Make registered_fb[] private to fbmem.c" 
This reverts commit 5727dcfd84.

Change-Id: I724a29c438f62d504a386795e59685e5b6c1c3a1
 2025-11-11 15:15:06 +00:00
David Ng
d842dcc46b arm64: Add 32-bit sigcontext definition to uapi signcontext.h 
The arm64 uapi sigcontext.h can be included by 32-bit userspace
modules.  Since arm and arm64 sigcontext definition are not
compatible, add arm sigcontext definition to arm64 sigcontext.h.

Signed-off-by: David Ng <dave@codeaurora.org>
Signed-off-by: Divya Sharma <c_shard@codeaurora.org>
Signed-off-by: Anh Nguyen <anguyen@codeaurora.org>
Change-Id: Iaed58045fd345e4ca66e8a6981c6b4f80c4bdfca
 2025-11-11 15:15:06 +00:00
Aaron Kling
39ed1555a2 arm64: Disable some cpu feature sanity checks 
On t186, these differ between denver and a57

Change-Id: I65b1515ef9f5d42b0da1dfa605e51536eb902ca5
 2025-11-11 15:15:06 +00:00
Aaron Kling
97f611dcd2 arm64: tegra: Enable mmu on Tegra194 display controllers 
These use a separate mmu instance compared to everything else currently
enabled for the soc.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
361e8f46a4 Revert "arm64: tegra: Disable ISO SMMU for Tegra194" 
This reverts commit ebea268ea5.

Mmu is now being enabled for the display controllers.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
8c79250f5e drm/tegra: Enable cmu for Tegra186 and Tegra194 
Without the cmu, nvdisplay will display colors that are notably darker
than intended. The vendor bootloader and the downstream display driver
enable the cmu and sets a sRGB table. Loading that table here results in
the intended colors.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Svyatoslav Ryhel
eb6a966d67 ARM: tegra: add device-tree for Xiaomi Mi Pad (A0101) 
The Mi Pad is a tablet computer based on Nvidia Tegra K1 SoC which
originally ran the Android operating system. The Mi Pad has a 7.9" IPS
display with 1536 x 2048 (324 ppi) resolution. 2 GB of RAM and 16/64 GB of
internal memory that can be supplemented with a microSDXC card giving up
to 128 GB of additional storage.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
 2025-11-11 15:15:06 +00:00
Svyatoslav Ryhel
afe22b10e3 drm/panel: Add Sharp LQ079L1SX01 support 
This panel requires dual-channel mode. The device accepts video-mode data
on 8 lanes and will therefore need a dual-channel DSI controller. The two
interfaces that make up this device need to be instantiated in the
controllers that gang up to provide the dual-channel DSI host.

Change-Id: I5ca26fe0cdcdf40620b8a9e7801962c66b0be2b5
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
bc31a9092d arm64: tegra: Add CPU OPP tables for Tegra194 
Add OPP table and interconnects property to scale DDR frequency with
CPU frequency for better performance. Each operating point entry of
the OPP table has CPU freq to per MC channel bandwidth mapping.
One table is added for each cluster even though the table data is
same because the bandwidth request is per cluster. This is done
because OPP framework creates a single icc path and hence single
bandwidth request if the table is marked as 'opp-shared' and shared
among all clusters. For us, the OPP table data is same but the MC
Client ID argument to interconnects property is different for each
cluster. So, having per cluster table makes different icc path for
each cluster and helps to make per cluster BW requests.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
99260f415c arm64: tegra: Add CPU OPP tables for Tegra186 
Add OPP table and interconnects property to scale DDR frequency with
CPU frequency for better performance. Each operating point entry of
the OPP table has CPU freq to per MC channel bandwidth mapping. One
table is added for each cluster because the different cpu types have
different scaling curves.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
2825a74d67 memory: tegra194: Support icc scaling 
Add Interconnect framework support to dynamically set the DRAM
bandwidth from different clients. The MC driver is added as an ICC
provider and the EMC is already a provider.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
da694360e3 memory: tegra186: Support icc scaling 
Add Interconnect framework support to dynamically set the DRAM
bandwidth from different clients. The MC driver is added as an ICC
provider and the EMC is already a provider.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:06 +00:00
Aaron Kling
1141b0ace0 memory: tegra186-emc: Support non-bpmp icc scaling 
This adds support for dynamic frequency scaling of external memory on
devices with bpmp firmware that does not support bwmgr.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
b6c886e75e cpufreq: tegra186: add OPP support and set bandwidth 
Add support to use OPP table from DT in Tegra186 cpufreq driver.
Tegra SoC's receive the frequency lookup table (LUT) from BPMP-FW.
Cross check the OPP's present in DT against the LUT from BPMP-FW
and enable only those DT OPP's which are present in LUT also.

The OPP table in DT has CPU Frequency to bandwidth mapping where
the bandwidth value is per MC channel. DRAM bandwidth depends on the
number of MC channels which can vary as per the boot configuration.
This per channel bandwidth from OPP table will be later converted by
MC driver to final bandwidth value by multiplying with number of
channels before being handled in the EMC driver.

If OPP table is not present in DT, then use the LUT from BPMP-FW
directy as the CPU frequency table and not do the DRAM frequency
scaling which is same as the current behavior.

Change-Id: I11a37b2bd7d6b7a7ee9d270ecd0430430a407d65
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
8b4602a837 dt-bindings: tegra: Add ICC IDs for dummy memory clients for Tegra194 
Add ICC IDs for dummy software clients representing CCPLEX clusters.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
13da52bbd1 dt-bindings: tegra: Add ICC IDs for dummy memory clients for Tegra186 
Add ICC IDs for dummy software clients representing CCPLEX clusters.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
25d30a45af arm64: tegra: Add OPP tables on Tegra210 
This adds OPP tables for actmon and emc, enabling dynamic frequency
scaling for ram.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
9401bac24d arm64: tegra: Add interconnect properties to Tegra210 device-tree 
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
8daf4ee46f arm64: tegra: tegra210: Add actmon 
This enables the action monitor to facilitate dynamic frequency scaling.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
343e60550d soc: tegra: fuse: speedo-tegra210: Add soc speedo 2 
The Jetson Nano series of modules only have 2 emc table entries,
different from other soc sku's. As the emc driver uses the soc speedo to
populate the emc opp tables, add a new speedo id to uniquely identify
this.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
091bffaf7e memory: tegra210: Support interconnect framework 
This makes mc and emc interconnect providers and allows for dynamic
memory clock scaling.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
50699fa40a memory: tegra210: Use bindings for client ids 
Since the related binding is being added, use that for the client ids
instead of hardcoded magic numbers.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
e95129a161 dt-bindings: memory: tegra210: Add memory client IDs 
Each memory client has unique hardware ID, add these IDs.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
b75fae54c9 soc: tegra: fuse: speedo-tegra210: Update speedo ids 
Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
code supports 11 ids and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align skus with the downstream list.

The Tegra210 CVB tables were added in the first referenced fixes commit.
Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.

Fixes: 2b2dbc2f94 ("clk: tegra: dfll: add CVB tables for Tegra210")
Fixes: 579db6e5d9 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
16e7bf68b1 drm/nouveau: Support devfreq for Tegra 
Using pmu counters for usage stats. This enables dynamic frequency
scaling on all of the currently supported Tegra gpus.

The register offsets are valid for gk20a, gm20b, gp10b, and gv11b. If
support is added for ga10b, this will need rearchitected.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Aaron Kling
06ba4c8e65 drm/nouveau: Support reclocking on gp10b 
Starting with Tegra186, gpu clock handling is done by the bpmp and there
is little to be done by the kernel. The only thing necessary for
reclocking is to set the gpcclk to the desired rate and the bpmp handles
the rest. The pstate list is based on the downstream driver generates.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:05 +00:00
Ard Biesheuvel
21164c1535 efistub: Lower default log level 
Change-Id: I4d4f6e5a93669ca2a99a79f5f760ced2f000a3c2
 2025-11-11 15:15:04 +00:00
Aaron Kling
cc70760341 WIP: drm/tegra: Add devfreq support to media engines 
TODO: Better limit frequency count

Change-Id: If86527dc4985d9afd9d510430d1f3c137ca7f220
 2025-11-11 15:15:04 +00:00
Aaron Kling
1ef6885568 drm/tegra: Support Tegra186+ in NVJPG 
Change-Id: I7bf2c200d4ad9690c4f21a004ecc6dea8065f93e
 2025-11-11 15:15:04 +00:00
Aaron Kling
b66348d05a drm/tegra: Add NVENC driver 
Add support for booting and using NVENC on Tegra210+ to the Host1x
and TegraDRM drivers. This driver only supports the new TegraDRM uAPI.

Change-Id: I07e1386604d7638ba43381c3f289688d7c5cb12b
 2025-11-11 15:15:04 +00:00
Aaron Kling
77a33fa2f7 arm64: tegra: Enable NVDEC and NVENC on Tegra210 
The other engines are already enabled, finish filling out the media
engine nodes and power domains.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:04 +00:00
Diogo Ivo
5de5a7b521 arm64: tegra: Add NVJPG node for Tegra210 platforms 
The Tegra X1 chip contains a NVJPG accelerator capable of
encoding/decoding JPEG files in hardware. Complete its DT node
and enable it.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
 2025-11-11 15:15:04 +00:00
Diogo Ivo
bd9ce31a9a arm64: tegra: Add Tegra210 NVJPG power-domain node 
Add the NVJPG power-domain node in order to support the NVJPG
accelerator in Tegra210 platforms.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
 2025-11-11 15:15:04 +00:00
Diogo Ivo
17c9b0eac7 drm/tegra: Add NVJPG driver 
Add support for booting and using NVJPG on Tegra210 to the Host1x
and TegraDRM drivers. This driver only supports the new TegraDRM uAPI.

Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
 2025-11-11 15:15:04 +00:00
Mikko Perttunen
796fc53eb5 gpu: host1x: Add MLOCK recovery for rest of engines 
Add class IDs / MLOCKs for MLOCK recovery for rest of engines
present on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-4-cyndis@kapsi.fi
 2025-11-11 15:15:04 +00:00
Mikko Perttunen
9490ce4c50 gpu: host1x: Complete stream ID entry tables 
These tables contain fixed values to program the host1x hardware
with, so fill in the missing entries.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-3-cyndis@kapsi.fi
 2025-11-11 15:15:04 +00:00
Aaron Kling
18f020320f arm64: tegra: Add support for NVIDIA Shield TV Pro 2019 
Add initial device-tree support for NVIDIA Shield TV Pro 2019 (a.k.a
MDarcy) based up the Tegra210B01 SoC with 3 GiB of LPDDR4 RAM.

This is very basic, intended for checking initial Tegra210B01 support.
More complete support for the device will be added later.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:04 +00:00
Aaron Kling
52dedf079c arm64: tegra: Add Tegra210B01 support 
Also known as Tegra X1+, the Tegra210B01 has higher CPU and GPU clocks
than the original Tegra210.

Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This is derived from the Tegra210 dtsi, as they
share a lot.

Co-authored-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:04 +00:00
Aaron Kling
e8eeb3dd61 arm64: tegra: Add BPMP node for Tegra210 
The Tegra210 soc supports bpmp offload for power management among other
things. This was considered insecure partway through the soc's lifecycle
and support was removed in the bootloader. However, Tegra210B01 returned
to using the bpmp. Plus old bootloaders on the original Tegra210 still
work with the existing driver. So add the node to the common Tegra210
soc dtsi, but disabled by default.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:04 +00:00
Thomas Makin
99c38e06b6 memory: tegra186-emc: support Tegra210B01 
Tegra210B01 uses Tegra186 style emc management, as in it is
offloaded to BPMP. This driver already implements this, so no
reason to shoehorn in elsewhere.

Signed-off-by: Thomas Makin <halorocker89@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
d5fb30731c clk: tegra: Add Tegra210B01 support 
This is based on the downstream Nvidia 5.10 kernel. That version was
semi-integrated into the Tegra210 clock driver. Looking at the existing
Tegra210 support, it made more sense to make this a fully independent
driver, so that is implemented here.

Co-authored-by: Thomas Makin <halorocker89@gmail.com>
Change-Id: Iadee08494eff823155e228063bee8f7a280cbcef
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
07ed2fb23b thermal: tegra: Add Tegra210B01 Support 
Add Tegra210B01 SOC_THERM configuration

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
47ce25d2c5 usb: gadget: tegra-xudc: Add Tegra210B01 Support 
It doesn't need some of the workarounds that the original Tegra210 does.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
dff5ed4c9a usb: xhci: tegra: Add Tegra210B01 support 
This uses a different firmware, but is otherwise compatible with
Tegra210.
 2025-11-11 15:15:03 +00:00
Aaron Kling
cce56005b7 phy: tegra: xusb: Add Tegra201B01 Support 
It has slightly different lanes compared to the original Tegra210.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Azkali Manad
16de65709b soc/tegra: pmc: Add Tegra210B01 support 
Co-authored-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Azkali Manad <a.ffcc7@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
fab2cba2df dt-bindings: clock: tegra: Document Tegra210B01 
* Add the compatible string for Tegra210B01 clock and reset
* Add Tegra210B01 specific clock bindings

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Venkat Reddy Talla
ec0d70298b regulator: max77812: add max77812 regulator driver 
Adding regulator driver for MAX77812 device which is
used in t210b01 based platforms for powering cpu,gpu
and dram io

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
412e4e172e power: supply: bq24190_charger: Support usb role switching 
Change-Id: Ia1e650f15ae55bb0972612b378d093a20d8a8a98
 2025-11-11 15:15:03 +00:00
Aaron Kling
e24dd8dceb power: supply: bq24190_charger: Export current regulator 
Change-Id: I3958896da66740d503aec5ed93e14a7d743a43ac
 2025-11-11 15:15:03 +00:00
Aaron Kling
5145442e1e power: bq24190: support bq24193 
Change-Id: I66f665af1913a6bf92fa28f10afd9bae845d8867
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
a5c7fa6a90 memory: tegra210-emc: Support Device Tree EMC Tables 
These are generated by the Tegra210 Android bootloader. This is similar
to the Tegra124 handling, so the support is based on that and modified
to match Tegra210 by referencing the downstream Nvidia 4.9 kernel.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:03 +00:00
Aaron Kling
ffe7238665 arm64: tegra: Add EMC timings to P2180 
These entries are imported from the downstream Nvidia Linux4Tegra
kernel. They are expected to be updated with the trained values by the
bootloader. This is done by the Nvidia Android bootloader, which is
different from the handling by the Nvidia Linux bootloader which places
these values in a reserved memory location. P2180 is supported by both
bootloaders, so lets support initializing emc on both.

It should be noted that the bootloader will not create these nodes in
the kernel dtb if they do not exist. It will only set in place existing
properties.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Svyatoslav Ryhel
ed8702254a ARM: tegra: Add DSI-A and DSI-B nodes on Tegra124 
Bind DSI devices and MIPI calibration.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Link: https://lore.kernel.org/r/20250226105615.61087-6-clamor95@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
07b857abe5 gpio: palmas: Allow building as a module 
The driver works fine as a module, so allowing building as such. This
adds an exit handler to support module unload.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
49a0bd6704 arm64: tegra: Add Tegra186 pin controllers 
Add the device tree nodes for the MAIN and AON pin controllers found on
the Tegra186 family of SoCs.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
c1548709ab pinctrl: tegra: Add Tegra186 pinmux driver 
This is based on Nvidia's downstream 5.10 driver, rewritten to match the
mainline Tegra194 pinmux driver.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
6aed033f53 dt-bindings: gpio: tegra186: Add gpio-ranges 
Add optional gpio-ranges property.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
dec2ac6aff dt-bindings: pinctrl: Document Tegra186 pin controllers 
Tegra186 contains two pin controllers. Document their compatible strings
and describe the list of pins and functions that they provide.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
78b406880f cpuidle: tegra: Export tegra_cpuidle_pcie_irqs_in_use 
Add export for tegra_cpuidle_pcie_irqs_in_use() so that drivers like
pci-tegra can be loaded as a module.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
b70766325d irqdomain: Export irq_domain_free_irqs 
Export irq_domain_free_irqs() to allow PCI/MSI drivers like pci-tegra to
be built as a module.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
65aa274d15 arm64: tegra: Enable HDA controller on P2894 
The HDA controller can be used for audio playback over HDMI.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
b715036d9c arm64: tegra: Enable HDMI on P2894 
Add regulators and enable the host1x nodes necessary to attain video
output via hdmi.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
d271e4e311 WIP: arm64: tegra: Enable APE on P2894 
TODO: Drop usused external codecs

Enable support for audio-graph based sound card on P2894. Required I/O
interfaces are enabled.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:02 +00:00
Aaron Kling
a4ac4e98a5 arm64: tegra: Enable DFLL clock on P2894 
Add pinmux for PWM-based DFLL support.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
b603d035b1 arm64: tegra: Enable PWM fan on P2894 
This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devices are similar, so using the same configuration.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
d66de87b6b arm64: tegra: Enable PCIe on P2894 
The p2894 product has a PCIe ethernet adapter

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
9e4030a477 WIP: arm64: tegra: Enable XUSB controller on P2894 
TODO: Correct otg connector for full size A port

Enable the XUSB controller on P2894. One of the USB 3.0 lanes goes to a
switchable USB-A port, while the second USB 3.0 lane supports the normal
USB-A port.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
7a04b9bc51 arm64: tegra: Add Wifi node for P2894 
The p2894 product has a BCM4354 module with wifi on sdio.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
0455ca103d arm64: tegra: Wire up Bluetooth for P2894 
The p2894 product contains a BCM4354 module with bluetooth on uart.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
169c7531b2 arm64: tegra: Enable gpu on P2894 
This adds the gpu regulator and enables the gpu node.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
6c03bcbfb3 arm64: tegra: Add support for NVIDIA Shield TV 2015 
Add initial device-tree support for NVIDIA Shield TV (a.k.a. Foster)
based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. It is based on P2571.

Change-Id: Ideeeb15f835ebf7f7617d3989908d245aff4b316
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
e6e75e0cc4 arm64: tegra: Enable HDA controller on P2571 
The HDA controller can be used for audio playback over HDMI.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
c5fc330ec4 arm64: tegra: Enable HDMI on P2571 
Add regulators and enable the host1x nodes necessary to attain video
output via hdmi.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
7816b529c5 WIP: arm64: tegra: Enable APE on P2571 
TODO: Drop unused external codec references

Enable support for audio-graph based sound card on P2571. Required I/O
interfaces are enabled.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
c01c8b6b14 arm64: tegra: Enable DFLL clock on P2571 
Add pinmux for PWM-based DFLL support.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
db2ded908b arm64: tegra: Enable XUSB controller on P2571 
Enable the XUSB controller on P2571. One of the USB 3.0 lanes goes to an
internal ethernet interface, while two other USB 3.0 lanes support the
the USB-A receptacles on the I/O board.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:01 +00:00
Aaron Kling
fca2d7886c arm64: tegra: Enable PWM fan on P2571 
This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devices are similar, so using the same configuration.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
0af726c616 arm64: tegra: Add Wifi node for P2530 
The p2530 som has a BCM4354 module with wifi on sdio.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
e99e8cac91 arm64: tegra: Wire up Bluetooth for P2530 
The p2530 som contains a BCM4354 module with bluetooth on uart.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
381fdbc5a5 arm64: tegra: Enable gpu on P2530 
This adds the gpu regulator and enables the gpu node.

Change-Id: I8a0f580fa600d8f37fb3fa497cf657abf2905d5f
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
888868a8e9 arm64: tegra: Add PMIC support on P2530 
Based on the p2180 pmic config, modified to match p2530

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
7a7de6ab35 arm64: tegra: Add P2530 SC7 timings 
Same as 106f7a0 and 47b4e12. Without these, the pmc driver locks up
during boot.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
3549513b0d arm64: tegra: Enable bluetooth on P3310 
The p3310 som contains a BCM4354 module with bluetooth on uart.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
30d99c8fd7 arm64: tegra: Enable wifi on P3310 
The p3310 som has a BCM4354 module with wifi on sdio.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
3d7de18141 arm64: tegra: Fix ldo5 voltage on P3310 
This appears to be a typo. The voltage input to the wireless module is
expected to be 1.8V-3.3V, per the downstream device tree.

Fixes: 02df3f03a8 ("arm64: tegra: Add initial power tree for P3310")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
6f188fca32 arm64: tegra: Add NVIDIA Jetson Nano 2GB Developer Kit support 
This devkit is very similar to P3450, except it has less ram, no display
port, and only 3 usb host ports. Derive from P3450 and disable the
hardware that is unavailable.

Gpio PA6 is used to control the hdmi power rail and needs to be on for
hotplug detect to work. This is mapped to the 3.3V usb hub on P3450.
That usb rail is not used here, so delete the regulator to avoid
conflicts.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
21041900eb arm64: tegra: Set usb micro-b port to otg mode on P3450 
The usb micro-b port on p3450 is capable of otg and doesn't need
hardcoded to peripheral. No other supported tegra device is set up like
this, so align for consistency.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
fbb227f786 arm64: tegra: Remove otg id gpio from Jetson TX2 NX 
The p3509 carrier board does not connect the id gpio. Prior to this, the
gpio role switch driver could not detect the mode of the otg port.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
13f4490c9d arm64: tegra: Add DMA properties for Tegra186 and Tegra194 UARTs 
Adding the missing dmas and dma-names properties which are required
for uart when using with the Tegra HSUART driver.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:15:00 +00:00
Aaron Kling
a6c8c18494 arm64: tegra: Enable PWM fan on the Jetson TX2 Devkit 
This is based on the existing configuration of the Jetson TX2 NX devkit.
The fan and thermal characteristics of the two devkits are similar, so
using the same configuration.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
d904038ff4 arm64: tegra: p3310: Explicitly enable GPU 
The gpu node originally was explicitly left disabled as it was expected
for the bootloader to enable it. However, this is only done in u-boot.
If u-boot is not in the boot chain, this will never be enabled. Other
Tegra186 devices already explicitly enable the gpu, so make p3310 match.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
0005ac0f5e arm64: tegra: Enable PWM fan on the Jetson TX1 Devkit 
This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devkits are similar, so using the same configuration.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
f25ac04f34 arm64: tegra: p2180: Explicitly enable GPU 
The gpu node originally was explicitly left disabled as it was expected
for the bootloader to enable it. However, this is only done in u-boot.
If u-boot is not in the boot chain, this will never be enabled. Other
Tegra210 devices already explicitly enable the gpu, so make p2180 match.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
0fe7d9f01b cpufreq: tegra186: Initialize all cores to max frequencies 
During initialization, the EDVD_COREx_VOLT_FREQ registers for some cores
are still at reset values and not reflecting the actual frequency. This
causes get calls to fail. Set all cores to their respective max
frequency during probe to initialize the registers to working values.

Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
d6fddffbe3 cpufreq: tegra186: Set target frequency for all cpus in policy 
The original commit set all cores in a cluster to a shared policy, but
did not update set_target to apply a frequency change to all cores for
the policy. This caused most cores to remain stuck at their boot
frequency.

Fixes: be4ae8c19492 ("cpufreq: tegra186: Share policy per cluster")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
ce444f4987 cpufreq: tegra186: Share policy per cluster 
This functionally brings tegra186 in line with tegra210 and tegra194,
sharing a cpufreq policy between all cores in a cluster.

Reviewed-by: Sumit Gupta <sumitg@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
 2025-11-11 15:14:59 +00:00
Aaron Kling
666dc7bf47 cpufreq: tegra124: Allow building as a module 
This requires four changes:
* Using the cpufreq-dt register helper to establish a hard dependency
  for depmod to track
* Adding a remove routine to remove the cpufreq-dt device
* Adding a exit routine to handle cleaning up the driver
* Populate module license

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
939d7a1bbd cpufreq: dt: Add register helper 
Cpufreq-dt currently exports no functions. This means that drivers that
are based on cpufreq-dt have no way of establishing a depmod dependency
on it. This helper allows that link.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
8b643632f0 cpufreq: Export disable_cpufreq() 
This is used by the tegra124-cpufreq driver.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
2df944f323 arm64: tegra: Bump #address-cells and #size-cells on Tegra186 
This was done for Tegra194 and Tegra234 in 2838cfd, but Tegra186 was not
part of that change. The same reasoning for that commit also applies to
Tegra186, plus keeping the archs as close to each other as possible makes
it easier to compare between them and support features concurrently.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
7ee206935e arm64: tegra: Wire up cec to devkits 
This enables hdmi cec and routes it to the hdmi port on all supported
Tegra210, Tegra186, and Tegra194 devkits.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
9c56b5cd14 arm64: tegra: Add CEC controller on Tegra210 
The CEC controller found on Tegra210 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-3-b6337b66ccad@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
3eb493ef4f arm64: tegra: Add fallback cec compatibles 
The tegra_cec driver only declares support up to Tegra210 and will not
declare support for Tegra186 or Tegra194. Thus list a fallback
compatible for these archs to tegra210-cec as they work as-is with the
existing driver.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:59 +00:00
Aaron Kling
bca7de3c9e mfd: max77620: Allow building as a module 
The driver works fine as a module, so allowing building as such.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
 2025-11-11 15:14:58 +00:00
Vidya Sagar
1064acd8e0 PCI: tegra194: Add support for PCIe RC & EP in Tegra234 Platforms 
Add PCIe RC & EP support for Tegra234 Platforms.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
 2025-11-11 15:14:58 +00:00
Lars-Peter Clausen
5ca021df5f gpio: tegra186: Allow to enable driver on Tegra234 
Support for Tegra234 was added to the tegra186 driver in 1db9b241bb (
"gpio: tegra186: Add support for Tegra234"). But the driver is not
selectable on Tegra234. Update the Kconfig entry to allow the driver to be
enabled on Tegra234.

Enable the driver by default on Tegra 234 as well, similar to the other
platforms it supports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241113162939.886242-1-lars@metafoo.de
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
 2025-11-11 15:14:58 +00:00
Lars-Peter Clausen
adf95f6f2d phy: tegra194: p2u: Allow to enable driver on Tegra234 
Commit de60266825 ("phy: tegra: Add PCIe PIPE2UPHY support for Tegra234")
add support for Tegra234 to the tegra194-p2u PHY driver. But the driver is
currently not selectable when Tegra234 SoC support is enabled.

Update the Kconfig entry to allow the driver to be built when support the
Tegra234 SoC is enabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2025-11-11 15:14:58 +00:00
173 changed files with 82286 additions and 1048 deletions
Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
View File

@@ -32,6 +32,7 @@ properties:
- nvidia,tegra30-car
- nvidia,tegra114-car
- nvidia,tegra210-car
- nvidia,tegra210b01-car
reg:
maxItems: 1

3
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
View File

@@ -111,6 +111,9 @@ properties:
gpio-controller: true
gpio-ranges:
maxItems: 1
"#gpio-cells":
description: |
Indicates how many cells are used in a consumer's GPIO specifier. In the

285
Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml Normal file
View File

@@ -0,0 +1,285 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra186-pinmux
- nvidia,tegra186-pinmux-aon
reg:
items:
- description: pinmux registers
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra-pinmux-common.yaml
unevaluatedProperties: false
properties:
nvidia,function:
enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1,
displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3,
extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7,
i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1,
nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3,
sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1,
spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte,
uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
wdt ]
nvidia,pull: true
nvidia,tristate: true
nvidia,schmitt: true
nvidia,enable-input: true
nvidia,open-drain: true
nvidia,lock: true
nvidia,drive-type: true
nvidia,io-hv: true
required:
- nvidia,pins
additionalProperties: false
allOf:
- if:
properties:
compatible:
const: nvidia,tegra186-pinmux
then:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
additionalProperties:
properties:
nvidia,pins:
description: An array of strings. Each string contains the name
of a pin or group. Valid values for these names are listed
below.
items:
enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1,
pex_wake_n_pa2, pex_l1_rst_n_pa3,
pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5,
pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1,
uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4,
gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0,
dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3,
dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6,
sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2,
sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5,
eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2,
eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5,
eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0,
eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3,
eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0,
sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3,
sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0,
gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3,
bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6,
gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2,
gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5,
gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0,
dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3,
aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6,
gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0,
gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3,
usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6,
gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1,
dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4,
dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1,
gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5,
gpio_cam7_pn6, extperiph1_clk_po0,
extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3,
dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2,
gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5,
gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1,
directdc1_out0_pq2, directdc1_out1_pq3,
directdc1_out2_pq4, directdc1_out3_pq5,
qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2,
qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5,
uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2,
uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1,
uart2_rts_px2, uart2_cts_px3, uart5_tx_px4,
uart5_rx_px5, uart5_rts_px6, uart5_cts_px7,
gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2,
gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5,
gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1,
dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2,
dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp,
sdmmc3_comp, qspi_comp,
# drive groups
drive_gpio_aud3_pk0, drive_gpio_aud2_pj7,
drive_gpio_aud1_pj6, drive_gpio_aud0_pj5,
drive_aud_mclk_pj4, drive_dap1_fs_pj3,
drive_dap1_din_pj2, drive_dap1_dout_pj1,
drive_dap1_sclk_pj0, drive_dmic1_clk_pm1,
drive_dmic1_dat_pm0, drive_dmic2_dat_pm2,
drive_dmic2_clk_pm3, drive_dmic4_dat_pm4,
drive_dmic4_clk_pm5, drive_dap4_fs_pcc3,
drive_dap4_din_pcc2, drive_dap4_dout_pcc1,
drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1,
drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3,
drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0,
drive_gpio_cam2_pn1, drive_gpio_cam3_pn2,
drive_gpio_cam4_pn3, drive_gpio_cam5_pn4,
drive_gpio_cam6_pn5, drive_gpio_cam7_pn6,
drive_dap2_din_pc3, drive_dap2_dout_pc2,
drive_dap2_fs_pc4, drive_dap2_sclk_pc1,
drive_uart4_cts_pb3, drive_uart4_rts_pb2,
drive_uart4_rx_pb1, drive_uart4_tx_pb0,
drive_gpio_wan4_pc0, drive_gpio_wan3_pb6,
drive_gpio_wan2_pb5, drive_gpio_wan1_pb4,
drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6,
drive_uart1_cts_pt3, drive_uart1_rts_pt2,
drive_uart1_rx_pt1, drive_uart1_tx_pt0,
drive_directdc1_out3_pq5, drive_directdc1_out2_pq4,
drive_directdc1_out1_pq3, drive_directdc1_out0_pq2,
drive_directdc1_in_pq1, drive_directdc1_clk_pq0,
drive_gpio_pq0_pi0, drive_gpio_pq1_pi1,
drive_gpio_pq2_pi2, drive_gpio_pq3_pi3,
drive_gpio_pq4_pi4, drive_gpio_pq5_pi5,
drive_gpio_pq6_pi6, drive_gpio_pq7_pi7,
drive_gpio_edp2_pp5, drive_gpio_edp3_pp6,
drive_gpio_edp0_pp3, drive_gpio_edp1_pp4,
drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1,
drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6,
drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4,
drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1,
drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5,
drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1,
drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4,
drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2,
drive_eqos_td3_pe4, drive_eqos_td2_pe3,
drive_eqos_td1_pe2, drive_eqos_td0_pe1,
drive_eqos_rd3_pf1, drive_eqos_rd2_pf0,
drive_eqos_rd1_pe7, drive_eqos_mdio_pf4,
drive_eqos_rd0_pe6, drive_eqos_mdc_pf5,
drive_eqos_txc_pe0, drive_eqos_rxc_pf3,
drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2,
drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4,
drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2,
drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0,
drive_qspi_io3_pr4, drive_qspi_io2_pr3,
drive_qspi_io1_pr2, drive_qspi_io0_pr1,
drive_qspi_sck_pr0, drive_qspi_cs_n_pr5,
drive_gpio_wan8_ph3, drive_gpio_wan7_ph2,
drive_gpio_wan6_ph1, drive_gpio_wan5_ph0,
drive_uart2_tx_px0, drive_uart2_rx_px1,
drive_uart2_rts_px2, drive_uart2_cts_px3,
drive_uart5_rx_px5, drive_uart5_tx_px4,
drive_uart5_rts_px6, drive_uart5_cts_px7,
drive_gpio_mdm1_py0, drive_gpio_mdm2_py1,
drive_gpio_mdm3_py2, drive_gpio_mdm4_py3,
drive_gpio_mdm5_py4, drive_gpio_mdm6_py5,
drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4,
drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6,
drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1,
drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2,
drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5,
drive_gp_pwm7_pl7, drive_gp_pwm6_pl6,
drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0,
drive_directdc_comp, drive_sdmmc1_comp,
drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk,
drive_sdmmc4_cmd, drive_sdmmc4_dqs,
drive_sdmmc4_dat7, drive_sdmmc4_dat6,
drive_sdmmc4_dat5, drive_sdmmc4_dat4,
drive_sdmmc4_dat3, drive_sdmmc4_dat2,
drive_sdmmc4_dat1, drive_sdmmc4_dat0,
drive_qspi_comp ]
- if:
properties:
compatible:
const: nvidia,tegra186-pinmux-aon
then:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
additionalProperties:
properties:
nvidia,pins:
items:
enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2,
safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0,
gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3,
gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0,
gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3,
gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6,
gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1,
uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4,
uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7,
can1_dout_pz0, can1_din_pz1, can0_dout_pz2,
can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1,
can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4,
can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7,
gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2,
power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2,
gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int,
soc_pwr_req, clk_32k_in,
# drive groups
drive_touch_clk_pee2, drive_uart3_cts_pw5,
drive_uart3_rts_pw4, drive_uart3_rx_pw3,
drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1,
drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7,
drive_uart7_tx_pw6, drive_gpio_sen0_pv0,
drive_gpio_sen1_pv1, drive_gpio_sen2_pv2,
drive_gpio_sen3_pv3, drive_gpio_sen4_pv4,
drive_gpio_sen5_pv5, drive_gpio_sen6_pv6,
drive_gpio_sen7_pv7, drive_gpio_sen8_pee0,
drive_gpio_sen9_pee1, drive_can_gpio7_paa7,
drive_can1_dout_pz0, drive_can1_din_pz1,
drive_can0_dout_pz2, drive_can0_din_pz3,
drive_can_gpio0_paa0, drive_can_gpio1_paa1,
drive_can_gpio2_paa2, drive_can_gpio3_paa3,
drive_can_gpio4_paa4, drive_can_gpio5_paa5,
drive_can_gpio6_paa6, drive_gpio_sw1_pff1,
drive_gpio_sw2_pff2, drive_gpio_sw3_pff3,
drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int,
drive_safe_state_ps3, drive_vcomp_alert_ps4,
drive_soc_pwr_req, drive_batt_oc_ps2,
drive_clk_32k_in, drive_power_on_pff0,
drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1,
drive_gpio_dis0_pu0, drive_gpio_dis1_pu1,
drive_gpio_dis2_pu2, drive_gpio_dis3_pu3,
drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ]
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@2430000 {
compatible = "nvidia,tegra186-pinmux";
reg = <0x2430000 0x15000>;
pinctrl-names = "jetson_io";
pinctrl-0 = <&jetson_io_pinmux>;
jetson_io_pinmux: pinmux {
hdr40-pin7 {
nvidia,pins = "aud_mclk_pj4";
nvidia,function = "aud";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
...

50
Documentation/devicetree/bindings/regulator/max77812-regulator.txt Normal file
View File

@@ -0,0 +1,50 @@
MAX77812 voltage regulator
Required properties:
- compatible: "maxim,max77812-regulator"
- reg: I2C slave address
Regulators subnode:
MAX77812 supports four regulators, regulators should be described under
regualtors subnode.
Optional properties:
-maxim,ramp-up-slew-rate: to configure slew rate during regulator
voltage ramp up time
-maxim,ramp-down-slew-rate: to configre slew rate during regulator
voltage ramp down time
-maxim,soft-start-slew-rate: to configure slew rate during regulator
enable time
-maxim,shutdown-slew-rate: to configure slew rate during regulator
disable time or shutdown time
Each regulator is defined using the standard binding for regulators.
Example:
max77812@1b {
compatible = "maxim,max77812-regulator";
reg = <0x1b>;
regulators {
m1vout {
regulator-name = "mvout1";
regulator-min-microvolt = <250000>;
regulator-max-microvolt = <1525000>;
regulator-boot-on;
regulator-always-on;
regulator-init-mode = <REGULATOR_MODE_NORMAL>;
};
m2vout {
regulator-name = "mvout2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <250000>;
regulator-max-microvolt = <1525000>;
regulator-init-mode = <REGULATOR_MODE_NORMAL>;
};
};
};

3
arch/arm/boot/dts/nvidia/Makefile
View File

@@ -11,7 +11,8 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-nyan-big.dtb \
tegra124-nyan-big-fhd.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
tegra124-venice2.dtb \
tegra124-xiaomi-mocha.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-tf101.dtb \

2514
arch/arm/boot/dts/nvidia/tegra124-xiaomi-mocha.dts Normal file
View File

File diff suppressed because it is too large Load Diff

40
arch/arm/boot/dts/nvidia/tegra124.dtsi
View File

@@ -165,6 +165,22 @@
status = "disabled";
};
dsia: dsi@54300000 {
compatible = "nvidia,tegra124-dsi";
reg = <0x0 0x54300000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA124_CLK_DSIA>,
<&tegra_car TEGRA124_CLK_DSIALP>,
<&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
vic@54340000 {
compatible = "nvidia,tegra124-vic";
reg = <0x0 0x54340000 0x0 0x00040000>;
@@ -177,6 +193,22 @@
iommus = <&mc TEGRA_SWGROUP_VIC>;
};
dsib: dsi@54400000 {
compatible = "nvidia,tegra124-dsi";
reg = <0x0 0x54400000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA124_CLK_DSIB>,
<&tegra_car TEGRA124_CLK_DSIBLP>,
<&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 82>;
reset-names = "dsi";
nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
sor@54540000 {
compatible = "nvidia,tegra124-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
@@ -938,6 +970,14 @@
};
};
mipi: mipi@700e3000 {
compatible = "nvidia,tegra124-mipi";
reg = <0x0 0x700e3000 0x0 0x100>;
clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
#nvidia,mipi-calibrate-cells = <1>;
};
dfll: clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */

2
arch/arm/mach-tegra/reset.c
View File

@@ -63,7 +63,7 @@ static void __init tegra_cpu_reset_handler_enable(void)
BUG_ON(is_enabled);
BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
memcpy_toio(iram_base, (void *)__tegra_cpu_reset_handler_start,
tegra_cpu_reset_handler_size);
err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);

54
arch/arm/mach-tegra/tegra.c
View File

@@ -27,7 +27,9 @@
#include <linux/firmware/trusted_foundations.h>
#include <soc/tegra/bootdata.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/partition.h>
#include <soc/tegra/pmc.h>
#include <asm/firmware.h>
@@ -61,9 +63,61 @@ u32 tegra_uart_config[3] = {
0,
};
static void __init tegra_boot_config_table_init(void)
{
struct tegra30_boot_config_table __iomem *t30_bct;
struct tegra20_boot_config_table __iomem *t20_bct;
struct tegra20_boot_info_table __iomem *t20_bit;
u32 iram_end = TEGRA_IRAM_BASE + TEGRA_IRAM_SIZE;
u32 iram_start = TEGRA_IRAM_BASE;
u32 pt_addr, pt_size, bct_size;
t20_bit = IO_ADDRESS(TEGRA_IRAM_BASE);
if (of_machine_is_compatible("nvidia,tegra20")) {
bct_size = sizeof(*t20_bct);
if (t20_bit->bct_size != bct_size ||
t20_bit->bct_ptr < iram_start ||
t20_bit->bct_ptr > iram_end - bct_size)
return;
t20_bct = IO_ADDRESS(t20_bit->bct_ptr);
if (t20_bct->boot_data_version != TEGRA_BOOTDATA_VERSION_T20)
return;
pt_addr = t20_bct->partition_table_logical_sector_address;
pt_size = t20_bct->partition_table_num_logical_sectors;
} else if (of_machine_is_compatible("nvidia,tegra30")) {
bct_size = sizeof(*t30_bct);
if (t20_bit->bct_size != bct_size ||
t20_bit->bct_ptr < iram_start ||
t20_bit->bct_ptr > iram_end - bct_size)
return;
t30_bct = IO_ADDRESS(t20_bit->bct_ptr);
if (t30_bct->boot_data_version != TEGRA_BOOTDATA_VERSION_T30)
return;
pt_addr = t30_bct->partition_table_logical_sector_address;
pt_size = t30_bct->partition_table_num_logical_sectors;
} else {
return;
}
pr_info("%s: BCT found in IRAM\n", __func__);
tegra_partition_table_setup(pt_addr, pt_size);
}
static void __init tegra_init_early(void)
{
of_register_trusted_foundations();
tegra_boot_config_table_init();
tegra_cpu_reset_handler_init();
call_firmware_op(l2x0_init);
}

11
arch/arm64/boot/dts/nvidia/Makefile
View File

@@ -2,7 +2,10 @@
# Enables support for device-tree overlays
DTC_FLAGS_tegra210-p2371-2180 := -@
DTC_FLAGS_tegra210-p2571-0930 := -@
DTC_FLAGS_tegra210-p2571-0932 := -@
DTC_FLAGS_tegra210-p3450-0000 := -@
DTC_FLAGS_tegra210-p3541-0000 := -@
DTC_FLAGS_tegra186-p2771-0000 := -@
DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@
DTC_FLAGS_tegra194-p2972-0000 := -@
@@ -17,9 +20,17 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571-0930.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571-0932.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3541-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-odin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210b01-p2894-0050-a08.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210b01-odin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210b01-vali.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210b01-fric.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb

115
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@@ -2394,6 +2394,12 @@
phy-names = "usb2-0";
};
cec@3960000 {
status = "okay";
hdmi-phandle = <&sor1>;
};
i2c@c250000 {
/* carrier board ID EEPROM */
eeprom@57 {
@@ -2409,6 +2415,10 @@
};
};
pwm@c340000 {
status = "okay";
};
pcie@10003000 {
status = "okay";
@@ -2508,6 +2518,16 @@
};
};
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm4 0 45334>;
fan-supply = <&vdd_fan>;
/* cooling level (0, 1, 2, 3) - pwm inverted */
cooling-levels = <255 128 64 0>;
#cooling-cells = <2>;
};
vdd_sd: regulator-vdd-sd {
compatible = "regulator-fixed";
regulator-name = "SD_CARD_SW_PWR";
@@ -2556,6 +2576,17 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_fan: regulator-vdd-fan {
compatible = "regulator-fixed";
regulator-name = "VDD_FAN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&exp1 4 GPIO_ACTIVE_LOW>;
vin-supply = <&vdd_5v0_sys>;
};
sound {
compatible = "nvidia,tegra186-audio-graph-card";
status = "okay";
@@ -2621,4 +2652,88 @@
label = "NVIDIA Jetson TX2 APE";
};
thermal-zones {
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
trips {
cpu_trip_critical: critical {
temperature = <96500>;
hysteresis = <0>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <79000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active: active {
temperature = <62000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_passive: passive {
temperature = <45000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map0 {
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_critical>;
};
map1 {
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_hot>;
};
map2 {
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active>;
};
map3 {
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
};
};
};
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
trips {
aux_alert0: critical {
temperature = <90000>;
hysteresis = <0>;
type = "critical";
};
};
};
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
trips {
gpu_alert0: critical {
temperature = <99000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};

62
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@@ -19,7 +19,9 @@
i2c7 = "/i2c@31e0000";
mmc0 = "/mmc@3460000";
mmc1 = "/mmc@3400000";
mmc2 = "/mmc@3440000";
serial0 = &uarta;
serial3 = &uartd;
};
chosen {
@@ -32,6 +34,24 @@
reg = <0x0 0x80000000 0x2 0x00000000>;
};
gpio@2200000 {
wifi-enable {
gpio-hog;
gpios = <TEGRA186_MAIN_GPIO(N, 0) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "wifi-enable";
};
};
gpio@c2f0000 {
wifi-wake-ap {
gpio-hog;
gpios = <TEGRA186_AON_GPIO(FF, 3) GPIO_ACTIVE_HIGH>;
input;
label = "wifi-wake-ap";
};
};
ethernet@2490000 {
status = "okay";
@@ -61,9 +81,29 @@
};
serial@3100000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
serial@3130000 {
/delete-property/ reg-shift;
status = "okay";
compatible = "nvidia,tegra30-hsuart";
reset-names = "serial";
bluetooth {
compatible = "brcm,bcm43540-bt";
device-wakeup-gpios = <&gpio TEGRA186_MAIN_GPIO(Y, 4) GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio TEGRA186_MAIN_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio_aon>;
interrupts = <TEGRA186_AON_GPIO(FF, 4) IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wakeup";
vbat-supply = <&vdd_5v0_sys>;
vddio-supply = <&vdd_1v8>;
};
};
i2c@3160000 {
status = "okay";
@@ -145,7 +185,21 @@
/* SDMMC3 (SDIO) */
mmc@3440000 {
status = "okay";
bus-width = <4>;
non-removable;
power-gpios = <&gpio TEGRA186_MAIN_GPIO(N, 0) GPIO_ACTIVE_HIGH>;
vqmmc-supply = <&vddio_sdmmc3>;
vmmc-supply = <&vdd_1v8>;
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio_aon>;
interrupts = <TEGRA186_AON_GPIO(FF, 3) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
/* SDMMC4 (eMMC) */
@@ -191,6 +245,10 @@
nvidia,invert-interrupt;
};
gpu@17000000 {
status = "okay";
};
bpmp {
i2c {
status = "okay";
@@ -342,8 +400,8 @@
vddio_sdmmc3: ldo5 {
regulator-name = "VDDIO_SDMMC3_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vdd_hdmi_1v05: ldo7 {

9
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts
View File

@@ -549,6 +549,8 @@
};
serial@3100000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
@@ -669,7 +671,6 @@
vbus-gpios = <&gpio
TEGRA186_MAIN_GPIO(L, 4)
GPIO_ACTIVE_LOW>;
id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
};
@@ -712,6 +713,12 @@
phy-names = "usb2-0";
};
cec@3960000 {
status = "okay";
hdmi-phandle = <&sor1>;
};
hsp@3c00000 {
status = "okay";
};

479
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@@ -36,6 +36,12 @@
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pinmux 0 0 140>;
};
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra186-pinmux";
reg = <0x0 0x2430000 0x0 0x15000>;
};
ethernet@2490000 {
@@ -124,28 +130,28 @@
<&bpmp TEGRA186_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900000 0x0 0x02900000 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
status = "disabled";
tegra_ahub: ahub@2900800 {
compatible = "nvidia,tegra186-ahub";
reg = <0x02900800 0x800>;
reg = <0x0 0x02900800 0x0 0x800>;
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900800 0x02900800 0x11800>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
status = "disabled";
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901000 0x100>;
reg = <0x0 0x2901000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S1>,
<&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -159,7 +165,7 @@
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901100 0x100>;
reg = <0x0 0x2901100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S2>,
<&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -173,7 +179,7 @@
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901200 0x100>;
reg = <0x0 0x2901200 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S3>,
<&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -187,7 +193,7 @@
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901300 0x100>;
reg = <0x0 0x2901300 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S4>,
<&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -201,7 +207,7 @@
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901400 0x100>;
reg = <0x0 0x2901400 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S5>,
<&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -215,7 +221,7 @@
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901500 0x100>;
reg = <0x0 0x2901500 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S6>,
<&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -229,7 +235,7 @@
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902000 0x200>;
reg = <0x0 0x2902000 0x0 0x200>;
sound-name-prefix = "SFC1";
status = "disabled";
};
@@ -237,7 +243,7 @@
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902200 0x200>;
reg = <0x0 0x2902200 0x0 0x200>;
sound-name-prefix = "SFC2";
status = "disabled";
};
@@ -245,7 +251,7 @@
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902400 0x200>;
reg = <0x0 0x2902400 0x0 0x200>;
sound-name-prefix = "SFC3";
status = "disabled";
};
@@ -253,7 +259,7 @@
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902600 0x200>;
reg = <0x0 0x2902600 0x0 0x200>;
sound-name-prefix = "SFC4";
status = "disabled";
};
@@ -261,7 +267,7 @@
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x2903000 0x100>;
reg = <0x0 0x2903000 0x0 0x100>;
sound-name-prefix = "AMX1";
status = "disabled";
};
@@ -269,7 +275,7 @@
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x2903100 0x100>;
reg = <0x0 0x2903100 0x0 0x100>;
sound-name-prefix = "AMX2";
status = "disabled";
};
@@ -277,7 +283,7 @@
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x2903200 0x100>;
reg = <0x0 0x2903200 0x0 0x100>;
sound-name-prefix = "AMX3";
status = "disabled";
};
@@ -285,7 +291,7 @@
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x2903300 0x100>;
reg = <0x0 0x2903300 0x0 0x100>;
sound-name-prefix = "AMX4";
status = "disabled";
};
@@ -293,7 +299,7 @@
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x2903800 0x100>;
reg = <0x0 0x2903800 0x0 0x100>;
sound-name-prefix = "ADX1";
status = "disabled";
};
@@ -301,7 +307,7 @@
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x2903900 0x100>;
reg = <0x0 0x2903900 0x0 0x100>;
sound-name-prefix = "ADX2";
status = "disabled";
};
@@ -309,7 +315,7 @@
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x2903a00 0x100>;
reg = <0x0 0x2903a00 0x0 0x100>;
sound-name-prefix = "ADX3";
status = "disabled";
};
@@ -317,14 +323,14 @@
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x2903b00 0x100>;
reg = <0x0 0x2903b00 0x0 0x100>;
sound-name-prefix = "ADX4";
status = "disabled";
};
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra210-dmic";
reg = <0x2904000 0x100>;
reg = <0x0 0x2904000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
@@ -336,7 +342,7 @@
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra210-dmic";
reg = <0x2904100 0x100>;
reg = <0x0 0x2904100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
@@ -348,7 +354,7 @@
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra210-dmic";
reg = <0x2904200 0x100>;
reg = <0x0 0x2904200 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
@@ -360,7 +366,7 @@
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra210-dmic";
reg = <0x2904300 0x100>;
reg = <0x0 0x2904300 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
@@ -372,7 +378,7 @@
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra186-dspk";
reg = <0x2905000 0x100>;
reg = <0x0 0x2905000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
@@ -384,7 +390,7 @@
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra186-dspk";
reg = <0x2905100 0x100>;
reg = <0x0 0x2905100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
@@ -397,9 +403,9 @@
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra186-ope",
"nvidia,tegra210-ope";
reg = <0x2908000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2908000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sound-name-prefix = "OPE1";
status = "disabled";
@@ -407,20 +413,20 @@
equalizer@2908100 {
compatible = "nvidia,tegra186-peq",
"nvidia,tegra210-peq";
reg = <0x2908100 0x100>;
reg = <0x0 0x2908100 0x0 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra186-mbdrc",
"nvidia,tegra210-mbdrc";
reg = <0x2908200 0x200>;
reg = <0x0 0x2908200 0x0 0x200>;
};
};
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
reg = <0x290a000 0x200>;
reg = <0x0 0x290a000 0x0 0x200>;
sound-name-prefix = "MVC1";
status = "disabled";
};
@@ -428,7 +434,7 @@
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
reg = <0x290a200 0x200>;
reg = <0x0 0x290a200 0x0 0x200>;
sound-name-prefix = "MVC2";
status = "disabled";
};
@@ -436,14 +442,14 @@
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra186-amixer",
"nvidia,tegra210-amixer";
reg = <0x290bb00 0x800>;
reg = <0x0 0x290bb00 0x0 0x800>;
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra186-admaif";
reg = <0x0290f000 0x1000>;
reg = <0x0 0x0290f000 0x0 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
@@ -489,7 +495,7 @@
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra186-asrc";
reg = <0x2910000 0x2000>;
reg = <0x0 0x2910000 0x0 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
@@ -497,7 +503,7 @@
adma: dma-controller@2930000 {
compatible = "nvidia,tegra186-adma";
reg = <0x02930000 0x20000>;
reg = <0x0 0x02930000 0x0 0x20000>;
interrupt-parent = <&agic>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -542,8 +548,8 @@
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x02a41000 0x1000>,
<0x02a42000 0x2000>;
reg = <0x0 0x02a41000 0x0 0x1000>,
<0x0 0x02a42000 0x0 0x2000>;
interrupts = <GIC_SPI 145
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA186_CLK_APE>;
@@ -612,6 +618,8 @@
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTA>;
resets = <&bpmp TEGRA186_RESET_UARTA>;
dmas = <&gpcdma 8>, <&gpcdma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -624,6 +632,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTB>;
reset-names = "serial";
dmas = <&gpcdma 9>, <&gpcdma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -636,6 +646,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTD>;
reset-names = "serial";
dmas = <&gpcdma 19>, <&gpcdma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -648,6 +660,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTE>;
reset-names = "serial";
dmas = <&gpcdma 20>, <&gpcdma 20>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -660,6 +674,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTF>;
reset-names = "serial";
dmas = <&gpcdma 12>, <&gpcdma 12>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1183,7 +1199,7 @@
};
cec@3960000 {
compatible = "nvidia,tegra186-cec";
compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec";
reg = <0x0 0x03960000 0x0 0x10000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_CEC>;
@@ -1239,6 +1255,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTC>;
reset-names = "serial";
dmas = <&gpcdma 3>, <&gpcdma 3>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1251,6 +1269,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA186_RESET_UARTG>;
reset-names = "serial";
dmas = <&gpcdma 2>, <&gpcdma 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1272,10 +1292,16 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux_aon 0 0 47>;
interrupt-controller;
#interrupt-cells = <2>;
};
pinmux_aon: pinmux@c300000 {
compatible = "nvidia,tegra186-pinmux-aon";
reg = <0x0 0xc300000 0x0 0x4000>;
};
pwm4: pwm@c340000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0xc340000 0x0 0x10000>;
@@ -1511,10 +1537,10 @@
resets = <&bpmp TEGRA186_RESET_HOST1X>;
reset-names = "host1x";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x15000000 0x0 0x15000000 0x01000000>;
ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
@@ -1533,7 +1559,7 @@
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x15040000 0x10000>;
reg = <0x0 0x15040000 0x0 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
<&bpmp TEGRA186_CLK_PLLDP>;
@@ -1567,7 +1593,7 @@
display-hub@15200000 {
compatible = "nvidia,tegra186-display";
reg = <0x15200000 0x00040000>;
reg = <0x0 0x15200000 0x0 0x00040000>;
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
@@ -1585,14 +1611,14 @@
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x15200000 0x15200000 0x40000>;
ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
display@15200000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15200000 0x10000>;
reg = <0x0 0x15200000 0x0 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
clock-names = "dc";
@@ -1611,7 +1637,7 @@
display@15210000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15210000 0x10000>;
reg = <0x0 0x15210000 0x0 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
clock-names = "dc";
@@ -1630,7 +1656,7 @@
display@15220000 {
compatible = "nvidia,tegra186-dc";
reg = <0x15220000 0x10000>;
reg = <0x0 0x15220000 0x0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
clock-names = "dc";
@@ -1650,7 +1676,7 @@
dsia: dsi@15300000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15300000 0x10000>;
reg = <0x0 0x15300000 0x0 0x10000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSI>,
<&bpmp TEGRA186_CLK_DSIA_LP>,
@@ -1665,7 +1691,7 @@
vic@15340000 {
compatible = "nvidia,tegra186-vic";
reg = <0x15340000 0x40000>;
reg = <0x0 0x15340000 0x0 0x40000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_VIC>;
clock-names = "vic";
@@ -1681,7 +1707,7 @@
nvjpg@15380000 {
compatible = "nvidia,tegra186-nvjpg";
reg = <0x15380000 0x40000>;
reg = <0x0 0x15380000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA186_RESET_NVJPG>;
@@ -1696,7 +1722,7 @@
dsib: dsi@15400000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15400000 0x10000>;
reg = <0x0 0x15400000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSIB>,
<&bpmp TEGRA186_CLK_DSIB_LP>,
@@ -1711,7 +1737,7 @@
nvdec@15480000 {
compatible = "nvidia,tegra186-nvdec";
reg = <0x15480000 0x40000>;
reg = <0x0 0x15480000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&bpmp TEGRA186_RESET_NVDEC>;
@@ -1727,7 +1753,7 @@
nvenc@154c0000 {
compatible = "nvidia,tegra186-nvenc";
reg = <0x154c0000 0x40000>;
reg = <0x0 0x154c0000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA186_RESET_NVENC>;
@@ -1742,7 +1768,7 @@
sor0: sor@15540000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15540000 0x10000>;
reg = <0x0 0x15540000 0x0 0x10000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SOR0>,
<&bpmp TEGRA186_CLK_SOR0_OUT>,
@@ -1766,7 +1792,7 @@
sor1: sor@15580000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15580000 0x10000>;
reg = <0x0 0x15580000 0x0 0x10000>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SOR1>,
<&bpmp TEGRA186_CLK_SOR1_OUT>,
@@ -1790,7 +1816,7 @@
dpaux: dpaux@155c0000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x155c0000 0x10000>;
reg = <0x0 0x155c0000 0x0 0x10000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DPAUX>,
<&bpmp TEGRA186_CLK_PLLDP>;
@@ -1824,7 +1850,7 @@
padctl@15880000 {
compatible = "nvidia,tegra186-dsi-padctl";
reg = <0x15880000 0x10000>;
reg = <0x0 0x15880000 0x0 0x10000>;
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
status = "disabled";
@@ -1832,7 +1858,7 @@
dsic: dsi@15900000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15900000 0x10000>;
reg = <0x0 0x15900000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSIC>,
<&bpmp TEGRA186_CLK_DSIC_LP>,
@@ -1847,7 +1873,7 @@
dsid: dsi@15940000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15940000 0x10000>;
reg = <0x0 0x15940000 0x0 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSID>,
<&bpmp TEGRA186_CLK_DSID_LP>,
@@ -1941,6 +1967,8 @@
denver_0: cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
operating-points-v2 = <&dnv_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -1954,6 +1982,8 @@
denver_1: cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
operating-points-v2 = <&dnv_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -1967,6 +1997,8 @@
ca57_0: cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
operating-points-v2 = <&a57_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -1980,6 +2012,8 @@
ca57_1: cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
operating-points-v2 = <&a57_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -1993,6 +2027,8 @@
ca57_2: cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
operating-points-v2 = <&a57_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -2006,6 +2042,8 @@
ca57_3: cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
operating-points-v2 = <&a57_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -2180,4 +2218,309 @@
interrupt-parent = <&gic>;
always-on;
};
dnv_opp_tbl: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp-998400000 {
opp-hz = /bits/ 64 <998400000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1152000000 {
opp-hz = /bits/ 64 <1152000000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1305600000 {
opp-hz = /bits/ 64 <1305600000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1459200000 {
opp-hz = /bits/ 64 <1459200000>;
opp-peak-kBps = <3200000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1536000000 {
opp-hz = /bits/ 64 <1536000000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1689600000 {
opp-hz = /bits/ 64 <1689600000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-peak-kBps = <3732000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3732000>;
};
};
a57_opp_tbl: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
opp-921600000 {
opp-hz = /bits/ 64 <921600000>;
opp-peak-kBps = <816000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
opp-998400000 {
opp-hz = /bits/ 64 <998400000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1152000000 {
opp-hz = /bits/ 64 <1152000000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1305600000 {
opp-hz = /bits/ 64 <1305600000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1459200000 {
opp-hz = /bits/ 64 <1459200000>;
opp-peak-kBps = <3200000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1536000000 {
opp-hz = /bits/ 64 <1536000000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1689600000 {
opp-hz = /bits/ 64 <1689600000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-peak-kBps = <3732000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3732000>;
};
};
};

2
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View File

@@ -104,6 +104,8 @@
};
serial@3110000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};

6
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
View File

@@ -2121,6 +2121,12 @@
phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
};
cec@3960000 {
status = "okay";
hdmi-phandle = <&sor2>;
};
i2c@c240000 {
typec@8 {
compatible = "cypress,cypd4226";

6
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
View File

@@ -2174,6 +2174,12 @@
phy-names = "usb2-1", "usb2-2", "usb3-2";
};
cec@3960000 {
status = "okay";
hdmi-phandle = <&sor1>;
};
host1x@13e00000 {
display-hub@15200000 {
status = "okay";

2
arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
View File

@@ -78,6 +78,8 @@
};
serial@3100000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};

662
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@@ -747,6 +747,8 @@
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTA>;
resets = <&bpmp TEGRA194_RESET_UARTA>;
dmas = <&gpcdma 8>, <&gpcdma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -757,6 +759,8 @@
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTB>;
resets = <&bpmp TEGRA194_RESET_UARTB>;
dmas = <&gpcdma 9>, <&gpcdma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -769,6 +773,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTD>;
reset-names = "serial";
dmas = <&gpcdma 19>, <&gpcdma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -781,6 +787,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTE>;
reset-names = "serial";
dmas = <&gpcdma 20>, <&gpcdma 20>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -793,6 +801,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTF>;
reset-names = "serial";
dmas = <&gpcdma 12>, <&gpcdma 12>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -820,6 +830,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTH>;
reset-names = "serial";
dmas = <&gpcdma 13>, <&gpcdma 13>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1339,7 +1351,7 @@
};
cec@3960000 {
compatible = "nvidia,tegra194-cec";
compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec";
reg = <0x0 0x03960000 0x0 0x10000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_CEC>;
@@ -1619,6 +1631,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTC>;
reset-names = "serial";
dmas = <&gpcdma 3>, <&gpcdma 3>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1631,6 +1645,8 @@
clock-names = "serial";
resets = <&bpmp TEGRA194_RESET_UARTG>;
reset-names = "serial";
dmas = <&gpcdma 2>, <&gpcdma 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1730,7 +1746,7 @@
status = "okay";
};
iommu@10000000 {
smmu_iso: iommu@10000000 {
compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
reg = <0x0 0x10000000 0x0 0x800000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
@@ -1803,7 +1819,7 @@
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
status = "disabled";
status = "okay";
};
smmu: iommu@12000000 {
@@ -1971,6 +1987,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <0>;
@@ -1989,6 +2006,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <1>;
@@ -2007,6 +2025,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <2>;
@@ -2025,6 +2044,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <3>;
@@ -2886,6 +2906,8 @@
device_type = "cpu";
reg = <0x000>;
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2900,6 +2922,8 @@
device_type = "cpu";
reg = <0x001>;
enable-method = "psci";
operating-points-v2 = <&cl0_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2914,6 +2938,8 @@
device_type = "cpu";
reg = <0x100>;
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2928,6 +2954,8 @@
device_type = "cpu";
reg = <0x101>;
enable-method = "psci";
operating-points-v2 = <&cl1_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2942,6 +2970,8 @@
device_type = "cpu";
reg = <0x200>;
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2956,6 +2986,8 @@
device_type = "cpu";
reg = <0x201>;
enable-method = "psci";
operating-points-v2 = <&cl2_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2970,6 +3002,8 @@
device_type = "cpu";
reg = <0x300>;
enable-method = "psci";
operating-points-v2 = <&cl3_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER3 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -2984,6 +3018,8 @@
device_type = "cpu";
reg = <0x301>;
enable-method = "psci";
operating-points-v2 = <&cl3_opp_tbl>;
interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER3 &emc>;
i-cache-size = <131072>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -3177,4 +3213,624 @@
interrupt-parent = <&gic>;
always-on;
};
cl0_opp_tbl: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1907200000 {
opp-hz = /bits/ 64 <1907200000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <4266000>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <4266000>;
};
opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <4266000>;
};
};
cl1_opp_tbl: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1907200000 {
opp-hz = /bits/ 64 <1907200000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <4266000>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <4266000>;
};
opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <4266000>;
};
};
cl2_opp_tbl: opp-table-cluster2 {
compatible = "operating-points-v2";
opp-shared;
opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1907200000 {
opp-hz = /bits/ 64 <1907200000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <4266000>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <4266000>;
};
opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <4266000>;
};
};
cl3_opp_tbl: opp-table-cluster3 {
compatible = "operating-points-v2";
opp-shared;
opp-115200000 {
opp-hz = /bits/ 64 <115200000>;
opp-peak-kBps = <816000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1600000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <1600000>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1600000>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1600000>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1600000>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3200000>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <3200000>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
opp-1907200000 {
opp-hz = /bits/ 64 <1907200000>;
opp-peak-kBps = <3200000>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <4266000>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <4266000>;
};
opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <4266000>;
};
};
};

969
arch/arm64/boot/dts/nvidia/tegra210-nx.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/mfd/max77620.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/tegra-pmc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210.dtsi"
/ {
aliases {
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c5 = "/i2c@7000d000";
rtc0 = "/i2c@7000d000/max77620@3c";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
};
chosen {
bootargs = "root=/dev/mmcblk0p2 rw rootwait fbcon=rotate:3 printk.synchronous=1 loglevel=4 console=fb0 console=ttyGS0 earlycon";
stdout-path = "serial1:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
vdd-cpu-supply = <&cpu_max_reg>;
};
idle-states {
cpu-sleep {
status = "okay";
};
};
};
gpu@57000000 {
status = "okay";
vdd-supply = <&gpu_max_reg>;
};
pcie@1003000 {
status = "okay";
avdd-pll-uerefe-supply = <&max77620_ldo1>;
hvddio-pex-supply = <&max77620_sd3>;
dvddio-pex-supply = <&max77620_ldo1>;
dvdd-pex-pll-supply = <&max77620_ldo1>;
hvdd-pex-pll-e-supply = <&max77620_sd3>;
vddio-pex-ctl-supply = <&max77620_sd3>;
pci@1,0 {
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, /* Referred to plat config */
<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
phy-names = "pcie-0", "pcie-1";
nvidia,num-lanes = <2>;
status = "disabled";
};
pci@2,0 {
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
phy-names = "pcie-0";
status = "okay";
};
};
host1x@50000000 {
dsia: dsi@54300000 {
status = "okay";
panel@0 {
compatible = "nintendo,panel-nx-dsi";
reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
vdd1-supply = <&v_pavdd_5v0>;
vdd2-supply = <&v_navdd_5v0>;
};
};
/* tegradc.0: DSI */
dc@54200000 {
status = "okay";
pavdd_lcd-supply = <&v_pavdd_5v0>;
navdd_lcd-supply = <&v_navdd_5v0>;
dvdd_lcd-supply = <&max77620_sd3>;
vdd_lcd_bl_en-supply = <&lcd_bl_en>;
nvidia,outputs = <&dsia>;
};
/* tegradc.1: DP */
dc@54240000 {
status = "okay";
avdd_hdmi-supply = <&max77620_ldo8>; /* 1V05 */
avdd_hdmi_pll-supply = <&max77620_sd3>; /* 1V8 */
// vdd_hdmi_5v0-supply = <&vdd_hdmi>; /* 5V0 GPIO_PCC7 fixed reg */
vdd-dp-pwr-supply = <&vdd_3v3>;
avdd-dp-pll-supply = <&max77620_sd3>;
vdd-dp-pad-supply = <&max77620_ldo8>;
extcon-cables = <&bm92t 3>;
extcon-cable-names = "typec1";
nvidia,outputs = <&sor1>;
};
dpaux1: dpaux@54040000 {
status = "okay";
vdd-supply = <&v_pavdd_5v0>;
};
sor1: sor@54580000 {
status = "okay";
nvidia,dpaux = <&dpaux1>;
avdd-io-hdmi-dp-supply = <&max77620_ldo8>;
vdd-hdmi-dp-pll-supply = <&max77620_sd3>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
};
vi: i2c@546c0000 {
status = "okay";
};
};
clock@70110000 {
status = "okay";
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,i2c-fs-rate = <400000>;
nvidia,sample-rate = <12500>;
vdd-cpu-supply = <&cpu_max_reg>;
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
reserved-memory {
/delete-node/ vpr-carveout;
/delete-node/ iram-carveout;
};
r2p {
compatible = "tegra-r2p";
status = "okay";
};
/* debug port */
serial@70006000 {
status = "disabled";
};
/* joycon ports:
invert TXD and RTS via IRDA_CSR
start @ 1000000 baud, switch to 3000000
when they are >= 3000000 baud, use 2 stop bits
use flow control
Note: hsuart driver is required for flow control
*/
/* right joycon */
serial@70006040 {
status = "okay";
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
nvidia,invert-txd;
nvidia,invert-rts;
reset-names = "serial";
joyconr {
status = "okay";
compatible = "nintendo,joycon-serdev";
charger-supply = <&en_vdd_jcr_chgr>;
detect-en-gpios = <&gpio TEGRA_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
detect-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
};
};
/* left joycon */
serial@70006200 {
status = "okay";
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
nvidia,invert-txd;
nvidia,invert-rts;
reset-names = "serial";
joyconl {
status = "okay";
compatible = "nintendo,joycon-serdev";
charger-supply = <&en_vdd_jcl_chgr>;
detect-en-gpios = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
detect-gpios = <&gpio TEGRA_GPIO(E, 6) GPIO_ACTIVE_LOW>;
};
};
/* bluetooth */
serial@70006300 {
dma-names = "tx";
status = "okay";
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
reset-names = "serial";
bluetooth {
compatible = "brcm,bcm43438-bt";
vbat-supply = <&battery_reg>;
vddio-supply = <&battery_reg>;
shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>;
max-speed = <3000000>; /* Max supported 4 MBaud */
sco-routing = <1>; /* Over HCI */
};
};
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 33898>;
pwm-names = "backlight";
brightness-levels = <
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58
59 60 61 62 63 64 65 66 67 68 69 70 71 72
73 74 75 76 77 78 79 80 81 82 83 84 85 86
87 88 89 90 91 92 93 94 95 96 97 98 99 100
>;
default-brightness-level = <50>;
enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
power-supply = <&max77620_sd3>;
};
/* Fixed regulators */
battery_reg: vdd-ac-bat {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "vdd-ac-bat";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: vdd-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpio = <&max77620 3 0>;
enable-active-high;
regulator-enable-ramp-delay = <160>;
regulator-disable-ramp-delay = <10000>;
};
max77620_gpio7: avdd-dsi-csi-1v2 {
compatible = "regulator-fixed";
regulator-name = "max77620-gpio7";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on; /* Must be set for seamless display */
gpio = <&max77620 7 0>;
enable-active-high;
regulator-enable-ramp-delay = <240>;
regulator-disable-ramp-delay = <11340>;
vin-supply = <&max77620_ldo0>;
};
lcd_bl_en: lcd-bl-en {
compatible = "regulator-fixed";
regulator-name = "lcd-bl-en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
regulator-boot-on; /* Must be set for seamless display */
enable-active-high;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
en_vdd_sd: en-vdd-sd {
compatible = "regulator-fixed";
regulator-name = "en-vdd-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(E, 4) 0>;
enable-active-high;
regulator-enable-ramp-delay = <472>;
regulator-disable-ramp-delay = <4880>;
vin-supply = <&vdd_3v3>;
};
/* LCD Power Enable +5V. Rohm BD8316GWL. */
v_pavdd_5v0: v-pavdd-5v0 {
compatible = "regulator-fixed";
regulator-name = "v_pavdd_5v0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(I, 0) 0>;
enable-active-high;
regulator-boot-on; /* Must be set for seamless display */
regulator-enable-ramp-delay = <232>;
};
/* LCD Power Enable -5V. Rohm BD8316GWL. */
v_navdd_5v0: v-navdd-5v0 {
compatible = "regulator-fixed";
regulator-name = "v_navdd_5v0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(I, 1) 0>;
enable-active-high;
regulator-boot-on; /* Must be set for seamless display */
regulator-enable-ramp-delay = <232>;
};
/* Joycon/Fan power (battery). Maxim MAX8969EWL53+. */
v_vdd50_a: v-vdd50-a {
compatible = "regulator-fixed";
regulator-name = "v_vdd50_a";
regulator-min-microvolt = <5300000>;
regulator-max-microvolt = <5300000>;
gpio = <&gpio TEGRA_GPIO(A, 5) 0>;
enable-active-high;
};
/* Joycon/Fan power (usb). DC0 on Odin. Maxim MAX8969EWL53+ on Modin. */
v_vdd50_b: v-vdd50-b {
compatible = "regulator-fixed";
regulator-name = "v_vdd50_b";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(CC, 4) 0>;
enable-active-high;
};
v_vdd5v3: v-vdd5v3 {
compatible = "regulator-fixed";
status = "okay"; /* Only enabled on Modin/Vali/Fric */
regulator-name = "v_vdd5v3";
regulator-min-microvolt = <5300000>;
regulator-max-microvolt = <5300000>;
gpio = <&gpio TEGRA_GPIO(X, 3) 0>;
enable-active-high;
regulator-enable-ramp-delay = <10000>;
};
vdd3v3_gc: vdd3v3-gc {
compatible = "regulator-fixed";
regulator-name = "vdd3v3_gc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(E, 5) 0>;
enable-active-high;
regulator-enable-ramp-delay = <472>;
regulator-disable-ramp-delay = <4880>;
vin-supply = <&vdd_3v3>;
};
/* TI TCR2EE48 4.8V */
en_vdd_jcl_chgr: left-joycon-charger {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "left-joycon-charger";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
gpio = <&gpio TEGRA_GPIO(CC, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&v_vdd50_a>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* TI TCR2EE48 4.8V */
en_vdd_jcr_chgr: right-joycon-charger {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "right-joycon-charger";
regulator-min-microvolt = <4800000>;
regulator-max-microvolt = <4800000>;
gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&v_vdd50_a>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
/* SDMMC4 for EMMC */
mmc@700b0600 {
status = "disabled";
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable;
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
/* SDMMC3 Not Used */
mmc@700b0400 {
status = "disabled";
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
/* SDMMC2 for Gamecard */
mmc@700b0200 {
status = "disabled";
bus-width = <8>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
mmc-hs200-1_8v;
cap-mmc-highspeed;
cap-sd-highspeed;
non-removable;
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
/* SDMMC1 for SD Card */
mmc@700b0000 {
status = "okay";
bus-width = <4>;
max-frequency = <200000000>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr50;
sd-uhs-sdr104;
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
vmmc-supply = <&en_vdd_sd>;
vqmmc-supply = <&max77620_ldo2>;
};
hda@70030000 {
status = "okay";
};
/* i2c1 @ 100000hz
1c: realtek 5639
18: rohm usb-pd
4c: ti temperature sensor
6b: ti charger
36: maxim fuel gauge
*/
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
bq24193@6b {
compatible = "ti,bq24193";
reg = <0x6b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 0) IRQ_TYPE_LEVEL_LOW>;
monitored-battery = <&fuel_gauge>;
#extcon-cells = <1>;
omit-battery-class;
battery_charger: charger {
regulator-name = "batt_regulator";
regulator-max-microamp = <4500000>;
};
usb0_vbus: usb-otg-vbus {
regulator-name = "vbus_regulator";
};
};
fuel_gauge: fuel-gauge@36 {
compatible = "maxim,max17050";
status = "okay";
reg = <0x36>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Y, 0) IRQ_TYPE_NONE>;
/* Actual is 5000 but driver does not account for CGAIN */
/* And does not take into account Rsense and CGAIN for capacity */
maxim,rsns-microohm = <10000>;
maxim,over-heat-temp = <600>;
maxim,dead-volt = <3000>;
maxim,over-volt = <4208>; /* Actual: 4258 mV */
#thermal-sensor-cells = <0>;
};
rt5639: audio-codec@1c {
status = "okay";
compatible = "realtek,rt5639";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(BB, 4) IRQ_TYPE_EDGE_RISING>;
realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
realtek,over-current-threshold-microamp = <600>;
realtek,over-current-scale-factor = <2>;
realtek,jack-detect-is-jd1;
};
/* PD Chip */
bm92t: bm92t@18 {
compatible = "rohm,bm92t";
reg = <0x18>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(K, 4) IRQ_TYPE_EDGE_RISING>;
#extcon-cells = <1>;
pd_bat_chg-supply = <&battery_charger>;
vbus-source-supply = <&v_vdd5v3>;
vbus-supply = <&usb0_vbus>;
rohm,dp-lanes = <2>;
rohm,dp-signal-toggle-on-resume;
/* Absolute max is 2.4A, constrained by BQ24193 ILIM */
rohm,pd-5v-current-limit-ma = <2000>;
rohm,pd-9v-current-limit-ma = <2000>;
rohm,pd-12v-current-limit-ma = <1500>;
rohm,pd-15v-current-limit-ma = <1200>;
port {
usb_con_ep: endpoint {
remote-endpoint = <&usb_port_0>;
};
};
};
tmp451: temperature-sensor@4c {
compatible = "ti,tmp451";
status = "okay";
reg = <0x4c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 4) IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&battery_reg>;
#thermal-sensor-cells = <1>;
};
};
/* i2c3 @ 400000hz
49: stm touchscreen controller
*/
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
touchscreen@49 {
compatible = "stm,ftm4_fts";
status = "okay";
reg = <0x49>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_LEVEL_LOW>;
vdd-tp-2v9-supply = <&max77620_ldo6>;
stm,vio-gpio = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_HIGH>;
stm,irq_type = <0x2000>; /* IRQF_ONESHOT */
stm,regulator_avdd = "vdd-tp-2v9";
stm,max_coords = <1280 720>;
stm,max-real-coords = <1264 704>;
stm,edge-offset = <15 15>;
stm,delayed-open;
stm,delayed-open-time = <0>;
};
};
/* i2c2 @ 400000hz
29: rohm ambient light sensor
*/
i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
bh1730fvc: bh1730fvc@29 {
status = "disabled";
compatible = "rohm,bh1730fvc";
reg = <0x29>;
als-vid-supply = <&max77620_ldo6>;
als-vdd-supply = <&vdd_3v3>;
rohm,integration-cycle = <38>;
rohm,lux-multiplier = <3600>;
rohm,opt-win-coeff = < 500 5002 7502
754 2250 2000
1029 1999 1667
1373 884 583
1879 309 165>;
rohm,gain-coeff = < 2500 0
1600 7800
10 50000
0 1000>;
};
};
spi@7000da00 {
status = "disabled"; /* Disabled for Vali */
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
// spi-cs-setup-delay-ns = <2>;
// spi-cs-hold-delay-ns = <2>;
// spi-cs-inactive-delay-ns = <2>;
/*
* Model WHOAMI:
* LSM6DS3H 0x69, LSM6DSE 0x6A, LSM6DSO 0x6C, ICM40607 0x38.
*/
gyroscope: imu@0 {
reg = <0>;
status = "disabled";
compatible = "st,lsm6ds3h";
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <8000000>;
/* SPI Mode-3 */
spi-cpha;
spi-cpol;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 2) IRQ_TYPE_LEVEL_HIGH>;
vdd-supply = <&battery_reg>;
vddio-supply = <&battery_reg>;
st,drdy-int-pin = <2>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
mount-matrix =
"1", "0", "0", /* X: x */
"0", "1", "0", /* Y: y */
"0", "0", "1"; /* Z: z */
};
};
gpio-keys {
compatible = "gpio-keys";
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
};
};
gpio@6000d000 {
boot-default-output-high {
gpio-hog;
output-high;
gpios = <TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; /* Wi-Fi Reset. Powered on by default. */
line-name = "boot-default-output-high";
};
};
pwm@7000a000 {
status = "okay";
#pwm-cells = <2>;
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-min-state = <0>;
cooling-max-state = <5>;
#cooling-cells = <2>;
pwms = <&pwm 1 33333>;
fan-supply = <&v_vdd50_a>;
enable-gpios = <&gpio TEGRA_GPIO(A, 5) GPIO_ACTIVE_HIGH>;
/* cooling level (0, 1, 2, 3, 4, 5) - pwm inverted */
cooling-levels = <255 204 153 102 51 0>;
};
sound {
status = "okay";
compatible = "nvidia,tegra-audio-rt5640-tx1",
"nvidia,tegra-audio-rt5640";
nvidia,model = "Nintendo Switch";
nvidia,audio-codec = <&rt5639>;
nvidia,i2s-controller = <&tegra_i2s1>;
// nvidia,hp-det-gpios = <&gpio 143 0>;
clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "pll_a", "plla_out0", "mclk";
assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_D_AUDIO>,
<&tegra_car TEGRA210_CLK_EXTERN1>;
assigned-clock-rates = <368640000>, <36864000>,
<36864000>, <12288000>;
nvidia,audio-routing =
"Headphones", "HPOL",
"Headphones", "HPOR",
"Speakers", "SPORP",
"Speakers", "SPORN",
"Speakers", "SPOLP",
"Speakers", "SPOLN",
"IN1P", "Mic Jack",
"IN1P", "Mic Jack";
};
thermal-zones {
cpu {
polling-delay-passive = <250>;
polling-delay = <500>;
status = "okay";
/* Based on Console profile SoC: 95% (100% at Handheld) */
coefficients = <95 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
thermal-sensors = <&tmp451 1>;
trips {
cpu_critical: cpu-critical {
temperature = <102500>;
hysteresis = <0>;
type = "critical";
};
cpu_heavy: cpu-heavy {
temperature = <98500>;
hysteresis = <1000>;
type = "hot";
};
cpu_throttle: cpu-throttle {
temperature = <89000>;
hysteresis = <2000>;
type = "passive";
};
cpu_cap_trip1: cpu-cap-trip1 {
temperature = <58000>;
hysteresis = <2000>;
type = "active";
};
cpu_floor_trip1: cpu-floor-trip1 {
temperature = <53000>;
hysteresis = <2000>;
type = "active";
};
cpu_cap_trip0: cpu-cap-trip0 {
temperature = <48000>;
hysteresis = <2000>;
type = "active";
};
cpu_floor_trip0: cpu-floor-trip0 {
temperature = <43000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map0 {
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
trip = <&cpu_critical>;
};
map1 {
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
trip = <&cpu_heavy>;
};
map2 {
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
trip = <&cpu_throttle>;
};
map3 {
cooling-device = <&fan 1 1>;
trip = <&cpu_cap_trip1>;
};
map4 {
cooling-device = <&fan 2 2>;
trip = <&cpu_floor_trip1>;
};
map5 {
cooling-device = <&fan 3 3>;
trip = <&cpu_cap_trip0>;
};
map6 {
cooling-device = <&fan 4 4>;
trip = <&cpu_floor_trip0>;
};
};
};
gpu {
polling-delay-passive = <250>;
polling-delay = <500>;
status = "okay";
thermal-sensors = <&tmp451 1>;
trips {
gpu_critical: gpu-critical {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
};
gpu_heavy: gpu-heavy {
temperature = <100000>;
hysteresis = <1000>;
type = "hot";
};
gpu_throttle: gpu-throttle {
temperature = <90500>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&gpu_critical>;
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&gpu_heavy>;
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
trip = <&gpu_throttle>;
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
pmic {
status = "okay";
polling-delay-passive = <250>;
polling-delay = <500>;
thermal-sensors = <&max77620>;
trips {
pmic_die_warn_temp_thresh: hot-die {
temperature = <120000>;
type = "hot";
hysteresis = <0>;
};
pmic_die_cirt_temp_thresh: critical-die {
temperature = <140000>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps {
map0 {
trip = <&pmic_die_warn_temp_thresh>;
cooling-device = <&throttle_heavy 1 1>;
contribution = <100>;
};
};
};
cpu_vreg {
status = "okay";
polling-delay-passive = <250>;
polling-delay = <500>;
thermal-sensors = <&cpu_max_reg>;
trips {
cpu_vreg_die_warn_temp_thresh: hot-die {
temperature = <120000>;
type = "hot";
hysteresis = <0>;
};
};
cooling-maps {
map0 {
trip = <&cpu_vreg_die_warn_temp_thresh>;
cooling-device = <&throttle_heavy 1 1>;
contribution = <100>;
};
};
};
gpu_vreg {
status = "okay";
polling-delay-passive = <250>;
polling-delay = <500>;
thermal-sensors = <&gpu_max_reg>;
trips {
gpu_vreg_die_warn_temp_thresh: hot-die {
temperature = <120000>;
type = "hot";
hysteresis = <0>;
};
};
cooling-maps {
/*
* There are currently no cooling maps,
* because there are no cooling devices.
*/
};
};
};
};

2253
arch/arm64/boot/dts/nvidia/tegra210-odin.dts Normal file
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File diff suppressed because it is too large Load Diff

49749
arch/arm64/boot/dts/nvidia/tegra210-p2180-emc.dtsi Normal file
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File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@@ -2,6 +2,7 @@
#include <dt-bindings/mfd/max77620.h>
#include "tegra210.dtsi"
#include "tegra210-p2180-emc.dtsi"
/ {
model = "NVIDIA Jetson TX1";
@@ -24,6 +25,7 @@
gpu@57000000 {
vdd-supply = <&vdd_gpu>;
status = "okay";
};
/* debug port */

6
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
View File

@@ -90,6 +90,12 @@
};
};
cec@70015000 {
status = "okay";
hdmi-phandle = <&sor1>;
};
clock@70110000 {
status = "okay";

298
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
View File

@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/mfd/max77620.h>
#include "tegra210.dtsi"
/ {
@@ -6,8 +8,10 @@
compatible = "nvidia,p2530", "nvidia,tegra210";
aliases {
rtc0 = "/i2c@7000d000/pmic@3c";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
serial3 = &uartd;
};
chosen {
@@ -19,6 +23,11 @@
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
gpu@57000000 {
vdd-supply = <&vdd_gpu>;
status = "okay";
};
/* debug port */
serial@70006000 {
/delete-property/ dmas;
@@ -26,13 +35,280 @@
status = "okay";
};
serial@70006300 {
/delete-property/ reg-shift;
status = "okay";
compatible = "nvidia,tegra30-hsuart";
reset-names = "serial";
bluetooth {
compatible = "brcm,bcm43540-bt";
device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wakeup";
};
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupt-parent = <&tegra_pmc>;
interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
fps {
fps0 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
maxim,shutdown-fps-time-period-us = <5120>;
};
fps1 {
maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
maxim,shutdown-fps-time-period-us = <5120>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
};
max77620_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
};
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
};
gpio2_3 {
pins = "gpio2", "gpio3";
function = "fps-out";
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
gpio4 {
pins = "gpio4";
function = "32k-out1";
};
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull = <1>;
};
};
regulators {
in-ldo0-1-supply = <&vdd_pre>;
in-ldo7-8-supply = <&vdd_pre>;
vdd_soc: sd0 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <146>;
regulator-ramp-delay = <9100>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vdd_ddr: sd1 {
regulator-name = "VDD_DDR_1V1_PMIC";
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <130>;
regulator-ramp-delay = <9100>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_pre: sd2 {
regulator-name = "VDD_PRE_REG_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-enable-ramp-delay = <176>;
regulator-ramp-delay = <7900>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_1v8: sd3 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <242>;
regulator-ramp-delay = <7700>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_sys_1v2: ldo0 {
regulator-name = "AVDD_SYS_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-enable-ramp-delay = <26>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_pex_1v05: ldo1 {
regulator-name = "VDD_PEX_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vddio_sdmmc: ldo2 {
regulator-name = "VDDIO_SDMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_cam_hv: ldo3 {
regulator-name = "VDD_CAM_HV";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <50>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_rtc: ldo4 {
regulator-name = "VDD_RTC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_ts_hv: ldo5 {
regulator-name = "VDD_TS_HV";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_ts: ldo6 {
regulator-name = "VDD_TS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-enable-ramp-delay = <36>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
avdd_1v05_pll: ldo7 {
regulator-name = "AVDD_1V05_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <24>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
avdd_1v05: ldo8 {
regulator-name = "AVDD_SATA_HDMI_DP_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <50000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
};
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <4587 3876>;
nvidia,core-pwr-off-time = <39065>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
};
mmc@700b0200 {
status = "okay";
bus-width = <4>;
non-removable;
power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
vqmmc-supply = <&vdd_1v8>;
vmmc-supply = <&vdd_3v3_sys>;
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
/* eMMC */
@@ -70,4 +346,26 @@
compatible = "arm,psci-0.2";
method = "smc";
};
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vdd_gpu: regulator-vdd-gpu {
compatible = "pwm-regulator";
pwms = <&pwm 1 8000>;
regulator-name = "VDD_GPU";
regulator-min-microvolt = <710000>;
regulator-max-microvolt = <1320000>;
enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
regulator-ramp-delay = <160>;
regulator-enable-ramp-delay = <2000>;
};
};

17
arch/arm64/boot/dts/nvidia/tegra210-p2571-0930.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210-p2571.dts"
/ {
model = "NVIDIA Shield TV 2015";
compatible = "nvidia,p2571-0930", "nvidia,tegra210";
hda@70030000 {
nvidia,model = "NVIDIA SHIELD TV APE";
};
sound {
label = "NVIDIA SHIELD TV APE";
};
};

18
arch/arm64/boot/dts/nvidia/tegra210-p2571-0932.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210-p2571-0930.dts"
/ {
model = "NVIDIA Shield TV Pro 2015";
compatible = "nvidia,p2571-0932", "nvidia,p2571-0930", "nvidia,tegra210";
sata@70020000 {
status = "okay";
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
};
mmc@700b0600 {
status = "disabled";
};
};

1633
arch/arm64/boot/dts/nvidia/tegra210-p2571.dts
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File diff suppressed because it is too large Load Diff

75
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@@ -1605,6 +1605,18 @@
};
};
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm 3 45334>;
fan-supply = <&vdd_fan>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(K, 7) IRQ_TYPE_EDGE_RISING>;
/* cooling level (0, 1, 2, 3) - pwm inverted */
cooling-levels = <255 128 64 0>;
#cooling-cells = <2>;
};
vdd_sys_mux: regulator-vdd-sys-mux {
compatible = "regulator-fixed";
regulator-name = "VDD_SYS_MUX";
@@ -1760,4 +1772,67 @@
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_fan: regulator-vdd-fan {
compatible = "regulator-fixed";
regulator-name = "VDD_FAN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&exp1 4 GPIO_ACTIVE_LOW>;
vin-supply = <&vdd_5v0_sys>;
regulator-enable-ramp-delay = <284>;
};
thermal-zones {
cpu-thermal {
trips {
cpu_trip_critical: critical {
temperature = <96500>;
hysteresis = <0>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <70000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active: active {
temperature = <50000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_passive: passive {
temperature = <30000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map0 {
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_critical>;
};
map1 {
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_hot>;
};
map2 {
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active>;
};
map3 {
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
};
};
};
};
};

1599
arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
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File diff suppressed because it is too large Load Diff

8
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@@ -429,6 +429,12 @@
nvidia,sys-clock-req-active-high;
};
cec@70015000 {
status = "okay";
hdmi-phandle = <&sor1>;
};
hda@70030000 {
nvidia,model = "NVIDIA Jetson Nano HDA";
@@ -524,7 +530,7 @@
ports {
usb2-0 {
status = "okay";
mode = "peripheral";
mode = "otg";
usb-role-switch;
vbus-supply = <&vdd_5v0_usb>;

59
arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts Normal file
View File

@@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210-p3450-0000.dts"
/ {
model = "NVIDIA Jetson Nano 2GB Developer Kit";
compatible = "nvidia,p3541-0000", "nvidia,p3450-0000", "nvidia,tegra210";
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
host1x@50000000 {
sor@54540000 {
status = "disabled";
};
dpaux@545c0000 {
status = "disabled";
};
};
padctl@7009f000 {
ports {
usb2-1 {
vbus-supply = <&vdd_hub_5v0>;
};
usb2-2 {
vbus-supply = <&vdd_hub_5v0>;
};
usb3-0 {
/delete-property/ vbus-supply;
};
};
};
regulator-vdd-hdmi-5v0 {
gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/delete-node/ regulator-vdd-hub-3v3;
vdd_hub_5v0: regulator-vdd-hub-5v0 {
compatible = "regulator-fixed";
regulator-name = "VDD_HUB_5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
};

135
arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi Normal file
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@@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0
/ {
/* EMC DVFS OPP table */
emc_icc_dvfs_opp_table: opp-table-dvfs0 {
compatible = "operating-points-v2";
opp-40800000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0003>;
};
opp-68000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0003>;
};
opp-102000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0003>;
};
opp-204000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0007>;
opp-suspend;
};
opp-408000000-812 {
opp-microvolt = <812000 812000 1150000>;
opp-hz = /bits/ 64 <408000000>;
opp-supported-hw = <0x0003>;
};
opp-665600000-825 {
opp-microvolt = <825000 825000 1150000>;
opp-hz = /bits/ 64 <665600000>;
opp-supported-hw = <0x0003>;
};
opp-800000000-825 {
opp-microvolt = <825000 825000 1150000>;
opp-hz = /bits/ 64 <800000000>;
opp-supported-hw = <0x0003>;
};
opp-1065600000-837 {
opp-microvolt = <837000 837000 1150000>;
opp-hz = /bits/ 64 <1065600000>;
opp-supported-hw = <0x0003>;
};
opp-1331200000-850 {
opp-microvolt = <850000 850000 1150000>;
opp-hz = /bits/ 64 <1331200000>;
opp-supported-hw = <0x0003>;
};
opp-1600000000-887 {
opp-microvolt = <887000 887000 1150000>;
opp-hz = /bits/ 64 <1600000000>;
opp-supported-hw = <0x0007>;
};
};
/* EMC bandwidth OPP table */
emc_bw_dfs_opp_table: opp-table-dvfs1 {
compatible = "operating-points-v2";
opp-40800000 {
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <652800>;
};
opp-68000000 {
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <1088000>;
};
opp-102000000 {
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <1632000>;
};
opp-204000000 {
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0007>;
opp-peak-kBps = <3264000>;
opp-suspend;
};
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <6528000>;
};
opp-665600000 {
opp-hz = /bits/ 64 <665600000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <10649600>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <12800000>;
};
opp-1065600000 {
opp-hz = /bits/ 64 <1065600000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <17049600>;
};
opp-1331200000 {
opp-hz = /bits/ 64 <1331200000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <21299200>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-supported-hw = <0x0007>;
opp-peak-kBps = <25600000>;
};
};
};

126
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@@ -9,6 +9,8 @@
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include <dt-bindings/soc/tegra-pmc.h>
#include "tegra210-peripherals-opp.dtsi"
/ {
compatible = "nvidia,tegra210";
interrupt-parent = <&lic>;
@@ -202,6 +204,19 @@
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <0>;
interconnects = <&mc TEGRA210_MC_DISPLAY0A &emc>,
<&mc TEGRA210_MC_DISPLAY0B &emc>,
<&mc TEGRA210_MC_DISPLAY0C &emc>,
<&mc TEGRA210_MC_DISPLAYHC &emc>,
<&mc TEGRA210_MC_DISPLAYD &emc>,
<&mc TEGRA210_MC_DISPLAYT &emc>;
interconnect-names = "wina",
"winb",
"winc",
"cursor",
"wind",
"wint";
};
dc@54240000 {
@@ -217,6 +232,15 @@
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <1>;
interconnects = <&mc TEGRA210_MC_DISPLAY0AB &emc>,
<&mc TEGRA210_MC_DISPLAY0BB &emc>,
<&mc TEGRA210_MC_DISPLAY0CB &emc>,
<&mc TEGRA210_MC_DISPLAYHCB &emc>;
interconnect-names = "wina",
"winb",
"winc",
"cursor";
};
dsia: dsi@54300000 {
@@ -253,7 +277,13 @@
nvjpg@54380000 {
compatible = "nvidia,tegra210-nvjpg";
reg = <0x0 0x54380000 0x0 0x00040000>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&tegra_car 195>;
reset-names = "nvjpg";
iommus = <&mc TEGRA_SWGROUP_NVJPG>;
power-domains = <&pd_nvjpg>;
};
dsib: dsi@54400000 {
@@ -277,13 +307,25 @@
nvdec@54480000 {
compatible = "nvidia,tegra210-nvdec";
reg = <0x0 0x54480000 0x0 0x00040000>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&tegra_car 194>;
reset-names = "nvdec";
iommus = <&mc TEGRA_SWGROUP_NVDEC>;
power-domains = <&pd_nvdec>;
};
nvenc@544c0000 {
compatible = "nvidia,tegra210-nvenc";
reg = <0x0 0x544c0000 0x0 0x00040000>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_NVENC>;
clock-names = "nvenc";
resets = <&tegra_car 219>;
reset-names = "nvenc";
iommus = <&mc TEGRA_SWGROUP_NVENC>;
power-domains = <&pd_nvenc>;
};
tsec@54500000 {
@@ -485,6 +527,21 @@
reg = <0x0 0x60007000 0x0 0x1000>;
};
actmon@6000c800 {
compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon";
reg = <0x0 0x6000c800 0x0 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_ACTMON>,
<&tegra_car TEGRA210_CLK_EMC>;
clock-names = "actmon", "emc";
resets = <&tegra_car 119>;
reset-names = "actmon";
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA210_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
#cooling-cells = <2>;
};
gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -884,6 +941,18 @@
#power-domain-cells = <0>;
};
pd_nvenc: mpe {
clocks = <&tegra_car TEGRA210_CLK_NVENC>;
resets = <&tegra_car 219>;
#power-domain-cells = <0>;
};
pd_nvdec: nvdec {
clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
resets = <&tegra_car 194>;
#power-domain-cells = <0>;
};
pd_sor: sor {
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
@@ -937,6 +1006,12 @@
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
#power-domain-cells = <0>;
};
pd_nvjpg: nvjpg {
clocks = <&tegra_car TEGRA210_CLK_NVJPG>;
resets = <&tegra_car 195>;
#power-domain-cells = <0>;
};
};
};
@@ -949,6 +1024,28 @@
reset-names = "fuse";
};
cec@70015000 {
compatible = "nvidia,tegra210-cec";
reg = <0x0 0x070015000 0x0 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_CEC>;
clock-names = "cec";
status = "disabled";
};
bpmp: bpmp@70016000 {
compatible = "nvidia,tegra210-bpmp";
reg = <0x0 0x70016000 0x0 0x2000
0x0 0x60001000 0x0 0x1000>;
status = "disabled";
interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tx", "rx";
#clock-cells = <1>;
};
mc: memory-controller@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
@@ -959,6 +1056,7 @@
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
emc: external-memory-controller@7001b000 {
@@ -970,6 +1068,9 @@
clock-names = "emc";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
#interconnect-cells = <0>;
#cooling-cells = <2>;
};
@@ -2162,6 +2263,25 @@
};
};
core_dvfs_floor: core_dvfs_cdev_floor {
compatible = "nvidia,tegra-core-cdev-action";
cdev-type = "CORE-floor";
#cooling-cells = <2>; /* min followed by max */
};
core_dvfs_cap: core_dvfs_cdev_cap {
compatible = "nvidia,tegra-core-cdev-action";
cdev-type = "CORE-cap";
#cooling-cells = <2>; /* min followed by max */
clocks = <&tegra_car TEGRA210_CLK_CAP_VCORE_C2BUS>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_C3BUS>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_SCLK>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_HOST1X>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_ABUS>;
clock-names = "c2bus_cap", "c3bus_cap", "sclk_cap",
"host1x_cap", "adsp_cap";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13

9
arch/arm64/boot/dts/nvidia/tegra210b01-fric.dts Normal file
View File

@@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210b01-nx.dtsi"
/ {
model = "Nintendo Switch (OLED model)";
compatible = "nvidia,fric", "nintendo,aula", "nintendo,nx", "nvidia,tegra210b01";
};

1292
arch/arm64/boot/dts/nvidia/tegra210b01-nx.dtsi Normal file
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File diff suppressed because it is too large Load Diff

10
arch/arm64/boot/dts/nvidia/tegra210b01-odin.dts Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210b01-nx.dtsi"
/ {
model = "Nintendo Switch (2019)";
compatible = "nvidia,modin", "nvidia,odin", "nintendo,iowa", "nintendo,nx", "nvidia,tegra210b01";
};

10
arch/arm64/boot/dts/nvidia/tegra210b01-p2894-0050-a08.dts Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210b01-p2894.dtsi"
/ {
model = "NVIDIA Shield TV Pro 2019";
compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210b01",
"nvidia,tegra210";
};

70
arch/arm64/boot/dts/nvidia/tegra210b01-p2894.dtsi Normal file
View File

@@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra210b01.dtsi"
/ {
aliases {
serial0 = &uarta;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <4587 3876>;
nvidia,core-pwr-off-time = <39065>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
status = "okay";
};
mmc@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
};
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
cpus {
cpu@0 {
enable-method = "psci";
};
cpu@1 {
enable-method = "psci";
};
cpu@2 {
enable-method = "psci";
};
cpu@3 {
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};

142
arch/arm64/boot/dts/nvidia/tegra210b01-vali.dts Normal file
View File

@@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra210b01-nx.dtsi"
/ {
model = "Nintendo Switch Lite";
compatible = "nvidia,vali", "nintendo,hoag", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
/* Joycon/Fan power (usb) */
v_vdd50_b: v-vdd50-b {
status = "disabled"; /* Only enabled on Odin/Modin */
};
en_vdd_jcl_chgr: left-joycon-charger {
status = "disabled"; /* Only enabled on Odin/Modin/Fric */
};
en_vdd_jcr_chgr: right-joycon-charger {
status = "disabled"; /* Only enabled on Odin/Modin/Fric */
};
spi@7000da00 {
status = "disabled"; /* Disabled for Vali since Sio uses it */
};
/* Right Joycon */
serial@70006040 {
status = "disabled";
joyconr {
status = "disabled";
};
};
/* Left Joycon / Sio */
serial@70006200 {
status = "okay";
/delete-property/ nvidia,invert-txd;
/delete-property/ nvidia,invert-rts;
joyconl {
status = "disabled";
};
sio {
status = "okay";
};
};
i2c@7000c000 {
bm92t: bm92t@18 {
status = "disabled";
/delete-property/ rohm,dp-signal-toggle-on-resume;
rohm,dp-disable;
rohm,pd-5v-current-limit-ma = <2000>;
rohm,pd-9v-current-limit-ma = <1500>;
rohm,pd-12v-current-limit-ma = <1200>;
rohm,pd-15v-current-limit-ma = <900>;
};
bq2419x: bq24193@6b {
battery_charger: charger {
ti,charge-voltage-limit-millivolt = <4320>; /* Adjusted by cell age */
ti,fast-charge-current-limit-milliamp = <1664>;
ti,temp-range = <0 18 47 58>;
ti,charge-thermal-voltage-limit = <4320 4320 4320 4080>; /* Adjusted by cell age */
ti,charge-current-limit = <512 640 1664 1664>;
};
};
fuel_gauge: fuel-gauge@36 {
maxim,over-volt = <4320>; /* Actual: 4370 mV */
maxim,kernel-maximum-soc = <100>; /* Adjusted by cell age */
};
};
i2c@7000d000 {
pmic_b: pmic@3c {
regulators {
/* Vali: Powers LDO 2V8 for Sio VDD
* Powers LDO 1V8 for I2C1 VDDQ and ALC5639.
*/
ldo8 {
regulator-name = "vdd-i2c1";
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
i2c@546c0000 {
bus-pullup-supply = <&battery_reg>;
};
host1x@50000000 {
/* tegradc.1: DP */
dc@54240000 {
status = "disabled";
};
};
xusb: usb@70090000 {
status = "okay";
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
phy-names = "usb2-0", "usb3-0";
extcon = <&bm92t 0>;
extcon-cable-names = "vbus";
avdd-usb-supply = <&vdd_3v3>;
dvddio-pex-supply = <&max77620_ldo1>;
hvddio-pex-supply = <&max77620_sd3>;
};
xudc: usb@700d0000 {
status = "okay";
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
phy-names = "usb2-0", "usb3-0";
extcon = <&bm92t 1>;
extcon-cable-names = "id";
hvdd-usb-supply = <&vdd_3v3>;
avddio-usb-supply = <&max77620_ldo1>;
};
padctl@7009f000 {
status = "okay";
avdd-pll-utmip-supply = <&max77620_sd3>;
avdd-pll-uerefe-supply = <&max77620_ldo1>;
dvdd-pex-pll-supply = <&max77620_ldo1>;
hvdd-pex-pll-e-supply = <&max77620_sd3>;
};
};

157
arch/arm64/boot/dts/nvidia/tegra210b01.dtsi Normal file
View File

@@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra210.dtsi"
/ {
compatible = "nvidia,tegra210b01", "nvidia,tegra210";
pcie@1003000 {
compatible = "nvidia,tegra210b01-pcie";
};
host1x@50000000 {
/delete-node/ sor@54540000;
/delete-node/ dpaux@545c0000;
/delete-node/ vi@54080000;
/delete-node/ i2c@546c0000;
dc@54200000 {
nvidia,outputs = <&dsia &dsib &sor1>;
};
dc@54240000 {
nvidia,outputs = <&dsia &dsib &sor1>;
};
dsi@54300000 {
compatible = "nvidia,tegra210b01-dsi";
};
dsi@54400000 {
compatible = "nvidia,tegra210b01-dsi";
};
};
clock@60006000 {
compatible = "nvidia,tegra210b01-car";
};
pinmux@700008d4 {
status = "okay";
sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
sdmmc1 {
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
sdmmc1 {
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
sdmmc3 {
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
sdmmc3 {
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
};
i2c@7000d100 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-1;
/delete-property/ pinctrl-names;
};
mc: memory-controller@70019000 {
emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra210b01-emc";
reg = <0x0 0x7001b000 0x0 0x1000>,
<0x0 0x7001e000 0x0 0x1000>,
<0x0 0x7001f000 0x0 0x1000>;
clocks = <&bpmp 0>;
clock-names = "emc";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <0>;
#cooling-cells = <2>;
nvidia,bpmp = <&bpmp>;
};
};
/delete-node/ external-memory-controller@7001b000;
mmc@700b0000 {
nvidia,default-tap = <0xb>;
nvidia,default-trim = <0xe>;
};
mmc@700b0200 {
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0xd>;
};
mmc@700b0400 {
nvidia,default-tap = <0xb>;
nvidia,default-trim = <0x12>;
};
mmc@700b0600 {
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0xd>;
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
};
/* Tegra210B01 has MBIST patched and is missing VI unit */
pmc@7000e400 {
compatible = "nvidia,tegra210b01-pmc";
powergates {
/delete-node/ venc;
};
};
bpmp: bpmp@70016000 {
status = "okay";
};
usb@70090000 {
compatible = "nvidia,tegra210b01-xusb";
};
padctl@7009f000 {
compatible = "nvidia,tegra210b01-xusb-padctl";
};
usb@700d0000 {
compatible = "nvidia,tegra210b01-xudc";
};
thermal-sensor@700e2000 {
compatible = "nvidia,tegra210b01-soctherm";
throttle-cfgs {
heavy {
nvidia,cpu-throt-percent = <0>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_NONE>;
};
};
};
clock@70110000 {
compatible = "nvidia,tegra210b01-dfll";
};
};

122
arch/arm64/configs/defconfig
View File

@@ -32,7 +32,6 @@ CONFIG_KALLSYMS_ALL=y
CONFIG_PROFILING=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
CONFIG_CRASH_DUMP=y
CONFIG_ARCH_ACTIONS=y
CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_SUNXI=y
@@ -94,7 +93,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_SCPI_CPUFREQ=y
@@ -106,6 +104,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_TEGRA186_CPUFREQ=y
CONFIG_QORIQ_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ACPI=y
CONFIG_ACPI_HOTPLUG_MEMORY=y
CONFIG_ACPI_HMAT=y
@@ -115,11 +114,9 @@ CONFIG_ACPI_APEI_PCIEAER=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_IOSCHED_BFQ=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MEMORY_HOTPLUG=y
@@ -129,8 +126,6 @@ CONFIG_MEMORY_FAILURE=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
@@ -177,6 +172,7 @@ CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_GACT=m
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_GATE=m
CONFIG_HSR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
CONFIG_CAN=m
@@ -198,8 +194,8 @@ CONFIG_BT_QCOMSMD=m
CONFIG_BT_NXPUART=m
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_MAC80211_LEDS=y
CONFIG_RFKILL=m
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NFC=m
@@ -248,7 +244,6 @@ CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_HISILICON_LPC=y
CONFIG_TEGRA_ACONNECT=m
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_INTEL_STRATIX10_SERVICE=y
@@ -281,6 +276,7 @@ CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_SPI_NAND=m
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=m
CONFIG_MTD_HYPERBUS=m
@@ -314,7 +310,6 @@ CONFIG_AHCI_XGENE=y
CONFIG_AHCI_QORIQ=y
CONFIG_SATA_SIL24=y
CONFIG_SATA_RCAR=y
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_OF_PLATFORM=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
@@ -330,6 +325,7 @@ CONFIG_VIRTIO_NET=y
CONFIG_MHI_NET=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_MSCC_FELIX=m
CONFIG_ENA_ETHERNET=m
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
CONFIG_ATL1C=m
@@ -358,6 +354,8 @@ CONFIG_IGBVF=y
CONFIG_MVNETA=y
CONFIG_MVPP2=y
CONFIG_SKY2=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
@@ -373,6 +371,7 @@ CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_MEDIATEK=m
CONFIG_DWMAC_TEGRA=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_TI_ICSSG_PRUETH=m
@@ -516,10 +515,10 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_BCM2835=m
CONFIG_I2C_CADENCE=m
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX_LPI2C=y
@@ -650,14 +649,16 @@ CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_GPIO_VF610=y
CONFIG_GPIO_VISCONTI=y
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_VF610=y
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_XGENE_SB=y
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
CONFIG_GPIO_ADP5585=m
CONFIG_GPIO_BD9571MWV=m
CONFIG_GPIO_MAX77620=y
@@ -689,6 +690,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_SL28CPLD=m
CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TMP102=m
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
@@ -699,9 +701,6 @@ CONFIG_K3_THERMAL=m
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
CONFIG_RZG2L_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_MTK_THERMAL=m
CONFIG_MTK_LVTS_THERMAL=m
@@ -709,6 +708,9 @@ CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_EXYNOS_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
CONFIG_RZG2L_THERMAL=y
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
@@ -736,6 +738,7 @@ CONFIG_MESON_WATCHDOG=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_RENESAS_WDT=y
CONFIG_RENESAS_RZG2LWDT=y
CONFIG_RENESAS_RZV2HWDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_PM8916_WATCHDOG=m
CONFIG_BCM2835_WDT=y
@@ -763,6 +766,7 @@ CONFIG_MFD_TI_LP873X=m
CONFIG_MFD_TPS65219=y
CONFIG_MFD_TPS6594_I2C=m
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_STM32_LPTIMER=m
CONFIG_MFD_WCD934X=m
CONFIG_MFD_KHADAS_MCU=m
CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -779,6 +783,7 @@ CONFIG_REGULATOR_LP873X=m
CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_REGULATOR_MAX20411=m
CONFIG_REGULATOR_MAX77812=y
CONFIG_REGULATOR_MP8859=y
CONFIG_REGULATOR_MT6315=m
CONFIG_REGULATOR_MT6357=y
@@ -823,10 +828,11 @@ CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_AMPHION_VPU=m
CONFIG_VIDEO_CADENCE_CSI2RX=m
CONFIG_VIDEO_MEDIATEK_JPEG=m
CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_WAVE_VPU=m
CONFIG_VIDEO_E5010_JPEG_ENC=m
CONFIG_VIDEO_MEDIATEK_JPEG=m
CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_MEDIATEK_MDP3=m
CONFIG_VIDEO_IMX7_CSI=m
CONFIG_VIDEO_IMX_MIPI_CSIS=m
CONFIG_VIDEO_IMX8_ISI=m
@@ -834,8 +840,8 @@ CONFIG_VIDEO_IMX8_ISI_M2M=y
CONFIG_VIDEO_IMX8_JPEG=m
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_VIDEO_QCOM_VENUS=m
CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_CSI2=m
CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_VIDEO_RZG2L_CSI2=m
CONFIG_VIDEO_RZG2L_CRU=m
@@ -853,7 +859,7 @@ CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_DRM=m
CONFIG_DRM=y
CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
@@ -876,26 +882,26 @@ CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_DW_HDMI=m
CONFIG_DRM_RCAR_MIPI_DSI=m
CONFIG_DRM_RZG2L_MIPI_DSI=m
CONFIG_DRM_RZG2L_DU=m
CONFIG_DRM_RZG2L_MIPI_DSI=m
CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_MSM=m
CONFIG_DRM_TEGRA=m
CONFIG_DRM_TEGRA=y
CONFIG_DRM_TEGRA_DEBUG=y
CONFIG_DRM_TEGRA_STAGING=y
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
CONFIG_DRM_PANEL_NX_DSI=y
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_FSL_LDB=m
@@ -905,7 +911,6 @@ CONFIG_DRM_LONTIUM_LT9611UXC=m
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_PARADE_PS8640=m
CONFIG_DRM_SAMSUNG_DSIM=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_THINE_THC63LVD1024=m
@@ -917,6 +922,7 @@ CONFIG_DRM_TI_SN65DSI86=m
CONFIG_DRM_ANALOGIX_ANX7625=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_CDNS_DSI=m
CONFIG_DRM_CDNS_MHDP8546=m
CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
@@ -942,7 +948,8 @@ CONFIG_DRM_POWERVR=m
CONFIG_FB=y
CONFIG_FB_EFI=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_LP855X=m
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
@@ -964,6 +971,8 @@ CONFIG_SND_SOC_IMX_AUDMIX=m
CONFIG_SND_SOC_MT8183=m
CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
CONFIG_SND_SOC_MT8188=m
CONFIG_SND_SOC_MT8188_MT6359=m
CONFIG_SND_SOC_MT8192=m
CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
CONFIG_SND_SOC_MT8195=m
@@ -992,6 +1001,7 @@ CONFIG_SND_SOC_RZ=m
CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_OF=y
CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
CONFIG_SND_SOC_SOF_MT8186=m
CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
@@ -1012,7 +1022,6 @@ CONFIG_SND_SOC_TEGRA210_AMX=m
CONFIG_SND_SOC_TEGRA210_ADX=m
CONFIG_SND_SOC_TEGRA210_MIXER=m
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
CONFIG_SND_SOC_DAVINCI_MCASP=m
CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4619=m
@@ -1020,10 +1029,10 @@ CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_RK3308=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RT5640=m
@@ -1036,7 +1045,6 @@ CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_WCD9335=m
CONFIG_SND_SOC_WCD934X=m
CONFIG_SND_SOC_WCD939X=m
CONFIG_SND_SOC_WCD939X_SDW=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8904=m
@@ -1049,8 +1057,6 @@ CONFIG_SND_SOC_WSA884X=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
@@ -1079,12 +1085,10 @@ CONFIG_USB_CDNS_SUPPORT=m
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_IMX=m
CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_DWC3=y
CONFIG_OMAP_USB2=m
CONFIG_USB_DWC2=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
@@ -1119,6 +1123,9 @@ CONFIG_USB_MASS_STORAGE=m
CONFIG_TYPEC=m
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
CONFIG_TYPEC_MT6360=m
CONFIG_TYPEC_TCPCI_MAXIM=m
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_QCOM_PMIC=m
CONFIG_TYPEC_UCSI=m
@@ -1128,6 +1135,7 @@ CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_GPIO_SBU=m
CONFIG_TYPEC_MUX_IT5205=m
CONFIG_TYPEC_MUX_NB7VPQ904M=m
CONFIG_TYPEC_MUX_WCD939X_USBSS=m
CONFIG_TYPEC_DP_ALTMODE=m
@@ -1234,6 +1242,7 @@ CONFIG_PL330_DMA=y
CONFIG_TEGRA186_GPC_DMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
CONFIG_MTK_UART_APDMA=m
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_GPI_DMA=m
CONFIG_QCOM_HIDMA_MGMT=y
@@ -1251,6 +1260,8 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_GREYBUS=m
CONFIG_GREYBUS_BEAGLEPLAY=m
CONFIG_STAGING=y
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_MAX96712=m
@@ -1264,7 +1275,6 @@ CONFIG_CROS_EC_SPI=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
CONFIG_CROS_EC_CHARDEV=m
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_FSL_SAI=y
@@ -1283,31 +1293,19 @@ CONFIG_CLK_IMX8QXP=y
CONFIG_CLK_IMX8ULP=y
CONFIG_CLK_IMX93=y
CONFIG_TI_SCI_CLK=y
CONFIG_COMMON_CLK_MT8192_AUDSYS=y
CONFIG_COMMON_CLK_MT8192_CAMSYS=y
CONFIG_COMMON_CLK_MT8192_IMGSYS=y
CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
CONFIG_COMMON_CLK_MT8192_IPESYS=y
CONFIG_COMMON_CLK_MT8192_MDPSYS=y
CONFIG_COMMON_CLK_MT8192_MFGCFG=y
CONFIG_COMMON_CLK_MT8192_MMSYS=y
CONFIG_COMMON_CLK_MT8192_MSDC=y
CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
CONFIG_COMMON_CLK_MT8192_VDECSYS=y
CONFIG_COMMON_CLK_MT8192_VENCSYS=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_CLK_X1E80100_CAMCC=m
CONFIG_CLK_X1E80100_DISPCC=m
CONFIG_CLK_X1E80100_GCC=y
CONFIG_CLK_X1E80100_GPUCC=m
CONFIG_CLK_X1E80100_TCSRCC=y
CONFIG_CLK_QCM2290_GPUCC=m
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_6018=y
@@ -1323,7 +1321,7 @@ CONFIG_MSM_MMCC_8998=m
CONFIG_QCM_GCC_2290=y
CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_GCC_404=y
CONFIG_QDU_GCC_1000=y
CONFIG_SC_CAMCC_7280=m
CONFIG_SC_CAMCC_8280XP=m
CONFIG_SC_DISPCC_7280=m
CONFIG_SC_DISPCC_8280XP=m
@@ -1336,7 +1334,10 @@ CONFIG_SC_GCC_8280XP=y
CONFIG_SC_GPUCC_7280=m
CONFIG_SC_GPUCC_8280XP=m
CONFIG_SC_LPASSCC_8280XP=m
CONFIG_SC_LPASS_CORECC_7280=m
CONFIG_SC_VIDEOCC_7280=m
CONFIG_SDM_CAMCC_845=m
CONFIG_QDU_GCC_1000=y
CONFIG_SDM_GPUCC_845=y
CONFIG_SDM_VIDEOCC_845=y
CONFIG_SDM_DISPCC_845=y
@@ -1347,7 +1348,6 @@ CONFIG_SM_DISPCC_6115=m
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_DISPCC_8450=m
CONFIG_SM_DISPCC_8550=m
CONFIG_SM_DISPCC_8650=m
CONFIG_SM_GCC_4450=y
CONFIG_SM_GCC_6115=y
CONFIG_SM_GCC_8350=y
@@ -1364,16 +1364,18 @@ CONFIG_SM_GPUCC_8650=m
CONFIG_SM_TCSRCC_8550=y
CONFIG_SM_TCSRCC_8650=y
CONFIG_SM_VIDEOCC_8250=y
CONFIG_SM_VIDEOCC_8550=m
CONFIG_QCOM_HFPLL=y
CONFIG_CLK_GFM_LPASS_SM8250=m
CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_OMAP=m
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_TEGRA186_TIMER=y
CONFIG_CLKSRC_STM32_LP=y
CONFIG_RENESAS_OSTM=y
CONFIG_ARM_MHU=y
CONFIG_IMX_MBOX=y
CONFIG_OMAP2PLUS_MBOX=m
CONFIG_PLATFORM_MHU=y
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
@@ -1394,6 +1396,7 @@ CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_SYSMON=m
CONFIG_QCOM_WCNSS_PIL=m
CONFIG_TI_K3_DSP_REMOTEPROC=m
CONFIG_TI_K3_M4_REMOTEPROC=m
CONFIG_TI_K3_R5_REMOTEPROC=m
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_CTRL=m
@@ -1472,12 +1475,14 @@ CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_FSL_IFC=y
CONFIG_RENESAS_RPCIF=m
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_IMX8QXP_ADC=m
CONFIG_IMX93_ADC=m
CONFIG_MAX9611=m
CONFIG_MEDIATEK_MT6359_AUXADC=m
CONFIG_MEDIATEK_MT6577_AUXADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
@@ -1510,7 +1515,7 @@ CONFIG_PWM_RZ_MTU3=m
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SL28CPLD=m
CONFIG_PWM_SUN4I=m
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TEGRA=y
CONFIG_PWM_TIECAP=m
CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_VISCONTI=m
@@ -1527,6 +1532,7 @@ CONFIG_PHY_XGENE=y
CONFIG_PHY_CAN_TRANSCEIVER=m
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_CADENCE_TORRENT=m
CONFIG_PHY_CADENCE_DPHY=m
CONFIG_PHY_CADENCE_DPHY_RX=m
CONFIG_PHY_CADENCE_SIERRA=m
CONFIG_PHY_CADENCE_SALVO=m
@@ -1536,6 +1542,7 @@ CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_HISTB_COMBPHY=y
CONFIG_PHY_HISI_INNO_USB2=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PHY_MTK_PCIE=m
CONFIG_PHY_MTK_TPHY=y
CONFIG_PHY_QCOM_EDP=m
CONFIG_PHY_QCOM_PCIE2=m
@@ -1569,6 +1576,7 @@ CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_AM654_SERDES=m
CONFIG_PHY_J721E_WIZ=m
CONFIG_OMAP_USB2=m
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
@@ -1610,10 +1618,8 @@ CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=y
CONFIG_SLIMBUS=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_SLIM_QCOM_NGD_CTRL=m
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_IMX=y
CONFIG_INTERCONNECT_IMX8MM=m
CONFIG_INTERCONNECT_IMX8MN=m
@@ -1643,6 +1649,7 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
CONFIG_INTERCONNECT_QCOM_X1E80100=y
CONFIG_COUNTER=m
CONFIG_RZ_MTU3_CNT=m
CONFIG_TI_EQEP=m
CONFIG_HTE=y
CONFIG_HTE_TEGRA194=y
CONFIG_HTE_TEGRA194_TEST=m
@@ -1661,7 +1668,6 @@ CONFIG_OVERLAY_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
CONFIG_UBIFS_FS=m
CONFIG_SQUASHFS=y
@@ -1677,8 +1683,8 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_CHACHA20_NEON=m
@@ -1688,7 +1694,6 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=m
CONFIG_CRYPTO_SHA3_ARM64=m
CONFIG_CRYPTO_SM3_ARM64_CE=m
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=m
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
@@ -1713,7 +1718,6 @@ CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_CORESIGHT=m
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m

32
arch/arm64/include/uapi/asm/sigcontext.h
View File

@@ -19,6 +19,7 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_64BIT
#include <linux/types.h>
/*
@@ -183,6 +184,37 @@ struct zt_context {
__u16 __reserved[3];
};
#else /* CONFIG_64BIT */
/*
* Signal context structure - contains all info to do with the state
* before the signal handler was invoked. Note: only add new entries
* to the end of the structure.
*/
struct sigcontext {
unsigned long trap_no;
unsigned long error_code;
unsigned long oldmask;
unsigned long arm_r0;
unsigned long arm_r1;
unsigned long arm_r2;
unsigned long arm_r3;
unsigned long arm_r4;
unsigned long arm_r5;
unsigned long arm_r6;
unsigned long arm_r7;
unsigned long arm_r8;
unsigned long arm_r9;
unsigned long arm_r10;
unsigned long arm_fp;
unsigned long arm_ip;
unsigned long arm_sp;
unsigned long arm_lr;
unsigned long arm_pc;
unsigned long arm_cpsr;
unsigned long fault_address;
};
#endif /* CONFIG_64BIT */
#endif /* !__ASSEMBLY__ */
#include <asm/sve_context.h>

7
arch/arm64/kernel/cpufeature.c
View File

@@ -481,7 +481,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
static const struct arm64_ftr_bits ftr_ctr[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
@@ -526,6 +526,7 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
* of support.
*/
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_TraceVer_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
ARM64_FTR_END,
};
@@ -671,8 +672,8 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
/* [31:28] TraceFilt */
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),

8
block/partitions/Kconfig
View File

@@ -270,4 +270,12 @@ config CMDLINE_PARTITION
Say Y here if you want to read the partition table from bootargs.
The format for the command line is just like mtdparts.
config TEGRA_PARTITION
bool "NVIDIA Tegra Partition support" if PARTITION_ADVANCED
default y if ARCH_TEGRA
depends on EFI_PARTITION && MMC_BLOCK && (ARCH_TEGRA || COMPILE_TEST)
help
Say Y here if you would like to be able to read the hard disk
partition table format used by NVIDIA Tegra machines.
endmenu

1
block/partitions/Makefile
View File

@@ -20,3 +20,4 @@ obj-$(CONFIG_IBM_PARTITION) += ibm.o
obj-$(CONFIG_EFI_PARTITION) += efi.o
obj-$(CONFIG_KARMA_PARTITION) += karma.o
obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o
obj-$(CONFIG_TEGRA_PARTITION) += tegra.o

1
block/partitions/check.h
View File

@@ -66,4 +66,5 @@ int osf_partition(struct parsed_partitions *state);
int sgi_partition(struct parsed_partitions *state);
int sun_partition(struct parsed_partitions *state);
int sysv68_partition(struct parsed_partitions *state);
int tegra_partition(struct parsed_partitions *state);
int ultrix_partition(struct parsed_partitions *state);

3
block/partitions/core.c
View File

@@ -81,6 +81,9 @@ static int (*const check_part[])(struct parsed_partitions *) = {
#endif
#ifdef CONFIG_SYSV68_PARTITION
sysv68_partition,
#endif
#ifdef CONFIG_TEGRA_PARTITION
tegra_partition,
#endif
NULL
};

9
block/partitions/efi.c
View File

@@ -98,6 +98,15 @@ static int force_gpt;
static int __init
force_gpt_fn(char *str)
{
/*
* This check allows to properly parse cmdline variants like
* "gpt gpt_sector=<sector>" and "gpt_sector=<sector> gpt" since
* "gpt" overlaps with the "gpt_sector=", see tegra_gpt_sector_fn().
* The argument is absent for a boolean cmdline option.
*/
if (strlen(str))
return 0;
force_gpt = 1;
return 1;
}

580
block/partitions/tegra.c Normal file
View File

@@ -0,0 +1,580 @@
// SPDX-License-Identifier: GPL-2.0
/*
* NVIDIA Tegra Partition Table
*
* Copyright (C) 2020 GRATE-DRIVER project
* Copyright (C) 2020 Dmitry Osipenko <digetx@gmail.com>
*
* Credits for the partition table format:
*
* Andrey Danin <danindrey@mail.ru> (Toshiba AC100 TegraPT format)
* Gilles Grandou <gilles@grandou.net> (Toshiba AC100 TegraPT format)
* Ryan Grachek <ryan@edited.us> (Google TV "Molly" TegraPT format)
* Stephen Warren <swarren@wwwdotorg.org> (Useful suggestions about eMMC/etc)
*/
#define pr_fmt(fmt) "tegra-partition: " fmt
#include <linux/blkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/sizes.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/mmc/blkdev.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <soc/tegra/common.h>
#include <soc/tegra/partition.h>
#include "check.h"
#define TEGRA_PT_SECTOR_SIZE(ptp) ((ptp)->logical_sector_size / SZ_512)
#define TEGRA_PT_SECTOR(ptp, s) ((s) * TEGRA_PT_SECTOR_SIZE(ptp))
#define TEGRA_PT_HEADER_SIZE \
(sizeof(struct tegra_partition_header_insecure) + \
sizeof(struct tegra_partition_header_secure))
#define TEGRA_PT_MAX_PARTITIONS(ptp) \
(((ptp)->logical_sector_size - TEGRA_PT_HEADER_SIZE) / \
sizeof(struct tegra_partition))
#define TEGRA_PT_ERR(ptp, fmt, ...) \
pr_debug("%s: " fmt, \
(ptp)->state->disk->disk_name, ##__VA_ARGS__)
#define TEGRA_PT_PARSE_ERR(ptp, fmt, ...) \
TEGRA_PT_ERR(ptp, "sector %llu: invalid " fmt, \
(ptp)->sector, ##__VA_ARGS__)
struct tegra_partition_table_parser {
struct tegra_partition_table *pt;
unsigned int logical_sector_size;
struct parsed_partitions *state;
bool pt_entry_checked;
sector_t sector;
int boot_offset;
u32 dev_instance;
u32 dev_id;
};
union tegra_partition_table_u {
struct tegra_partition_table pt;
u8 pt_parts[SZ_4K / SZ_512][SZ_512];
};
struct tegra_partition_type {
unsigned int type;
char *name;
};
static sector_t tegra_pt_logical_sector_address;
static sector_t tegra_pt_logical_sectors_num;
void tegra_partition_table_setup(unsigned int logical_sector_address,
unsigned int logical_sectors_num)
{
tegra_pt_logical_sector_address = logical_sector_address;
tegra_pt_logical_sectors_num = logical_sectors_num;
pr_info("initialized to logical sector = %llu sectors_num = %llu\n",
tegra_pt_logical_sector_address, tegra_pt_logical_sectors_num);
}
/*
* Some partitions are very sensitive, changing data on them may brick device.
*
* For more details about partitions see:
*
* "https://docs.nvidia.com/jetson/l4t/Tegra Linux Driver Package Development Guide/part_config.html"
*/
static const char * const partitions_blacklist[] = {
"BCT", "EBT", "EB2", "EKS", "GP1", "GPT", "MBR", "PT",
};
static bool tegra_partition_name_match(struct tegra_partition *p,
const char *name)
{
return !strncmp(p->partition_name, name, TEGRA_PT_NAME_SIZE);
}
static bool tegra_partition_skip(struct tegra_partition *p,
struct tegra_partition_table_parser *ptp,
sector_t sector)
{
unsigned int i;
/* skip eMMC boot partitions */
if (sector < ptp->boot_offset)
return true;
for (i = 0; i < ARRAY_SIZE(partitions_blacklist); i++) {
if (tegra_partition_name_match(p, partitions_blacklist[i]))
return true;
}
return false;
}
static const struct tegra_partition_type tegra_partition_expected_types[] = {
{ .type = TEGRA_PT_PART_TYPE_BCT, .name = "BCT", },
{ .type = TEGRA_PT_PART_TYPE_EBT, .name = "EBT", },
{ .type = TEGRA_PT_PART_TYPE_EBT, .name = "EB2", },
{ .type = TEGRA_PT_PART_TYPE_PT, .name = "PT", },
{ .type = TEGRA_PT_PART_TYPE_GP1, .name = "GP1", },
{ .type = TEGRA_PT_PART_TYPE_GPT, .name = "GPT", },
{ .type = TEGRA_PT_PART_TYPE_GENERIC, .name = NULL, },
};
static int tegra_partition_type_valid(struct tegra_partition_table_parser *ptp,
struct tegra_partition *p)
{
const struct tegra_partition_type *ptype;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(tegra_partition_expected_types); i++) {
ptype = &tegra_partition_expected_types[i];
if (ptype->name && !tegra_partition_name_match(p, ptype->name))
continue;
if (p->part_info.partition_type == ptype->type)
return 0;
/*
* Unsure about all possible types, let's emit error and
* allow to continue for now.
*/
if (!ptype->name)
return 1;
}
return -1;
}
static bool tegra_partition_valid(struct tegra_partition_table_parser *ptp,
struct tegra_partition *p,
struct tegra_partition *prev,
sector_t sector,
sector_t size)
{
struct tegra_partition_info *prev_pi = &prev->part_info;
sector_t sect_end = TEGRA_PT_SECTOR(ptp,
prev_pi->logical_sector_address +
prev_pi->logical_sectors_num);
char *type, name[2][TEGRA_PT_NAME_SIZE + 1];
int err;
strscpy(name[0], p->partition_name, sizeof(name[0]));
strscpy(name[1], prev->partition_name, sizeof(name[1]));
/* validate expected partition name/type */
err = tegra_partition_type_valid(ptp, p);
if (err) {
TEGRA_PT_PARSE_ERR(ptp, "partition_type: [%s] partition_type=%u\n",
name[0], p->part_info.partition_type);
if (err < 0)
return false;
TEGRA_PT_ERR(ptp, "continuing, please update list of expected types\n");
}
/* validate partition table BCT addresses */
if (tegra_partition_name_match(p, "PT")) {
if (sector != TEGRA_PT_SECTOR(ptp, tegra_pt_logical_sector_address) &&
size != TEGRA_PT_SECTOR(ptp, tegra_pt_logical_sectors_num)) {
TEGRA_PT_PARSE_ERR(ptp, "PT location: sector=%llu size=%llu\n",
sector, size);
return false;
}
if (ptp->pt_entry_checked) {
TEGRA_PT_PARSE_ERR(ptp, "(duplicated) PT\n");
return false;
}
ptp->pt_entry_checked = true;
}
if (sector + size < sector) {
TEGRA_PT_PARSE_ERR(ptp, "size: [%s] integer overflow sector=%llu size=%llu\n",
name[0], sector, size);
return false;
}
/* validate allocation_policy=sequential (absolute unsupported) */
if (p != prev && sect_end > sector) {
TEGRA_PT_PARSE_ERR(ptp, "allocation_policy: [%s] end=%llu [%s] sector=%llu size=%llu\n",
name[1], sect_end, name[0], sector, size);
return false;
}
if (ptp->dev_instance != p->mount_info.device_instance) {
TEGRA_PT_PARSE_ERR(ptp, "device_instance: [%s] device_instance=%u|%u\n",
name[0], ptp->dev_instance,
p->mount_info.device_instance);
return false;
}
if (ptp->dev_id != p->mount_info.device_id) {
TEGRA_PT_PARSE_ERR(ptp, "device_id: [%s] device_id=%u|%u\n",
name[0], ptp->dev_id,
p->mount_info.device_id);
return false;
}
if (p->partition_id > 127) {
TEGRA_PT_PARSE_ERR(ptp, "partition_id: [%s] partition_id=%u\n",
name[0], p->partition_id);
return false;
}
sect_end = get_capacity(ptp->state->disk);
/* eMMC boot partitions are below ptp->boot_offset */
if (sector < ptp->boot_offset) {
sect_end += ptp->boot_offset;
type = "boot";
} else {
sector -= ptp->boot_offset;
type = "main";
}
/* validate size */
if (!size || sector + size > sect_end) {
TEGRA_PT_PARSE_ERR(ptp, "size: [%s] %s partition boot_offt=%d end=%llu sector=%llu size=%llu\n",
name[0], type, ptp->boot_offset, sect_end,
sector, size);
return false;
}
return true;
}
static bool tegra_partitions_parsed(struct tegra_partition_table_parser *ptp,
bool check_only)
{
struct parsed_partitions *state = ptp->state;
struct tegra_partition_table *pt = ptp->pt;
sector_t sector, size;
int i, slot = 1;
ptp->pt_entry_checked = false;
for (i = 0; i < pt->secure.num_partitions; i++) {
struct tegra_partition *p = &pt->partitions[i];
struct tegra_partition *prev = &pt->partitions[max(i - 1, 0)];
struct tegra_partition_info *pi = &p->part_info;
if (slot == state->limit && !check_only)
break;
sector = TEGRA_PT_SECTOR(ptp, pi->logical_sector_address);
size = TEGRA_PT_SECTOR(ptp, pi->logical_sectors_num);
if (check_only &&
!tegra_partition_valid(ptp, p, prev, sector, size))
return false;
if (check_only ||
tegra_partition_skip(p, ptp, sector))
continue;
put_partition(state, slot++, sector - ptp->boot_offset, size);
}
if (check_only && !ptp->pt_entry_checked) {
TEGRA_PT_PARSE_ERR(ptp, "PT: table entry not found\n");
return false;
}
return true;
}
static bool
tegra_partition_table_parsed(struct tegra_partition_table_parser *ptp)
{
if (ptp->pt->secure.num_partitions == 0 ||
ptp->pt->secure.num_partitions > TEGRA_PT_MAX_PARTITIONS(ptp)) {
TEGRA_PT_PARSE_ERR(ptp, "num_partitions=%u\n",
ptp->pt->secure.num_partitions);
return false;
}
return tegra_partitions_parsed(ptp, true) &&
tegra_partitions_parsed(ptp, false);
}
static int
tegra_partition_table_insec_hdr_valid(struct tegra_partition_table_parser *ptp)
{
if (ptp->pt->insecure.magic != TEGRA_PT_MAGIC ||
ptp->pt->insecure.version != TEGRA_PT_VERSION) {
TEGRA_PT_PARSE_ERR(ptp, "insecure header: magic=0x%llx ver=0x%x\n",
ptp->pt->insecure.magic,
ptp->pt->insecure.version);
return 0;
}
return 1;
}
static int
tegra_partition_table_sec_hdr_valid(struct tegra_partition_table_parser *ptp)
{
size_t pt_size = ptp->pt->secure.num_partitions;
pt_size *= sizeof(ptp->pt->partitions[0]);
pt_size += TEGRA_PT_HEADER_SIZE;
if (ptp->pt->secure.magic != TEGRA_PT_MAGIC ||
ptp->pt->secure.version != TEGRA_PT_VERSION ||
ptp->pt->secure.length != ptp->pt->insecure.length ||
ptp->pt->secure.length < pt_size) {
TEGRA_PT_PARSE_ERR(ptp, "secure header: magic=0x%llx ver=0x%x length=%u|%u|%zu\n",
ptp->pt->secure.magic,
ptp->pt->secure.version,
ptp->pt->secure.length,
ptp->pt->insecure.length,
pt_size);
return 0;
}
return 1;
}
static int
tegra_partition_table_unencrypted(struct tegra_partition_table_parser *ptp)
{
/* AES IV, all zeros if unencrypted */
if (ptp->pt->secure.random_data[0] || ptp->pt->secure.random_data[1] ||
ptp->pt->secure.random_data[2] || ptp->pt->secure.random_data[3]) {
pr_err_once("encrypted partition table unsupported\n");
return 0;
}
return 1;
}
static int tegra_read_partition_table(struct tegra_partition_table_parser *ptp)
{
union tegra_partition_table_u *ptu = (typeof(ptu))ptp->pt;
unsigned int i;
Sector sect;
void *part;
for (i = 0; i < ptp->logical_sector_size / SZ_512; i++) {
/*
* Partition table takes at maximum 4096 bytes, but
* read_part_sector() guarantees only that SECTOR_SIZE will
* be read at minimum.
*/
part = read_part_sector(ptp->state, ptp->sector + i, &sect);
if (!part) {
TEGRA_PT_ERR(ptp, "failed to read sector %llu\n",
ptp->sector + i);
return 0;
}
memcpy(ptu->pt_parts[i], part, SZ_512);
put_dev_sector(sect);
}
return 1;
}
static int tegra_partition_scan(struct tegra_partition_table_parser *ptp)
{
sector_t start_sector, num_sectors;
int ret = 0;
num_sectors = TEGRA_PT_SECTOR(ptp, tegra_pt_logical_sectors_num);
start_sector = TEGRA_PT_SECTOR(ptp, tegra_pt_logical_sector_address);
if (start_sector < ptp->boot_offset) {
TEGRA_PT_ERR(ptp,
"scanning eMMC boot partitions unimplemented\n");
return 0;
}
ptp->sector = start_sector - ptp->boot_offset;
/*
* Partition table is duplicated for num_sectors.
* If first table is corrupted, we will try next.
*/
while (num_sectors--) {
ret = tegra_read_partition_table(ptp);
if (!ret)
goto next_sector;
ret = tegra_partition_table_insec_hdr_valid(ptp);
if (!ret)
goto next_sector;
ret = tegra_partition_table_unencrypted(ptp);
if (!ret)
goto next_sector;
ret = tegra_partition_table_sec_hdr_valid(ptp);
if (!ret)
goto next_sector;
ret = tegra_partition_table_parsed(ptp);
if (ret)
break;
next_sector:
ptp->sector += TEGRA_PT_SECTOR_SIZE(ptp);
}
return ret;
}
static const u32 tegra20_sdhci_bases[TEGRA_PT_SDHCI_DEVICE_INSTANCES] = {
0xc8000000, 0xc8000200, 0xc8000400, 0xc8000600,
};
static const u32 tegra30_sdhci_bases[TEGRA_PT_SDHCI_DEVICE_INSTANCES] = {
0x78000000, 0x78000200, 0x78000400, 0x78000600,
};
static const u32 tegra124_sdhci_bases[TEGRA_PT_SDHCI_DEVICE_INSTANCES] = {
0x700b0000, 0x700b0200, 0x700b0400, 0x700b0600,
};
static const struct of_device_id tegra_sdhci_match[] = {
{ .compatible = "nvidia,tegra20-sdhci", .data = tegra20_sdhci_bases, },
{ .compatible = "nvidia,tegra30-sdhci", .data = tegra30_sdhci_bases, },
{ .compatible = "nvidia,tegra114-sdhci", .data = tegra30_sdhci_bases, },
{ .compatible = "nvidia,tegra124-sdhci", .data = tegra124_sdhci_bases, },
{}
};
static int
tegra_partition_table_emmc_boot_offset(struct tegra_partition_table_parser *ptp)
{
struct gendisk *disk = ptp->state->disk;
struct block_device *bdev = disk->part0;
struct mmc_card *card = mmc_bdev_to_card(bdev);
const struct of_device_id *matched;
const u32 *sdhci_bases;
const __be32 *addrp;
u32 sdhci_base;
unsigned int i;
/* filter out unexpected/untested boot sources */
if (!card || card->ext_csd.rev < 3 ||
!mmc_card_mmc(card) ||
!mmc_card_is_blockaddr(card) ||
mmc_card_is_removable(card->host) ||
bdev_logical_block_size(bdev) != SZ_512) {
TEGRA_PT_ERR(ptp, "unexpected boot source\n");
return -1;
}
/* skip everything unrelated to Tegra eMMC */
matched = of_match_node(tegra_sdhci_match, card->host->parent->of_node);
if (!matched)
return -1;
sdhci_bases = matched->data;
/* figure out SDHCI instance ID by the base address */
addrp = of_get_address(card->host->parent->of_node, 0, NULL, NULL);
if (!addrp)
return -1;
sdhci_base = of_translate_address(card->host->parent->of_node, addrp);
for (i = 0; i < TEGRA_PT_SDHCI_DEVICE_INSTANCES; i++) {
if (sdhci_base == sdhci_bases[i])
break;
}
if (i == TEGRA_PT_SDHCI_DEVICE_INSTANCES)
return -1;
ptp->dev_id = TEGRA_PT_SDHCI_DEVICE_ID;
ptp->dev_instance = i;
/*
* eMMC storage has two special boot partitions in addition to the
* main one. NVIDIA's bootloader linearizes eMMC boot0->boot1->main
* accesses, this means that the partition table addresses are shifted
* by the size of boot partitions. In accordance with the eMMC
* specification, the boot partition size is calculated as follows:
*
* boot partition size = 128K byte x BOOT_SIZE_MULT
*
* This function returns number of sectors occupied by the both boot
* partitions.
*/
return card->ext_csd.raw_boot_mult * SZ_128K /
SZ_512 * MMC_NUM_BOOT_PARTITION;
}
/*
* Logical sector size may vary per device model and apparently there is no
* way to get information about the size from kernel. The info is hardcoded
* into bootloader and it doesn't tell us, so we'll just try all possible
* well-known sizes until succeed.
*
* For example Samsung Galaxy Tab 10.1 uses 2K sectors. While Acer A500,
* Nexus 7 and Ouya are using 4K sectors.
*/
static const unsigned int tegra_pt_logical_sector_sizes[] = {
SZ_4K, SZ_2K,
};
/*
* The 'tegraboot=<source>' command line option is provided to kernel
* by NVIDIA's proprietary bootloader on most Tegra devices. If it isn't
* provided, then it should be added to the cmdline via device-tree bootargs
* or by other means.
*/
static bool tegra_boot_sdmmc;
static int __init tegra_boot_fn(char *str)
{
tegra_boot_sdmmc = !strcmp(str, "sdmmc");
return 1;
}
__setup("tegraboot=", tegra_boot_fn);
int tegra_partition(struct parsed_partitions *state)
{
struct tegra_partition_table_parser ptp = {};
unsigned int i;
int ret;
if (!soc_is_tegra() || !tegra_boot_sdmmc)
return 0;
ptp.state = state;
ptp.boot_offset = tegra_partition_table_emmc_boot_offset(&ptp);
if (ptp.boot_offset < 0)
return 0;
ptp.pt = kmalloc(SZ_4K, GFP_KERNEL);
if (!ptp.pt)
return 0;
for (i = 0; i < ARRAY_SIZE(tegra_pt_logical_sector_sizes); i++) {
ptp.logical_sector_size = tegra_pt_logical_sector_sizes[i];
ret = tegra_partition_scan(&ptp);
if (ret == 1) {
strlcat(state->pp_buf, "\n", PAGE_SIZE);
break;
}
}
kfree(ptp.pt);
return ret;
}

9
drivers/base/core.c
View File

@@ -2179,6 +2179,15 @@ static int fw_devlink_create_devlink(struct device *con,
goto out;
}
/*
* SYNC_STATE_ONLY links are useless once a consumer device has probed.
* So, only create it if the consumer hasn't probed yet.
*/
if (flags & DL_FLAG_SYNC_STATE_ONLY &&
con->links.status != DL_DEV_NO_DRIVER &&
con->links.status != DL_DEV_PROBING)
goto out;
if (con != sup_dev && !device_link_add(con, sup_dev, flags)) {
dev_err(con, "Failed to create device link (0x%x) with %s\n",
flags, dev_name(sup_dev));

23
drivers/clk/clk.c
View File

@@ -2475,6 +2475,13 @@ static void clk_change_rate(struct clk_core *core)
if (core->flags & CLK_RECALC_NEW_RATES)
(void)clk_calc_new_rates(core, core->new_rate);
/*
* Allow children to be aware that next set rate operation is triggered
* by downward rate propagation, rather than direct set rate on itself.
*/
if (core->notifier_count)
__clk_notify(core, PRE_SUBTREE_CHANGE, old_rate, core->rate);
/*
* Use safe iteration, as change_rate can actually swap parents
* for certain clock types.
@@ -2490,6 +2497,9 @@ static void clk_change_rate(struct clk_core *core)
if (core->new_child)
clk_change_rate(core->new_child);
if (core->notifier_count)
__clk_notify(core, POST_SUBTREE_CHANGE, old_rate, core->rate);
clk_pm_runtime_put(core);
}
@@ -2870,6 +2880,7 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
int ret = 0;
int p_index = 0;
unsigned long p_rate = 0;
unsigned long old_p_rate = 0;
lockdep_assert_held(&prepare_lock);
@@ -2912,13 +2923,23 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
if (ret & NOTIFY_STOP_MASK)
goto runtime_put;
/* do the re-parent */
/* propagate PRE_PARENT_CHANGE notifications */
if (core->parent)
old_p_rate = core->parent->rate;
ret = __clk_notify(core, PRE_PARENT_CHANGE, old_p_rate, p_rate);
/* do the re-parent if no objections */
if (!(ret & NOTIFY_STOP_MASK))
ret = __clk_set_parent(core, parent, p_index);
/* propagate rate an accuracy recalculation accordingly */
if (ret) {
__clk_notify(core, ABORT_PARENT_CHANGE, old_p_rate, p_rate);
__clk_recalc_rates(core, true, ABORT_RATE_CHANGE);
} else {
__clk_notify(core, POST_PARENT_CHANGE, old_p_rate, p_rate);
__clk_recalc_rates(core, true, POST_RATE_CHANGE);
__clk_recalc_accuracies(core);
}

1
drivers/clk/tegra/Makefile
View File

@@ -27,6 +27,7 @@ obj-$(CONFIG_TEGRA124_CLK_EMC) += clk-tegra124-emc.o
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
obj-y += cvb.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210b01.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210-emc.o
obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o
obj-y += clk-utils.o

2876
drivers/clk/tegra/clk-dfll.c
View File

File diff suppressed because it is too large Load Diff

40
drivers/clk/tegra/clk-dfll.h
View File

@@ -13,36 +13,64 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/types.h>
#include <soc/tegra/tegra-dfll.h>
#include "cvb.h"
struct thermal_tv;
/**
* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
* @dev: struct device * that holds the OPP table for the DFLL
* @max_freq: maximum frequency supported on this SoC
* @cvb: CPU frequency table for this SoC
* @alignment: parameters of the regulator step and offset
* @init_clock_trimmers: callback to initialize clock trimmers
* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
* @tune0_low: DFLL tuning register 0 (low voltage range)
* @tune0_high: DFLL tuning register 0 (high voltage range)
* @tune1: DFLL tuning register 1
* @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage
* @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage
* @thermal_floor_table: table mapping a given temperature to a minimum voltage
* @thermal_cap_table: table mapping a given temperature to a maximum voltage
* @thermal_floor_table_size: size of thermal_floor_table
* @thermal_cap_table_size: size of thermal_cap_table
*/
struct tegra_dfll_soc_data {
struct device *dev;
unsigned long max_freq;
const struct cvb_table *cvb;
struct rail_alignment alignment;
unsigned int min_millivolts;
unsigned int tune_high_min_millivolts;
u32 tune0_low;
u32 tune0_high;
u32 tune1_low;
u32 tune1_high;
unsigned int tune_high_margin_millivolts;
void (*init_clock_trimmers)(void);
void (*set_clock_trimmers_high)(void);
void (*set_clock_trimmers_low)(void);
const struct thermal_tv *thermal_floor_table;
const struct thermal_tv *thermal_cap_table;
unsigned int thermal_floor_table_size;
unsigned int thermal_cap_table_size;
};
/*
* These thermal boundaries are not set in thermal zone as trip-points, but
* must be below/above all other actually set DFLL thermal trip-points.
*/
#define DFLL_THERMAL_CAP_NOCAP 0
#define DFLL_THERMAL_FLOOR_NOFLOOR 125000
int tegra_dfll_register(struct platform_device *pdev,
struct tegra_dfll_soc_data *soc);
struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
void tegra_dfll_suspend(struct platform_device *pdev);
void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll);
int tegra_dfll_resume_tuning(struct device *dev);
int tegra_dfll_runtime_suspend(struct device *dev);
int tegra_dfll_runtime_resume(struct device *dev);
int tegra_dfll_suspend(struct device *dev);
int tegra_dfll_resume(struct device *dev);
#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */

3
drivers/clk/tegra/clk-tegra-periph.c
View File

@@ -878,6 +878,9 @@ static void __init periph_clk_init(void __iomem *clk_base,
if (!bank)
continue;
if (tegra_clks[data->clk_id].use_integer_div)
data->periph.divider.flags |= TEGRA_DIVIDER_INT;
data->periph.gate.regs = bank;
clk = tegra_clk_register_periph_data(clk_base, data);
*dt_clk = clk;

571
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
View File

@@ -17,15 +17,18 @@
#include <linux/regulator/consumer.h>
#include <soc/tegra/fuse.h>
#include <dt-bindings/thermal/tegra210-dfll-trips.h>
#include <dt-bindings/thermal/tegra210b01-trips.h>
#include "clk.h"
#include "clk-dfll.h"
#include "cvb.h"
struct dfll_fcpu_data {
const unsigned long *cpu_max_freq_table;
unsigned int cpu_max_freq_table_size;
const struct cvb_table *cpu_cvb_tables;
unsigned int cpu_cvb_tables_size;
const struct thermal_table *cpu_thermal_table;
};
/* Maximum CPU frequency, indexed by CPU speedo id */
@@ -42,6 +45,9 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
.process_id = -1,
.min_millivolts = 900,
.max_millivolts = 1260,
.alignment = {
.step_uv = 10000, /* 10mV */
},
.speedo_scale = 100,
.voltage_scale = 1000,
.entries = {
@@ -74,7 +80,7 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0x005020ff,
.tune0_high = 0x005040ff,
.tune1 = 0x00000060,
.tune1_low = 0x00000060,
}
},
};
@@ -97,142 +103,142 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 1007452, -23865, 370 } }, \
{ 306000000UL, { 1052709, -24875, 370 } }, \
{ 408000000UL, { 1099069, -25895, 370 } }, \
{ 510000000UL, { 1146534, -26905, 370 } }, \
{ 612000000UL, { 1195102, -27915, 370 } }, \
{ 714000000UL, { 1244773, -28925, 370 } }, \
{ 816000000UL, { 1295549, -29935, 370 } }, \
{ 918000000UL, { 1347428, -30955, 370 } }, \
{ 1020000000UL, { 1400411, -31965, 370 } }, \
{ 1122000000UL, { 1454497, -32975, 370 } }, \
{ 1224000000UL, { 1509687, -33985, 370 } }, \
{ 1326000000UL, { 1565981, -35005, 370 } }, \
{ 1428000000UL, { 1623379, -36015, 370 } }, \
{ 1530000000UL, { 1681880, -37025, 370 } }, \
{ 1632000000UL, { 1741485, -38035, 370 } }, \
{ 1734000000UL, { 1802194, -39055, 370 } }, \
{ 1836000000UL, { 1864006, -40065, 370 } }, \
{ 1912500000UL, { 1910780, -40815, 370 } }, \
{ 2014500000UL, { 1227000, 0, 0 } }, \
{ 2218500000UL, { 1227000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {1007452, -23865, 370} }, \
{306000000UL, {1052709, -24875, 370} }, \
{408000000UL, {1099069, -25895, 370} }, \
{510000000UL, {1146534, -26905, 370} }, \
{612000000UL, {1195102, -27915, 370} }, \
{714000000UL, {1244773, -28925, 370} }, \
{816000000UL, {1295549, -29935, 370} }, \
{918000000UL, {1347428, -30955, 370} }, \
{1020000000UL, {1400411, -31965, 370} }, \
{1122000000UL, {1454497, -32975, 370} }, \
{1224000000UL, {1509687, -33985, 370} }, \
{1326000000UL, {1565981, -35005, 370} }, \
{1428000000UL, {1623379, -36015, 370} }, \
{1530000000UL, {1681880, -37025, 370} }, \
{1632000000UL, {1741485, -38035, 370} }, \
{1734000000UL, {1802194, -39055, 370} }, \
{1836000000UL, {1864006, -40065, 370} }, \
{1912500000UL, {1910780, -40815, 370} }, \
{2014500000UL, {1227000, 0, 0} }, \
{2218500000UL, {1227000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_XA \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 1250024, -39785, 565 } }, \
{ 306000000UL, { 1297556, -41145, 565 } }, \
{ 408000000UL, { 1346718, -42505, 565 } }, \
{ 510000000UL, { 1397511, -43855, 565 } }, \
{ 612000000UL, { 1449933, -45215, 565 } }, \
{ 714000000UL, { 1503986, -46575, 565 } }, \
{ 816000000UL, { 1559669, -47935, 565 } }, \
{ 918000000UL, { 1616982, -49295, 565 } }, \
{ 1020000000UL, { 1675926, -50645, 565 } }, \
{ 1122000000UL, { 1736500, -52005, 565 } }, \
{ 1224000000UL, { 1798704, -53365, 565 } }, \
{ 1326000000UL, { 1862538, -54725, 565 } }, \
{ 1428000000UL, { 1928003, -56085, 565 } }, \
{ 1530000000UL, { 1995097, -57435, 565 } }, \
{ 1606500000UL, { 2046149, -58445, 565 } }, \
{ 1632000000UL, { 2063822, -58795, 565 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {1250024, -39785, 565} }, \
{306000000UL, {1297556, -41145, 565} }, \
{408000000UL, {1346718, -42505, 565} }, \
{510000000UL, {1397511, -43855, 565} }, \
{612000000UL, {1449933, -45215, 565} }, \
{714000000UL, {1503986, -46575, 565} }, \
{816000000UL, {1559669, -47935, 565} }, \
{918000000UL, {1616982, -49295, 565} }, \
{1020000000UL, {1675926, -50645, 565} }, \
{1122000000UL, {1736500, -52005, 565} }, \
{1224000000UL, {1798704, -53365, 565} }, \
{1326000000UL, {1862538, -54725, 565} }, \
{1428000000UL, {1928003, -56085, 565} }, \
{1530000000UL, {1995097, -57435, 565} }, \
{1606500000UL, {2046149, -58445, 565} }, \
{1632000000UL, {2063822, -58795, 565} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM1 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 734429, 0, 0 } }, \
{ 306000000UL, { 768191, 0, 0 } }, \
{ 408000000UL, { 801953, 0, 0 } }, \
{ 510000000UL, { 835715, 0, 0 } }, \
{ 612000000UL, { 869477, 0, 0 } }, \
{ 714000000UL, { 903239, 0, 0 } }, \
{ 816000000UL, { 937001, 0, 0 } }, \
{ 918000000UL, { 970763, 0, 0 } }, \
{ 1020000000UL, { 1004525, 0, 0 } }, \
{ 1122000000UL, { 1038287, 0, 0 } }, \
{ 1224000000UL, { 1072049, 0, 0 } }, \
{ 1326000000UL, { 1105811, 0, 0 } }, \
{ 1428000000UL, { 1130000, 0, 0 } }, \
{ 1555500000UL, { 1130000, 0, 0 } }, \
{ 1632000000UL, { 1170000, 0, 0 } }, \
{ 1734000000UL, { 1227500, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {734429, 0, 0} }, \
{306000000UL, {768191, 0, 0} }, \
{408000000UL, {801953, 0, 0} }, \
{510000000UL, {835715, 0, 0} }, \
{612000000UL, {869477, 0, 0} }, \
{714000000UL, {903239, 0, 0} }, \
{816000000UL, {937001, 0, 0} }, \
{918000000UL, {970763, 0, 0} }, \
{1020000000UL, {1004525, 0, 0} }, \
{1122000000UL, {1038287, 0, 0} }, \
{1224000000UL, {1072049, 0, 0} }, \
{1326000000UL, {1105811, 0, 0} }, \
{1428000000UL, {1130000, 0, 0} }, \
{1555500000UL, {1130000, 0, 0} }, \
{1632000000UL, {1170000, 0, 0} }, \
{1734000000UL, {1227500, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM2 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 742283, 0, 0 } }, \
{ 306000000UL, { 776249, 0, 0 } }, \
{ 408000000UL, { 810215, 0, 0 } }, \
{ 510000000UL, { 844181, 0, 0 } }, \
{ 612000000UL, { 878147, 0, 0 } }, \
{ 714000000UL, { 912113, 0, 0 } }, \
{ 816000000UL, { 946079, 0, 0 } }, \
{ 918000000UL, { 980045, 0, 0 } }, \
{ 1020000000UL, { 1014011, 0, 0 } }, \
{ 1122000000UL, { 1047977, 0, 0 } }, \
{ 1224000000UL, { 1081943, 0, 0 } }, \
{ 1326000000UL, { 1090000, 0, 0 } }, \
{ 1479000000UL, { 1090000, 0, 0 } }, \
{ 1555500000UL, { 1162000, 0, 0 } }, \
{ 1683000000UL, { 1195000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {742283, 0, 0} }, \
{306000000UL, {776249, 0, 0} }, \
{408000000UL, {810215, 0, 0} }, \
{510000000UL, {844181, 0, 0} }, \
{612000000UL, {878147, 0, 0} }, \
{714000000UL, {912113, 0, 0} }, \
{816000000UL, {946079, 0, 0} }, \
{918000000UL, {980045, 0, 0} }, \
{1020000000UL, {1014011, 0, 0} }, \
{1122000000UL, {1047977, 0, 0} }, \
{1224000000UL, {1081943, 0, 0} }, \
{1326000000UL, {1090000, 0, 0} }, \
{1479000000UL, {1090000, 0, 0} }, \
{1555500000UL, {1162000, 0, 0} }, \
{1683000000UL, {1195000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 742283, 0, 0 } }, \
{ 306000000UL, { 776249, 0, 0 } }, \
{ 408000000UL, { 810215, 0, 0 } }, \
{ 510000000UL, { 844181, 0, 0 } }, \
{ 612000000UL, { 878147, 0, 0 } }, \
{ 714000000UL, { 912113, 0, 0 } }, \
{ 816000000UL, { 946079, 0, 0 } }, \
{ 918000000UL, { 980045, 0, 0 } }, \
{ 1020000000UL, { 1014011, 0, 0 } }, \
{ 1122000000UL, { 1047977, 0, 0 } }, \
{ 1224000000UL, { 1081943, 0, 0 } }, \
{ 1326000000UL, { 1090000, 0, 0 } }, \
{ 1479000000UL, { 1090000, 0, 0 } }, \
{ 1504500000UL, { 1120000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {742283, 0, 0} }, \
{306000000UL, {776249, 0, 0} }, \
{408000000UL, {810215, 0, 0} }, \
{510000000UL, {844181, 0, 0} }, \
{612000000UL, {878147, 0, 0} }, \
{714000000UL, {912113, 0, 0} }, \
{816000000UL, {946079, 0, 0} }, \
{918000000UL, {980045, 0, 0} }, \
{1020000000UL, {1014011, 0, 0} }, \
{1122000000UL, {1047977, 0, 0} }, \
{1224000000UL, {1081943, 0, 0} }, \
{1326000000UL, {1090000, 0, 0} }, \
{1479000000UL, {1090000, 0, 0} }, \
{1504500000UL, {1120000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_ODN \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 721094, 0, 0 } }, \
{ 306000000UL, { 754040, 0, 0 } }, \
{ 408000000UL, { 786986, 0, 0 } }, \
{ 510000000UL, { 819932, 0, 0 } }, \
{ 612000000UL, { 852878, 0, 0 } }, \
{ 714000000UL, { 885824, 0, 0 } }, \
{ 816000000UL, { 918770, 0, 0 } }, \
{ 918000000UL, { 915716, 0, 0 } }, \
{ 1020000000UL, { 984662, 0, 0 } }, \
{ 1122000000UL, { 1017608, 0, 0 } }, \
{ 1224000000UL, { 1050554, 0, 0 } }, \
{ 1326000000UL, { 1083500, 0, 0 } }, \
{ 1428000000UL, { 1116446, 0, 0 } }, \
{ 1581000000UL, { 1130000, 0, 0 } }, \
{ 1683000000UL, { 1168000, 0, 0 } }, \
{ 1785000000UL, { 1227500, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {721094, 0, 0} }, \
{306000000UL, {754040, 0, 0} }, \
{408000000UL, {786986, 0, 0} }, \
{510000000UL, {819932, 0, 0} }, \
{612000000UL, {852878, 0, 0} }, \
{714000000UL, {885824, 0, 0} }, \
{816000000UL, {918770, 0, 0} }, \
{918000000UL, {915716, 0, 0} }, \
{1020000000UL, {984662, 0, 0} }, \
{1122000000UL, {1017608, 0, 0} }, \
{1224000000UL, {1050554, 0, 0} }, \
{1326000000UL, {1083500, 0, 0} }, \
{1428000000UL, {1116446, 0, 0} }, \
{1581000000UL, {1130000, 0, 0} }, \
{1683000000UL, {1168000, 0, 0} }, \
{1785000000UL, {1227500, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
static struct cvb_table tegra210_cpu_cvb_tables[] = {
struct cvb_table tegra210_cpu_cvb_tables[] = {
{
.speedo_id = 10,
.process_id = 0,
@@ -242,7 +248,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -255,7 +261,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -268,7 +274,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -280,7 +286,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -292,7 +298,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -304,7 +310,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -316,7 +322,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -329,7 +335,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -341,7 +347,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -352,7 +358,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
}
},
{
@@ -364,7 +370,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -377,7 +383,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
.tune_high_min_millivolts = 864,
}
},
@@ -389,7 +395,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
CPU_CVB_TABLE_XA,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x17711BD,
.tune1_low = 0x17711BD,
}
},
{
@@ -401,7 +407,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -414,7 +420,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
.tune_high_min_millivolts = 864,
}
},
@@ -426,7 +432,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
}
},
{
@@ -437,7 +443,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
}
},
{
@@ -449,7 +455,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -462,7 +468,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
.tune_high_min_millivolts = 864,
}
},
@@ -475,7 +481,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x20091d9,
.tune1_low = 0x20091d9,
.tune_high_min_millivolts = 864,
}
},
@@ -488,12 +494,213 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
.tune1 = 0x25501d0,
.tune1_low = 0x25501d0,
.tune_high_min_millivolts = 864,
}
},
};
static const unsigned long tegra210b01_cpu_max_freq_table[] = {
[0] = 1963500000UL,
[1] = 1963500000UL,
[2] = 2091000000UL,
[3] = 2014500000UL,
};
#define CPUB01_CVB_TABLE_SLT_B1 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
/* f c0, c1, c2 */ \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 600000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FFA0, \
.tune0_high = 0x0000FFFF, \
.tune1_low = 0x21107FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3-AggressiveSLT"
#define CPUB01_CVB_TABLE_SLT_B0 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
/* f c0, c1, c2 */ \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 600000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FF90, \
.tune0_high = 0x0000FFFF, \
.tune1_low = 0x21107FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3-AggressiveSLT"
#define CPUB01_CVB_TABLE \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
/* f c0, c1, c2 */ \
{ 204000000UL, { 721589, -12695, 27 } }, \
{ 306000000UL, { 747134, -14195, 27 } }, \
{ 408000000UL, { 776324, -15705, 27 } }, \
{ 510000000UL, { 809160, -17205, 27 } }, \
{ 612000000UL, { 845641, -18715, 27 } }, \
{ 714000000UL, { 885768, -20215, 27 } }, \
{ 816000000UL, { 929540, -21725, 27 } }, \
{ 918000000UL, { 976958, -23225, 27 } }, \
{ 1020000000UL, { 1028021, -24725, 27 } }, \
{ 1122000000UL, { 1082730, -26235, 27 } }, \
{ 1224000000UL, { 1141084, -27735, 27 } }, \
{ 1326000000UL, { 1203084, -29245, 27 } }, \
{ 1428000000UL, { 1268729, -30745, 27 } }, \
{ 1581000000UL, { 1374032, -33005, 27 } }, \
{ 1683000000UL, { 1448791, -34505, 27 } }, \
{ 1785000000UL, { 1527196, -36015, 27 } }, \
{ 1887000000UL, { 1609246, -37515, 27 } }, \
{ 1963500000UL, { 1675751, -38635, 27 } }, \
{ 2014500000UL, { 1716501, -39395, 27 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 620000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FFCF, \
.tune1_low = 0x012207FF, \
.tune1_high = 0x03FFF7FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3"
struct cvb_table tegra210b01_cpu_cvb_tables[] = {
{
.speedo_id = 3,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
},
{
.speedo_id = 2,
.process_id = 1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B1,
},
{
.speedo_id = 2,
.process_id = 0,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B0,
},
{
.speedo_id = -1,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
},
};
static struct thermal_tv tegra210_thermal_floor_table[] = {
{TEGRA210_DFLL_THERMAL_FLOOR_0 / 1000, 950},
{DFLL_THERMAL_FLOOR_NOFLOOR / 1000, 0},
};
static const struct thermal_tv tegra210_thermal_cap_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210_DFLL_THERMAL_CAP_0 / 1000, 1170},
{TEGRA210_DFLL_THERMAL_CAP_1 / 1000, 1132},
};
static const struct thermal_tv tegra210_thermal_cap_ucm2_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210_DFLL_THERMAL_CAP_0 / 1000, 1162},
{TEGRA210_DFLL_THERMAL_CAP_1 / 1000, 1090},
};
static const struct thermal_table tegra210_cpu_thermal_table = {
.thermal_floor_table = tegra210_thermal_floor_table,
.thermal_floor_table_size = ARRAY_SIZE(tegra210_thermal_floor_table),
.coefficients = { {800000, 0, 0}, 0, 0, 0 },
.speedo_scale = 100,
.voltage_scale = 1000,
.temp_scale = 10,
.thermal_cap_table = tegra210_thermal_cap_table,
.thermal_cap_table_size = ARRAY_SIZE(tegra210_thermal_cap_table),
.thermal_cap_ucm2_table = tegra210_thermal_cap_ucm2_table,
.thermal_cap_ucm2_table_size = ARRAY_SIZE(tegra210_thermal_cap_ucm2_table),
};
static struct thermal_tv tegra210b01_thermal_floor_table[] = {
{TEGRA210B01_DFLL_THERMAL_FLOOR_0 / 1000, 800},
{TEGRA210B01_DFLL_THERMAL_FLOOR_1 / 1000, 0},
{DFLL_THERMAL_FLOOR_NOFLOOR / 1000, 0},
};
static const struct thermal_tv tegra210b01_thermal_cap_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210B01_DFLL_THERMAL_CAP_0 / 1000, 1060},
{TEGRA210B01_DFLL_THERMAL_CAP_1 / 1000, 1010},
};
static const struct thermal_table tegra210b01_cpu_thermal_table = {
.thermal_floor_table = tegra210b01_thermal_floor_table,
.thermal_floor_table_size = ARRAY_SIZE(tegra210b01_thermal_floor_table),
.speedo_scale = 100,
.voltage_scale = 1000,
.temp_scale = 10,
.thermal_cap_table = tegra210b01_thermal_cap_table,
.thermal_cap_table_size = ARRAY_SIZE(tegra210b01_thermal_cap_table),
.thermal_cap_ucm2_table = tegra210b01_thermal_cap_table,
.thermal_cap_ucm2_table_size = ARRAY_SIZE(tegra210b01_thermal_cap_table)
};
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@@ -506,6 +713,15 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
.cpu_cvb_tables = tegra210_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
.cpu_thermal_table = &tegra210_cpu_thermal_table
};
static const struct dfll_fcpu_data tegra210b01_dfll_fcpu_data = {
.cpu_max_freq_table = tegra210b01_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210b01_cpu_max_freq_table),
.cpu_cvb_tables = tegra210b01_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210b01_cpu_cvb_tables),
.cpu_thermal_table = &tegra210b01_cpu_thermal_table
};
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
@@ -517,50 +733,76 @@ static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
.compatible = "nvidia,tegra210-dfll",
.data = &tegra210_dfll_fcpu_data
},
{
.compatible = "nvidia,tegra210b01-dfll",
.data = &tegra210b01_dfll_fcpu_data
},
{ },
};
static void get_alignment_from_dt(struct device *dev,
struct rail_alignment *align)
{
align->step_uv = 0;
align->offset_uv = 0;
if (of_property_read_u32(dev->of_node,
"nvidia,pwm-voltage-step-microvolts",
&align->step_uv))
align->step_uv = 0;
if (of_property_read_u32(dev->of_node,
"nvidia,pwm-min-microvolts",
&align->offset_uv))
"nvidia,pwm-min-microvolts", &align->offset_uv))
align->offset_uv = 0;
}
static int get_alignment_from_regulator(struct device *dev,
struct rail_alignment *align)
{
struct regulator *reg = regulator_get(dev, "vdd-cpu");
int min_uV, max_uV, n_voltages, ret;
struct regulator *reg = devm_regulator_get(dev, "vdd-cpu");
if (IS_ERR(reg))
return PTR_ERR(reg);
align->offset_uv = regulator_list_voltage(reg, 0);
align->step_uv = regulator_get_linear_step(reg);
ret = regulator_get_constraint_voltages(reg, &min_uV, &max_uV);
if (!ret)
align->offset_uv = min_uV;
regulator_put(reg);
align->step_uv = regulator_get_linear_step(reg);
if (!align->step_uv && !ret) {
n_voltages = regulator_count_voltages(reg);
if (n_voltages > 1)
align->step_uv = (max_uV - min_uV) / (n_voltages - 1);
}
devm_regulator_put(reg);
return 0;
}
#define INIT_TUNE_PRAM(p) \
do { \
if (of_property_read_u32(pdev->dev.of_node, \
"nvidia,dfll-override-" #p, &soc->p)) \
soc->p = soc->cvb->cpu_dfll_data.p; \
} while (0)
static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
{
int process_id, speedo_id, speedo_value, err;
struct tegra_dfll_soc_data *soc;
const struct dfll_fcpu_data *fcpu_data;
struct rail_alignment align;
const struct thermal_table *thermal;
unsigned long max_freq;
u32 f;
bool ucm2;
fcpu_data = of_device_get_match_data(&pdev->dev);
if (!fcpu_data)
return -ENODEV;
ucm2 = tegra_sku_info.ucm == TEGRA_UCM2;
process_id = tegra_sku_info.cpu_process_id;
speedo_id = tegra_sku_info.cpu_speedo_id;
speedo_value = tegra_sku_info.cpu_speedo_value;
@@ -570,6 +812,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
speedo_id);
return -ENODEV;
}
max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
if (!of_property_read_u32(pdev->dev.of_node, "nvidia,dfll-max-freq-khz",
&f))
max_freq = min(max_freq, f * 1000UL);
soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
if (!soc)
@@ -581,20 +827,33 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return -ENODEV;
}
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) {
get_alignment_from_dt(&pdev->dev, &align);
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")
&& (!align.step_uv || !align.offset_uv)) {
dev_info(&pdev->dev, "Missing required align data in DT");
return -EINVAL;
} else {
if (!align.step_uv) {
dev_info(&pdev->dev, "no align data in DT, try from vdd-cpu\n");
err = get_alignment_from_regulator(&pdev->dev, &align);
if (err)
return err;
if (err == -EPROBE_DEFER) {
dev_info(&pdev->dev, "defer probe to get vdd-cpu\n");
return -EPROBE_DEFER;
}
}
}
soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
if (!align.step_uv) {
dev_err(&pdev->dev, "missing step uv\n");
return -EINVAL;
}
soc->max_freq = max_freq;
soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
fcpu_data->cpu_cvb_tables_size,
&align, process_id, speedo_id,
speedo_value, soc->max_freq);
speedo_value, soc->max_freq,
&soc->min_millivolts);
soc->alignment = align;
if (IS_ERR(soc->cvb)) {
@@ -603,6 +862,33 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return PTR_ERR(soc->cvb);
}
INIT_TUNE_PRAM(tune0_low);
INIT_TUNE_PRAM(tune0_high);
INIT_TUNE_PRAM(tune1_low);
INIT_TUNE_PRAM(tune1_high);
INIT_TUNE_PRAM(tune_high_min_millivolts);
INIT_TUNE_PRAM(tune_high_margin_millivolts);
thermal = fcpu_data->cpu_thermal_table;
err = tegra_cvb_build_thermal_table(thermal, speedo_value,
soc->min_millivolts);
if (err < 0) {
pr_warn("couldn't build thermal floor table\n");
} else {
soc->thermal_floor_table = thermal->thermal_floor_table;
soc->thermal_floor_table_size = thermal->thermal_floor_table_size;
}
if (thermal && thermal->thermal_cap_table && !ucm2) {
soc->thermal_cap_table = thermal->thermal_cap_table;
soc->thermal_cap_table_size = thermal->thermal_cap_table_size;
} else if (thermal && thermal->thermal_cap_ucm2_table && ucm2) {
soc->thermal_cap_table = thermal->thermal_cap_ucm2_table;
soc->thermal_cap_table_size = thermal->thermal_cap_ucm2_table_size;
} else {
pr_warn("couldn't get thermal cap table\n");
}
err = tegra_dfll_register(pdev, soc);
if (err < 0) {
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
@@ -616,13 +902,10 @@ static void tegra124_dfll_fcpu_remove(struct platform_device *pdev)
{
struct tegra_dfll_soc_data *soc;
/*
* Note that exiting early here is dangerous as after this function
* returns *soc is freed.
*/
soc = tegra_dfll_unregister(pdev);
if (IS_ERR(soc))
return;
dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
PTR_ERR(soc));
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
}
@@ -630,7 +913,7 @@ static void tegra124_dfll_fcpu_remove(struct platform_device *pdev)
static const struct dev_pm_ops tegra124_dfll_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
tegra_dfll_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, tegra_dfll_resume_tuning)
};
static struct platform_driver tegra124_dfll_fcpu_driver = {

3520
drivers/clk/tegra/clk-tegra210b01.c Normal file
View File

File diff suppressed because it is too large Load Diff

5
drivers/clk/tegra/clk-utils.c
View File

@@ -31,7 +31,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
if (flags & TEGRA_DIVIDER_INT)
divider_ux1 *= mul;
if (divider_ux1 < mul)
if (!div1_5_not_allowed && divider_ux1 < mul)
return 0;
divider_ux1 -= mul;
@@ -39,5 +39,8 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
if (divider_ux1 > div_mask(width))
return div_mask(width);
if (div1_5_not_allowed && (divider_ux1 > 0) && (divider_ux1 < mul))
divider_ux1 = (flags & TEGRA_DIVIDER_ROUND_UP) ? mul : 0;
return divider_ux1;
}

19
drivers/clk/tegra/clk.c
View File

@@ -26,6 +26,7 @@ static struct tegra_cpu_car_ops dummy_car_ops;
struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
int *periph_clk_enb_refcnt;
bool div1_5_not_allowed;
static int periph_banks;
static u32 *periph_state_ctx;
static struct clk **clks;
@@ -291,13 +292,27 @@ void tegra_init_from_table(struct tegra_clk_init_table *tbl,
}
}
if (tbl->rate)
if (clk_set_rate(clk, tbl->rate)) {
if (tbl->rate) {
bool can_set_rate = true;
if ((tbl->flags & TEGRA_TABLE_RATE_CHANGE_OVERCLOCK) &&
__clk_is_enabled(clk)) {
if (tbl->rate != clk_get_rate(clk)) {
pr_err("%s: Can't set rate %lu of %s\n",
__func__, tbl->rate,
__clk_get_name(clk));
WARN_ON(1);
}
can_set_rate = false;
}
if (can_set_rate && clk_set_rate(clk, tbl->rate)) {
pr_err("%s: Failed to set rate %lu of %s\n",
__func__, tbl->rate,
__clk_get_name(clk));
WARN_ON(1);
}
}
if (tbl->state)
if (clk_prepare_enable(clk)) {

6
drivers/clk/tegra/clk.h
View File

@@ -87,6 +87,7 @@ struct tegra_clk_sync_source {
extern const struct clk_ops tegra_clk_sync_source_ops;
extern int *periph_clk_enb_refcnt;
extern bool div1_5_not_allowed;
struct clk *tegra_clk_register_sync_source(const char *name,
unsigned long max_rate);
@@ -801,14 +802,18 @@ struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
* @parent_id: parent clock id as mentioned in device tree bindings
* @rate: rate to set
* @state: enable/disable
* @flags: clock initialization flags
*/
struct tegra_clk_init_table {
unsigned int clk_id;
unsigned int parent_id;
unsigned long rate;
int state;
u32 flags;
};
#define TEGRA_TABLE_RATE_CHANGE_OVERCLOCK BIT(0)
/**
* struct clk_duplicate - duplicate clocks
* @clk_id: clock id as mentioned in device tree bindings
@@ -831,6 +836,7 @@ struct tegra_clk_duplicate {
struct tegra_clk {
int dt_id;
bool present;
bool use_integer_div;
};
struct tegra_devclk {

121
drivers/clk/tegra/cvb.c
View File

@@ -11,7 +11,7 @@
#include "cvb.h"
/* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) */
static inline int get_cvb_voltage(int speedo, int s_scale,
int tegra_get_cvb_voltage(int speedo, int s_scale,
const struct cvb_coefficients *cvb)
{
int mv;
@@ -22,7 +22,20 @@ static inline int get_cvb_voltage(int speedo, int s_scale,
return mv;
}
static int round_cvb_voltage(int mv, int v_scale,
/* cvb_t_mv =
((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale) / v_scale */
int tegra_get_cvb_t_voltage(int speedo, int s_scale, int t, int t_scale,
struct cvb_coefficients *cvb)
{
/* apply speedo & temperature scales: output mv = cvb_t_mv * v_scale */
int mv;
mv = DIV_ROUND_CLOSEST(cvb->c3 * speedo, s_scale) + cvb->c4 +
DIV_ROUND_CLOSEST(cvb->c5 * t, t_scale);
mv = DIV_ROUND_CLOSEST(mv * t, t_scale);
return mv;
}
int tegra_round_cvb_voltage(int mv, int v_scale,
const struct rail_alignment *align)
{
/* combined: apply voltage scale and round to cvb alignment step */
@@ -40,7 +53,7 @@ enum {
UP
};
static int round_voltage(int mv, const struct rail_alignment *align, int up)
int tegra_round_voltage(int mv, const struct rail_alignment *align, int up)
{
if (align->step_uv) {
int uv;
@@ -52,14 +65,46 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up)
return mv;
}
/**
* cvb_t_mv =
* ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) +
* ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale)
*/
static inline int get_cvb_thermal_floor(int speedo, int temp,
int s_scale, int t_scale,
const struct thermal_coefficients *coef)
{
int cvb_mv, mv;
cvb_mv = tegra_get_cvb_voltage(speedo, s_scale, &coef->cvb_coef);
mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +
DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv;
return mv;
}
static int build_opp_table(struct device *dev, const struct cvb_table *table,
struct rail_alignment *align,
int speedo_value, unsigned long max_freq)
int speedo_value, unsigned long max_freq, int *vmin)
{
int i, ret, dfll_mv, min_mv, max_mv;
min_mv = round_voltage(table->min_millivolts, align, UP);
max_mv = round_voltage(table->max_millivolts, align, DOWN);
if (!align->step_uv)
align->step_uv = table->alignment.step_uv;
if (!align->step_uv)
return -EINVAL;
if (!align->offset_uv)
align->offset_uv = table->alignment.offset_uv;
min_mv = tegra_round_voltage(table->min_millivolts, align, UP);
max_mv = tegra_round_voltage(table->max_millivolts, align, DOWN);
dfll_mv = tegra_get_cvb_voltage(
speedo_value, table->speedo_scale, &table->vmin_coefficients);
dfll_mv = tegra_round_cvb_voltage(dfll_mv, table->voltage_scale, align);
min_mv = max(min_mv, dfll_mv);
for (i = 0; i < MAX_DVFS_FREQS; i++) {
const struct cvb_table_freq_entry *entry = &table->entries[i];
@@ -67,10 +112,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
if (!entry->freq || (entry->freq > max_freq))
break;
dfll_mv = get_cvb_voltage(speedo_value, table->speedo_scale,
&entry->coefficients);
dfll_mv = round_cvb_voltage(dfll_mv, table->voltage_scale,
align);
dfll_mv = tegra_get_cvb_voltage(
speedo_value, table->speedo_scale, &entry->coefficients);
dfll_mv = tegra_round_cvb_voltage(dfll_mv, table->voltage_scale, align);
dfll_mv = clamp(dfll_mv, min_mv, max_mv);
ret = dev_pm_opp_add(dev, entry->freq, dfll_mv * 1000);
@@ -78,32 +122,35 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
return ret;
}
if (vmin)
*vmin = min_mv;
return 0;
}
/**
* tegra_cvb_add_opp_table - build OPP table from Tegra CVB tables
* @dev: the struct device * for which the OPP table is built
* @tables: array of CVB tables
* @count: size of the previously mentioned array
* @align: parameters of the regulator step and offset
* @cvb_tables: array of CVB tables
* @sz: size of the previously mentioned array
* @process_id: process id of the HW module
* @speedo_id: speedo id of the HW module
* @speedo_value: speedo value of the HW module
* @max_freq: highest safe clock rate
* @max_rate: highest safe clock rate
* @opp_dev: the struct device * for which the OPP table is built
* @vmin: final minimum voltage returned to the caller
*
* On Tegra, a CVB table encodes the relationship between operating voltage
* and safe maximal frequency for a given module (e.g. GPU or CPU). This
* function calculates the optimal voltage-frequency operating points
* for the given arguments and exports them via the OPP library for the
* given @dev. Returns a pointer to the struct cvb_table that matched
* given @opp_dev. Returns a pointer to the struct cvb_table that matched
* or an ERR_PTR on failure.
*/
const struct cvb_table *
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
size_t count, struct rail_alignment *align,
int process_id, int speedo_id, int speedo_value,
unsigned long max_freq)
unsigned long max_freq, int *vmin)
{
size_t i;
int ret;
@@ -118,7 +165,7 @@ tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
continue;
ret = build_opp_table(dev, table, align, speedo_value,
max_freq);
max_freq, vmin);
return ret ? ERR_PTR(ret) : table;
}
@@ -140,3 +187,41 @@ void tegra_cvb_remove_opp_table(struct device *dev,
dev_pm_opp_remove(dev, entry->freq);
}
}
/**
* tegra_cvb_build_thermal_table - build thermal table from Tegra CVB tables
* @table: the hardware characterization thermal table
* @speedo_value: speedo value of the HW module
* @soc_min_mv: minimum voltage applied across all temperature ranges
*
* The minimum voltage for the IP blocks inside Tegra SoCs might depend on
* the current temperature. This function calculates the voltage-thermal
* relations according to the given coefficients. Note that if the
* coefficients are not defined, the fixed thermal floors in the @table will
* be used. Returns 0 on success or a negative error code on failure.
*/
int tegra_cvb_build_thermal_table(const struct thermal_table *table,
int speedo_value, unsigned int soc_min_mv)
{
int i;
if (!table)
return -EINVAL;
/* The vmin for the lowest trip point is fixed */
for (i = 1; i < table->thermal_floor_table_size; i++) {
unsigned int mv;
mv = get_cvb_thermal_floor(speedo_value,
table->thermal_floor_table[i-1].temp,
table->speedo_scale,
table->temp_scale,
&table->coefficients);
mv = DIV_ROUND_UP(mv, table->voltage_scale);
mv = max(mv, soc_min_mv);
table->thermal_floor_table[i].millivolts = max(mv,
table->thermal_floor_table[i].millivolts);
}
return 0;
}

60
drivers/clk/tegra/cvb.h
View File

@@ -21,6 +21,9 @@ struct cvb_coefficients {
int c0;
int c1;
int c2;
int c3;
int c4;
int c5;
};
struct cvb_table_freq_entry {
@@ -31,8 +34,24 @@ struct cvb_table_freq_entry {
struct cvb_cpu_dfll_data {
u32 tune0_low;
u32 tune0_high;
u32 tune1;
u32 tune1_low;
u32 tune1_high;
unsigned int tune_high_min_millivolts;
unsigned int tune_high_margin_millivolts;
unsigned long dvco_calibration_max;
};
struct thermal_coefficients {
struct cvb_coefficients cvb_coef;
int c3;
int c4;
int c5;
};
/* Thermal trips and voltages */
struct thermal_tv {
int temp;
unsigned int millivolts;
};
struct cvb_table {
@@ -41,20 +60,57 @@ struct cvb_table {
int min_millivolts;
int max_millivolts;
struct rail_alignment alignment;
int speedo_scale;
int voltage_scale;
struct cvb_table_freq_entry entries[MAX_DVFS_FREQS];
struct cvb_cpu_dfll_data cpu_dfll_data;
struct cvb_coefficients vmin_coefficients;
const char *cvb_version;
};
const struct cvb_table *
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
size_t count, struct rail_alignment *align,
int process_id, int speedo_id, int speedo_value,
unsigned long max_freq);
unsigned long max_freq, int *vmin);
void tegra_cvb_remove_opp_table(struct device *dev,
const struct cvb_table *table,
unsigned long max_freq);
struct thermal_table {
struct thermal_tv *thermal_floor_table;
unsigned int thermal_floor_table_size;
struct thermal_coefficients coefficients;
unsigned int speedo_scale;
unsigned int voltage_scale;
unsigned int temp_scale;
const struct thermal_tv *thermal_cap_table;
unsigned int thermal_cap_table_size;
const struct thermal_tv *thermal_cap_ucm2_table;
unsigned int thermal_cap_ucm2_table_size;
};
const struct cvb_table *tegra_cvb_build_opp_table(
const struct cvb_table *cvb_tables,
size_t sz,
const struct rail_alignment *align,
int process_id,
int speedo_id,
int speedo_value,
unsigned long max_rate,
struct device *opp_dev);
int tegra_get_cvb_voltage(int speedo, int s_scale,
const struct cvb_coefficients *cvb);
int tegra_round_cvb_voltage(int mv, int v_scale,
const struct rail_alignment *align);
int tegra_round_voltage(int mv, const struct rail_alignment *align, int up);
int tegra_get_cvb_t_voltage(int speedo, int s_scale, int t, int t_scale,
struct cvb_coefficients *cvb);
int tegra_cvb_build_thermal_table(const struct thermal_table *table,
int speedo_value, unsigned int soc_min_mv);
#endif

2
drivers/cpufreq/Kconfig.arm
View File

@@ -229,7 +229,7 @@ config ARM_TEGRA20_CPUFREQ
This adds the CPUFreq driver support for Tegra20/30 SOCs.
config ARM_TEGRA124_CPUFREQ
bool "Tegra124 CPUFreq support"
tristate "Tegra124 CPUFreq support"
depends on ARCH_TEGRA || COMPILE_TEST
depends on CPUFREQ_DT
default y

11
drivers/cpufreq/cpufreq-dt.c
View File

@@ -349,6 +349,17 @@ static struct platform_driver dt_cpufreq_platdrv = {
};
module_platform_driver(dt_cpufreq_platdrv);
struct platform_device *cpufreq_dt_pdev_register(struct device *dev)
{
struct platform_device_info cpufreq_dt_devinfo = {};
cpufreq_dt_devinfo.name = "cpufreq-dt";
cpufreq_dt_devinfo.parent = dev;
return platform_device_register_full(&cpufreq_dt_devinfo);
}
EXPORT_SYMBOL_GPL(cpufreq_dt_pdev_register);
MODULE_ALIAS("platform:cpufreq-dt");
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");

2
drivers/cpufreq/cpufreq-dt.h
View File

@@ -22,4 +22,6 @@ struct cpufreq_dt_platform_data {
int (*resume)(struct cpufreq_policy *policy);
};
struct platform_device *cpufreq_dt_pdev_register(struct device *dev);
#endif /* __CPUFREQ_DT_H__ */

1
drivers/cpufreq/cpufreq.c
View File

@@ -107,6 +107,7 @@ void disable_cpufreq(void)
{
off = 1;
}
EXPORT_SYMBOL_GPL(disable_cpufreq);
static DEFINE_MUTEX(cpufreq_governor_mutex);
bool have_governor_per_policy(void)

44
drivers/cpufreq/tegra124-cpufreq.c
View File

@@ -16,6 +16,10 @@
#include <linux/pm_opp.h>
#include <linux/types.h>
#include "cpufreq-dt.h"
static struct platform_device *tegra124_cpufreq_pdev;
struct tegra124_cpufreq_priv {
struct clk *cpu_clk;
struct clk *pllp_clk;
@@ -55,7 +59,6 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
struct device_node *np __free(device_node) = of_cpu_device_node_get(0);
struct tegra124_cpufreq_priv *priv;
struct device *cpu_dev;
struct platform_device_info cpufreq_dt_devinfo = {};
int ret;
if (!np)
@@ -95,11 +98,7 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
if (ret)
goto out_put_pllp_clk;
cpufreq_dt_devinfo.name = "cpufreq-dt";
cpufreq_dt_devinfo.parent = &pdev->dev;
priv->cpufreq_dt_pdev =
platform_device_register_full(&cpufreq_dt_devinfo);
priv->cpufreq_dt_pdev = cpufreq_dt_pdev_register(&pdev->dev);
if (IS_ERR(priv->cpufreq_dt_pdev)) {
ret = PTR_ERR(priv->cpufreq_dt_pdev);
goto out_put_pllp_clk;
@@ -173,6 +172,21 @@ disable_cpufreq:
return err;
}
static void tegra124_cpufreq_remove(struct platform_device *pdev)
{
struct tegra124_cpufreq_priv *priv = dev_get_drvdata(&pdev->dev);
if (!IS_ERR(priv->cpufreq_dt_pdev)) {
platform_device_unregister(priv->cpufreq_dt_pdev);
priv->cpufreq_dt_pdev = ERR_PTR(-ENODEV);
}
clk_put(priv->pllp_clk);
clk_put(priv->pllx_clk);
clk_put(priv->dfll_clk);
clk_put(priv->cpu_clk);
}
static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
tegra124_cpufreq_resume)
@@ -182,12 +196,12 @@ static struct platform_driver tegra124_cpufreq_platdrv = {
.driver.name = "cpufreq-tegra124",
.driver.pm = &tegra124_cpufreq_pm_ops,
.probe = tegra124_cpufreq_probe,
.remove = tegra124_cpufreq_remove,
};
static int __init tegra_cpufreq_init(void)
{
int ret;
struct platform_device *pdev;
if (!(of_machine_is_compatible("nvidia,tegra124") ||
of_machine_is_compatible("nvidia,tegra210")))
@@ -201,15 +215,25 @@ static int __init tegra_cpufreq_init(void)
if (ret)
return ret;
pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
if (IS_ERR(pdev)) {
tegra124_cpufreq_pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
if (IS_ERR(tegra124_cpufreq_pdev)) {
platform_driver_unregister(&tegra124_cpufreq_platdrv);
return PTR_ERR(pdev);
return PTR_ERR(tegra124_cpufreq_pdev);
}
return 0;
}
module_init(tegra_cpufreq_init);
static void __exit tegra_cpufreq_module_exit(void)
{
if (!IS_ERR_OR_NULL(tegra124_cpufreq_pdev))
platform_device_unregister(tegra124_cpufreq_pdev);
platform_driver_unregister(&tegra124_cpufreq_platdrv);
}
module_exit(tegra_cpufreq_module_exit);
MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");
MODULE_LICENSE("GPL");

189
drivers/cpufreq/tegra186-cpufreq.c
View File

@@ -8,6 +8,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/units.h>
#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>
@@ -58,7 +59,7 @@ static const struct tegra186_cpufreq_cpu tegra186_cpus[] = {
};
struct tegra186_cpufreq_cluster {
struct cpufreq_frequency_table *table;
struct cpufreq_frequency_table *bpmp_lut;
u32 ref_clk_khz;
u32 div;
};
@@ -66,18 +67,145 @@ struct tegra186_cpufreq_cluster {
struct tegra186_cpufreq_data {
void __iomem *regs;
const struct tegra186_cpufreq_cpu *cpus;
bool icc_dram_bw_scaling;
struct tegra186_cpufreq_cluster clusters[];
};
static int tegra_cpufreq_set_bw(struct cpufreq_policy *policy, unsigned long freq_khz)
{
struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
struct device *dev;
int ret;
dev = get_cpu_device(policy->cpu);
if (!dev)
return -ENODEV;
struct dev_pm_opp *opp =
dev_pm_opp_find_freq_exact(dev, freq_khz * HZ_PER_KHZ, true);
if (IS_ERR(opp))
return PTR_ERR(opp);
ret = dev_pm_opp_set_opp(dev, opp);
if (ret)
data->icc_dram_bw_scaling = false;
dev_pm_opp_put(opp);
return ret;
}
static int tegra_cpufreq_init_cpufreq_table(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *bpmp_lut,
struct cpufreq_frequency_table **opp_table)
{
struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
struct cpufreq_frequency_table *freq_table = NULL;
struct cpufreq_frequency_table *pos;
struct device *cpu_dev;
struct dev_pm_opp *opp;
unsigned long rate;
int ret, max_opps;
int j = 0;
cpu_dev = get_cpu_device(policy->cpu);
if (!cpu_dev) {
pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu);
return -ENODEV;
}
/* Initialize OPP table mentioned in operating-points-v2 property in DT */
ret = dev_pm_opp_of_add_table_indexed(cpu_dev, 0);
if (ret) {
dev_err(cpu_dev, "Invalid or empty opp table in device tree\n");
data->icc_dram_bw_scaling = false;
return ret;
}
max_opps = dev_pm_opp_get_opp_count(cpu_dev);
if (max_opps <= 0) {
dev_err(cpu_dev, "Failed to add OPPs\n");
return max_opps;
}
/* Disable all opps and cross-validate against LUT later */
for (rate = 0; ; rate++) {
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
if (IS_ERR(opp))
break;
dev_pm_opp_put(opp);
dev_pm_opp_disable(cpu_dev, rate);
}
freq_table = kcalloc((max_opps + 1), sizeof(*freq_table), GFP_KERNEL);
if (!freq_table)
return -ENOMEM;
/*
* Cross check the frequencies from BPMP-FW LUT against the OPP's present in DT.
* Enable only those DT OPP's which are present in LUT also.
*/
cpufreq_for_each_valid_entry(pos, bpmp_lut) {
opp = dev_pm_opp_find_freq_exact(cpu_dev, pos->frequency * HZ_PER_KHZ, false);
if (IS_ERR(opp))
continue;
dev_pm_opp_put(opp);
ret = dev_pm_opp_enable(cpu_dev, pos->frequency * HZ_PER_KHZ);
if (ret < 0)
return ret;
freq_table[j].driver_data = pos->driver_data;
freq_table[j].frequency = pos->frequency;
j++;
}
freq_table[j].driver_data = pos->driver_data;
freq_table[j].frequency = CPUFREQ_TABLE_END;
*opp_table = &freq_table[0];
dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
/* Prime interconnect data */
tegra_cpufreq_set_bw(policy, freq_table[j - 1].frequency);
return ret;
}
static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
{
struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;
struct cpufreq_frequency_table *freq_table;
struct cpufreq_frequency_table *bpmp_lut;
u32 cpu;
int ret;
policy->freq_table = data->clusters[cluster].table;
policy->cpuinfo.transition_latency = 300 * 1000;
policy->driver_data = NULL;
/* set same policy for all cpus in a cluster */
for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) {
if (data->cpus[cpu].bpmp_cluster_id == cluster)
cpumask_set_cpu(cpu, policy->cpus);
}
bpmp_lut = data->clusters[cluster].bpmp_lut;
if (data->icc_dram_bw_scaling) {
ret = tegra_cpufreq_init_cpufreq_table(policy, bpmp_lut, &freq_table);
if (!ret) {
policy->freq_table = freq_table;
return 0;
}
}
data->icc_dram_bw_scaling = false;
policy->freq_table = bpmp_lut;
pr_info("OPP tables missing from DT, EMC frequency scaling disabled\n");
return 0;
}
@@ -86,10 +214,18 @@ static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
{
struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
struct cpufreq_frequency_table *tbl = policy->freq_table + index;
unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset;
unsigned int edvd_offset;
u32 edvd_val = tbl->driver_data;
u32 cpu;
for_each_cpu(cpu, policy->cpus) {
edvd_offset = data->cpus[cpu].edvd_offset;
writel(edvd_val, data->regs + edvd_offset);
}
if (data->icc_dram_bw_scaling)
tegra_cpufreq_set_bw(policy, tbl->frequency);
return 0;
}
@@ -126,15 +262,16 @@ static struct cpufreq_driver tegra186_cpufreq_driver = {
.attr = cpufreq_generic_attr,
};
static struct cpufreq_frequency_table *init_vhint_table(
static struct cpufreq_frequency_table *tegra_cpufreq_bpmp_read_lut(
struct platform_device *pdev, struct tegra_bpmp *bpmp,
struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id)
struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id,
int *num_rates)
{
struct cpufreq_frequency_table *table;
struct mrq_cpu_vhint_request req;
struct tegra_bpmp_message msg;
struct cpu_vhint_data *data;
int err, i, j, num_rates = 0;
int err, i, j;
dma_addr_t phys;
void *virt;
@@ -164,6 +301,7 @@ static struct cpufreq_frequency_table *init_vhint_table(
goto free;
}
*num_rates = 0;
for (i = data->vfloor; i <= data->vceil; i++) {
u16 ndiv = data->ndiv[i];
@@ -174,10 +312,10 @@ static struct cpufreq_frequency_table *init_vhint_table(
if (i > 0 && ndiv == data->ndiv[i - 1])
continue;
num_rates++;
(*num_rates)++;
}
table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
table = devm_kcalloc(&pdev->dev, *num_rates + 1, sizeof(*table),
GFP_KERNEL);
if (!table) {
table = ERR_PTR(-ENOMEM);
@@ -219,7 +357,10 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
{
struct tegra186_cpufreq_data *data;
struct tegra_bpmp *bpmp;
unsigned int i = 0, err;
struct device *cpu_dev;
unsigned int i = 0, err, edvd_offset;
int num_rates = 0;
u32 edvd_val, cpu;
data = devm_kzalloc(&pdev->dev,
struct_size(data, clusters, TEGRA186_NUM_CLUSTERS),
@@ -242,15 +383,39 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) {
struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
cluster->table = init_vhint_table(pdev, bpmp, cluster, i);
if (IS_ERR(cluster->table)) {
err = PTR_ERR(cluster->table);
cluster->bpmp_lut = tegra_cpufreq_bpmp_read_lut(pdev, bpmp, cluster, i, &num_rates);
if (IS_ERR(cluster->bpmp_lut)) {
err = PTR_ERR(cluster->bpmp_lut);
goto put_bpmp;
} else if (!num_rates) {
err = -EINVAL;
goto put_bpmp;
}
for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) {
if (data->cpus[cpu].bpmp_cluster_id == i) {
edvd_val = cluster->bpmp_lut[num_rates - 1].driver_data;
edvd_offset = data->cpus[cpu].edvd_offset;
writel(edvd_val, data->regs + edvd_offset);
}
}
}
tegra186_cpufreq_driver.driver_data = data;
/* Check for optional OPPv2 and interconnect paths on CPU0 to enable ICC scaling */
cpu_dev = get_cpu_device(0);
if (!cpu_dev) {
err = -EPROBE_DEFER;
goto put_bpmp;
}
if (dev_pm_opp_of_get_opp_desc_node(cpu_dev)) {
err = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
if (!err)
data->icc_dram_bw_scaling = true;
}
err = cpufreq_register_driver(&tegra186_cpufreq_driver);
put_bpmp:

1
drivers/cpuidle/cpuidle-tegra.c
View File

@@ -336,6 +336,7 @@ void tegra_cpuidle_pcie_irqs_in_use(void)
pr_info("disabling CC6 state, since PCIe IRQs are in use\n");
tegra_cpuidle_disable_state(TEGRA_CC6);
}
EXPORT_SYMBOL_GPL(tegra_cpuidle_pcie_irqs_in_use);
static void tegra_cpuidle_setup_tegra114_c7_state(void)
{

4
drivers/firmware/efi/libstub/printk.c
View File

@@ -5,13 +5,13 @@
#include <linux/ctype.h>
#include <linux/efi.h>
#include <linux/kernel.h>
#include <linux/printk.h> /* For CONSOLE_LOGLEVEL_* */
#include <linux/kern_levels.h>
#include <asm/efi.h>
#include <asm/setup.h>
#include "efistub.h"
int efi_loglevel = CONSOLE_LOGLEVEL_DEFAULT;
int efi_loglevel = LOGLEVEL_NOTICE;
/**
* efi_char16_puts() - Write a UCS-2 encoded string to the console

8
drivers/gpio/Kconfig
View File

@@ -714,13 +714,13 @@ config GPIO_TEGRA
config GPIO_TEGRA186
tristate "NVIDIA Tegra186 GPIO support"
default ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC
depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
default ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC || COMPILE_TEST
depends on OF_GPIO
select GPIOLIB_IRQCHIP
select IRQ_DOMAIN_HIERARCHY
help
Say yes here to support GPIO pins on NVIDIA Tegra186 SoCs.
Say yes here to support GPIO pins on NVIDIA Tegra186, 194 and 234 SoCs.
config GPIO_TS4800
tristate "TS-4800 DIO blocks and compatibles"
@@ -1451,7 +1451,7 @@ config GPIO_MAX77650
These chips have a single pin that can be configured as GPIO.
config GPIO_PALMAS
bool "TI PALMAS series PMICs GPIO"
tristate "TI PALMAS series PMICs GPIO"
depends on MFD_PALMAS
help
Select this option to enable GPIO driver for the TI PALMAS

11
drivers/gpio/gpio-palmas.c
View File

@@ -140,6 +140,7 @@ static const struct of_device_id of_palmas_gpio_match[] = {
{ .compatible = "ti,tps80036-gpio", .data = &tps80036_dev_data,},
{ },
};
MODULE_DEVICE_TABLE(of, of_palmas_gpio_match);
static int palmas_gpio_probe(struct platform_device *pdev)
{
@@ -197,3 +198,13 @@ static int __init palmas_gpio_init(void)
return platform_driver_register(&palmas_gpio_driver);
}
subsys_initcall(palmas_gpio_init);
static void __exit palmas_gpio_exit(void)
{
platform_driver_unregister(&palmas_gpio_driver);
}
module_exit(palmas_gpio_exit);
MODULE_DESCRIPTION("TI PALMAS series GPIO driver");
MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
MODULE_LICENSE("GPL");

1
drivers/gpu/drm/nouveau/Kconfig
View File

@@ -26,6 +26,7 @@ config DRM_NOUVEAU
select THERMAL if ACPI && X86
select ACPI_VIDEO if ACPI && X86
select SND_HDA_COMPONENT if SND_HDA_CORE
select PM_DEVFREQ if ARCH_TEGRA
help
Choose this option for open-source NVIDIA support.

2
drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
View File

@@ -9,6 +9,8 @@ struct nvkm_device_tegra {
struct nvkm_device device;
struct platform_device *pdev;
void __iomem *regs;
struct reset_control *rst;
struct clk *clk;
struct clk *clk_ref;

2
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
View File

@@ -134,4 +134,6 @@ int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gm20b_b01_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gp10b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
#endif

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
View File

@@ -42,4 +42,5 @@ int gf117_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
int gk104_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
int gk20a_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
int gm20b_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
int gm20b_b01_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
#endif

20
drivers/gpu/drm/nouveau/nouveau_platform.c
View File

@@ -21,6 +21,8 @@
*/
#include "nouveau_platform.h"
#include <nvkm/subdev/clk/gk20a_devfreq.h>
static int nouveau_platform_probe(struct platform_device *pdev)
{
const struct nvkm_device_tegra_func *func;
@@ -43,6 +45,21 @@ static void nouveau_platform_remove(struct platform_device *pdev)
nouveau_drm_device_remove(drm);
}
#ifdef CONFIG_PM_SLEEP
static int nouveau_platform_suspend(struct device *dev)
{
return gk20a_devfreq_suspend(dev);
}
static int nouveau_platform_resume(struct device *dev)
{
return gk20a_devfreq_resume(dev);
}
static SIMPLE_DEV_PM_OPS(nouveau_pm_ops, nouveau_platform_suspend,
nouveau_platform_resume);
#endif
#if IS_ENABLED(CONFIG_OF)
static const struct nvkm_device_tegra_func gk20a_platform_data = {
.iommu_bit = 34,
@@ -84,6 +101,9 @@ struct platform_driver nouveau_platform_driver = {
.driver = {
.name = "nouveau",
.of_match_table = of_match_ptr(nouveau_platform_match),
#ifdef CONFIG_PM_SLEEP
.pm = &nouveau_pm_ops,
#endif
},
.probe = nouveau_platform_probe,
.remove_new = nouveau_platform_remove,

2
drivers/gpu/drm/nouveau/nouveau_sgdma.c
View File

@@ -73,7 +73,7 @@ nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo, uint32_t page_flags)
enum ttm_caching caching;
if (nvbo->force_coherent)
caching = ttm_uncached;
caching = ttm_write_combined;
else if (drm->agp.bridge)
caching = ttm_write_combined;
else

27
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@@ -2072,6 +2072,31 @@ nv12b_chipset = {
.sw = { 0x00000001, gf100_sw_new },
};
static const struct nvkm_device_chip
nv12e_chipset = {
.name = "GM20B",
.acr = { 0x00000001, gm20b_acr_new },
.bar = { 0x00000001, gm20b_bar_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = { 0x00000001, gm20b_b01_clk_new },
.fb = { 0x00000001, gm20b_fb_new },
.fuse = { 0x00000001, gm107_fuse_new },
.imem = { 0x00000001, gk20a_instmem_new },
.ltc = { 0x00000001, gm200_ltc_new },
.mc = { 0x00000001, gk20a_mc_new },
.mmu = { 0x00000001, gm20b_mmu_new },
.pmu = { 0x00000001, gm20b_pmu_new },
.privring = { 0x00000001, gk20a_privring_new },
.timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gm20b_b01_volt_new },
.ce = { 0x00000004, gm200_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = { 0x00000001, gm20b_gr_new },
.sw = { 0x00000001, gf100_sw_new },
};
static const struct nvkm_device_chip
nv130_chipset = {
.name = "GP100",
@@ -2280,6 +2305,7 @@ nv13b_chipset = {
.acr = { 0x00000001, gp10b_acr_new },
.bar = { 0x00000001, gm20b_bar_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = { 0x00000001, gp10b_clk_new },
.fault = { 0x00000001, gp10b_fault_new },
.fb = { 0x00000001, gp10b_fb_new },
.fuse = { 0x00000001, gm107_fuse_new },
@@ -3224,6 +3250,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case 0x124: device->chip = &nv124_chipset; break;
case 0x126: device->chip = &nv126_chipset; break;
case 0x12b: device->chip = &nv12b_chipset; break;
case 0x12e: device->chip = &nv12e_chipset; break;
case 0x130: device->chip = &nv130_chipset; break;
case 0x132: device->chip = &nv132_chipset; break;
case 0x134: device->chip = &nv134_chipset; break;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
View File

@@ -249,6 +249,10 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
tdev->func = func;
tdev->pdev = pdev;
tdev->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(tdev->regs))
return PTR_ERR(tdev->regs);
if (func->require_vdd) {
tdev->vdd = devm_regulator_get(&pdev->dev, "vdd");
if (IS_ERR(tdev->vdd)) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
View File

@@ -10,6 +10,8 @@ nvkm-y += nvkm/subdev/clk/gf100.o
nvkm-y += nvkm/subdev/clk/gk104.o
nvkm-y += nvkm/subdev/clk/gk20a.o
nvkm-y += nvkm/subdev/clk/gm20b.o
nvkm-y += nvkm/subdev/clk/gp10b.o
nvkm-$(CONFIG_PM_DEVFREQ) += nvkm/subdev/clk/gk20a_devfreq.o
nvkm-y += nvkm/subdev/clk/pllnv04.o
nvkm-y += nvkm/subdev/clk/pllgt215.o

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
View File

@@ -23,6 +23,7 @@
*
*/
#include "priv.h"
#include "gk20a_devfreq.h"
#include "gk20a.h"
#include <core/tegra.h>
@@ -589,6 +590,10 @@ gk20a_clk_init(struct nvkm_clk *base)
return ret;
}
ret = gk20a_devfreq_init(base, &clk->devfreq);
if (ret)
return ret;
return 0;
}

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
View File

@@ -118,6 +118,7 @@ struct gk20a_clk {
const struct gk20a_clk_pllg_params *params;
struct gk20a_pll pll;
u32 parent_rate;
struct gk20a_devfreq *devfreq;
u32 (*div_to_pl)(u32);
u32 (*pl_to_div)(u32);

320
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c Normal file
View File

@@ -0,0 +1,320 @@
// SPDX-License-Identifier: MIT
#include <linux/clk.h>
#include <linux/math64.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <drm/drm_managed.h>
#include <subdev/clk.h>
#include "nouveau_drv.h"
#include "nouveau_chan.h"
#include "priv.h"
#include "gk20a_devfreq.h"
#include "gk20a.h"
#include "gp10b.h"
#define PMU_BUSY_CYCLES_NORM_MAX 1000U
#define PWR_PMU_IDLE_COUNTER_TOTAL 0U
#define PWR_PMU_IDLE_COUNTER_BUSY 4U
#define PWR_PMU_IDLE_COUNT_REG_OFFSET 0x0010A508U
#define PWR_PMU_IDLE_COUNT_REG_SIZE 16U
#define PWR_PMU_IDLE_COUNT_MASK 0x7FFFFFFFU
#define PWR_PMU_IDLE_COUNT_RESET_VALUE (0x1U << 31U)
#define PWR_PMU_IDLE_INTR_REG_OFFSET 0x0010A9E8U
#define PWR_PMU_IDLE_INTR_ENABLE_VALUE 0U
#define PWR_PMU_IDLE_INTR_STATUS_REG_OFFSET 0x0010A9ECU
#define PWR_PMU_IDLE_INTR_STATUS_MASK 0x00000001U
#define PWR_PMU_IDLE_INTR_STATUS_RESET_VALUE 0x1U
#define PWR_PMU_IDLE_THRESHOLD_REG_OFFSET 0x0010A8A0U
#define PWR_PMU_IDLE_THRESHOLD_REG_SIZE 4U
#define PWR_PMU_IDLE_THRESHOLD_MAX_VALUE 0x7FFFFFFFU
#define PWR_PMU_IDLE_CTRL_REG_OFFSET 0x0010A50CU
#define PWR_PMU_IDLE_CTRL_REG_SIZE 16U
#define PWR_PMU_IDLE_CTRL_VALUE_MASK 0x3U
#define PWR_PMU_IDLE_CTRL_VALUE_BUSY 0x2U
#define PWR_PMU_IDLE_CTRL_VALUE_ALWAYS 0x3U
#define PWR_PMU_IDLE_CTRL_FILTER_MASK (0x1U << 2)
#define PWR_PMU_IDLE_CTRL_FILTER_DISABLED 0x0U
#define PWR_PMU_IDLE_MASK_REG_OFFSET 0x0010A504U
#define PWR_PMU_IDLE_MASK_REG_SIZE 16U
#define PWM_PMU_IDLE_MASK_GR_ENABLED 0x1U
#define PWM_PMU_IDLE_MASK_CE_2_ENABLED 0x200000U
/**
* struct gk20a_devfreq - Device frequency management
*/
struct gk20a_devfreq {
/** @devfreq: devfreq device. */
struct devfreq *devfreq;
/** @regs: Device registers. */
void __iomem *regs;
/** @gov_data: Governor data. */
struct devfreq_simple_ondemand_data gov_data;
/** @busy_time: Busy time. */
ktime_t busy_time;
/** @total_time: Total time. */
ktime_t total_time;
/** @time_last_update: Last update time. */
ktime_t time_last_update;
};
static struct gk20a_devfreq *dev_to_gk20a_devfreq(struct device *dev)
{
struct nouveau_drm *drm = dev_get_drvdata(dev);
struct nvkm_subdev *subdev = nvkm_device_subdev(drm->nvkm, NVKM_SUBDEV_CLK, 0);
struct nvkm_clk *base = nvkm_clk(subdev);
switch (drm->nvkm->chipset) {
case 0x13b: return gp10b_clk(base)->devfreq; break;
default: return gk20a_clk(base)->devfreq; break;
}
}
static void gk20a_pmu_init_perfmon_counter(struct gk20a_devfreq *gdevfreq)
{
u32 data;
// Set pmu idle intr status bit on total counter overflow
writel(PWR_PMU_IDLE_INTR_ENABLE_VALUE,
gdevfreq->regs + PWR_PMU_IDLE_INTR_REG_OFFSET);
writel(PWR_PMU_IDLE_THRESHOLD_MAX_VALUE,
gdevfreq->regs + PWR_PMU_IDLE_THRESHOLD_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_TOTAL * PWR_PMU_IDLE_THRESHOLD_REG_SIZE));
// Setup counter for total cycles
data = readl(gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_TOTAL * PWR_PMU_IDLE_CTRL_REG_SIZE));
data &= ~(PWR_PMU_IDLE_CTRL_VALUE_MASK | PWR_PMU_IDLE_CTRL_FILTER_MASK);
data |= PWR_PMU_IDLE_CTRL_VALUE_ALWAYS | PWR_PMU_IDLE_CTRL_FILTER_DISABLED;
writel(data, gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_TOTAL * PWR_PMU_IDLE_CTRL_REG_SIZE));
// Setup counter for busy cycles
writel(PWM_PMU_IDLE_MASK_GR_ENABLED | PWM_PMU_IDLE_MASK_CE_2_ENABLED,
gdevfreq->regs + PWR_PMU_IDLE_MASK_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_BUSY * PWR_PMU_IDLE_MASK_REG_SIZE));
data = readl(gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_BUSY * PWR_PMU_IDLE_CTRL_REG_SIZE));
data &= ~(PWR_PMU_IDLE_CTRL_VALUE_MASK | PWR_PMU_IDLE_CTRL_FILTER_MASK);
data |= PWR_PMU_IDLE_CTRL_VALUE_BUSY | PWR_PMU_IDLE_CTRL_FILTER_DISABLED;
writel(data, gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
(PWR_PMU_IDLE_COUNTER_BUSY * PWR_PMU_IDLE_CTRL_REG_SIZE));
}
static u32 gk20a_pmu_read_idle_counter(struct gk20a_devfreq *gdevfreq, u32 counter_id)
{
u32 ret;
ret = readl(gdevfreq->regs + PWR_PMU_IDLE_COUNT_REG_OFFSET +
(counter_id * PWR_PMU_IDLE_COUNT_REG_SIZE));
return ret & PWR_PMU_IDLE_COUNT_MASK;
}
static void gk20a_pmu_reset_idle_counter(struct gk20a_devfreq *gdevfreq, u32 counter_id)
{
writel(PWR_PMU_IDLE_COUNT_RESET_VALUE, gdevfreq->regs + PWR_PMU_IDLE_COUNT_REG_OFFSET +
(counter_id * PWR_PMU_IDLE_COUNT_REG_SIZE));
}
static u32 gk20a_pmu_read_idle_intr_status(struct gk20a_devfreq *gdevfreq)
{
u32 ret;
ret = readl(gdevfreq->regs + PWR_PMU_IDLE_INTR_STATUS_REG_OFFSET);
return ret & PWR_PMU_IDLE_INTR_STATUS_MASK;
}
static void gk20a_pmu_clear_idle_intr_status(struct gk20a_devfreq *gdevfreq)
{
writel(PWR_PMU_IDLE_INTR_STATUS_RESET_VALUE,
gdevfreq->regs + PWR_PMU_IDLE_INTR_STATUS_REG_OFFSET);
}
static void gk20a_devfreq_update_utilization(struct gk20a_devfreq *gdevfreq)
{
ktime_t now, last;
u64 busy_cycles, total_cycles;
u32 norm, intr_status;
now = ktime_get();
last = gdevfreq->time_last_update;
gdevfreq->total_time = ktime_us_delta(now, last);
busy_cycles = gk20a_pmu_read_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_BUSY);
total_cycles = gk20a_pmu_read_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_TOTAL);
intr_status = gk20a_pmu_read_idle_intr_status(gdevfreq);
gk20a_pmu_reset_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_BUSY);
gk20a_pmu_reset_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_TOTAL);
if (intr_status != 0UL) {
norm = PMU_BUSY_CYCLES_NORM_MAX;
gk20a_pmu_clear_idle_intr_status(gdevfreq);
} else if (total_cycles == 0ULL || busy_cycles > total_cycles) {
norm = PMU_BUSY_CYCLES_NORM_MAX;
} else {
norm = (u32)div64_u64(busy_cycles * PMU_BUSY_CYCLES_NORM_MAX,
total_cycles);
}
gdevfreq->busy_time = div_u64(gdevfreq->total_time * norm, PMU_BUSY_CYCLES_NORM_MAX);
gdevfreq->time_last_update = now;
}
static int gk20a_devfreq_target(struct device *dev, unsigned long *freq,
u32 flags)
{
struct nouveau_drm *drm = dev_get_drvdata(dev);
struct nvkm_subdev *subdev = nvkm_device_subdev(drm->nvkm, NVKM_SUBDEV_CLK, 0);
struct nvkm_clk *base = nvkm_clk(subdev);
struct nvkm_pstate *pstates = base->func->pstates;
int nr_pstates = base->func->nr_pstates;
int i, ret;
for (i = 0; i < nr_pstates - 1; i++)
if (pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV >= *freq)
break;
ret = nvkm_clk_ustate(base, pstates[i].pstate, 0);
ret |= nvkm_clk_ustate(base, pstates[i].pstate, 1);
if (ret) {
nvkm_error(subdev, "cannot update clock\n");
return ret;
}
*freq = pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV;
return 0;
}
static int gk20a_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
{
struct nouveau_drm *drm = dev_get_drvdata(dev);
struct nvkm_subdev *subdev = nvkm_device_subdev(drm->nvkm, NVKM_SUBDEV_CLK, 0);
struct nvkm_clk *base = nvkm_clk(subdev);
*freq = nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;
return 0;
}
static void gk20a_devfreq_reset(struct gk20a_devfreq *gdevfreq)
{
gk20a_pmu_reset_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_BUSY);
gk20a_pmu_reset_idle_counter(gdevfreq, PWR_PMU_IDLE_COUNTER_TOTAL);
gk20a_pmu_clear_idle_intr_status(gdevfreq);
gdevfreq->busy_time = 0;
gdevfreq->total_time = 0;
gdevfreq->time_last_update = ktime_get();
}
static int gk20a_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *status)
{
struct nouveau_drm *drm = dev_get_drvdata(dev);
struct gk20a_devfreq *gdevfreq = dev_to_gk20a_devfreq(dev);
gk20a_devfreq_get_cur_freq(dev, &status->current_frequency);
gk20a_devfreq_update_utilization(gdevfreq);
status->busy_time = ktime_to_ns(gdevfreq->busy_time);
status->total_time = ktime_to_ns(gdevfreq->total_time);
gk20a_devfreq_reset(gdevfreq);
NV_DEBUG(drm, "busy %lu total %lu %lu %% freq %lu MHz\n",
status->busy_time, status->total_time,
status->busy_time / (status->total_time / 100),
status->current_frequency / 1000 / 1000);
return 0;
}
static struct devfreq_dev_profile gk20a_devfreq_profile = {
.timer = DEVFREQ_TIMER_DELAYED,
.polling_ms = 50,
.target = gk20a_devfreq_target,
.get_cur_freq = gk20a_devfreq_get_cur_freq,
.get_dev_status = gk20a_devfreq_get_dev_status,
};
int gk20a_devfreq_init(struct nvkm_clk *base, struct gk20a_devfreq **gdevfreq)
{
struct nvkm_device *device = base->subdev.device;
struct nouveau_drm *drm = dev_get_drvdata(device->dev);
struct nvkm_device_tegra *tdev = device->func->tegra(device);
struct nvkm_pstate *pstates = base->func->pstates;
int nr_pstates = base->func->nr_pstates;
struct gk20a_devfreq *new_gdevfreq;
int i;
new_gdevfreq = drmm_kzalloc(drm->dev, sizeof(struct gk20a_devfreq), GFP_KERNEL);
if (!new_gdevfreq)
return -ENOMEM;
new_gdevfreq->regs = tdev->regs;
for (i = 0; i < nr_pstates; i++)
dev_pm_opp_add(base->subdev.device->dev,
pstates[i].base.domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV, 0);
gk20a_pmu_init_perfmon_counter(new_gdevfreq);
gk20a_devfreq_reset(new_gdevfreq);
gk20a_devfreq_profile.initial_freq =
nvkm_clk_read(base, nv_clk_src_gpc) * GK20A_CLK_GPC_MDIV;
new_gdevfreq->gov_data.upthreshold = 45;
new_gdevfreq->gov_data.downdifferential = 5;
new_gdevfreq->devfreq = devm_devfreq_add_device(device->dev,
&gk20a_devfreq_profile,
DEVFREQ_GOV_SIMPLE_ONDEMAND,
&new_gdevfreq->gov_data);
if (IS_ERR(new_gdevfreq->devfreq))
return PTR_ERR(new_gdevfreq->devfreq);
*gdevfreq = new_gdevfreq;
return 0;
}
int gk20a_devfreq_resume(struct device *dev)
{
struct gk20a_devfreq *gdevfreq = dev_to_gk20a_devfreq(dev);
if (!gdevfreq || !gdevfreq->devfreq)
return 0;
return devfreq_resume_device(gdevfreq->devfreq);
}
int gk20a_devfreq_suspend(struct device *dev)
{
struct gk20a_devfreq *gdevfreq = dev_to_gk20a_devfreq(dev);
if (!gdevfreq || !gdevfreq->devfreq)
return 0;
return devfreq_suspend_device(gdevfreq->devfreq);
}

24
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.h Normal file
View File

@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: MIT */
#ifndef __GK20A_DEVFREQ_H__
#define __GK20A_DEVFREQ_H__
#include <linux/devfreq.h>
struct gk20a_devfreq;
#if defined(CONFIG_PM_DEVFREQ)
int gk20a_devfreq_init(struct nvkm_clk *base, struct gk20a_devfreq **devfreq);
int gk20a_devfreq_resume(struct device *dev);
int gk20a_devfreq_suspend(struct device *dev);
#else
static inline int gk20a_devfreq_init(struct nvkm_clk *base, struct gk20a_devfreq **devfreq)
{
return 0;
}
static inline int gk20a_devfreq_resume(struct device dev) { return 0; }
static inline int gk20a_devfreq_suspend(struct device *dev) { return 0; }
#endif /* CONFIG_PM_DEVFREQ */
#endif /* __GK20A_DEVFREQ_H__ */

224
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
View File

@@ -27,6 +27,7 @@
#include <core/tegra.h>
#include "priv.h"
#include "gk20a_devfreq.h"
#include "gk20a.h"
#define GPCPLL_CFG_SYNC_MODE BIT(2)
@@ -716,6 +717,112 @@ gm20b_pstates[] = {
},
};
static struct nvkm_pstate
gm20b_b01_pstates[] = {
{
.base = {
.domain[nv_clk_src_gpc] = 76800,
.voltage = 0,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 153600,
.voltage = 1,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 230400,
.voltage = 2,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 307200,
.voltage = 3,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 384000,
.voltage = 4,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 460800,
.voltage = 5,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 537600,
.voltage = 6,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 614400,
.voltage = 7,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 691200,
.voltage = 8,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 768000,
.voltage = 9,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 844800,
.voltage = 10,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 921600,
.voltage = 11,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 998400,
.voltage = 12,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1075200,
.voltage = 13,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1152000,
.voltage = 14,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1228800,
.voltage = 15,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1267200,
.voltage = 16,
},
},
};
static void
gm20b_clk_fini(struct nvkm_clk *base)
{
@@ -869,6 +976,10 @@ gm20b_clk_init(struct nvkm_clk *base)
return ret;
}
ret = gk20a_devfreq_init(base, &clk->devfreq);
if (ret)
return ret;
return 0;
}
@@ -907,6 +1018,41 @@ gm20b_clk = {
},
};
static const struct nvkm_clk_func
gm20b_b01_clk = {
.init = gm20b_clk_init,
.fini = gk20a_clk_fini,
.read = gk20a_clk_read,
.calc = gk20a_clk_calc,
.prog = gk20a_clk_prog,
.tidy = gk20a_clk_tidy,
.pstates = gm20b_b01_pstates,
.nr_pstates = ARRAY_SIZE(gm20b_b01_pstates),
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_max },
},
};
static const struct nvkm_clk_func
gm20b_b01_hiopt_clk_speedo = {
.init = gm20b_clk_init,
.fini = gk20a_clk_fini,
.read = gk20a_clk_read,
.calc = gk20a_clk_calc,
.prog = gk20a_clk_prog,
.tidy = gk20a_clk_tidy,
.pstates = gm20b_pstates,
/* HIOPT speedo only supports 16 voltages */
.nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_max },
},
};
static int
gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
@@ -925,6 +1071,24 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, in
return ret;
}
static int
gm20b_b01_clk_new_hiopt(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gk20a_clk *clk;
int ret;
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
*pclk = &clk->base;
ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_hiopt_clk_speedo, &gm20b_pllg_params, clk);
clk->pl_to_div = pl_to_div;
clk->div_to_pl = div_to_pl;
return ret;
}
/* FUSE register */
#define FUSE_RESERVED_CALIB0 0x204
#define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT 0
@@ -1069,3 +1233,63 @@ gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
return 0;
}
int
gm20b_b01_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct nvkm_device_tegra *tdev = device->func->tegra(device);
struct gm20b_clk *clk;
struct nvkm_subdev *subdev;
struct gk20a_clk_pllg_params *clk_params;
int ret;
/* Speedo 0 GPUs cannot use noise-aware PLL */
if (tdev->gpu_speedo_id == 0)
return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
/* Speedo >= 1, use NAPLL */
clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL);
if (!clk)
return -ENOMEM;
*pclk = &clk->base.base;
subdev = &clk->base.base.subdev;
/* duplicate the clock parameters since we will patch them below */
clk_params = (void *) (clk + 1);
*clk_params = gm20b_pllg_params;
ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_clk, clk_params, &clk->base);
if (ret)
return ret;
/*
* NAPLL can only work with max_u, clamp the m range so
* gk20a_pllg_calc_mnp always uses it
*/
clk_params->max_m = clk_params->min_m = DIV_ROUND_UP(clk_params->max_u,
(clk->base.parent_rate / KHZ));
if (clk_params->max_m == 0) {
nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n");
kfree(clk);
return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
}
clk->base.pl_to_div = pl_to_div;
clk->base.div_to_pl = div_to_pl;
clk->dvfs_params = &gm20b_dvfs_params;
ret = gm20b_clk_init_fused_params(clk);
/*
* we will calibrate during init - should never happen on
* prod parts
*/
if (ret)
nvkm_warn(subdev, "no fused calibration parameters\n");
ret = gm20b_clk_init_safe_fmax(clk);
if (ret)
return ret;
return 0;
}

185
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c Normal file
View File

@@ -0,0 +1,185 @@
// SPDX-License-Identifier: MIT
#include <subdev/clk.h>
#include <subdev/timer.h>
#include <core/device.h>
#include <core/tegra.h>
#include "priv.h"
#include "gk20a_devfreq.h"
#include "gk20a.h"
#include "gp10b.h"
static int
gp10b_clk_init(struct nvkm_clk *base)
{
struct gp10b_clk *clk = gp10b_clk(base);
struct nvkm_subdev *subdev = &clk->base.subdev;
int ret;
/* Start with the highest frequency, matching the BPMP default */
base->func->calc(base, &base->func->pstates[base->func->nr_pstates - 1].base);
ret = base->func->prog(base);
if (ret) {
nvkm_error(subdev, "cannot initialize clock\n");
return ret;
}
ret = gk20a_devfreq_init(base, &clk->devfreq);
if (ret)
return ret;
return 0;
}
int
gp10b_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
{
struct gp10b_clk *clk = gp10b_clk(base);
struct nvkm_subdev *subdev = &clk->base.subdev;
switch (src) {
case nv_clk_src_gpc:
return clk_get_rate(clk->clk) / GK20A_CLK_GPC_MDIV;
default:
nvkm_error(subdev, "invalid clock source %d\n", src);
return -EINVAL;
}
}
static int
gp10b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
{
struct gp10b_clk *clk = gp10b_clk(base);
u32 target_rate = cstate->domain[nv_clk_src_gpc] * GK20A_CLK_GPC_MDIV;
clk->new_rate = clk_round_rate(clk->clk, target_rate) / GK20A_CLK_GPC_MDIV;
return 0;
}
static int
gp10b_clk_prog(struct nvkm_clk *base)
{
struct gp10b_clk *clk = gp10b_clk(base);
int ret;
ret = clk_set_rate(clk->clk, clk->new_rate * GK20A_CLK_GPC_MDIV);
if (ret < 0)
return ret;
clk->rate = clk_get_rate(clk->clk) / GK20A_CLK_GPC_MDIV;
return 0;
}
static struct nvkm_pstate
gp10b_pstates[] = {
{
.base = {
.domain[nv_clk_src_gpc] = 114750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 216750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 318750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 420750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 522750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 624750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 726750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 828750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 930750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1032750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1134750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1236750,
},
},
{
.base = {
.domain[nv_clk_src_gpc] = 1300500,
},
},
};
static const struct nvkm_clk_func
gp10b_clk = {
.init = gp10b_clk_init,
.read = gp10b_clk_read,
.calc = gp10b_clk_calc,
.prog = gp10b_clk_prog,
.tidy = gk20a_clk_tidy,
.pstates = gp10b_pstates,
.nr_pstates = ARRAY_SIZE(gp10b_pstates),
.domains = {
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_max }
}
};
int
gp10b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct nvkm_device_tegra *tdev = device->func->tegra(device);
const struct nvkm_clk_func *func = &gp10b_clk;
struct gp10b_clk *clk;
int ret, i;
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
*pclk = &clk->base;
clk->clk = tdev->clk;
/* Finish initializing the pstates */
for (i = 0; i < func->nr_pstates; i++) {
INIT_LIST_HEAD(&func->pstates[i].list);
func->pstates[i].pstate = i + 1;
}
ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);
if (ret)
return ret;
return 0;
}

17
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.h Normal file
View File

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_CLK_GP10B_H__
#define __NVKM_CLK_GP10B_H__
struct gp10b_clk {
/* currently applied parameters */
struct nvkm_clk base;
struct gk20a_devfreq *devfreq;
struct clk *clk;
u32 rate;
/* new parameters to apply */
u32 new_rate;
};
#define gp10b_clk(p) container_of((p), struct gp10b_clk, base)
#endif

96
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c
View File

@@ -91,3 +91,99 @@ gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef,
ARRAY_SIZE(gm20b_cvb_coef), vmin, volt);
}
static const struct cvb_coef gm20b_b01_na_cvb_slt_coef[] = {
/* KHz, c0, c1, c2, c3, c4, c5 */
/* 76800 */ { 590000, 0, 0, 0, 0, 0 },
/* 153600 */ { 590000, 0, 0, 0, 0, 0 },
/* 230400 */ { 590000, 0, 0, 0, 0, 0 },
/* 307200 */ { 590000, 0, 0, 0, 0, 0 },
/* 384000 */ { 590000, 0, 0, 0, 0, 0 },
/* 460800 */ { 795089, -11096, -163, 298, -10421, 162},
/* 537600 */ { 795089, -11096, -163, 298, -10421, 162 },
/* 614400 */ { 820606, -6285, -452, 238, -6182, 81 },
/* 691200 */ { 846289, -4565, -552, 119, -3958, -2 },
/* 768000 */ { 888720, -5110, -584, 0, -2849, 39 },
/* 844800 */ { 936634, -6089, -602, -60, -99, -93 },
/* 921600 */ { 982562, -7373, -614, -179, 1797, -13 },
/* 998400 */ { 1090179, -14125, -497, -179, 3518, 9 },
/* 1075200 */ { 1155798, -13465, -648, 0, 1077, 40 },
/* 1152000 */ { 1198568, -10904, -830, 0, 1469, 110 },
/* 1228800 */ { 1269988, -12707, -859, 0, 3722, 313 },
/* 1267200 */ { 1308155, -13694, -867, 0, 3681, 559 },
};
static const struct cvb_coef gm20b_b01_na_cvb_coef[] = {
/* KHz, c0, c1, c2, c3, c4, c5 */
/* 76800 */ { 610000, 0, 0, 0, 0, 0 },
/* 153600 */ { 610000, 0, 0, 0, 0, 0 },
/* 230400 */ { 610000, 0, 0, 0, 0, 0 },
/* 307200 */ { 610000, 0, 0, 0, 0, 0 },
/* 384000 */ { 610000, 0, 0, 0, 0, 0 },
/* 460800 */ { 610000, 0, 0, 0, 0, 0 },
/* 537600 */ { 801688, -10900, -163, 298, -10599, 162 },
/* 614400 */ { 824214, -5743, -452, 238, -6325, 81 },
/* 691200 */ { 848830, -3903, -552, 119, -4030, -2 },
/* 768000 */ { 891575, -4409, -584, 0, -2849, 39 },
/* 844800 */ { 940071, -5367, -602, -60, -63, -93 },
/* 921600 */ { 986765, -6637, -614, -179, 1905, -13 },
/* 998400 */ { 1098475, -13529, -497, -179, 3626, 9 },
/* 1075200 */ { 1163644, -12688, -648, 0, 1077, 40 },
/* 1152000 */ { 1204812, -9908, -830, 0, 1469, 110 },
/* 1228800 */ { 1277303, -11675, -859, 0, 3722, 313 },
/* 1267200 */ { 1335531, -12567, -867, 0, 3681, 559 },
};
static const struct cvb_coef gm20b_b01_na_cvb_hiopt_coef[] = {
/* KHz, c0, c1, c2, c3, c4, c5 */
/* 76800 */ { 590000, 0, 0, 0, 0, 0 },
/* 153600 */ { 590000, 0, 0, 0, 0, 0 },
/* 230400 */ { 590000, 0, 0, 0, 0, 0 },
/* 307200 */ { 590000, 0, 0, 0, 0, 0 },
/* 384000 */ { 590000, 0, 0, 0, 0, 0 },
/* 460800 */ { 590000, 0, 0, 0, 0, 0 },
/* 537600 */ { 590000, 0, 0, 0, 0, 0 },
/* 614400 */ { 590000, 0, 0, 0, 0, 0 },
/* 691200 */ { 838712, -7304, -552, 1785, -56250, -450 },
/* 768000 */ { 880210, -7955, -584, 0, -42735, 8775 },
/* 844800 */ { 926398, -8892, -602, -900, -5760, -20925 },
/* 921600 */ { 970060, -10108, -614, -2685, 22620, -2925 },
/* 998400 */ { 1065665, -16075, -497, -2685, 48195, 2025 },
/* 1075200 */ { 1132576, -16093, -648, 0, 16155, 9000 },
/* 1152000 */ { 1180029, -14534, -830, 0, 22035, 24750 },
/* 1228800 */ { 1248293, -16383, -859, 0, 55830, 70425 },
};
int
gm20b_b01_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_volt **pvolt)
{
struct nvkm_device_tegra *tdev = device->func->tegra(device);
struct gk20a_volt *volt;
u32 vmin;
if (tdev->gpu_speedo_id >= ARRAY_SIZE(speedo_to_vmin)) {
nvdev_error(device, "unsupported speedo %d\n",
tdev->gpu_speedo_id);
return -EINVAL;
}
volt = kzalloc(sizeof(*volt), GFP_KERNEL);
if (!volt)
return -ENOMEM;
*pvolt = &volt->base;
vmin = speedo_to_vmin[tdev->gpu_speedo_id];
switch (tdev->gpu_speedo_id) {
case 3: /* HIOPT table */
return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_hiopt_coef,
ARRAY_SIZE(gm20b_b01_na_cvb_hiopt_coef), vmin, volt);
case 2: /* SLT table */
return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_slt_coef,
ARRAY_SIZE(gm20b_b01_na_cvb_slt_coef), vmin, volt);
default:
return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_coef,
ARRAY_SIZE(gm20b_b01_na_cvb_coef), vmin, volt);
}
}

24
drivers/gpu/drm/panel/Kconfig
View File

@@ -282,6 +282,15 @@ config DRM_PANEL_JDI_LPM102A188A
The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
to the host.
config DRM_PANEL_NX_DSI
tristate "Nintendo Switch 720x1280 DSI panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here if you want to enable support for the DSI panels
used in the Nintendo Switch.
config DRM_PANEL_JDI_LT070ME05000
tristate "JDI LT070ME05000 WUXGA DSI panel"
depends on OF
@@ -750,6 +759,21 @@ config DRM_PANEL_SEIKO_43WVF1G
Say Y here if you want to enable support for the Seiko
43WVF1G controller for 800x480 LCD panels
config DRM_PANEL_SHARP_LQ079L1SX01
tristate "Sharp LQ079L1SX01 panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
select VIDEOMODE_HELPERS
help
Say Y here if you want to enable support for Sharp LQ079L1SX01
TFT-LCD modules. The panel has a 2560x1600 resolution and uses
24 bit RGB per pixel. It provides a dual MIPI DSI interface to
the host.
To compile this driver as a module, choose M here: the module
will be called panel-sharp-lq079l1sx01.
config DRM_PANEL_SHARP_LQ101R1SX01
tristate "Sharp LQ101R1SX01 panel"
depends on OF

2
drivers/gpu/drm/panel/Makefile
View File

@@ -50,6 +50,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672E) += panel-novatek-nt36672e.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o
obj-$(CONFIG_DRM_PANEL_NX_DSI) += panel-nx-dsi.o
obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o
obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o
obj-$(CONFIG_DRM_PANEL_ORISETECH_OTA5601A) += panel-orisetech-ota5601a.o
@@ -78,6 +79,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01) += panel-samsung-s6e88a0-ams4
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_SOFEF00) += panel-samsung-sofef00.o
obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ079L1SX01) += panel-sharp-lq079l1sx01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o

795
drivers/gpu/drm/panel/panel-nx-dsi.c Normal file
View File

@@ -0,0 +1,795 @@
/*
* Copyright (C) 2018 SwtcR <swtcr0@gmail.com>
* Copyright (C) 2023-2024 Azkali <a.ffcc7@gmail.com>
*
* Based on Sharp ls043t1le01 panel driver by Werner Johansson <werner.johansson@sonymobile.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_crtc.h>
#include <drm/drm_panel.h>
#include <drm/drm_modes.h>
/*! MIPI DCS Panel Private CMDs. */
#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE ((u8)0xA0)
#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET ((u8)0xB0)
#define MIPI_DCS_PRIV_SM_SET_ELVSS ((u8)0xB1) /* OLED backlight tuning. Byte7: PWM transition time in frames. */
#define MIPI_DCS_PRIV_SET_POWER_CONTROL ((u8)0xB1)
#define MIPI_DCS_PRIV_SET_EXTC ((u8)0xB9) /* Enable extended commands. */
#define MIPI_DCS_PRIV_UNK_BD ((u8)0xBD)
#define MIPI_DCS_PRIV_UNK_D5 ((u8)0xD5)
#define MIPI_DCS_PRIV_UNK_D6 ((u8)0xD6)
#define MIPI_DCS_PRIV_UNK_D8 ((u8)0xD8)
#define MIPI_DCS_PRIV_UNK_D9 ((u8)0xD9)
#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK ((u8)0xE2)
/* BL Control */
#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT ((u8)BIT(2))
#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL ((u8)BIT(2))
#define DCS_CONTROL_DISPLAY_DIMMING_CTRL ((u8)BIT(3))
#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL ((u8)BIT(5))
/* OLED Panels color mode */
#define DCS_SM_COLOR_MODE_SATURATED ((u8)0x00) /* Disabled. Similar to vivid but over-saturated. Wide gamut? */
#define DCS_SM_COLOR_MODE_WASHED ((u8)0x45)
#define DCS_SM_COLOR_MODE_BASIC ((u8)0x03)
#define DCS_SM_COLOR_MODE_POR_RESET ((u8)0x20) /* Reset value on power on. */
#define DCS_SM_COLOR_MODE_NATURAL ((u8)0x23) /* Not actually natural.. */
#define DCS_SM_COLOR_MODE_VIVID ((u8)0x65)
#define DCS_SM_COLOR_MODE_NIGHT0 ((u8)0x43) /* Based on washed out. */
#define DCS_SM_COLOR_MODE_NIGHT1 ((u8)0x15) /* Based on basic. */
#define DCS_SM_COLOR_MODE_NIGHT2 ((u8)0x35) /* Based on natural. */
#define DCS_SM_COLOR_MODE_NIGHT3 ((u8)0x75) /* Based on vivid. */
#define DCS_SM_COLOR_MODE_ENABLE ((u8)BIT(0))
enum
{
PANEL_JDI_XXX062M = 0x10,
PANEL_JDI_LAM062M109A = 0x0910,
PANEL_JDI_LPM062M326A = 0x2610,
PANEL_INL_P062CCA_AZ1 = 0x0F20,
PANEL_AUO_A062TAN01 = 0x0F30,
PANEL_INL_2J055IA_27A = 0x1020,
PANEL_AUO_A055TAN01 = 0x1030,
PANEL_SHP_LQ055T1SW10 = 0x1040,
PANEL_SAM_AMS699VC01 = 0x2050,
PANEL_RR_SUPER5_OLED_V1 = 0x10E0,
PANEL_RR_SUPER5_OLED_HD_V1 = 0x10E1,
PANEL_RR_SUPER7_IPS_V1 = 0x0FE0,
PANEL_RR_SUPER7_IPS_HD_V1 = 0x0FE1,
PANEL_RR_SUPER7_OLED_7_V1 = 0x20E0,
PANEL_RR_SUPER7_OLED_HD_7_V1 = 0x20E1,
// Found on 6/2" clones. Unknown markings. Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F].
PANEL_OEM_CLONE_6_2 = 0x0F83,
// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
PANEL_OEM_CLONE_5_5 = 0x00B3,
// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
PANEL_OEM_CLONE = 0x0000
};
struct init_cmd {
u8 cmd;
int length;
u8 data[64];
};
struct nx_panel {
struct drm_panel base;
struct mipi_dsi_device *dsi;
struct backlight_device *backlight;
struct regulator *supply1;
struct regulator *supply2;
struct gpio_desc *reset_gpio;
bool prepared;
bool enabled;
const struct drm_display_mode *mode;
struct init_cmd *init_cmds;
struct init_cmd *suspend_cmds;
u16 display_id;
};
struct init_cmd init_cmds_default[] = {
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
120,
},
{ MIPI_DCS_SET_DISPLAY_ON, 2, { 0x00, 0x0 } },
{
0xFF,
20,
},
};
struct init_cmd init_cmds_PANEL_JDI_XXX062M[] = {
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x00, 0x0 } },
{ MIPI_DCS_PRIV_UNK_D8, 24, { 0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA } },
{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x01, 0x0 } },
{ MIPI_DCS_PRIV_UNK_D8,
38,
{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } },
{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x02, 0x0 } },
{ MIPI_DCS_PRIV_UNK_D8,
14,
{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF } },
{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x00, 0x00 } },
{ MIPI_DCS_PRIV_UNK_D9, 2, { 0x06, 0x0 } },
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0x00, 0x00, 0x00 } },
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
180,
},
{ MIPI_DCS_SET_DISPLAY_ON, 2, { 0x00, 0x0 } },
{
0xFF,
20,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd suspend_cmds_PANEL_JDI_XXX062M[] = {
{ MIPI_DCS_SET_DISPLAY_OFF, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{ MIPI_DCS_PRIV_UNK_D5,
32,
{ 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19 } },
{ MIPI_DCS_PRIV_SET_POWER_CONTROL,
10,
{ 0x41, 0x0F, 0x4F, 0x33, 0xA4, 0x79, 0xF1, 0x81, 0x2D, 0x00 } },
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0x00, 0x00, 0x00 } },
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
{ MIPI_DCS_NOP, -1, { 0x00 } },
};
struct init_cmd init_cmds_PANEL_SAM_AMS699VC01[] = {
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
180,
},
// Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20).
{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE, 2, { 0x23, 0x0 } },
// Enable backlight and smooth PWM.
{ MIPI_DCS_WRITE_CONTROL_DISPLAY, 2, { 0x28, 0x0 } },
// Unlock Level 2 registers.
{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0x5A, 0x5A, 0x0, 0x0 } },
// Set registers offset and set PWM transition to 6 frames (100ms).
{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET, 2, { 0x07, 0x0 } },
{ MIPI_DCS_PRIV_SM_SET_ELVSS, 2, { 0x06, 0x0 } },
// Relock Level 2 registers.
{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0xA5, 0xA5, 0x0, 0x0 } },
// MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%.
{ 0x03, 7, { 0x00, 0x00, 0x51, 0x0, 0x0, 0x0, 0x0 } },
{
0xFF,
5,
},
};
struct init_cmd init_cmds_PANEL_AUO_A062TAN01[] = {
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
180,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{
0xFF,
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x11, 0x71, 0x09, 0x32, 0x14 } },
};
struct init_cmd suspend_cmds_PANEL_AUO_A062TAN01[] = {
{
0xFF,
100,
},
{
0xFF,
5,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
};
struct init_cmd suspend_cmds_PANEL_AUO_A055TAN01[] = {
{
0xFF,
100,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{
0xFF,
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x11, 0x71, 0x09, 0x32, 0x14, 0x71, 0x31, 0x4D, 0x11 } },
{
0xFF,
5,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
};
struct init_cmd init_cmds_PANEL_INL_P062CCA_AZ1[] = {
{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
180,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{
0xFF,
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x15, 0x75, 0x09, 0x32, 0x14 } },
};
struct init_cmd suspend_cmds_PANEL_INL_2J055IA_27A[] = {
{
0xFF,
100,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{
0xFF,
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x15, 0x75, 0x09, 0x32, 0x14, 0x71, 0x31, 0x4D, 0x11 } },
{
0xFF,
5,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
};
struct init_cmd suspend_cmds_PANEL_SHP_LQ055T1SW10[] = {
{
0xFF,
100,
},
{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
{
0xFF,
5,
},
{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x13, 0x73, 0x09, 0x32, 0x24, 0x71, 0x31, 0x4C, 0x00 } },
{
0xFF,
5,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
50,
},
};
struct init_cmd suspend_cmds_PANEL_SAM_AMS699VC01[] = {
{
0xFF,
100,
},
{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
{
0xFF,
120,
},
};
static inline struct nx_panel *to_nx_panel(struct drm_panel *panel)
{
return container_of(panel, struct nx_panel, base);
}
static void nx_panel_detect(struct nx_panel *nx)
{
int ret;
nx->init_cmds = NULL;
nx->suspend_cmds = NULL;
printk("nx_panel_detect");
memset(&(nx->display_id), 0, sizeof(nx->display_id));
ret = mipi_dsi_dcs_read(nx->dsi, MIPI_DCS_GET_DISPLAY_ID,
&(nx->display_id), sizeof(nx->display_id));
if (ret < 0) {
dev_err(&nx->dsi->dev, "failed to read panel ID: %d\n", ret);
} else {
dev_info(&nx->dsi->dev, "display ID[%d]: %04x\n",
ret, nx->display_id);
}
dev_info(&nx->dsi->dev,
"setting init sequence for ID %04x\n", nx->display_id);
switch (nx->display_id) {
case PANEL_JDI_XXX062M:
nx->init_cmds = init_cmds_PANEL_JDI_XXX062M;
break;
case PANEL_SAM_AMS699VC01:
nx->init_cmds = init_cmds_PANEL_SAM_AMS699VC01;
break;
case PANEL_INL_P062CCA_AZ1:
nx->init_cmds = init_cmds_PANEL_INL_P062CCA_AZ1;
break;
case PANEL_AUO_A062TAN01:
nx->init_cmds = init_cmds_PANEL_AUO_A062TAN01;
break;
case PANEL_INL_2J055IA_27A:
case PANEL_AUO_A055TAN01:
case PANEL_SHP_LQ055T1SW10:
default:
dev_info(&nx->dsi->dev, "using default init sequence\n");
nx->init_cmds = init_cmds_default;
break;
}
dev_info(&nx->dsi->dev,
"setting suspend sequence for ID %04x\n", nx->display_id);
switch (nx->display_id) {
case PANEL_JDI_XXX062M:
nx->suspend_cmds = suspend_cmds_PANEL_JDI_XXX062M;
break;
case PANEL_AUO_A062TAN01:
nx->suspend_cmds = suspend_cmds_PANEL_AUO_A062TAN01;
break;
case PANEL_INL_2J055IA_27A:
nx->suspend_cmds = suspend_cmds_PANEL_INL_2J055IA_27A;
break;
case PANEL_AUO_A055TAN01:
nx->suspend_cmds = suspend_cmds_PANEL_AUO_A055TAN01;
break;
case PANEL_SHP_LQ055T1SW10:
nx->suspend_cmds = suspend_cmds_PANEL_SHP_LQ055T1SW10;
break;
case PANEL_SAM_AMS699VC01:
nx->suspend_cmds = suspend_cmds_PANEL_SAM_AMS699VC01;
break;
case PANEL_INL_P062CCA_AZ1:
default:
dev_info(&nx->dsi->dev, "using default suspend sequence\n");
break;
}
msleep(20);
}
static int nx_mipi_dsi_dcs_cmds(struct init_cmd *cmds, struct nx_panel *nx)
{
int ret = 0;
while (cmds && cmds->length != -1) {
if (cmds->cmd == 0xFF)
msleep(cmds->length);
else {
ret = mipi_dsi_dcs_write(nx->dsi, cmds->cmd,
cmds->data, cmds->length);
if (ret < 0) {
dev_err(&nx->dsi->dev,
"failed to write dsi_cmd: %d error: %d\n",
cmds->cmd, ret);
return ret;
}
}
cmds++;
}
return ret;
}
static int nx_panel_init(struct nx_panel *nx)
{
struct mipi_dsi_device *dsi = nx->dsi;
struct device *dev = &nx->dsi->dev;
int ret;
dsi->mode_flags |= MIPI_DSI_MODE_LPM;
printk("nx_panel_init");
ret = mipi_dsi_set_maximum_return_packet_size(dsi, 3);
if (ret < 0) {
dev_err(dev, "failed to set maximum return packet size: %d\n",
ret);
return ret;
}
nx_panel_detect(nx);
ret = nx_mipi_dsi_dcs_cmds(nx->init_cmds, nx);
if (ret < 0)
return ret;
ret = mipi_dsi_dcs_set_column_address(dsi, 0, nx->mode->hdisplay - 1);
if (ret < 0) {
dev_err(dev, "failed to set page address: %d\n", ret);
return ret;
}
ret = mipi_dsi_dcs_set_page_address(dsi, 0, nx->mode->vdisplay - 1);
if (ret < 0) {
dev_err(dev, "failed to set column address: %d\n", ret);
return ret;
}
ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
if (ret < 0) {
dev_err(dev, "failed to set vblank tear on: %d\n", ret);
return ret;
}
ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT);
if (ret < 0) {
dev_err(dev, "failed to set pixel format: %d\n", ret);
return ret;
}
return 0;
}
static int nx_panel_enable(struct drm_panel *panel)
{
struct nx_panel *nx = to_nx_panel(panel);
if (nx->enabled)
return 0;
backlight_enable(nx->backlight);
nx->enabled = true;
return 0;
}
static int nx_panel_disable(struct drm_panel *panel)
{
struct nx_panel *nx = to_nx_panel(panel);
if (!nx->enabled)
return 0;
backlight_disable(nx->backlight);
nx->enabled = false;
return 0;
}
static int nx_panel_unprepare(struct drm_panel *panel)
{
struct nx_panel *nx = to_nx_panel(panel);
int ret;
if (!nx->prepared)
return 0;
nx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
ret = nx_mipi_dsi_dcs_cmds(nx->suspend_cmds, nx);
if (ret < 0)
dev_err(&nx->dsi->dev, "failed to write suspend cmds: %d\n",
ret);
if (nx->reset_gpio)
gpiod_set_value(nx->reset_gpio, 0);
msleep(10);
regulator_disable(nx->supply2);
msleep(10);
regulator_disable(nx->supply1);
nx->prepared = false;
return 0;
}
static int nx_panel_prepare(struct drm_panel *panel)
{
struct nx_panel *nx = to_nx_panel(panel);
struct device *dev = &nx->dsi->dev;
int ret;
printk("nx panel prepare");
if (nx->prepared)
return 0;
ret = regulator_enable(nx->supply1);
if (ret < 0)
return ret;
msleep(10);
ret = regulator_enable(nx->supply2);
if (ret < 0)
goto poweroff;
msleep(10);
if (nx->reset_gpio) {
gpiod_set_value(nx->reset_gpio, 0);
msleep(10);
gpiod_set_value(nx->reset_gpio, 1);
msleep(60);
}
nx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
ret = nx_panel_init(nx);
if (ret < 0) {
dev_err(dev, "failed to init panel: %d\n", ret);
goto reset;
}
nx->prepared = true;
return 0;
reset:
if (nx->reset_gpio)
gpiod_set_value(nx->reset_gpio, 0);
regulator_disable(nx->supply2);
poweroff:
regulator_disable(nx->supply1);
return ret;
}
static const struct drm_display_mode default_mode = {
.clock = 78000,
.hdisplay = 720,
.hsync_start = 720 + 136,
.hsync_end = 720 + 136 + 72,
.htotal = 720 + 136 + 72 + 72,
.vdisplay = 1280,
.vsync_start = 1280 + 10,
.vsync_end = 1280 + 10 + 2,
.vtotal = 1280 + 10 + 1 + 9,
.width_mm = 77,
.height_mm = 137,
};
static int nx_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct drm_display_mode *mode;
struct nx_panel *nx = to_nx_panel(panel);
struct device *dev = &nx->dsi->dev;
printk("nx panel get_modes");
mode = drm_mode_duplicate(connector->dev, &default_mode);
if (!mode) {
dev_err(dev, "failed to add mode %ux%ux@%u\n",
default_mode.hdisplay, default_mode.vdisplay,
drm_mode_vrefresh(&default_mode));
return -ENOMEM;
}
drm_mode_set_name(mode);
drm_mode_probed_add(connector, mode);
connector->display_info.width_mm = default_mode.width_mm;
connector->display_info.height_mm = default_mode.height_mm;
return 1;
}
static const struct drm_panel_funcs nx_panel_funcs = {
.prepare = nx_panel_prepare,
.unprepare = nx_panel_unprepare,
.enable = nx_panel_enable,
.disable = nx_panel_disable,
.get_modes = nx_panel_get_modes,
};
static int nx_panel_add(struct nx_panel *nx)
{
struct device *dev = &nx->dsi->dev;
struct device_node *np;
printk("nx_panel_add");
nx->mode = &default_mode;
nx->supply1 = devm_regulator_get(dev, "vdd1");
if (IS_ERR(nx->supply1))
return PTR_ERR(nx->supply1);
nx->supply2 = devm_regulator_get(dev, "vdd2");
if (IS_ERR(nx->supply2))
return PTR_ERR(nx->supply2);
nx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(nx->reset_gpio)) {
dev_err(dev, "cannot get reset-gpios %ld\n",
PTR_ERR(nx->reset_gpio));
nx->reset_gpio = NULL;
} else {
gpiod_set_value(nx->reset_gpio, 0);
}
printk("backlight");
np = of_parse_phandle(dev->of_node, "backlight", 0);
if (np) {
nx->backlight = of_find_backlight_by_node(np);
of_node_put(np);
if (!nx->backlight)
return -EPROBE_DEFER;
}
printk("panel init");
drm_panel_init(&nx->base, &nx->dsi->dev, &nx_panel_funcs,
DRM_MODE_CONNECTOR_DSI);
printk("drm panel add");
drm_panel_add(&nx->base);
return 0;
}
static void nx_panel_del(struct nx_panel *nx)
{
if (nx->base.dev)
drm_panel_remove(&nx->base);
if (nx->backlight)
put_device(&nx->backlight->dev);
}
static int nx_panel_probe(struct mipi_dsi_device *dsi)
{
struct nx_panel *nx;
int ret;
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_CLOCK_NON_CONTINUOUS |
MIPI_DSI_MODE_NO_EOT_PACKET;
printk("nx_panel_probe");
nx = devm_kzalloc(&dsi->dev, sizeof(*nx), GFP_KERNEL);
if (!nx)
return -ENOMEM;
printk("set drvdata");
mipi_dsi_set_drvdata(dsi, nx);
nx->dsi = dsi;
printk("add panel");
ret = nx_panel_add(nx);
if (ret < 0)
return ret;
printk("dsi attach");
ret = mipi_dsi_attach(dsi);
if (ret < 0) {
nx_panel_del(nx);
return ret;
}
return 0;
}
static void nx_panel_remove(struct mipi_dsi_device *dsi)
{
struct nx_panel *nx = mipi_dsi_get_drvdata(dsi);
int ret;
printk("nx_panel_remove");
ret = nx_panel_disable(&nx->base);
if (ret < 0)
dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
ret = mipi_dsi_detach(dsi);
if (ret < 0)
dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
nx_panel_del(nx);
}
static void nx_panel_shutdown(struct mipi_dsi_device *dsi)
{
struct nx_panel *nx = mipi_dsi_get_drvdata(dsi);
nx_panel_disable(&nx->base);
}
static const struct of_device_id nx_panel_of_match[] = {
{
.compatible = "nintendo,nx-dsi",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, nx_panel_of_match);
static struct mipi_dsi_driver nx_panel_driver = {
.driver = {
.name = "panel-nx-dsi",
.of_match_table = nx_panel_of_match,
},
.probe = nx_panel_probe,
.remove = nx_panel_remove,
.shutdown = nx_panel_shutdown,
};
module_mipi_dsi_driver(nx_panel_driver);
MODULE_AUTHOR("SwtcR <swtcr0@gmail.com>");
MODULE_DESCRIPTION("Nintendo Switch DSI (720x1280) panel driver");
MODULE_LICENSE("GPL v2");

233
drivers/gpu/drm/panel/panel-sharp-lq079l1sx01.c Normal file
View File

@@ -0,0 +1,233 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NVIDIA Corporation
* Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <drm/drm_connector.h>
#include <drm/drm_crtc.h>
#include <drm/drm_device.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>
static const struct regulator_bulk_data sharp_supplies[] = {
{ .supply = "avdd" }, { .supply = "vddio" },
{ .supply = "vsp" }, { .supply = "vsn" },
};
struct sharp_panel {
struct drm_panel panel;
struct mipi_dsi_device *dsi[2];
struct gpio_desc *reset_gpio;
struct regulator_bulk_data *supplies;
const struct drm_display_mode *mode;
};
#define mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, cmd, seq...) \
do { \
dsi_ctx.dsi = dsi0; \
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, cmd, seq); \
dsi_ctx.dsi = dsi1; \
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, cmd, seq); \
} while (0)
static inline struct sharp_panel *to_sharp_panel(struct drm_panel *panel)
{
return container_of(panel, struct sharp_panel, panel);
}
static void sharp_panel_reset(struct sharp_panel *sharp)
{
gpiod_set_value_cansleep(sharp->reset_gpio, 1);
usleep_range(2000, 3000);
gpiod_set_value_cansleep(sharp->reset_gpio, 0);
usleep_range(2000, 3000);
}
static int sharp_panel_prepare(struct drm_panel *panel)
{
struct sharp_panel *sharp = to_sharp_panel(panel);
struct device *dev = panel->dev;
struct mipi_dsi_device *dsi0 = sharp->dsi[0];
struct mipi_dsi_device *dsi1 = sharp->dsi[1];
struct mipi_dsi_multi_context dsi_ctx = { .dsi = NULL };
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(sharp_supplies), sharp->supplies);
if (ret) {
dev_err(dev, "error enabling regulators (%d)\n", ret);
return ret;
}
msleep(24);
if (sharp->reset_gpio)
sharp_panel_reset(sharp);
msleep(32);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, MIPI_DCS_EXIT_SLEEP_MODE);
mipi_dsi_msleep(&dsi_ctx, 120);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1,
MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0xff);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1,
MIPI_DCS_WRITE_POWER_SAVE, 0x01);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1,
MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, MIPI_DCS_SET_DISPLAY_ON);
return 0;
}
static int sharp_panel_unprepare(struct drm_panel *panel)
{
struct sharp_panel *sharp = to_sharp_panel(panel);
struct mipi_dsi_device *dsi0 = sharp->dsi[0];
struct mipi_dsi_device *dsi1 = sharp->dsi[1];
struct mipi_dsi_multi_context dsi_ctx = { .dsi = NULL };
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, MIPI_DCS_SET_DISPLAY_OFF);
mipi_dsi_msleep(&dsi_ctx, 100);
mipi_dsi_dual_dcs_write_seq_multi(dsi_ctx, dsi0, dsi1, MIPI_DCS_ENTER_SLEEP_MODE);
mipi_dsi_msleep(&dsi_ctx, 150);
gpiod_set_value_cansleep(sharp->reset_gpio, 1);
return regulator_bulk_disable(ARRAY_SIZE(sharp_supplies), sharp->supplies);
}
static const struct drm_display_mode default_mode = {
.clock = (1536 + 136 + 28 + 28) * (2048 + 14 + 8 + 2) * 60 / 1000,
.hdisplay = 1536,
.hsync_start = 1536 + 136,
.hsync_end = 1536 + 136 + 28,
.htotal = 1536 + 136 + 28 + 28,
.vdisplay = 2048,
.vsync_start = 2048 + 14,
.vsync_end = 2048 + 14 + 8,
.vtotal = 2048 + 14 + 8 + 2,
.width_mm = 120,
.height_mm = 160,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static int sharp_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
return drm_connector_helper_get_modes_fixed(connector, &default_mode);
}
static const struct drm_panel_funcs sharp_panel_funcs = {
.unprepare = sharp_panel_unprepare,
.prepare = sharp_panel_prepare,
.get_modes = sharp_panel_get_modes,
};
static int sharp_panel_probe(struct mipi_dsi_device *dsi)
{
const struct mipi_dsi_device_info info = { "sharp-link1", 0, NULL };
struct device *dev = &dsi->dev;
struct device_node *dsi_r;
struct mipi_dsi_host *dsi_r_host;
struct sharp_panel *sharp;
int i, ret;
sharp = devm_kzalloc(dev, sizeof(*sharp), GFP_KERNEL);
if (!sharp)
return -ENOMEM;
ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(sharp_supplies),
sharp_supplies, &sharp->supplies);
if (ret)
return dev_err_probe(dev, ret, "failed to get supplies\n");
sharp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(sharp->reset_gpio))
return dev_err_probe(dev, PTR_ERR(sharp->reset_gpio),
"failed to get reset GPIO\n");
/* Panel is always connected to two DSI hosts, DSI0 is left, DSI1 is right */
dsi_r = of_graph_get_remote_node(dsi->dev.of_node, 1, -1);
if (!dsi_r)
return dev_err_probe(dev, -ENODEV, "failed to find second DSI host node\n");
dsi_r_host = of_find_mipi_dsi_host_by_node(dsi_r);
of_node_put(dsi_r);
if (!dsi_r_host)
return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");
sharp->dsi[1] = devm_mipi_dsi_device_register_full(dev, dsi_r_host, &info);
if (IS_ERR(sharp->dsi[1]))
return dev_err_probe(dev, PTR_ERR(sharp->dsi[1]),
"second link registration failed\n");
sharp->dsi[0] = dsi;
mipi_dsi_set_drvdata(dsi, sharp);
drm_panel_init(&sharp->panel, dev, &sharp_panel_funcs,
DRM_MODE_CONNECTOR_DSI);
ret = drm_panel_of_backlight(&sharp->panel);
if (ret)
return dev_err_probe(dev, ret, "Failed to get backlight\n");
drm_panel_add(&sharp->panel);
for (i = 0; i < ARRAY_SIZE(sharp->dsi); i++) {
if (!sharp->dsi[i])
continue;
sharp->dsi[i]->lanes = 4;
sharp->dsi[i]->format = MIPI_DSI_FMT_RGB888;
sharp->dsi[i]->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
ret = devm_mipi_dsi_attach(dev, sharp->dsi[i]);
if (ret < 0) {
drm_panel_remove(&sharp->panel);
return dev_err_probe(dev, ret, "failed to attach to DSI%d\n", i);
}
}
return 0;
}
static void sharp_panel_remove(struct mipi_dsi_device *dsi)
{
struct sharp_panel *sharp = mipi_dsi_get_drvdata(dsi);
drm_panel_remove(&sharp->panel);
}
static const struct of_device_id sharp_of_match[] = {
{ .compatible = "sharp,lq079l1sx01" },
{ }
};
MODULE_DEVICE_TABLE(of, sharp_of_match);
static struct mipi_dsi_driver sharp_panel_driver = {
.driver = {
.name = "panel-sharp-lq079l1sx01",
.of_match_table = sharp_of_match,
},
.probe = sharp_panel_probe,
.remove = sharp_panel_remove,
};
module_mipi_dsi_driver(sharp_panel_driver);
MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
MODULE_DESCRIPTION("Sharp LQ079L1SX01 panel driver");
MODULE_LICENSE("GPL");

2
drivers/gpu/drm/tegra/Makefile
View File

@@ -25,6 +25,8 @@ tegra-drm-y := \
falcon.o \
vic.o \
nvdec.o \
nvenc.o \
nvjpg.o \
riscv.o
tegra-drm-y += trace.o

120
drivers/gpu/drm/tegra/dc.c
View File

@@ -35,6 +35,103 @@
#include "hub.h"
#include "plane.h"
static u16 default_srgb_lut[] = {
0x6000, 0x60CE, 0x619D, 0x626C, 0x632D, 0x63D4, 0x6469, 0x64F0, 0x656B, 0x65DF, 0x664A,
0x66B0, 0x6711, 0x676D, 0x67C4, 0x6819, 0x686A, 0x68B8, 0x6904, 0x694D, 0x6994, 0x69D8,
0x6A1B, 0x6A5D, 0x6A9C, 0x6ADA, 0x6B17, 0x6B52, 0x6B8C, 0x6BC5, 0x6BFD, 0x6C33, 0x6C69,
0x6C9E, 0x6CD1, 0x6D04, 0x6D36, 0x6D67, 0x6D98, 0x6DC7, 0x6DF6, 0x6E25, 0x6E52, 0x6E7F,
0x6EAC, 0x6ED7, 0x6F03, 0x6F2D, 0x6F58, 0x6F81, 0x6FAA, 0x6FD3, 0x6FFB, 0x7023, 0x704B,
0x7071, 0x7098, 0x70BE, 0x70E4, 0x7109, 0x712E, 0x7153, 0x7177, 0x719B, 0x71BF, 0x71E2,
0x7205, 0x7227, 0x724A, 0x726C, 0x728E, 0x72AF, 0x72D0, 0x72F1, 0x7312, 0x7333, 0x7353,
0x7373, 0x7392, 0x73B2, 0x73D1, 0x73F0, 0x740F, 0x742D, 0x744C, 0x746A, 0x7488, 0x74A6,
0x74C3, 0x74E0, 0x74FE, 0x751B, 0x7537, 0x7554, 0x7570, 0x758D, 0x75A9, 0x75C4, 0x75E0,
0x75FC, 0x7617, 0x7632, 0x764D, 0x7668, 0x7683, 0x769E, 0x76B8, 0x76D3, 0x76ED, 0x7707,
0x7721, 0x773B, 0x7754, 0x776E, 0x7787, 0x77A0, 0x77B9, 0x77D2, 0x77EB, 0x7804, 0x781D,
0x7835, 0x784E, 0x7866, 0x787E, 0x7896, 0x78AE, 0x78C6, 0x78DD, 0x78F5, 0x790D, 0x7924,
0x793B, 0x7952, 0x796A, 0x7981, 0x7997, 0x79AE, 0x79C5, 0x79DB, 0x79F2, 0x7A08, 0x7A1F,
0x7A35, 0x7A4B, 0x7A61, 0x7A77, 0x7A8D, 0x7AA3, 0x7AB8, 0x7ACE, 0x7AE3, 0x7AF9, 0x7B0E,
0x7B24, 0x7B39, 0x7B4E, 0x7B63, 0x7B78, 0x7B8D, 0x7BA2, 0x7BB6, 0x7BCB, 0x7BE0, 0x7BF4,
0x7C08, 0x7C1D, 0x7C31, 0x7C45, 0x7C59, 0x7C6E, 0x7C82, 0x7C96, 0x7CA9, 0x7CBD, 0x7CD1,
0x7CE5, 0x7CF8, 0x7D0C, 0x7D1F, 0x7D33, 0x7D46, 0x7D59, 0x7D6D, 0x7D80, 0x7D93, 0x7DA6,
0x7DB9, 0x7DCC, 0x7DDF, 0x7DF2, 0x7E04, 0x7E17, 0x7E2A, 0x7E3C, 0x7E4F, 0x7E61, 0x7E74,
0x7E86, 0x7E98, 0x7EAB, 0x7EBD, 0x7ECF, 0x7EE1, 0x7EF3, 0x7F05, 0x7F17, 0x7F29, 0x7F3B,
0x7F4D, 0x7F5E, 0x7F70, 0x7F82, 0x7F93, 0x7FA5, 0x7FB6, 0x7FC8, 0x7FD9, 0x7FEB, 0x7FFC,
0x800D, 0x801E, 0x8030, 0x8041, 0x8052, 0x8063, 0x8074, 0x8085, 0x8096, 0x80A7, 0x80B7,
0x80C8, 0x80D9, 0x80EA, 0x80FA, 0x810B, 0x811C, 0x812C, 0x813D, 0x814D, 0x815D, 0x816E,
0x817E, 0x818E, 0x819F, 0x81AF, 0x81BF, 0x81CF, 0x81DF, 0x81EF, 0x81FF, 0x820F, 0x821F,
0x822F, 0x823F, 0x824F, 0x825F, 0x826F, 0x827E, 0x828E, 0x829E, 0x82AD, 0x82BD, 0x82CC,
0x82DC, 0x82EB, 0x82FB, 0x830A, 0x831A, 0x8329, 0x8338, 0x8348, 0x8357, 0x8366, 0x8375,
0x8385, 0x8394, 0x83A3, 0x83B2, 0x83C1, 0x83D0, 0x83DF, 0x83EE, 0x83FD, 0x840C, 0x841A,
0x8429, 0x8438, 0x8447, 0x8455, 0x8464, 0x8473, 0x8481, 0x8490, 0x849F, 0x84AD, 0x84BC,
0x84CA, 0x84D9, 0x84E7, 0x84F5, 0x8504, 0x8512, 0x8521, 0x852F, 0x853D, 0x854B, 0x855A,
0x8568, 0x8576, 0x8584, 0x8592, 0x85A0, 0x85AE, 0x85BC, 0x85CA, 0x85D8, 0x85E6, 0x85F4,
0x8602, 0x8610, 0x861E, 0x862C, 0x8639, 0x8647, 0x8655, 0x8663, 0x8670, 0x867E, 0x868C,
0x8699, 0x86A7, 0x86B5, 0x86C2, 0x86D0, 0x86DD, 0x86EB, 0x86F8, 0x8705, 0x8713, 0x8720,
0x872E, 0x873B, 0x8748, 0x8756, 0x8763, 0x8770, 0x877D, 0x878B, 0x8798, 0x87A5, 0x87B2,
0x87BF, 0x87CC, 0x87D9, 0x87E6, 0x87F3, 0x8801, 0x880E, 0x881A, 0x8827, 0x8834, 0x8841,
0x884E, 0x885B, 0x8868, 0x8875, 0x8882, 0x888E, 0x889B, 0x88A8, 0x88B5, 0x88C1, 0x88CE,
0x88DB, 0x88E7, 0x88F4, 0x8900, 0x890D, 0x891A, 0x8926, 0x8933, 0x893F, 0x894C, 0x8958,
0x8965, 0x8971, 0x897D, 0x898A, 0x8996, 0x89A3, 0x89AF, 0x89BB, 0x89C8, 0x89D4, 0x89E0,
0x89EC, 0x89F9, 0x8A05, 0x8A11, 0x8A1D, 0x8A29, 0x8A36, 0x8A42, 0x8A4E, 0x8A5A, 0x8A66,
0x8A72, 0x8A7E, 0x8A8A, 0x8A96, 0x8AA2, 0x8AAE, 0x8ABA, 0x8AC6, 0x8AD2, 0x8ADE, 0x8AEA,
0x8AF5, 0x8B01, 0x8B0D, 0x8B19, 0x8B25, 0x8B31, 0x8B3C, 0x8B48, 0x8B54, 0x8B60, 0x8B6B,
0x8B77, 0x8B83, 0x8B8E, 0x8B9A, 0x8BA6, 0x8BB1, 0x8BBD, 0x8BC8, 0x8BD4, 0x8BDF, 0x8BEB,
0x8BF6, 0x8C02, 0x8C0D, 0x8C19, 0x8C24, 0x8C30, 0x8C3B, 0x8C47, 0x8C52, 0x8C5D, 0x8C69,
0x8C74, 0x8C80, 0x8C8B, 0x8C96, 0x8CA1, 0x8CAD, 0x8CB8, 0x8CC3, 0x8CCF, 0x8CDA, 0x8CE5,
0x8CF0, 0x8CFB, 0x8D06, 0x8D12, 0x8D1D, 0x8D28, 0x8D33, 0x8D3E, 0x8D49, 0x8D54, 0x8D5F,
0x8D6A, 0x8D75, 0x8D80, 0x8D8B, 0x8D96, 0x8DA1, 0x8DAC, 0x8DB7, 0x8DC2, 0x8DCD, 0x8DD8,
0x8DE3, 0x8DEE, 0x8DF9, 0x8E04, 0x8E0E, 0x8E19, 0x8E24, 0x8E2F, 0x8E3A, 0x8E44, 0x8E4F,
0x8E5A, 0x8E65, 0x8E6F, 0x8E7A, 0x8E85, 0x8E90, 0x8E9A, 0x8EA5, 0x8EB0, 0x8EBA, 0x8EC5,
0x8ECF, 0x8EDA, 0x8EE5, 0x8EEF, 0x8EFA, 0x8F04, 0x8F0F, 0x8F19, 0x8F24, 0x8F2E, 0x8F39,
0x8F43, 0x8F4E, 0x8F58, 0x8F63, 0x8F6D, 0x8F78, 0x8F82, 0x8F8C, 0x8F97, 0x8FA1, 0x8FAC,
0x8FB6, 0x8FC0, 0x8FCB, 0x8FD5, 0x8FDF, 0x8FEA, 0x8FF4, 0x8FFE, 0x9008, 0x9013, 0x901D,
0x9027, 0x9031, 0x903C, 0x9046, 0x9050, 0x905A, 0x9064, 0x906E, 0x9079, 0x9083, 0x908D,
0x9097, 0x90A1, 0x90AB, 0x90B5, 0x90BF, 0x90C9, 0x90D3, 0x90DD, 0x90E7, 0x90F1, 0x90FB,
0x9105, 0x910F, 0x9119, 0x9123, 0x912D, 0x9137, 0x9141, 0x914B, 0x9155, 0x915F, 0x9169,
0x9173, 0x917D, 0x9186, 0x9190, 0x919A, 0x91A4, 0x91AE, 0x91B8, 0x91C1, 0x91CB, 0x91D5,
0x91DF, 0x91E9, 0x91F2, 0x91FC, 0x9206, 0x9210, 0x9219, 0x9223, 0x922D, 0x9236, 0x9240,
0x924A, 0x9253, 0x925D, 0x9267, 0x9270, 0x927A, 0x9283, 0x928D, 0x9297, 0x92A0, 0x92AA,
0x92B3, 0x92BD, 0x92C6, 0x92D0, 0x92DA, 0x92E3, 0x92ED, 0x92F6, 0x9300, 0x9309, 0x9313,
0x931C, 0x9325, 0x932F, 0x9338, 0x9342, 0x934B, 0x9355, 0x935E, 0x9367, 0x9371, 0x937A,
0x9384, 0x938D, 0x9396, 0x93A0, 0x93A9, 0x93B2, 0x93BC, 0x93C5, 0x93CE, 0x93D7, 0x93E1,
0x93EA, 0x93F3, 0x93FC, 0x9406, 0x940F, 0x9418, 0x9421, 0x942B, 0x9434, 0x943D, 0x9446,
0x944F, 0x9459, 0x9462, 0x946B, 0x9474, 0x947D, 0x9486, 0x948F, 0x9499, 0x94A2, 0x94AB,
0x94B4, 0x94BD, 0x94C6, 0x94CF, 0x94D8, 0x94E1, 0x94EA, 0x94F3, 0x94FC, 0x9505, 0x950E,
0x9517, 0x9520, 0x9529, 0x9532, 0x953B, 0x9544, 0x954D, 0x9556, 0x955F, 0x9568, 0x9571,
0x957A, 0x9583, 0x958C, 0x9595, 0x959D, 0x95A6, 0x95AF, 0x95B8, 0x95C1, 0x95CA, 0x95D3,
0x95DB, 0x95E4, 0x95ED, 0x95F6, 0x95FF, 0x9608, 0x9610, 0x9619, 0x9622, 0x962B, 0x9633,
0x963C, 0x9645, 0x964E, 0x9656, 0x965F, 0x9668, 0x9671, 0x9679, 0x9682, 0x968B, 0x9693,
0x969C, 0x96A5, 0x96AD, 0x96B6, 0x96BF, 0x96C7, 0x96D0, 0x96D9, 0x96E1, 0x96EA, 0x96F2,
0x96FB, 0x9704, 0x970C, 0x9715, 0x971D, 0x9726, 0x972E, 0x9737, 0x9740, 0x9748, 0x9751,
0x9759, 0x9762, 0x976A, 0x9773, 0x977B, 0x9784, 0x978C, 0x9795, 0x979D, 0x97A6, 0x97AE,
0x97B6, 0x97BF, 0x97C7, 0x97D0, 0x97D8, 0x97E1, 0x97E9, 0x97F1, 0x97FA, 0x9802, 0x980B,
0x9813, 0x981B, 0x9824, 0x982C, 0x9834, 0x983D, 0x9845, 0x984D, 0x9856, 0x985E, 0x9866,
0x986F, 0x9877, 0x987F, 0x9888, 0x9890, 0x9898, 0x98A0, 0x98A9, 0x98B1, 0x98B9, 0x98C1,
0x98CA, 0x98D2, 0x98DA, 0x98E2, 0x98EB, 0x98F3, 0x98FB, 0x9903, 0x990B, 0x9914, 0x991C,
0x9924, 0x992C, 0x9934, 0x993C, 0x9945, 0x994D, 0x9955, 0x995D, 0x9965, 0x996D, 0x9975,
0x997D, 0x9986, 0x998E, 0x9996, 0x999E, 0x99A6, 0x99AE, 0x99B6, 0x99BE, 0x99C6, 0x99CE,
0x99D6, 0x99DE, 0x99E6, 0x99EE, 0x99F6, 0x99FE, 0x9A06, 0x9A0E, 0x9A16, 0x9A1E, 0x9A26,
0x9A2E, 0x9A36, 0x9A3E, 0x9A46, 0x9A4E, 0x9A56, 0x9A5E, 0x9A66, 0x9A6E, 0x9A76, 0x9A7E,
0x9A86, 0x9A8E, 0x9A96, 0x9A9D, 0x9AA5, 0x9AAD, 0x9AB5, 0x9ABD, 0x9AC5, 0x9ACD, 0x9AD5,
0x9ADC, 0x9AE4, 0x9AEC, 0x9AF4, 0x9AFC, 0x9B04, 0x9B0C, 0x9B13, 0x9B1B, 0x9B23, 0x9B2B,
0x9B33, 0x9B3A, 0x9B42, 0x9B4A, 0x9B52, 0x9B59, 0x9B61, 0x9B69, 0x9B71, 0x9B79, 0x9B80,
0x9B88, 0x9B90, 0x9B97, 0x9B9F, 0x9BA7, 0x9BAF, 0x9BB6, 0x9BBE, 0x9BC6, 0x9BCD, 0x9BD5,
0x9BDD, 0x9BE5, 0x9BEC, 0x9BF4, 0x9BFC, 0x9C03, 0x9C0B, 0x9C12, 0x9C1A, 0x9C22, 0x9C29,
0x9C31, 0x9C39, 0x9C40, 0x9C48, 0x9C50, 0x9C57, 0x9C5F, 0x9C66, 0x9C6E, 0x9C75, 0x9C7D,
0x9C85, 0x9C8C, 0x9C94, 0x9C9B, 0x9CA3, 0x9CAA, 0x9CB2, 0x9CBA, 0x9CC1, 0x9CC9, 0x9CD0,
0x9CD8, 0x9CDF, 0x9CE7, 0x9CEE, 0x9CF6, 0x9CFD, 0x9D05, 0x9D0C, 0x9D14, 0x9D1B, 0x9D23,
0x9D2A, 0x9D32, 0x9D39, 0x9D40, 0x9D48, 0x9D4F, 0x9D57, 0x9D5E, 0x9D66, 0x9D6D, 0x9D75,
0x9D7C, 0x9D83, 0x9D8B, 0x9D92, 0x9D9A, 0x9DA1, 0x9DA8, 0x9DB0, 0x9DB7, 0x9DBE, 0x9DC6,
0x9DCD, 0x9DD5, 0x9DDC, 0x9DE3, 0x9DEB, 0x9DF2, 0x9DF9, 0x9E01, 0x9E08, 0x9E0F, 0x9E17,
0x9E1E, 0x9E25, 0x9E2D, 0x9E34, 0x9E3B, 0x9E43, 0x9E4A, 0x9E51, 0x9E58, 0x9E60, 0x9E67,
0x9E6E, 0x9E75, 0x9E7D, 0x9E84, 0x9E8B, 0x9E92, 0x9E9A, 0x9EA1, 0x9EA8, 0x9EAF, 0x9EB7,
0x9EBE, 0x9EC5, 0x9ECC, 0x9ED4, 0x9EDB, 0x9EE2, 0x9EE9, 0x9EF0, 0x9EF7, 0x9EFF, 0x9F06,
0x9F0D, 0x9F14, 0x9F1B, 0x9F23, 0x9F2A, 0x9F31, 0x9F38, 0x9F3F, 0x9F46, 0x9F4D, 0x9F55,
0x9F5C, 0x9F63, 0x9F6A, 0x9F71, 0x9F78, 0x9F7F, 0x9F86, 0x9F8D, 0x9F95, 0x9F9C, 0x9FA3,
0x9FAA, 0x9FB1, 0x9FB8, 0x9FBF, 0x9FC6, 0x9FCD, 0x9FD4, 0x9FDB, 0x9FE2, 0x9FE9, 0x9FF0,
0x9FF7, 0x9FFF,
};
static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
@@ -3241,6 +3338,25 @@ static int tegra_dc_probe(struct platform_device *pdev)
if (dc->irq < 0)
return -ENXIO;
if (dc->soc->has_nvdisplay) {
unsigned int i;
u64 r;
dc->cmu_output_lut =
dma_alloc_coherent(dc->dev, ARRAY_SIZE(default_srgb_lut) * sizeof(u64),
&dc->cmu_output_phys, GFP_KERNEL);
if (!dc->cmu_output_lut || !dc->cmu_output_phys) {
dev_err(dc->dev, "failed to allocate lut for cmu\n");
return -ENOMEM;
}
for (i = 0; i < ARRAY_SIZE(default_srgb_lut); i++) {
r = default_srgb_lut[i];
dc->cmu_output_lut[i] = (r << 32) | (r << 16) | r;
}
}
err = tegra_dc_rgb_probe(dc);
if (err < 0 && err != -ENODEV)
return dev_err_probe(&pdev->dev, err,
@@ -3277,6 +3393,10 @@ static void tegra_dc_remove(struct platform_device *pdev)
tegra_dc_rgb_remove(dc);
if (dc->soc->has_nvdisplay)
dma_free_coherent(dc->dev, ARRAY_SIZE(default_srgb_lut) * sizeof(u64),
dc->cmu_output_lut, dc->cmu_output_phys);
pm_runtime_disable(&pdev->dev);
}

13
drivers/gpu/drm/tegra/dc.h
View File

@@ -103,6 +103,9 @@ struct tegra_dc {
const struct tegra_dc_soc_info *soc;
bool has_opp_table;
u64 *cmu_output_lut;
dma_addr_t cmu_output_phys;
};
static inline struct tegra_dc *
@@ -447,6 +450,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define BASE_COLOR_SIZE_888 ( 8 << 0)
#define BASE_COLOR_SIZE_101010 ( 10 << 0)
#define BASE_COLOR_SIZE_121212 ( 12 << 0)
#define CMU_ENABLE_ENABLE (1 << 20)
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
#define SC1_H_QUALIFIER_NONE (1 << 16)
@@ -732,6 +736,15 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
#define PROTOCOL_MASK (0xf << 8)
#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT 0x431
#define OUTPUT_LUT_MODE_MASK (3 << 5)
#define OUTPUT_LUT_MODE_INTERPOLATE (1 << 5)
#define OUTPUT_LUT_SIZE_MASK (3 << 1)
#define OUTPUT_LUT_SIZE_SIZE_1025 (2 << 1)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE 0x432
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI 0x433
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446

11
drivers/gpu/drm/tegra/drm.c
View File

@@ -1378,23 +1378,32 @@ static const struct of_device_id host1x_drm_subdevs[] = {
{ .compatible = "nvidia,tegra132-dsi", },
{ .compatible = "nvidia,tegra210-dc", },
{ .compatible = "nvidia,tegra210-dsi", },
{ .compatible = "nvidia,tegra210b01-dsi", },
{ .compatible = "nvidia,tegra210-sor", },
{ .compatible = "nvidia,tegra210-sor1", },
{ .compatible = "nvidia,tegra210-vic", },
{ .compatible = "nvidia,tegra210-nvdec", },
{ .compatible = "nvidia,tegra210-nvenc", },
{ .compatible = "nvidia,tegra210-nvjpg", },
{ .compatible = "nvidia,tegra186-display", },
{ .compatible = "nvidia,tegra186-dc", },
{ .compatible = "nvidia,tegra186-sor", },
{ .compatible = "nvidia,tegra186-sor1", },
{ .compatible = "nvidia,tegra186-vic", },
{ .compatible = "nvidia,tegra186-nvdec", },
{ .compatible = "nvidia,tegra186-nvenc", },
{ .compatible = "nvidia,tegra186-nvjpg", },
{ .compatible = "nvidia,tegra194-display", },
{ .compatible = "nvidia,tegra194-dc", },
{ .compatible = "nvidia,tegra194-sor", },
{ .compatible = "nvidia,tegra194-vic", },
{ .compatible = "nvidia,tegra194-nvdec", },
{ .compatible = "nvidia,tegra194-nvenc", },
{ .compatible = "nvidia,tegra194-nvjpg", },
{ .compatible = "nvidia,tegra234-vic", },
{ .compatible = "nvidia,tegra234-nvdec", },
{ .compatible = "nvidia,tegra234-nvenc", },
{ .compatible = "nvidia,tegra234-nvjpg", },
{ /* sentinel */ }
};
@@ -1420,6 +1429,8 @@ static struct platform_driver * const drivers[] = {
&tegra_gr3d_driver,
&tegra_vic_driver,
&tegra_nvdec_driver,
&tegra_nvenc_driver,
&tegra_nvjpg_driver,
};
static int __init host1x_drm_init(void)

15
drivers/gpu/drm/tegra/drm.h
View File

@@ -126,9 +126,22 @@ void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
struct cec_notifier;
struct notify_dev {
const char *name;
struct device *dev;
int index;
int state;
ssize_t (*print_name)(struct notify_dev *sdev, char *buf);
ssize_t (*print_state)(struct notify_dev *sdev, char *buf);
};
struct tegra_output {
struct device_node *of_node;
struct device *dev;
struct notify_dev notify_data;
struct class *switch_class;
atomic_t switch_count;
struct drm_bridge *bridge;
struct drm_panel *panel;
@@ -206,5 +219,7 @@ extern struct platform_driver tegra_gr2d_driver;
extern struct platform_driver tegra_gr3d_driver;
extern struct platform_driver tegra_vic_driver;
extern struct platform_driver tegra_nvdec_driver;
extern struct platform_driver tegra_nvenc_driver;
extern struct platform_driver tegra_nvjpg_driver;
#endif /* HOST1X_DRM_H */

167
drivers/gpu/drm/tegra/dsi.c
View File

@@ -52,6 +52,21 @@ to_dsi_state(struct drm_connector_state *state)
return container_of(state, struct tegra_dsi_state, base);
}
/*
* remap of registers revised in Tegra210B01
*/
struct dsi_regmap {
int init_seq_data_15;
int slew_impedance[4];
int preemphasis;
int bias;
int ganged_mode_control;
int ganged_mode_start;
int ganged_mode_size;
int dbg_regs_cnt;
struct debugfs_reg32 dbg_regs_ext[16];
};
struct tegra_dsi {
struct host1x_client client;
struct tegra_output output;
@@ -81,6 +96,8 @@ struct tegra_dsi {
/* for ganged-mode support */
struct tegra_dsi *master;
struct tegra_dsi *slave;
const struct dsi_regmap *regmap;
};
static inline struct tegra_dsi *
@@ -122,7 +139,7 @@ static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
static const struct debugfs_reg32 tegra_dsi_regs[] = {
static const struct debugfs_reg32 tegra_dsi_regs_common[] = {
DEBUGFS_REG32(DSI_INCR_SYNCPT),
DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
@@ -181,19 +198,6 @@ static const struct debugfs_reg32 tegra_dsi_regs[] = {
DEBUGFS_REG32(DSI_PAD_CONTROL_2),
DEBUGFS_REG32(DSI_PAD_CONTROL_3),
DEBUGFS_REG32(DSI_PAD_CONTROL_4),
DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
DEBUGFS_REG32(DSI_GANGED_MODE_START),
DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
};
static int tegra_dsi_show_regs(struct seq_file *s, void *data)
@@ -212,10 +216,17 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data)
goto unlock;
}
for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
unsigned int offset = tegra_dsi_regs[i].offset;
for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs_common); i++) {
unsigned int offset = tegra_dsi_regs_common[i].offset;
seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs_common[i].name,
offset, tegra_dsi_readl(dsi, offset));
}
for (i = 0; i < dsi->regmap->dbg_regs_cnt; i++) {
unsigned int offset = dsi->regmap->dbg_regs_ext[i].offset;
seq_printf(s, "%-32s %#05x %08x\n", dsi->regmap->dbg_regs_ext[i].name,
offset, tegra_dsi_readl(dsi, offset));
}
@@ -446,11 +457,11 @@ static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
{
u32 value;
tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
tegra_dsi_writel(dsi, start, dsi->regmap->ganged_mode_start);
tegra_dsi_writel(dsi, size << 16 | size, dsi->regmap->ganged_mode_size);
value = DSI_GANGED_MODE_CONTROL_ENABLE;
tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
tegra_dsi_writel(dsi, value, dsi->regmap->ganged_mode_control);
}
static void tegra_dsi_enable(struct tegra_dsi *dsi)
@@ -653,9 +664,9 @@ static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
{
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
tegra_dsi_writel(dsi, 0, dsi->regmap->ganged_mode_start);
tegra_dsi_writel(dsi, 0, dsi->regmap->ganged_mode_size);
tegra_dsi_writel(dsi, 0, dsi->regmap->ganged_mode_control);
}
static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
@@ -671,7 +682,7 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
{
u32 value;
int err;
int err, i;
/*
* XXX Is this still needed? The module reset is deasserted right
@@ -679,21 +690,29 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
*/
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
for (i = 0; i < ARRAY_SIZE(dsi->regmap->slew_impedance); i++) {
if (dsi->regmap->slew_impedance[i])
tegra_dsi_writel(dsi, 0, dsi->regmap->slew_impedance[i]);
}
/* start calibration */
tegra_dsi_pad_enable(dsi);
/* do not set padctl 2 slew by default */
if (of_property_read_bool(dsi->dev->of_node, "nvidia,slew-enable")) {
value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
DSI_PAD_OUT_CLK(0x0);
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
}
value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
value = tegra_dsi_readl(dsi, dsi->regmap->preemphasis);
value |= DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
tegra_dsi_writel(dsi, value, dsi->regmap->preemphasis);
tegra_dsi_writel(dsi, 0, dsi->regmap->bias);
err = tegra_mipi_start_calibration(dsi->mipi);
if (err < 0)
@@ -1643,6 +1662,12 @@ static int tegra_dsi_probe(struct platform_device *pdev)
goto remove;
}
dsi->regmap = of_device_get_match_data(&pdev->dev);
if (IS_ERR(dsi->regmap)) {
err = PTR_ERR(dsi->regmap);
goto remove;
}
dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
if (IS_ERR(dsi->mipi)) {
err = PTR_ERR(dsi->mipi);
@@ -1698,11 +1723,87 @@ static void tegra_dsi_remove(struct platform_device *pdev)
tegra_mipi_free(dsi->mipi);
}
static const struct dsi_regmap tegra_dsi_regmap = {
.init_seq_data_15 = DSI_INIT_SEQ_DATA_15,
.slew_impedance = { DSI_PAD_CONTROL_2 },
.preemphasis = DSI_PAD_CONTROL_3,
.bias = DSI_PAD_CONTROL_4,
.ganged_mode_control = DSI_GANGED_MODE_CONTROL,
.ganged_mode_start = DSI_GANGED_MODE_START,
.ganged_mode_size = DSI_GANGED_MODE_SIZE,
.dbg_regs_cnt = 13,
.dbg_regs_ext = {
DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
DEBUGFS_REG32(DSI_GANGED_MODE_START),
DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
},
};
static const struct dsi_regmap tegra_dsi_regmap_b01 = {
.init_seq_data_15 = DSI_INIT_SEQ_DATA_15_B01,
.slew_impedance = {
DSI_PAD_CONTROL_2,
DSI_PAD_CONTROL_3,
DSI_PAD_CONTROL_4,
DSI_PAD_CONTROL_5_B01,
},
.preemphasis = DSI_PAD_CONTROL_6_B01,
.bias = DSI_PAD_CONTROL_7_B01,
.ganged_mode_control = DSI_GANGED_MODE_CONTROL_B01,
.ganged_mode_start = DSI_GANGED_MODE_START_B01,
.ganged_mode_size = DSI_GANGED_MODE_SIZE_B01,
.dbg_regs_cnt = 16,
.dbg_regs_ext = {
DEBUGFS_REG32(DSI_PAD_CONTROL_5_B01),
DEBUGFS_REG32(DSI_PAD_CONTROL_6_B01),
DEBUGFS_REG32(DSI_PAD_CONTROL_7_B01),
DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL_B01),
DEBUGFS_REG32(DSI_GANGED_MODE_START_B01),
DEBUGFS_REG32(DSI_GANGED_MODE_SIZE_B01),
DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT_B01),
DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14_B01),
DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15_B01),
},
};
static const struct of_device_id tegra_dsi_of_match[] = {
{ .compatible = "nvidia,tegra210-dsi", },
{ .compatible = "nvidia,tegra132-dsi", },
{ .compatible = "nvidia,tegra124-dsi", },
{ .compatible = "nvidia,tegra114-dsi", },
{
.compatible = "nvidia,tegra210b01-dsi",
.data = &tegra_dsi_regmap_b01
},
{
.compatible = "nvidia,tegra210-dsi",
.data = &tegra_dsi_regmap
},
{
.compatible = "nvidia,tegra132-dsi",
.data = &tegra_dsi_regmap
},
{
.compatible = "nvidia,tegra124-dsi",
.data = &tegra_dsi_regmap
},
{
.compatible = "nvidia,tegra114-dsi",
.data = &tegra_dsi_regmap
},
{ },
};
MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);

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