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PCI: tegra: Advertise ASPM L1 PM support

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Enables advertisement of ASPM-L1 support in capability
registers of applicable Tegra chips

bug 200420606

Change-Id: Ie5dbb3a262ca1c0c9cc59c91a8710bf6bd6a6900
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786543
(cherry picked from commit 7eedf2a02489b529374bc1ca95234be1f02b9119)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407872
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vidya Sagar
2017-11-12 18:47:54 +05:30
committed by Thomas Makin
parent 8e42e98420
commit dd0f08b513
1 changed files with 16 additions and 0 deletions
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16
drivers/pci/controller/pci-tegra.c
View File

@@ -205,6 +205,9 @@
#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18)
#define RP_VEND_XP1 0xf04
#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT (1 << 21)
#define RP_VEND_CTL0 0x00000f44
#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12)
@@ -311,6 +314,7 @@ struct tegra_pcie_soc {
bool update_fc_timer;
bool has_cache_bars;
bool enable_wrap;
bool has_aspm_l1;
struct {
struct {
u32 rp_ectl_1_r1;
@@ -612,6 +616,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
}
writel(value, port->base + RP_PRIV_MISC);
if (soc->has_aspm_l1) {
/* Advertise ASPM-L1 state capability*/
value = readl(port->base + RP_VEND_XP1);
value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT;
writel(value, port->base + RP_VEND_XP1);
}
}
static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
@@ -2487,6 +2498,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.update_fc_timer = false,
.has_cache_bars = true,
.enable_wrap = false,
.has_aspm_l1 = false,
.ectl.enable = false,
};
@@ -2517,6 +2529,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.update_fc_timer = false,
.has_cache_bars = false,
.enable_wrap = false,
.has_aspm_l1 = true,
.ectl.enable = false,
};
@@ -2539,6 +2552,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.update_fc_timer = false,
.has_cache_bars = false,
.enable_wrap = false,
.has_aspm_l1 = true,
.ectl.enable = false,
};
@@ -2563,6 +2577,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.update_fc_timer = true,
.has_cache_bars = false,
.enable_wrap = true,
.has_aspm_l1 = true,
.ectl = {
.regs = {
.rp_ectl_1_r1 = 0x0000001f,
@@ -2643,6 +2658,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.update_fc_timer = false,
.has_cache_bars = false,
.enable_wrap = false,
.has_aspm_l1 = true,
.ectl.enable = false,
};