This is based on 6f78a94, which enabled added the fan and thermal zones
for the Jetson Nano Devkit. The fan and thermal characteristics of the
two devices are similar, so using the same configuration.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
The Tegra210B01 p2894 product has a BCM4356 module with wifi on pcie.
Enable the pcie port it is plugged into add a node for the wifi card,
and add a gpio-hog to enable power to the card. Attempts to tie the gpio
to power sequencing has not worked.
Change-Id: I7236fa1a3eabeb7fbb5b94af05f951b922955a38
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
The P2894 product has a Realtek r6168 PCIe ethernet adapter. Enable the
pcie port the adapter is attached to.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Enable the XUSB controller on P2894. One of the USB 3.0 lanes goes to a
switchable USB-A port, while the second USB 3.0 lane supports the normal
USB-A port.
The padctl layout is different between the Tegra210 and Tegra210B01
variants. The latter is overridden in the device specific dts.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
This adds the gpu regulator and enables the gpu node.
Change-Id: I7d9580967edf9af4c31d500608f880eeb9d1e0b5
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Add initial device-tree support for NVIDIA Shield TV Pro 2019 (a.k.a
MDarcy) based up the Tegra210B01 SoC with 3 GiB of LPDDR4 RAM.
This device is very similar to the Tegra210 p2894 device, so this shares
the p2894 dtsi with a few overrides to the pinmux and power tree.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
In preparation for support of the Tegra210B01 p2894 variant, move the
arch dtsi include to the Tegra210 revision specific dts. This will allow
the p2894 dtsi to be shared across archs, as the variants share a
majority of the hardware design.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Also known as Tegra X1+, the Tegra210B01 has higher CPU and GPU clocks
than the original Tegra210.
Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This is derived from the Tegra210 dtsi, as they
share a lot.
Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
The Tegra210 soc supports bpmp offload for power management among other
things. This was considered insecure partway through the soc's lifecycle
and support was removed in the bootloader. However, Tegra210B01 returned
to using the bpmp. Plus old bootloaders on the original Tegra210 still
work with the existing driver. So add the node to the common Tegra210
soc dtsi, but disabled by default.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Tegra210B01 is basically the same as Tegra210 but uses different tap
delays.
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
This covers a few differences:
* Lanes compared to the original Tegra210
* The soc has a different clock driver and thus callbacks
* The soc has an extra clock for uphy management
Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Change-Id: I455358267b3a700461caa8f9f9963d33596dd189
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Tegra210b01 uses tegra186-emc driver as emc clock is controlled by BPMP.
However, this driver expects emc as subnode of mc. Adjust Tegra30 mc
probe routine to populate subnodes.
This is a revision of the GM20B chipset with some minor changes.
- Support new ID for b01 variant
- Support C1 PLL revision
- Differentiate DVFS parameters between B1 (t210) and C1 (t210b01)
- Add pstates for t210b01 (start with NA table for now)
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Previously, all supported SoCs only used the A major revision. The
Tegra210B01 SoC incremented the major revision. Add support for this.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
This is based on the downstream Nvidia 5.10 kernel. That version was
semi-integrated into the Tegra210 clock driver. Looking at the existing
Tegra210 support, it made more sense to make this a fully independent
driver, so that is implemented here.
Co-authored-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
* Add the compatible string for Tegra210B01 clock and reset
* Add Tegra210B01 specific clock bindings
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
On Tegra devices, uncached maps traslate to device memory, causing
unaligned accesses by userspace resulting in a SIGBUS. Instead, use
write-combined maps to ensure proper access.
It was also determined that discrete cards should also use
write-combined maps for coherent. Thus this change is made for all gpu
types.
Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Add support for prod framework in spi core
Change-Id: Iaa70f8b3bb3efb3a3b13aa7f2d43562b9fff9e51
Signed-off-by: Vishwaroop A <va@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Abhilash G <abhilashg@nvidia.com>
The arm64 uapi sigcontext.h can be included by 32-bit userspace
modules. Since arm and arm64 sigcontext definition are not
compatible, add arm sigcontext definition to arm64 sigcontext.h.
Signed-off-by: David Ng <dave@codeaurora.org>
Signed-off-by: Divya Sharma <c_shard@codeaurora.org>
Signed-off-by: Anh Nguyen <anguyen@codeaurora.org>
Change-Id: Iaed58045fd345e4ca66e8a6981c6b4f80c4bdfca
Since commit ece67f4758 ("soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults
for NVIDIA Tegra"), all Tegra arm64 archs are enabled for GKI. Commit
eb5e5c1f62 ("ANDROID: gki_defconfig: Enable Tegra SoCs") disabled
options related to Tegra archs older than Tegra234 since that was the
only one supported at the time. Now that all archs are supported, these
options can be used.
* SERIAL_8250_TEGRA is used by Tegra210 and Tegra186 for UART serial
* TEGRA186_TIMER is used by Tegra186 and newer for watchdog timers
* TEGRA_IOMMU_SMMU is required by Tegra210 for mmu
* TEGRA210_EMC can be a module, but depends on an additional built-in
config; plus all other Tegra emc support is built-in already
* TEGRA_AHB is used by Tegra210
* ARM_TEGRA20_CPUFREQ and ARM_TEGRA124_CPUFREQ Kconfig changes are reset
to match mainline. New vendor snippets enabling CPUFREQ_DT can disable
as needed. The rockpi4 target is updated as an example of this.
Change-Id: I05541c6e1fc1ccd9ab430451a66f0d5cc3c7b0e1
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Select hidden config CONFIG_TEGRA_HOST1X_CONTEXT_BUS.
This config is needed as it adds host1x_context_device_bus_type
to iommu_buses private array, needed for host1x.ko module
Bug: 418986815
Change-Id: Icbc697638e39a08a648b2a3dbf7947d6107ac310
Signed-off-by: Ahmad Chaudhry <ahmadc@nvidia.com>
Adding regulator driver for MAX77812 device which is
used in t210b01 based platforms for powering cpu,gpu
and dram io
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
These are generated by the Tegra210 Android bootloader. This is similar
to the Tegra124 handling, so the support is based on that and modified
to match Tegra210 by referencing the downstream Nvidia 4.9 kernel.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
These entries are imported from the downstream Nvidia Linux4Tegra
kernel. They are expected to be updated with the trained values by the
bootloader. This is done by the Nvidia Android bootloader, which is
different from the handling by the Nvidia Linux bootloader which places
these values in a reserved memory location. P2180 is supported by both
bootloaders, so lets support initializing emc on both.
It should be noted that the bootloader will not create these nodes in
the kernel dtb if they do not exist. It will only set in place existing
properties.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Add support for booting and using NVENC on Tegra210+ to the Host1x
and TegraDRM drivers. This driver only supports the new TegraDRM uAPI.
Change-Id: I07e1386604d7638ba43381c3f289688d7c5cb12b
Add initial device-tree support for NVIDIA Shield TV (a.k.a. Foster)
based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. It is based on P2571.
Change-Id: Ideeeb15f835ebf7f7617d3989908d245aff4b316
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Aaron Kling
tmakin
Alexandre Hamamdjian
Faith Ekstrand
Vishwaroop A
Shardar Shariff Md
David Ng
Ahmad Chaudhry
Venkat Reddy Talla