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Merge 68cf01760b ("Merge tag 'v6.6-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6") into android-mainline

Browse Source 
Steps on the way to 6.6-rc1

Change-Id: I4c4c5ec8a5fb164fc5734e19cef975d85ab1f0c1
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-10-08 16:25:54 +00:00
parent 292721e539 68cf01760b
commit ebdd06a2e3
751 changed files with 24214 additions and 10489 deletions
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Documentation/ABI/testing/debugfs-driver-qat
+61
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@@ -0,0 +1,61 @@
What: /sys/kernel/debug/qat_<device>_<BDF>/qat/fw_counters
Date: November 2023
KernelVersion: 6.6
Contact: qat-linux@intel.com
Description: (RO) Read returns the number of requests sent to the FW and the number of responses
received from the FW for each Acceleration Engine
Reported firmware counters::
<N>: Number of requests sent from Acceleration Engine N to FW and responses
Acceleration Engine N received from FW
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/config
Date: November 2023
KernelVersion: 6.6
Contact: qat-linux@intel.com
Description: (RW) Read returns value of the Heartbeat update period.
Write to the file changes this period value.
This period should reflect planned polling interval of device
health status. High frequency Heartbeat monitoring wastes CPU cycles
but minimizes the customer’s system downtime. Also, if there are
large service requests that take some time to complete, high frequency
Heartbeat monitoring could result in false reports of unresponsiveness
and in those cases, period needs to be increased.
This parameter is effective only for c3xxx, c62x, dh895xcc devices.
4xxx has this value internally fixed to 200ms.
Default value is set to 500. Minimal allowed value is 200.
All values are expressed in milliseconds.
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/queries_failed
Date: November 2023
KernelVersion: 6.6
Contact: qat-linux@intel.com
Description: (RO) Read returns the number of times the device became unresponsive.
Attribute returns value of the counter which is incremented when
status query results negative.
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/queries_sent
Date: November 2023
KernelVersion: 6.6
Contact: qat-linux@intel.com
Description: (RO) Read returns the number of times the control process checked
if the device is responsive.
Attribute returns value of the counter which is incremented on
every status query.
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/status
Date: November 2023
KernelVersion: 6.6
Contact: qat-linux@intel.com
Description: (RO) Read returns the device health status.
Returns 0 when device is healthy or -1 when is unresponsive
or the query failed to send.
The driver does not monitor for Heartbeat. It is left for a user
to poll the status periodically.
Documentation/ABI/testing/sysfs-driver-ccp
+18
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@@ -85,3 +85,21 @@ Description:
Possible values:
0: Not enforced
1: Enforced
What: /sys/bus/pci/devices/<BDF>/bootloader_version
Date: June 2023
KernelVersion: 6.4
Contact: mario.limonciello@amd.com
Description:
The /sys/bus/pci/devices/<BDF>/bootloader_version
file reports the firmware version of the AMD AGESA
bootloader.
What: /sys/bus/pci/devices/<BDF>/tee_version
Date: June 2023
KernelVersion: 6.4
Contact: mario.limonciello@amd.com
Description:
The /sys/bus/pci/devices/<BDF>/tee_version
file reports the firmware version of the AMD Trusted
Execution Environment (TEE).
Documentation/ABI/testing/sysfs-platform-power-on-reason
+12
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@@ -0,0 +1,12 @@
What: /sys/devices/platform/.../power_on_reason
Date: June 2023
KernelVersion: 6.5
Contact: Kamel Bouhara <kamel.bouhara@bootlin.com>
Description: Shows system power on reason. The following strings/reasons can
be read (the list can be extended):
"regular power-up", "RTC wakeup", "watchdog timeout",
"software reset", "reset button action", "CPU clock failure",
"crystal oscillator failure", "brown-out reset",
"unknown reason".
The file is read only.
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+1
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@@ -20,6 +20,7 @@ properties:
- stericsson,ux500-hash
- st,stm32f456-hash
- st,stm32f756-hash
- st,stm32mp13-hash
reg:
maxItems: 1
Documentation/devicetree/bindings/gpio/adi,ds4520-gpio.yaml
+51
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@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/adi,ds4520-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DS4520 I2C GPIO expander
maintainers:
- Okan Sahin <okan.sahin@analog.com>
properties:
compatible:
enum:
- adi,ds4520-gpio
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
ngpios:
minimum: 1
maximum: 9
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- ngpios
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
gpio@50 {
compatible = "adi,ds4520-gpio";
reg = <0x50>;
ngpios = <9>;
gpio-controller;
#gpio-cells = <2>;
};
};
Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt
-52
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@@ -1,52 +0,0 @@
Broadcom Kona Family GPIO
=========================
This GPIO driver is used in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
The Broadcom GPIO Controller IP can be configured prior to synthesis to
support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
GPIO controller only supports edge, not level, triggering of interrupts.
Required properties
-------------------
- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends on the
number of GPIO banks on the SoC. The interrupts must be ordered by bank,
starting with bank 0. There is always a 1:1 mapping between banks and
IRQs.
- #gpio-cells: Should be <2>. The first cell is the pin number, the second
cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
second cell is used to specify flags. The following subset of flags is
supported:
- trigger type (bits[1:0]):
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
3 = low-to-high or high-to-low edge triggered
Valid values are 1, 2, 3
See also .../devicetree/bindings/interrupt-controller/interrupts.txt.
- gpio-controller: Marks the device node as a GPIO controller.
- interrupt-controller: Marks the device node as an interrupt controller.
Example:
gpio: gpio@35003000 {
compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x800>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};
Documentation/devicetree/bindings/gpio/brcm,kona-gpio.yaml
+100
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@@ -0,0 +1,100 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,kona-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family GPIO controller
description:
The Broadcom GPIO Controller IP can be configured prior to synthesis to
support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
GPIO controller only supports edge, not level, triggering of interrupts.
maintainers:
- Ray Jui <rjui@broadcom.com>
properties:
compatible:
items:
- enum:
- brcm,bcm11351-gpio
- brcm,bcm21664-gpio
- brcm,bcm23550-gpio
- const: brcm,kona-gpio
reg:
maxItems: 1
interrupts:
minItems: 4
maxItems: 6
description:
The interrupt outputs from the controller. There is one GPIO interrupt
per GPIO bank. The number of interrupts listed depends on the number of
GPIO banks on the SoC. The interrupts must be ordered by bank, starting
with bank 0. There is always a 1:1 mapping between banks and IRQs.
'#gpio-cells':
const: 2
'#interrupt-cells':
const: 2
gpio-controller: true
interrupt-controller: true
required:
- compatible
- reg
- interrupts
- '#gpio-cells'
- '#interrupt-cells'
- gpio-controller
- interrupt-controller
allOf:
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-gpio
then:
properties:
interrupts:
minItems: 6
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm21664-gpio
- brcm,bcm23550-gpio
then:
properties:
interrupts:
maxItems: 4
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
gpio@35003000 {
compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x800>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};
...
Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
+2
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@@ -32,10 +32,12 @@ properties:
- fsl,imx6sx-gpio
- fsl,imx6ul-gpio
- fsl,imx7d-gpio
- fsl,imx8dxl-gpio
- fsl,imx8mm-gpio
- fsl,imx8mn-gpio
- fsl,imx8mp-gpio
- fsl,imx8mq-gpio
- fsl,imx8qm-gpio
- fsl,imx8qxp-gpio
- fsl,imxrt1050-gpio
- fsl,imxrt1170-gpio
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
+1
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@@ -66,6 +66,7 @@ properties:
- ti,tca6408
- ti,tca6416
- ti,tca6424
- ti,tca9538
- ti,tca9539
- ti,tca9554
Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
+4
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@@ -61,6 +61,10 @@ patternProperties:
'#gpio-cells':
const: 2
gpio-line-names:
minItems: 1
maxItems: 32
ngpios:
default: 32
minimum: 1
Documentation/devicetree/bindings/gpio/st,stmpe-gpio.yaml
+4
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@@ -28,6 +28,10 @@ properties:
gpio-controller: true
gpio-line-names:
minItems: 1
maxItems: 24
interrupt-controller: true
st,norequest-mask:
Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+6
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@@ -160,6 +160,12 @@ properties:
description:
The MIO bank number in which the command and data lines are configured.
iommus:
maxItems: 1
power-domains:
maxItems: 1
dependencies:
'#clock-cells': [ clock-output-names ]
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+1 -1
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@@ -269,7 +269,7 @@ properties:
post-power-on-delay-ms:
description:
It was invented for MMC pwrseq-simple which could be referred to
mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
waiting for I/O signalling and card power supply to be stable,
regardless of whether pwrseq-simple is used. Default to 10ms if
no available.
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
-10
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@@ -91,16 +91,6 @@ properties:
should switch dat1 pin to GPIO mode.
maxItems: 1
assigned-clocks:
description:
PLL of the source clock.
maxItems: 1
assigned-clock-parents:
description:
parent of source clock, used for HS400 mode to get 400Mhz source clock.
maxItems: 1
hs400-ds-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Documentation/devicetree/bindings/mmc/sdhci-atmel.txt
+3 -1
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@@ -5,11 +5,13 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
sdhci-of-at91 driver.
Required properties:
- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci".
- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci"
or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci".
- clocks: Phandlers to the clocks.
- clock-names: Must be "hclock", "multclk", "baseclk" for
"atmel,sama5d2-sdhci".
Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
Must be "hclock", "multclk" for "microchip,sam9x7-sdhci".
Optional properties:
- assigned-clocks: The same with "multclk".
Documentation/devicetree/bindings/regulator/active-semi,act8846.yaml
+22 -60
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@@ -28,75 +28,37 @@ properties:
the VSEL pin is assumed to be low.
type: boolean
inl1-supply:
description: Handle to the INL1 input supply (REG5-7)
inl2-supply:
description: Handle to the INL2 input supply (REG8-9)
inl3-supply:
description: Handle to the INL3 input supply (REG10-12)
vp1-supply:
description: Handle to the VP1 input supply (REG1)
vp2-supply:
description: Handle to the VP2 input supply (REG2)
vp3-supply:
description: Handle to the VP3 input supply (REG3)
vp4-supply:
description: Handle to the VP4 input supply (REG4)
regulators:
type: object
additionalProperties: false
properties:
REG1:
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
vp1-supply:
description: Handle to the VP1 input supply
REG2:
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
vp2-supply:
description: Handle to the VP2 input supply
REG3:
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
vp3-supply:
description: Handle to the VP3 input supply
REG4:
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
vp4-supply:
description: Handle to the VP4 input supply
patternProperties:
"^REG[5-7]$":
"^REG([1-9]|1[0-2])$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
inl1-supply:
description: Handle to the INL1 input supply
"^REG[8-9]$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
inl2-supply:
description: Handle to the INL2 input supply
"^REG1[0-2]$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
inl3-supply:
description: Handle to the INL3 input supply
additionalProperties: false
required:
Documentation/devicetree/bindings/regulator/adi,max77857.yaml
+86
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@@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2022 Analog Devices Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/adi,max77857.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices MAX77857 Buck-Boost Converter
maintainers:
- Ibrahim Tilki <Ibrahim.Tilki@analog.com>
- Okan Sahin <Okan.Sahin@analog.com>
description: Analog Devices MAX77857 Buck-Boost Converter
properties:
compatible:
enum:
- adi,max77831
- adi,max77857
- adi,max77859
- adi,max77859a
reg:
description: I2C address of the device
items:
- enum: [0x66, 0x67, 0x6E, 0x6F]
interrupts:
maxItems: 1
adi,switch-frequency-hz:
description: Switching frequency of the Buck-Boost converter in Hz.
items:
- enum: [1200000, 1500000, 1800000, 2100000]
adi,rtop-ohms:
description: Top feedback resistor value in ohms for external feedback.
minimum: 150000
maximum: 330000
adi,rbot-ohms:
description: Bottom feedback resistor value in ohms for external feedback.
dependencies:
adi,rtop-ohms: [ 'adi,rbot-ohms' ]
adi,rbot-ohms: [ 'adi,rtop-ohms' ]
required:
- compatible
- reg
allOf:
- $ref: regulator.yaml#
- if:
properties:
compatible:
contains:
enum:
- adi,max77831
then:
properties:
adi,switch-frequency-hz:
items:
enum: [1200000, 1500000, 1800000]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@66 {
reg = <0x66>;
compatible = "adi,max77857";
interrupt-parent = <&gpio>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
adi,rtop-ohms = <312000>;
adi,rbot-ohms = <12000>;
};
};
Documentation/devicetree/bindings/regulator/awinic,aw37503.yaml
+78
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@@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/awinic,aw37503.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Awinic AW37503 Voltage Regulator
maintainers:
- Alec Li <like@awinic.com>
description:
The AW37503 are dual voltage regulator, designed to support positive/negative
supply for driving TFT-LCD panels. It support software-configurable output
switching and monitoring. The output voltages can be programmed via an I2C
compatible interface.
properties:
compatible:
const: awinic,aw37503
reg:
maxItems: 1
patternProperties:
"^out[pn]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for single regulator.
properties:
enable-gpios:
maxItems: 1
description:
GPIO specifier to enable the GPIO control (on/off) for regulator.
required:
- regulator-name
required:
- compatible
- reg
- outp
- outn
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@3e {
compatible = "awinic,aw37503";
reg = <0x3e>;
outp {
regulator-name = "outp";
regulator-boot-on;
regulator-always-on;
enable-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
outn {
regulator-name = "outn";
regulator-boot-on;
regulator-always-on;
enable-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
};
};
};
...
Documentation/devicetree/bindings/regulator/dlg,da9121.yaml
+17 -5
View File
@@ -95,11 +95,6 @@ properties:
Properties for a single BUCK regulator
properties:
regulator-name:
pattern: "^BUCK([1-2])$"
description: |
BUCK2 present in DA9122, DA9220, DA9131, DA9132 only
regulator-initial-mode:
enum: [ 0, 1, 2, 3 ]
description: Defined in include/dt-bindings/regulator/dlg,da9121-regulator.h
@@ -122,6 +117,23 @@ required:
- reg
- regulators
allOf:
- if:
properties:
compatible:
not:
contains:
enum:
- dlg,da9122
- dlg,da9131
- dlg,da9132
- dlg,da9220
then:
properties:
regulators:
properties:
buck2: false
additionalProperties: false
examples:
Documentation/devicetree/bindings/regulator/dlg,slg51000.yaml
+132
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@@ -0,0 +1,132 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/dlg,slg51000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Dialog Semiconductor SLG51000 Voltage Regulator
maintainers:
- Eric Jeong <eric.jeong.opensource@diasemi.com>
- Support Opensource <support.opensource@diasemi.com>
properties:
compatible:
const: dlg,slg51000
reg:
maxItems: 1
interrupts:
maxItems: 1
dlg,cs-gpios:
maxItems: 1
description:
GPIO for chip select
vin3-supply:
description:
Input supply for ldo3, required if regulator is enabled
vin4-supply:
description:
Input supply for ldo4, required if regulator is enabled
vin5-supply:
description:
Input supply for ldo5, required if regulator is enabled
vin6-supply:
description:
Input supply for ldo6, required if regulator is enabled
vin7-supply:
description:
Input supply for ldo7, required if regulator is enabled
regulators:
type: object
additionalProperties: false
patternProperties:
"^ldo[1-7]$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
enable-gpios:
maxItems: 1
required:
- regulator-name
required:
- compatible
- reg
- regulators
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/dlg,da9121-regulator.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@75 {
compatible = "dlg,slg51000";
reg = <0x75>;
dlg,cs-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
vin5-supply = <&vreg_s1f_1p2>;
vin6-supply = <&vreg_s1f_1p2>;
regulators {
ldo1 {
regulator-name = "slg51000_b_ldo1";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
};
ldo2 {
regulator-name = "slg51000_b_ldo2";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
};
ldo3 {
regulator-name = "slg51000_b_ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
ldo4 {
regulator-name = "slg51000_b_ldo4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
ldo5 {
regulator-name = "slg51000_b_ldo5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
};
ldo6 {
regulator-name = "slg51000_b_ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
};
ldo7 {
regulator-name = "slg51000_b_ldo7";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
};
};
};
Documentation/devicetree/bindings/regulator/mps,mp5416.yaml
+2
View File
@@ -29,10 +29,12 @@ properties:
patternProperties:
"^buck[1-4]$":
$ref: regulator.yaml#
unevaluatedProperties: false
type: object
"^ldo[1-4]$":
$ref: regulator.yaml#
unevaluatedProperties: false
type: object
additionalProperties: false
Documentation/devicetree/bindings/regulator/mps,mpq7920.yaml
+2 -1
View File
@@ -21,7 +21,6 @@ properties:
regulators:
type: object
$ref: regulator.yaml#
description: |
list of regulators provided by this controller, must be named
@@ -39,11 +38,13 @@ properties:
ldortc:
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
patternProperties:
"^ldo[1-4]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
"^buck[1-4]$":
type: object
Documentation/devicetree/bindings/regulator/pfuze100.yaml
+4
View File
@@ -68,18 +68,22 @@ properties:
"^sw([1-4]|[1-4][a-c]|[1-4][a-c][a-c])$":
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
"^vgen[1-6]$":
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
"^vldo[1-4]$":
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
"^(vsnvs|vref|vrefddr|swbst|coin|v33|vccsd)$":
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
additionalProperties: false
Documentation/devicetree/bindings/regulator/qcom,rpm-regulator.yaml
+1 -1
View File
@@ -49,7 +49,7 @@ patternProperties:
".*-supply$":
description: Input supply phandle(s) for this node
"^((s|l|lvs)[0-9]*)|(s[1-2][a-b])|(ncp)|(mvs)|(usb-switch)|(hdmi-switch)$":
"^((s|l|lvs)[0-9]*|s[1-2][a-b]|ncp|mvs|usb-switch|hdmi-switch)$":
description: List of regulators and its properties
$ref: regulator.yaml#
unevaluatedProperties: false
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
+24 -2
View File
@@ -53,6 +53,7 @@ description: |
For PMR735A, smps1 - smps3, ldo1 - ldo7
For PMX55, smps1 - smps7, ldo1 - ldo16
For PMX65, smps1 - smps8, ldo1 - ldo21
For PMX75, smps1 - smps10, ldo1 - ldo21
properties:
compatible:
@@ -84,13 +85,14 @@ properties:
- qcom,pmr735a-rpmh-regulators
- qcom,pmx55-rpmh-regulators
- qcom,pmx65-rpmh-regulators
- qcom,pmx75-rpmh-regulators
qcom,pmic-id:
description: |
RPMh resource name suffix used for the regulators found
on this PMIC.
$ref: /schemas/types.yaml#/definitions/string
enum: [a, b, c, d, e, f, g, h, k]
enum: [a, b, c, d, e, f, g, h, i, j, k, l, m, n]
qcom,always-wait-for-ack:
description: |
@@ -109,6 +111,7 @@ properties:
bob:
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description: BOB regulator node.
dependencies:
regulator-allow-set-load: [ regulator-allowed-modes ]
@@ -117,6 +120,7 @@ patternProperties:
"^(smps|ldo|lvs|bob)[0-9]+$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description: smps/ldo regulator nodes(s).
dependencies:
regulator-allow-set-load: [ regulator-allowed-modes ]
@@ -424,10 +428,28 @@ allOf:
vdd-l11-l13-supply: true
patternProperties:
"^vdd-l[1347]-supply$": true
"^vdd-l1[0245789]-supply$": true
"^vdd-l1[024579]-supply$": true
"^vdd-l2[01]-supply$": true
"^vdd-s[1-8]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pmx75-rpmh-regulators
then:
properties:
vdd-l2-l18-supply: true
vdd-l4-l16-supply: true
vdd-l5-l6-supply: true
vdd-l8-l9-supply: true
vdd-l11-l13-supply: true
vdd-l20-l21-supply: true
patternProperties:
"^vdd-l[137]-supply$": true
"^vdd-l1[024579]-supply$": true
"^vdd-s([1-9]|10)-supply$": true
unevaluatedProperties: false
examples:
Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml
+57
View File
@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/qcom,sdm845-refgen-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. REFGEN Regulator
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description:
The REFGEN (reference voltage generator) regulator provides reference
voltage for on-chip IPs (like PHYs) on some Qualcomm SoCs.
allOf:
- $ref: regulator.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,sc7180-refgen-regulator
- qcom,sc8180x-refgen-regulator
- qcom,sm8150-refgen-regulator
- const: qcom,sdm845-refgen-regulator
- items:
- enum:
- qcom,sc7280-refgen-regulator
- qcom,sc8280xp-refgen-regulator
- qcom,sm6350-refgen-regulator
- qcom,sm6375-refgen-regulator
- qcom,sm8350-refgen-regulator
- const: qcom,sm8250-refgen-regulator
- enum:
- qcom,sdm845-refgen-regulator
- qcom,sm8250-refgen-regulator
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
regulator@162f000 {
compatible = "qcom,sm8250-refgen-regulator";
reg = <0x0162f000 0x84>;
};
...
Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
+1
View File
@@ -110,6 +110,7 @@ patternProperties:
"^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
description: List of regulators and its properties
$ref: regulator.yaml#
unevaluatedProperties: false
additionalProperties: false
Documentation/devicetree/bindings/regulator/richtek,rt4831-regulator.yaml
+1
View File
@@ -29,6 +29,7 @@ patternProperties:
"^DSV(LCM|P|N)$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for single Display Bias Voltage regulator.
Documentation/devicetree/bindings/regulator/richtek,rt5739.yaml
+1
View File
@@ -21,6 +21,7 @@ allOf:
properties:
compatible:
enum:
- richtek,rt5733
- richtek,rt5739
reg:
Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml
+1
View File
@@ -121,6 +121,7 @@ properties:
description: load switch current regulator description.
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
required:
- compatible
Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml
+197
View File
@@ -0,0 +1,197 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/richtek,rtq2208.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Richtek RTQ2208 SubPMIC Regulator
maintainers:
- Alina Yu <alina_yu@richtek.com>
description: |
RTQ2208 is a highly integrated power converter that offers functional safety dual
multi-configurable synchronous buck converters and two LDOs.
Bucks support "regulator-allowed-modes" and "regulator-mode". The former defines the permitted
switching operation in normal mode; the latter defines the operation in suspend to RAM mode.
No matter the RTQ2208 is configured to normal or suspend to RAM mode, there are two switching
operation modes for all buck rails, automatic power saving mode (Auto mode) and forced continuous
conduction mode (FCCM).
The definition of modes is in the datasheet which is available in below link
and their meaning is::
0 - Auto mode for power saving, which reducing the switching frequency at light load condition
to maintain high frequency.
1 - FCCM to meet the strict voltage regulation accuracy, which keeping constant switching frequency.
Datasheet will be available soon at
https://www.richtek.com/assets/Products
properties:
compatible:
enum:
- richtek,rtq2208
reg:
maxItems: 1
interrupts:
maxItems: 1
richtek,mtp-sel-high:
type: boolean
description:
vout register selection based on this boolean value.
false - Using DVS0 register setting to adjust vout
true - Using DVS1 register setting to adjust vout
regulators:
type: object
additionalProperties: false
patternProperties:
"^buck-[a-h]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
description for buck-[a-h] regulator.
properties:
regulator-allowed-modes:
description:
two buck modes in different switching accuracy.
0 - Auto mode
1 - FCCM
items:
enum: [0, 1]
"^ldo[1-2]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
regulator description for ldo[1-2].
required:
- compatible
- reg
- regulators
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@10 {
compatible = "richtek,rtq2208";
reg = <0x10>;
interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
richtek,mtp-sel-high;
regulators {
buck-a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-c {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-d {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-e {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-f {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-g {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
buck-h {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <2050000>;
regulator-allowed-modes = <0 1>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-mode = <1>;
};
};
ldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
ldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};
};
Documentation/devicetree/bindings/regulator/richtek,rtq6752-regulator.yaml
+1
View File
@@ -35,6 +35,7 @@ properties:
"^(p|n)avdd$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description: |
regulator description for pavdd and navdd.
Documentation/devicetree/bindings/regulator/slg51000.txt
-88
View File
@@ -1,88 +0,0 @@
* Dialog Semiconductor SLG51000 Voltage Regulator
Required properties:
- compatible : Should be "dlg,slg51000" for SLG51000
- reg : Specifies the I2C slave address.
- xxx-supply: Input voltage supply regulator for ldo3 to ldo7.
These entries are required if regulators are enabled for a device.
An absence of these properties can cause the regulator registration to fail.
If some of input supply is powered through battery or always-on supply then
also it is required to have these parameters with proper node handle of always
on power supply.
vin3-supply: Input supply for ldo3
vin4-supply: Input supply for ldo4
vin5-supply: Input supply for ldo5
vin6-supply: Input supply for ldo6
vin7-supply: Input supply for ldo7
Optional properties:
- interrupt-parent : Specifies the reference to the interrupt controller.
- interrupts : IRQ line information.
- dlg,cs-gpios : Specify a valid GPIO for chip select
Sub-nodes:
- regulators : This node defines the settings for the regulators.
The content of the sub-node is defined by the standard binding
for regulators; see regulator.txt.
The SLG51000 regulators are bound using their names listed below:
ldo1
ldo2
ldo3
ldo4
ldo5
ldo6
ldo7
Optional properties for regulators:
- enable-gpios : Specify a valid GPIO for platform control of the regulator.
Example:
pmic: slg51000@75 {
compatible = "dlg,slg51000";
reg = <0x75>;
regulators {
ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
};
ldo2 {
regulator-name = "ldo2";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
};
ldo3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
ldo4 {
regulator-name = "ldo4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
ldo5 {
regulator-name = "ldo5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
};
ldo6 {
regulator-name = "ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
};
ldo7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3750000>;
};
};
};
Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml
+1 -1
View File
@@ -25,8 +25,8 @@ properties:
patternProperties:
"^(reg11|reg18|usb33)$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
required:
- compatible
Documentation/devicetree/bindings/regulator/wlf,arizona.yaml
+2
View File
@@ -29,11 +29,13 @@ properties:
Initial data for the LDO1 regulator.
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
micvdd:
description:
Initial data for the MICVDD regulator.
$ref: regulator.yaml#
type: object
unevaluatedProperties: false
additionalProperties: true
Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
+313
View File
@@ -0,0 +1,313 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/cirrus,cs42l43.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CS42L43 Audio CODEC
maintainers:
- patches@opensource.cirrus.com
description: |
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface
(Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed
for portable applications. It provides a high dynamic range, stereo
DAC for headphone output, two integrated Class D amplifiers for
loudspeakers, and two ADCs for wired headset microphone input or
stereo line input. PDM inputs are provided for digital microphones.
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
enum:
- cirrus,cs42l43
reg:
maxItems: 1
vdd-p-supply:
description:
Power supply for the high voltage interface.
vdd-a-supply:
description:
Power supply for internal analog circuits.
vdd-d-supply:
description:
Power supply for internal digital circuits. Can be internally supplied.
vdd-io-supply:
description:
Power supply for external interface and internal digital logic.
vdd-cp-supply:
description:
Power supply for the amplifier 3 and 4 charge pump.
vdd-amp-supply:
description:
Power supply for amplifier 1 and 2.
reset-gpios:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts:
maxItems: 1
"#sound-dai-cells":
const: 1
clocks:
items:
- description: Synchronous audio clock provided on mclk_in.
clock-names:
const: mclk
cirrus,bias-low:
type: boolean
description:
Select a 1.8V headset micbias rather than 2.8V.
cirrus,bias-sense-microamp:
description:
Current at which the headset micbias sense clamp will engage, 0 to
disable.
enum: [ 0, 14, 23, 41, 50, 60, 68, 86, 95 ]
default: 0
cirrus,bias-ramp-ms:
description:
Time in milliseconds the hardware allows for the headset micbias to
ramp up.
enum: [ 10, 40, 90, 170 ]
default: 170
cirrus,detect-us:
description:
Time in microseconds the type detection will run for. Long values will
cause more audible effects, but give more accurate detection.
enum: [ 20, 100, 1000, 10000, 50000, 75000, 100000, 200000 ]
default: 10000
cirrus,button-automute:
type: boolean
description:
Enable the hardware automuting of decimator 1 when a headset button is
pressed.
cirrus,buttons-ohms:
description:
Impedance in Ohms for each headset button, these should be listed in
ascending order.
minItems: 1
maxItems: 6
cirrus,tip-debounce-ms:
description:
Software debounce on tip sense triggering in milliseconds.
default: 0
cirrus,tip-invert:
type: boolean
description:
Indicates tip detect polarity, inverted implies open-circuit whilst the
jack is inserted.
cirrus,tip-disable-pullup:
type: boolean
description:
Indicates if the internal pullup on the tip detect should be disabled.
cirrus,tip-fall-db-ms:
description:
Time in milliseconds a falling edge on the tip detect should be hardware
debounced for. Note the falling edge is considered after the invert.
enum: [ 0, 125, 250, 500, 750, 1000, 1250, 1500 ]
default: 500
cirrus,tip-rise-db-ms:
description:
Time in milliseconds a rising edge on the tip detect should be hardware
debounced for. Note the rising edge is considered after the invert.
enum: [ 0, 125, 250, 500, 750, 1000, 1250, 1500 ]
default: 500
cirrus,use-ring-sense:
type: boolean
description:
Indicates if the ring sense should be used.
cirrus,ring-invert:
type: boolean
description:
Indicates ring detect polarity, inverted implies open-circuit whilst the
jack is inserted.
cirrus,ring-disable-pullup:
type: boolean
description:
Indicates if the internal pullup on the ring detect should be disabled.
cirrus,ring-fall-db-ms:
description:
Time in milliseconds a falling edge on the ring detect should be hardware
debounced for. Note the falling edge is considered after the invert.
enum: [ 0, 125, 250, 500, 750, 1000, 1250, 1500 ]
default: 500
cirrus,ring-rise-db-ms:
description:
Time in milliseconds a rising edge on the ring detect should be hardware
debounced for. Note the rising edge is considered after the invert.
enum: [ 0, 125, 250, 500, 750, 1000, 1250, 1500 ]
default: 500
pinctrl:
type: object
$ref: /schemas/pinctrl/pinctrl.yaml#
additionalProperties: false
properties:
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
items:
- description: A phandle to the CODEC pinctrl node
minimum: 0
- const: 0
- const: 0
- const: 3
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/cirrus-cs42l43-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/cirrus-cs42l43-state"
additionalProperties: false
spi:
type: object
$ref: /schemas/spi/spi-controller.yaml#
unevaluatedProperties: false
$defs:
cirrus-cs42l43-state:
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml#
- $ref: /schemas/pinctrl/pinmux-node.yaml#
oneOf:
- required: [ groups ]
- required: [ pins ]
additionalProperties: false
properties:
groups:
enum: [ gpio1, gpio2, gpio3, asp, pdmout2, pdmout1, i2c, spi ]
pins:
enum: [ gpio1, gpio2, gpio3,
asp_dout, asp_fsync, asp_bclk,
pdmout2_clk, pdmout2_data, pdmout1_clk, pdmout1_data,
i2c_sda, i2c_scl,
spi_miso, spi_sck, spi_ssb ]
function:
enum: [ gpio, spdif, irq, mic-shutter, spk-shutter ]
drive-strength:
description: Set drive strength in mA
enum: [ 1, 2, 4, 8, 9, 10, 12, 16 ]
input-debounce:
description: Set input debounce in uS
enum: [ 0, 85 ]
required:
- compatible
- reg
- vdd-p-supply
- vdd-a-supply
- vdd-io-supply
- vdd-cp-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
cs42l43: codec@1a {
compatible = "cirrus,cs42l43";
reg = <0x1a>;
vdd-p-supply = <&vdd5v0>;
vdd-a-supply = <&vdd1v8>;
vdd-io-supply = <&vdd1v8>;
vdd-cp-supply = <&vdd1v8>;
vdd-amp-supply = <&vdd5v0>;
reset-gpios = <&gpio 0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio>;
interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
#sound-dai-cells = <1>;
clocks = <&clks 0>;
clock-names = "mclk";
cs42l43_pins: pinctrl {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cs42l43_pins 0 0 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinsettings>;
pinsettings: default-state {
shutter-pins {
groups = "gpio3";
function = "mic-shutter";
};
};
};
spi {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&cs42l43_pins 1 0>;
sensor@0 {
compatible = "bosch,bme680";
reg = <0>;
spi-max-frequency = <1400000>;
};
};
};
};
Documentation/devicetree/bindings/spi/brcm,bcm63xx-spi.yaml
+71
View File
@@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6348/BCM6358 SPI controller
maintainers:
- Jonas Gorski <jonas.gorski@gmail.com>
description: |
Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband
SoCs.
This controller has a limitation that can not keep the chip select line active
between the SPI transfers within the same SPI message. This can terminate the
transaction to some SPI devices prematurely. The issue can be worked around by
the controller's prepend mode.
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,bcm6368-spi
- brcm,bcm6362-spi
- brcm,bcm63268-spi
- const: brcm,bcm6358-spi
- enum:
- brcm,bcm6348-spi
- brcm,bcm6358-spi
reg:
maxItems: 1
clocks:
items:
- description: SPI master reference clock
clock-names:
items:
- const: spi
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
unevaluatedProperties: false
examples:
- |
spi@10000800 {
compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
reg = <0x10000800 0x70c>;
interrupts = <1>;
clocks = <&clkctl 9>;
clock-names = "spi";
num-cs = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+11 -1
View File
@@ -86,7 +86,17 @@ properties:
maxItems: 1
clocks:
maxItems: 1
minItems: 1
maxItems: 3
clock-names:
oneOf:
- items:
- const: ref
- items:
- const: ref
- const: ahb
- const: apb
cdns,fifo-depth:
description:
Documentation/devicetree/bindings/spi/loongson,ls2k-spi.yaml
+46
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@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/loongson,ls2k-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson SPI controller
maintainers:
- Yinbo Zhu <zhuyinbo@loongson.cn>
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
oneOf:
- enum:
- loongson,ls2k1000-spi
- items:
- enum:
- loongson,ls2k0500-spi
- const: loongson,ls2k1000-spi
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
unevaluatedProperties: false
examples:
- |
spi0: spi@1fff0220{
compatible = "loongson,ls2k1000-spi";
reg = <0x1fff0220 0x10>;
clocks = <&clk 17>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
-61
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@@ -1,61 +0,0 @@
NVIDIA Tegra114 SPI controller.
Required properties:
- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
<chip> is tegra124, tegra132, or tegra210.
- reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts.
- clock-names : Must include the following entries:
- spi
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- spi
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
Optional properties:
- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
with this tap value. This property is used to tune the outgoing data from
Tegra SPI master with respect to outgoing Tegra SPI master clock.
Tap values vary based on the platform design trace lengths from Tegra SPI
to corresponding slave devices. Valid tap values are from 0 thru 63.
- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
with this tap value. This property is used to adjust the Tegra SPI master
clock with respect to the data from the SPI slave device.
Tap values vary based on the platform design trace lengths from Tegra SPI
to corresponding slave devices. Valid tap values are from 0 thru 63.
Example:
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
<spi-client>@<bus_num> {
...
...
nvidia,rx-clk-tap-delay = <0>;
nvidia,tx-clk-tap-delay = <16>;
...
};
};
Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.yaml
+100
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@@ -0,0 +1,100 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra114 SPI controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- const: nvidia,tegra114-spi
- items:
- enum:
- nvidia,tegra210-spi
- nvidia,tegra124-spi
- const: nvidia,tegra114-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: SPI module clock
clock-names:
items:
- const: spi
resets:
items:
- description: SPI module reset
reset-names:
items:
- const: spi
dmas:
items:
- description: DMA channel for the reception FIFO
- description: DMA channel for the transmission FIFO
dma-names:
items:
- const: rx
- const: tx
spi-max-frequency:
description: Maximum SPI clocking speed of the controller in Hz.
$ref: /schemas/types.yaml#/definitions/uint32
allOf:
- $ref: spi-controller.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- dmas
- dma-names
examples:
- |
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
clocks = <&tegra_car 44>;
clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
nvidia,rx-clk-tap-delay = <0>;
nvidia,tx-clk-tap-delay = <16>;
};
};
Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
-37
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@@ -1,37 +0,0 @@
NVIDIA Tegra20 SFLASH controller.
Required properties:
- compatible : should be "nvidia,tegra20-sflash".
- reg: Should contain SFLASH registers location and length.
- interrupts: Should contain SFLASH interrupts.
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- spi
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
Example:
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
interrupts = <0 39 0x04>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 43>;
resets = <&tegra_car 43>;
reset-names = "spi";
dmas = <&apbdma 11>, <&apbdma 11>;
dma-names = "rx", "tx";
};
Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.yaml
+81
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@@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 SFLASH controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra20-sflash
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: spi
dmas:
items:
- description: DMA channel used for reception
- description: DMA channel used for transmission
dma-names:
items:
- const: rx
- const: tx
spi-max-frequency:
description: Maximum SPI clocking speed of the controller in Hz.
$ref: /schemas/types.yaml#/definitions/uint32
allOf:
- $ref: spi-controller.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
- reset-names
- dmas
- dma-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SPI>;
resets = <&tegra_car 43>;
reset-names = "spi";
dmas = <&apbdma 11>, <&apbdma 11>;
dma-names = "rx", "tx";
};
Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
-37
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@@ -1,37 +0,0 @@
NVIDIA Tegra20/Tegra30 SLINK controller.
Required properties:
- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
- reg: Should contain SLINK registers location and length.
- interrupts: Should contain SLINK interrupts.
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- spi
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
Example:
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
};
Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.yaml
+90
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@@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20/30 SLINK controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra20-slink
- nvidia,tegra30-slink
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: spi
dmas:
items:
- description: DMA channel used for reception
- description: DMA channel used for transmission
dma-names:
items:
- const: rx
- const: tx
operating-points-v2:
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
items:
- description: phandle to the core power domain
spi-max-frequency:
description: Maximum SPI clocking speed of the controller in Hz.
$ref: /schemas/types.yaml#/definitions/uint32
allOf:
- $ref: spi-controller.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
- reset-names
- dmas
- dma-names
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC2>;
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
};
Documentation/devicetree/bindings/spi/spi-bcm63xx.txt
-33
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@@ -1,33 +0,0 @@
Binding for Broadcom BCM6348/BCM6358 SPI controller
Required properties:
- compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
- reg: Base address and size of the controllers memory area.
- interrupts: Interrupt for the SPI block.
- clocks: phandle of the SPI clock.
- clock-names: has to be "spi".
- #address-cells: <1>, as required by generic SPI binding.
- #size-cells: <0>, also as required by generic SPI binding.
Optional properties:
- num-cs: some controllers have less than 8 cs signals. Defaults to 8
if absent.
Child nodes as per the generic SPI binding.
Example:
spi@10000800 {
compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
reg = <0x10000800 0x70c>;
interrupts = <1>;
clocks = <&clkctl 9>;
clock-names = "spi";
num-cs = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/spi-cadence.yaml
+6
View File
@@ -49,6 +49,12 @@ properties:
enum: [ 0, 1 ]
default: 0
power-domains:
maxItems: 1
label:
description: Descriptive name of the SPI controller.
required:
- compatible
- reg
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+3
View File
@@ -63,6 +63,9 @@ properties:
maximum: 2
default: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
+3
View File
@@ -45,6 +45,9 @@ properties:
- const: fspi_en
- const: fspi
power-domains:
maxItems: 1
required:
- compatible
- reg
Documentation/devicetree/bindings/spi/spi-pl022.yaml
+1
View File
@@ -11,6 +11,7 @@ maintainers:
allOf:
- $ref: spi-controller.yaml#
- $ref: /schemas/arm/primecell.yaml#
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
Documentation/devicetree/bindings/trivial-devices.yaml
+6
View File
@@ -119,6 +119,10 @@ properties:
- fsl,mpr121
# Monolithic Power Systems Inc. multi-phase controller mp2888
- mps,mp2888
# Monolithic Power Systems Inc. multi-phase controller mp2971
- mps,mp2971
# Monolithic Power Systems Inc. multi-phase controller mp2973
- mps,mp2973
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
@@ -315,6 +319,8 @@ properties:
- plx,pex8648
# Pulsedlight LIDAR range-finding sensor
- pulsedlight,lidar-lite-v2
# Renesas HS3001 Temperature and Relative Humidity Sensors
- renesas,hs3001
# Renesas ISL29501 time-of-flight sensor
- renesas,isl29501
# Rohm DH2228FV
Documentation/hwmon/hs3001.rst
+37
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@@ -0,0 +1,37 @@
.. SPDX-License-Identifier: GPL-2.0-or-later
Kernel driver HS3001
====================
Supported chips:
* Renesas HS3001, HS3002, HS3003, HS3004
Prefix: 'hs3001'
Addresses scanned: -
Datasheet: https://www.renesas.com/us/en/document/dst/hs300x-datasheet?r=417401
Author:
- Andre Werner <andre.werner@systec-electronic.com>
Description
-----------
This driver implements support for the Renesas HS3001 chips, a humidity
and temperature family. Temperature is measured in degrees celsius, relative
humidity is expressed as a percentage. In the sysfs interface, all values are
scaled by 1000, i.e. the value for 31.5 degrees celsius is 31500.
The device communicates with the I2C protocol. Sensors have the I2C
address 0x44 by default.
sysfs-Interface
---------------
=================== =================
temp1_input: temperature input
humidity1_input: humidity input
=================== =================
Documentation/hwmon/index.rst
+1 -1
View File
@@ -78,6 +78,7 @@ Hardware Monitoring Kernel Drivers
gxp-fan-ctrl
hih6130
hp-wmi-sensors
hs3001
ibmaem
ibm-cffps
ibmpowernv
@@ -195,7 +196,6 @@ Hardware Monitoring Kernel Drivers
shtc1
sis5595
sl28cpld
smm665
smpro-hwmon
smsc47b397
smsc47m192
Documentation/hwmon/nct6775.rst
+10 -1
View File
@@ -80,7 +80,13 @@ Supported chips:
Datasheet: Available from Nuvoton upon request
* Nuvoton NCT6796D-S/NCT6799D-R
Prefix: 'nct6799'
Addresses scanned: ISA address retrieved from Super I/O registers
Datasheet: Available from Nuvoton upon request
Authors:
@@ -277,4 +283,7 @@ will not reflect a usable value. It often reports unreasonably high
temperatures, and in some cases the reported temperature declines if the actual
temperature increases (similar to the raw PECI temperature value - see PECI
specification for details). CPUTIN should therefore be ignored on ASUS
boards. The CPU temperature on ASUS boards is reported from PECI 0.
boards. The CPU temperature on ASUS boards is reported from PECI 0 or TSI 0.
NCT6796D-S and NCT6799D-R chips are very similar and their chip_id indicates
they are different versions. This driver treats them the same way.
Documentation/hwmon/pmbus.rst
+1 -1
View File
@@ -163,7 +163,7 @@ Emerson DS1200 power modules might look as follows::
.driver = {
.name = "ds1200",
},
.probe_new = ds1200_probe,
.probe = ds1200_probe,
.id_table = ds1200_id,
};
Documentation/hwmon/smm665.rst
-187
View File
@@ -1,187 +0,0 @@
Kernel driver smm665
====================
Supported chips:
* Summit Microelectronics SMM465
Prefix: 'smm465'
Addresses scanned: -
Datasheet:
http://www.summitmicro.com/prod_select/summary/SMM465/SMM465DS.pdf
* Summit Microelectronics SMM665, SMM665B
Prefix: 'smm665'
Addresses scanned: -
Datasheet:
http://www.summitmicro.com/prod_select/summary/SMM665/SMM665B_2089_20.pdf
* Summit Microelectronics SMM665C
Prefix: 'smm665c'
Addresses scanned: -
Datasheet:
http://www.summitmicro.com/prod_select/summary/SMM665C/SMM665C_2125.pdf
* Summit Microelectronics SMM764
Prefix: 'smm764'
Addresses scanned: -
Datasheet:
http://www.summitmicro.com/prod_select/summary/SMM764/SMM764_2098.pdf
* Summit Microelectronics SMM766, SMM766B
Prefix: 'smm766'
Addresses scanned: -
Datasheets:
http://www.summitmicro.com/prod_select/summary/SMM766/SMM766_2086.pdf
http://www.summitmicro.com/prod_select/summary/SMM766B/SMM766B_2122.pdf
Author: Guenter Roeck <linux@roeck-us.net>
Module Parameters
-----------------
* vref: int
Default: 1250 (mV)
Reference voltage on VREF_ADC pin in mV. It should not be necessary to set
this parameter unless a non-default reference voltage is used.
Description
-----------
[From datasheet] The SMM665 is an Active DC Output power supply Controller
that monitors, margins and cascade sequences power. The part monitors six
power supply channels as well as VDD, 12V input, two general-purpose analog
inputs and an internal temperature sensor using a 10-bit ADC.
Each monitored channel has its own high and low limits, plus a critical
limit.
Support for SMM465, SMM764, and SMM766 has been implemented but is untested.
Usage Notes
-----------
This driver does not probe for devices, since there is no register which
can be safely used to identify the chip. You will have to instantiate
the devices explicitly. When instantiating the device, you have to specify
its configuration register address.
Example: the following will load the driver for an SMM665 at address 0x57
on I2C bus #1::
$ modprobe smm665
$ echo smm665 0x57 > /sys/bus/i2c/devices/i2c-1/new_device
Sysfs entries
-------------
This driver uses the values in the datasheet to convert ADC register values
into the values specified in the sysfs-interface document. All attributes are
read only.
Min, max, lcrit, and crit values are used by the chip to trigger external signals
and/or other activity. Triggered signals can include HEALTHY, RST, Power Off,
or Fault depending on the chip configuration. The driver reports values as lcrit
or crit if exceeding the limits triggers RST, Power Off, or Fault, and as min or
max otherwise. For details please see the SMM665 datasheet.
For SMM465 and SMM764, values for Channel E and F are reported but undefined.
======================= =======================================================
in1_input 12V input voltage (mV)
in2_input 3.3V (VDD) input voltage (mV)
in3_input Channel A voltage (mV)
in4_input Channel B voltage (mV)
in5_input Channel C voltage (mV)
in6_input Channel D voltage (mV)
in7_input Channel E voltage (mV)
in8_input Channel F voltage (mV)
in9_input AIN1 voltage (mV)
in10_input AIN2 voltage (mV)
in1_min 12v input minimum voltage (mV)
in2_min 3.3V (VDD) input minimum voltage (mV)
in3_min Channel A minimum voltage (mV)
in4_min Channel B minimum voltage (mV)
in5_min Channel C minimum voltage (mV)
in6_min Channel D minimum voltage (mV)
in7_min Channel E minimum voltage (mV)
in8_min Channel F minimum voltage (mV)
in9_min AIN1 minimum voltage (mV)
in10_min AIN2 minimum voltage (mV)
in1_max 12v input maximum voltage (mV)
in2_max 3.3V (VDD) input maximum voltage (mV)
in3_max Channel A maximum voltage (mV)
in4_max Channel B maximum voltage (mV)
in5_max Channel C maximum voltage (mV)
in6_max Channel D maximum voltage (mV)
in7_max Channel E maximum voltage (mV)
in8_max Channel F maximum voltage (mV)
in9_max AIN1 maximum voltage (mV)
in10_max AIN2 maximum voltage (mV)
in1_lcrit 12v input critical minimum voltage (mV)
in2_lcrit 3.3V (VDD) input critical minimum voltage (mV)
in3_lcrit Channel A critical minimum voltage (mV)
in4_lcrit Channel B critical minimum voltage (mV)
in5_lcrit Channel C critical minimum voltage (mV)
in6_lcrit Channel D critical minimum voltage (mV)
in7_lcrit Channel E critical minimum voltage (mV)
in8_lcrit Channel F critical minimum voltage (mV)
in9_lcrit AIN1 critical minimum voltage (mV)
in10_lcrit AIN2 critical minimum voltage (mV)
in1_crit 12v input critical maximum voltage (mV)
in2_crit 3.3V (VDD) input critical maximum voltage (mV)
in3_crit Channel A critical maximum voltage (mV)
in4_crit Channel B critical maximum voltage (mV)
in5_crit Channel C critical maximum voltage (mV)
in6_crit Channel D critical maximum voltage (mV)
in7_crit Channel E critical maximum voltage (mV)
in8_crit Channel F critical maximum voltage (mV)
in9_crit AIN1 critical maximum voltage (mV)
in10_crit AIN2 critical maximum voltage (mV)
in1_crit_alarm 12v input critical alarm
in2_crit_alarm 3.3V (VDD) input critical alarm
in3_crit_alarm Channel A critical alarm
in4_crit_alarm Channel B critical alarm
in5_crit_alarm Channel C critical alarm
in6_crit_alarm Channel D critical alarm
in7_crit_alarm Channel E critical alarm
in8_crit_alarm Channel F critical alarm
in9_crit_alarm AIN1 critical alarm
in10_crit_alarm AIN2 critical alarm
temp1_input Chip temperature
temp1_min Minimum chip temperature
temp1_max Maximum chip temperature
temp1_crit Critical chip temperature
temp1_crit_alarm Temperature critical alarm
======================= =======================================================
MAINTAINERS
+35 -10
View File
@@ -915,6 +915,18 @@ S: Supported
F: drivers/crypto/ccp/sev*
F: include/uapi/linux/psp-sev.h
AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT
M: Mario Limonciello <mario.limonciello@amd.com>
L: linux-crypto@vger.kernel.org
S: Supported
F: drivers/crypto/ccp/dbc.c
F: drivers/crypto/ccp/dbc.h
F: drivers/crypto/ccp/platform-access.c
F: drivers/crypto/ccp/platform-access.h
F: include/uapi/linux/psp-dbc.h
F: tools/crypto/ccp/*.c
F: tools/crypto/ccp/*.py
AMD DISPLAY CORE
M: Harry Wentland <harry.wentland@amd.com>
M: Leo Li <sunpeng.li@amd.com>
@@ -4126,7 +4138,7 @@ BROADCOM BCM6348/BCM6358 SPI controller DRIVER
M: Jonas Gorski <jonas.gorski@gmail.com>
L: linux-spi@vger.kernel.org
S: Odd Fixes
F: Documentation/devicetree/bindings/spi/spi-bcm63xx.txt
F: Documentation/devicetree/bindings/spi/brcm,bcm63xx-spi.yaml
F: drivers/spi/spi-bcm63xx.c
BROADCOM ETHERNET PHY DRIVERS
@@ -4195,7 +4207,7 @@ BROADCOM KONA GPIO DRIVER
M: Ray Jui <rjui@broadcom.com>
R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
S: Supported
F: Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt
F: Documentation/devicetree/bindings/gpio/brcm,kona-gpio.yaml
F: drivers/gpio/gpio-bcm-kona.c
BROADCOM MPI3 STORAGE CONTROLLER DRIVER
@@ -4887,7 +4899,11 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers)
L: patches@opensource.cirrus.com
S: Maintained
F: Documentation/devicetree/bindings/sound/cirrus,cs*
F: drivers/mfd/cs42l43*
F: drivers/pinctrl/cirrus/pinctrl-cs42l43*
F: drivers/spi/spi-cs42l43*
F: include/dt-bindings/sound/cs*
F: include/linux/mfd/cs42l43*
F: include/sound/cs*
F: sound/pci/hda/cs*
F: sound/pci/hda/hda_cs_dsp_ctl.*
@@ -6010,7 +6026,7 @@ F: Documentation/devicetree/bindings/mfd/da90*.txt
F: Documentation/devicetree/bindings/mfd/dlg,da90*.yaml
F: Documentation/devicetree/bindings/regulator/da92*.txt
F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
F: Documentation/devicetree/bindings/regulator/slg51000.txt
F: Documentation/devicetree/bindings/regulator/dlg,slg51000.yaml
F: Documentation/devicetree/bindings/sound/da[79]*.txt
F: Documentation/devicetree/bindings/thermal/da90??-thermal.txt
F: Documentation/devicetree/bindings/watchdog/da90??-wdt.txt
@@ -9505,6 +9521,12 @@ S: Maintained
W: http://artax.karlin.mff.cuni.cz/~mikulas/vyplody/hpfs/index-e.cgi
F: fs/hpfs/
HS3001 Hardware Temperature and Humidity Sensor
M: Andre Werner <andre.werner@systec-electronic.com>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: drivers/hwmon/hs3001.c
HSI SUBSYSTEM
M: Sebastian Reichel <sre@kernel.org>
S: Maintained
@@ -12289,6 +12311,16 @@ F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
F: drivers/clk/clk-loongson2.c
F: include/dt-bindings/clock/loongson,ls2k-clk.h
LOONGSON SPI DRIVER
M: Yinbo Zhu <zhuyinbo@loongson.cn>
L: linux-spi@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/loongson,ls2k-spi.yaml
F: drivers/spi/spi-loongson-core.c
F: drivers/spi/spi-loongson-pci.c
F: drivers/spi/spi-loongson-plat.c
F: drivers/spi/spi-loongson.h
LOONGSON-2 SOC SERIES GUTS DRIVER
M: Yinbo Zhu <zhuyinbo@loongson.cn>
L: loongarch@lists.linux.dev
@@ -19618,13 +19650,6 @@ M: Nicolas Pitre <nico@fluxnic.net>
S: Odd Fixes
F: drivers/net/ethernet/smsc/smc91x.*
SMM665 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/hwmon/smm665.rst
F: drivers/hwmon/smm665.c
SMSC EMC2103 HARDWARE MONITOR DRIVER
M: Steve Glendinning <steve.glendinning@shawell.net>
L: linux-hwmon@vger.kernel.org
arch/arm64/crypto/Makefile
-5
View File
@@ -81,11 +81,6 @@ aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
obj-$(CONFIG_CRYPTO_AES_ARM64_BS) += aes-neon-bs.o
aes-neon-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
$(obj)/aes-glue-%.o: $(src)/aes-glue.c FORCE
$(call if_changed_rule,cc_o_c)
quiet_cmd_perlasm = PERLASM $@
cmd_perlasm = $(PERL) $(<) void $(@)
arch/arm64/crypto/aes-glue-ce.c
+2
View File
@@ -0,0 +1,2 @@
#define USE_V8_CRYPTO_EXTENSIONS
#include "aes-glue.c"
arch/arm64/crypto/aes-glue-neon.c
+1
View File
@@ -0,0 +1 @@
#include "aes-glue.c"
arch/powerpc/crypto/Kconfig
+26
View File
@@ -111,4 +111,30 @@ config CRYPTO_AES_GCM_P10
Support for cryptographic acceleration instructions on Power10 or
later CPU. This module supports stitched acceleration for AES/GCM.
config CRYPTO_CHACHA20_P10
tristate "Ciphers: ChaCha20, XChacha20, XChacha12 (P10 or later)"
depends on PPC64 && CPU_LITTLE_ENDIAN
select CRYPTO_SKCIPHER
select CRYPTO_LIB_CHACHA_GENERIC
select CRYPTO_ARCH_HAVE_LIB_CHACHA
help
Length-preserving ciphers: ChaCha20, XChaCha20, and XChaCha12
stream cipher algorithms
Architecture: PowerPC64
- Power10 or later
- Little-endian
config CRYPTO_POLY1305_P10
tristate "Hash functions: Poly1305 (P10 or later)"
depends on PPC64 && CPU_LITTLE_ENDIAN
select CRYPTO_HASH
select CRYPTO_LIB_POLY1305_GENERIC
help
Poly1305 authenticator algorithm (RFC7539)
Architecture: PowerPC64
- Power10 or later
- Little-endian
endmenu
arch/powerpc/crypto/Makefile
+4
View File
@@ -14,6 +14,8 @@ obj-$(CONFIG_CRYPTO_CRC32C_VPMSUM) += crc32c-vpmsum.o
obj-$(CONFIG_CRYPTO_CRCT10DIF_VPMSUM) += crct10dif-vpmsum.o
obj-$(CONFIG_CRYPTO_VPMSUM_TESTER) += crc-vpmsum_test.o
obj-$(CONFIG_CRYPTO_AES_GCM_P10) += aes-gcm-p10-crypto.o
obj-$(CONFIG_CRYPTO_CHACHA20_P10) += chacha-p10-crypto.o
obj-$(CONFIG_CRYPTO_POLY1305_P10) += poly1305-p10-crypto.o
aes-ppc-spe-y := aes-spe-core.o aes-spe-keys.o aes-tab-4k.o aes-spe-modes.o aes-spe-glue.o
md5-ppc-y := md5-asm.o md5-glue.o
@@ -23,6 +25,8 @@ sha256-ppc-spe-y := sha256-spe-asm.o sha256-spe-glue.o
crc32c-vpmsum-y := crc32c-vpmsum_asm.o crc32c-vpmsum_glue.o
crct10dif-vpmsum-y := crct10dif-vpmsum_asm.o crct10dif-vpmsum_glue.o
aes-gcm-p10-crypto-y := aes-gcm-p10-glue.o aes-gcm-p10.o ghashp10-ppc.o aesp10-ppc.o
chacha-p10-crypto-y := chacha-p10-glue.o chacha-p10le-8x.o
poly1305-p10-crypto-y := poly1305-p10-glue.o poly1305-p10le_64.o
quiet_cmd_perl = PERL $@
cmd_perl = $(PERL) $< $(if $(CONFIG_CPU_LITTLE_ENDIAN), linux-ppc64le, linux-ppc64) > $@
arch/powerpc/crypto/chacha-p10-glue.c
+221
View File
@@ -0,0 +1,221 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PowerPC P10 (ppc64le) accelerated ChaCha and XChaCha stream ciphers,
* including ChaCha20 (RFC7539)
*
* Copyright 2023- IBM Corp. All rights reserved.
*/
#include <crypto/algapi.h>
#include <crypto/internal/chacha.h>
#include <crypto/internal/simd.h>
#include <crypto/internal/skcipher.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpufeature.h>
#include <linux/sizes.h>
#include <asm/simd.h>
#include <asm/switch_to.h>
asmlinkage void chacha_p10le_8x(u32 *state, u8 *dst, const u8 *src,
unsigned int len, int nrounds);
static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_p10);
static void vsx_begin(void)
{
preempt_disable();
enable_kernel_vsx();
}
static void vsx_end(void)
{
disable_kernel_vsx();
preempt_enable();
}
static void chacha_p10_do_8x(u32 *state, u8 *dst, const u8 *src,
unsigned int bytes, int nrounds)
{
unsigned int l = bytes & ~0x0FF;
if (l > 0) {
chacha_p10le_8x(state, dst, src, l, nrounds);
bytes -= l;
src += l;
dst += l;
state[12] += l / CHACHA_BLOCK_SIZE;
}
if (bytes > 0)
chacha_crypt_generic(state, dst, src, bytes, nrounds);
}
void hchacha_block_arch(const u32 *state, u32 *stream, int nrounds)
{
hchacha_block_generic(state, stream, nrounds);
}
EXPORT_SYMBOL(hchacha_block_arch);
void chacha_init_arch(u32 *state, const u32 *key, const u8 *iv)
{
chacha_init_generic(state, key, iv);
}
EXPORT_SYMBOL(chacha_init_arch);
void chacha_crypt_arch(u32 *state, u8 *dst, const u8 *src, unsigned int bytes,
int nrounds)
{
if (!static_branch_likely(&have_p10) || bytes <= CHACHA_BLOCK_SIZE ||
!crypto_simd_usable())
return chacha_crypt_generic(state, dst, src, bytes, nrounds);
do {
unsigned int todo = min_t(unsigned int, bytes, SZ_4K);
vsx_begin();
chacha_p10_do_8x(state, dst, src, todo, nrounds);
vsx_end();
bytes -= todo;
src += todo;
dst += todo;
} while (bytes);
}
EXPORT_SYMBOL(chacha_crypt_arch);
static int chacha_p10_stream_xor(struct skcipher_request *req,
const struct chacha_ctx *ctx, const u8 *iv)
{
struct skcipher_walk walk;
u32 state[16];
int err;
err = skcipher_walk_virt(&walk, req, false);
if (err)
return err;
chacha_init_generic(state, ctx->key, iv);
while (walk.nbytes > 0) {
unsigned int nbytes = walk.nbytes;
if (nbytes < walk.total)
nbytes = rounddown(nbytes, walk.stride);
if (!crypto_simd_usable()) {
chacha_crypt_generic(state, walk.dst.virt.addr,
walk.src.virt.addr, nbytes,
ctx->nrounds);
} else {
vsx_begin();
chacha_p10_do_8x(state, walk.dst.virt.addr,
walk.src.virt.addr, nbytes, ctx->nrounds);
vsx_end();
}
err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
if (err)
break;
}
return err;
}
static int chacha_p10(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
return chacha_p10_stream_xor(req, ctx, req->iv);
}
static int xchacha_p10(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
struct chacha_ctx subctx;
u32 state[16];
u8 real_iv[16];
chacha_init_generic(state, ctx->key, req->iv);
hchacha_block_arch(state, subctx.key, ctx->nrounds);
subctx.nrounds = ctx->nrounds;
memcpy(&real_iv[0], req->iv + 24, 8);
memcpy(&real_iv[8], req->iv + 16, 8);
return chacha_p10_stream_xor(req, &subctx, real_iv);
}
static struct skcipher_alg algs[] = {
{
.base.cra_name = "chacha20",
.base.cra_driver_name = "chacha20-p10",
.base.cra_priority = 300,
.base.cra_blocksize = 1,
.base.cra_ctxsize = sizeof(struct chacha_ctx),
.base.cra_module = THIS_MODULE,
.min_keysize = CHACHA_KEY_SIZE,
.max_keysize = CHACHA_KEY_SIZE,
.ivsize = CHACHA_IV_SIZE,
.chunksize = CHACHA_BLOCK_SIZE,
.setkey = chacha20_setkey,
.encrypt = chacha_p10,
.decrypt = chacha_p10,
}, {
.base.cra_name = "xchacha20",
.base.cra_driver_name = "xchacha20-p10",
.base.cra_priority = 300,
.base.cra_blocksize = 1,
.base.cra_ctxsize = sizeof(struct chacha_ctx),
.base.cra_module = THIS_MODULE,
.min_keysize = CHACHA_KEY_SIZE,
.max_keysize = CHACHA_KEY_SIZE,
.ivsize = XCHACHA_IV_SIZE,
.chunksize = CHACHA_BLOCK_SIZE,
.setkey = chacha20_setkey,
.encrypt = xchacha_p10,
.decrypt = xchacha_p10,
}, {
.base.cra_name = "xchacha12",
.base.cra_driver_name = "xchacha12-p10",
.base.cra_priority = 300,
.base.cra_blocksize = 1,
.base.cra_ctxsize = sizeof(struct chacha_ctx),
.base.cra_module = THIS_MODULE,
.min_keysize = CHACHA_KEY_SIZE,
.max_keysize = CHACHA_KEY_SIZE,
.ivsize = XCHACHA_IV_SIZE,
.chunksize = CHACHA_BLOCK_SIZE,
.setkey = chacha12_setkey,
.encrypt = xchacha_p10,
.decrypt = xchacha_p10,
}
};
static int __init chacha_p10_init(void)
{
static_branch_enable(&have_p10);
return crypto_register_skciphers(algs, ARRAY_SIZE(algs));
}
static void __exit chacha_p10_exit(void)
{
crypto_unregister_skciphers(algs, ARRAY_SIZE(algs));
}
module_cpu_feature_match(PPC_MODULE_FEATURE_P10, chacha_p10_init);
module_exit(chacha_p10_exit);
MODULE_DESCRIPTION("ChaCha and XChaCha stream ciphers (P10 accelerated)");
MODULE_AUTHOR("Danny Tsen <dtsen@linux.ibm.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS_CRYPTO("chacha20");
MODULE_ALIAS_CRYPTO("chacha20-p10");
MODULE_ALIAS_CRYPTO("xchacha20");
MODULE_ALIAS_CRYPTO("xchacha20-p10");
MODULE_ALIAS_CRYPTO("xchacha12");
MODULE_ALIAS_CRYPTO("xchacha12-p10");
arch/powerpc/crypto/chacha-p10le-8x.S
+842
View File
@@ -0,0 +1,842 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#
# Accelerated chacha20 implementation for ppc64le.
#
# Copyright 2023- IBM Corp. All rights reserved
#
#===================================================================================
# Written by Danny Tsen <dtsen@us.ibm.com>
#
# chacha_p10le_8x(u32 *state, byte *dst, const byte *src,
# size_t len, int nrounds);
#
# do rounds, 8 quarter rounds
# 1. a += b; d ^= a; d <<<= 16;
# 2. c += d; b ^= c; b <<<= 12;
# 3. a += b; d ^= a; d <<<= 8;
# 4. c += d; b ^= c; b <<<= 7
#
# row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
# row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
# row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 8
# row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
#
# 4 blocks (a b c d)
#
# a0 b0 c0 d0
# a1 b1 c1 d1
# ...
# a4 b4 c4 d4
# ...
# a8 b8 c8 d8
# ...
# a12 b12 c12 d12
# a13 ...
# a14 ...
# a15 b15 c15 d15
#
# Column round (v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
# Diagnal round (v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
#
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/asm-compat.h>
#include <linux/linkage.h>
.machine "any"
.text
.macro SAVE_GPR GPR OFFSET FRAME
std \GPR,\OFFSET(\FRAME)
.endm
.macro SAVE_VRS VRS OFFSET FRAME
li 16, \OFFSET
stvx \VRS, 16, \FRAME
.endm
.macro SAVE_VSX VSX OFFSET FRAME
li 16, \OFFSET
stxvx \VSX, 16, \FRAME
.endm
.macro RESTORE_GPR GPR OFFSET FRAME
ld \GPR,\OFFSET(\FRAME)
.endm
.macro RESTORE_VRS VRS OFFSET FRAME
li 16, \OFFSET
lvx \VRS, 16, \FRAME
.endm
.macro RESTORE_VSX VSX OFFSET FRAME
li 16, \OFFSET
lxvx \VSX, 16, \FRAME
.endm
.macro SAVE_REGS
mflr 0
std 0, 16(1)
stdu 1,-752(1)
SAVE_GPR 14, 112, 1
SAVE_GPR 15, 120, 1
SAVE_GPR 16, 128, 1
SAVE_GPR 17, 136, 1
SAVE_GPR 18, 144, 1
SAVE_GPR 19, 152, 1
SAVE_GPR 20, 160, 1
SAVE_GPR 21, 168, 1
SAVE_GPR 22, 176, 1
SAVE_GPR 23, 184, 1
SAVE_GPR 24, 192, 1
SAVE_GPR 25, 200, 1
SAVE_GPR 26, 208, 1
SAVE_GPR 27, 216, 1
SAVE_GPR 28, 224, 1
SAVE_GPR 29, 232, 1
SAVE_GPR 30, 240, 1
SAVE_GPR 31, 248, 1
addi 9, 1, 256
SAVE_VRS 20, 0, 9
SAVE_VRS 21, 16, 9
SAVE_VRS 22, 32, 9
SAVE_VRS 23, 48, 9
SAVE_VRS 24, 64, 9
SAVE_VRS 25, 80, 9
SAVE_VRS 26, 96, 9
SAVE_VRS 27, 112, 9
SAVE_VRS 28, 128, 9
SAVE_VRS 29, 144, 9
SAVE_VRS 30, 160, 9
SAVE_VRS 31, 176, 9
SAVE_VSX 14, 192, 9
SAVE_VSX 15, 208, 9
SAVE_VSX 16, 224, 9
SAVE_VSX 17, 240, 9
SAVE_VSX 18, 256, 9
SAVE_VSX 19, 272, 9
SAVE_VSX 20, 288, 9
SAVE_VSX 21, 304, 9
SAVE_VSX 22, 320, 9
SAVE_VSX 23, 336, 9
SAVE_VSX 24, 352, 9
SAVE_VSX 25, 368, 9
SAVE_VSX 26, 384, 9
SAVE_VSX 27, 400, 9
SAVE_VSX 28, 416, 9
SAVE_VSX 29, 432, 9
SAVE_VSX 30, 448, 9
SAVE_VSX 31, 464, 9
.endm # SAVE_REGS
.macro RESTORE_REGS
addi 9, 1, 256
RESTORE_VRS 20, 0, 9
RESTORE_VRS 21, 16, 9
RESTORE_VRS 22, 32, 9
RESTORE_VRS 23, 48, 9
RESTORE_VRS 24, 64, 9
RESTORE_VRS 25, 80, 9
RESTORE_VRS 26, 96, 9
RESTORE_VRS 27, 112, 9
RESTORE_VRS 28, 128, 9
RESTORE_VRS 29, 144, 9
RESTORE_VRS 30, 160, 9
RESTORE_VRS 31, 176, 9
RESTORE_VSX 14, 192, 9
RESTORE_VSX 15, 208, 9
RESTORE_VSX 16, 224, 9
RESTORE_VSX 17, 240, 9
RESTORE_VSX 18, 256, 9
RESTORE_VSX 19, 272, 9
RESTORE_VSX 20, 288, 9
RESTORE_VSX 21, 304, 9
RESTORE_VSX 22, 320, 9
RESTORE_VSX 23, 336, 9
RESTORE_VSX 24, 352, 9
RESTORE_VSX 25, 368, 9
RESTORE_VSX 26, 384, 9
RESTORE_VSX 27, 400, 9
RESTORE_VSX 28, 416, 9
RESTORE_VSX 29, 432, 9
RESTORE_VSX 30, 448, 9
RESTORE_VSX 31, 464, 9
RESTORE_GPR 14, 112, 1
RESTORE_GPR 15, 120, 1
RESTORE_GPR 16, 128, 1
RESTORE_GPR 17, 136, 1
RESTORE_GPR 18, 144, 1
RESTORE_GPR 19, 152, 1
RESTORE_GPR 20, 160, 1
RESTORE_GPR 21, 168, 1
RESTORE_GPR 22, 176, 1
RESTORE_GPR 23, 184, 1
RESTORE_GPR 24, 192, 1
RESTORE_GPR 25, 200, 1
RESTORE_GPR 26, 208, 1
RESTORE_GPR 27, 216, 1
RESTORE_GPR 28, 224, 1
RESTORE_GPR 29, 232, 1
RESTORE_GPR 30, 240, 1
RESTORE_GPR 31, 248, 1
addi 1, 1, 752
ld 0, 16(1)
mtlr 0
.endm # RESTORE_REGS
.macro QT_loop_8x
# QR(v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
xxlor 0, 32+25, 32+25
xxlor 32+25, 20, 20
vadduwm 0, 0, 4
vadduwm 1, 1, 5
vadduwm 2, 2, 6
vadduwm 3, 3, 7
vadduwm 16, 16, 20
vadduwm 17, 17, 21
vadduwm 18, 18, 22
vadduwm 19, 19, 23
vpermxor 12, 12, 0, 25
vpermxor 13, 13, 1, 25
vpermxor 14, 14, 2, 25
vpermxor 15, 15, 3, 25
vpermxor 28, 28, 16, 25
vpermxor 29, 29, 17, 25
vpermxor 30, 30, 18, 25
vpermxor 31, 31, 19, 25
xxlor 32+25, 0, 0
vadduwm 8, 8, 12
vadduwm 9, 9, 13
vadduwm 10, 10, 14
vadduwm 11, 11, 15
vadduwm 24, 24, 28
vadduwm 25, 25, 29
vadduwm 26, 26, 30
vadduwm 27, 27, 31
vxor 4, 4, 8
vxor 5, 5, 9
vxor 6, 6, 10
vxor 7, 7, 11
vxor 20, 20, 24
vxor 21, 21, 25
vxor 22, 22, 26
vxor 23, 23, 27
xxlor 0, 32+25, 32+25
xxlor 32+25, 21, 21
vrlw 4, 4, 25 #
vrlw 5, 5, 25
vrlw 6, 6, 25
vrlw 7, 7, 25
vrlw 20, 20, 25 #
vrlw 21, 21, 25
vrlw 22, 22, 25
vrlw 23, 23, 25
xxlor 32+25, 0, 0
vadduwm 0, 0, 4
vadduwm 1, 1, 5
vadduwm 2, 2, 6
vadduwm 3, 3, 7
vadduwm 16, 16, 20
vadduwm 17, 17, 21
vadduwm 18, 18, 22
vadduwm 19, 19, 23
xxlor 0, 32+25, 32+25
xxlor 32+25, 22, 22
vpermxor 12, 12, 0, 25
vpermxor 13, 13, 1, 25
vpermxor 14, 14, 2, 25
vpermxor 15, 15, 3, 25
vpermxor 28, 28, 16, 25
vpermxor 29, 29, 17, 25
vpermxor 30, 30, 18, 25
vpermxor 31, 31, 19, 25
xxlor 32+25, 0, 0
vadduwm 8, 8, 12
vadduwm 9, 9, 13
vadduwm 10, 10, 14
vadduwm 11, 11, 15
vadduwm 24, 24, 28
vadduwm 25, 25, 29
vadduwm 26, 26, 30
vadduwm 27, 27, 31
xxlor 0, 32+28, 32+28
xxlor 32+28, 23, 23
vxor 4, 4, 8
vxor 5, 5, 9
vxor 6, 6, 10
vxor 7, 7, 11
vxor 20, 20, 24
vxor 21, 21, 25
vxor 22, 22, 26
vxor 23, 23, 27
vrlw 4, 4, 28 #
vrlw 5, 5, 28
vrlw 6, 6, 28
vrlw 7, 7, 28
vrlw 20, 20, 28 #
vrlw 21, 21, 28
vrlw 22, 22, 28
vrlw 23, 23, 28
xxlor 32+28, 0, 0
# QR(v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
xxlor 0, 32+25, 32+25
xxlor 32+25, 20, 20
vadduwm 0, 0, 5
vadduwm 1, 1, 6
vadduwm 2, 2, 7
vadduwm 3, 3, 4
vadduwm 16, 16, 21
vadduwm 17, 17, 22
vadduwm 18, 18, 23
vadduwm 19, 19, 20
vpermxor 15, 15, 0, 25
vpermxor 12, 12, 1, 25
vpermxor 13, 13, 2, 25
vpermxor 14, 14, 3, 25
vpermxor 31, 31, 16, 25
vpermxor 28, 28, 17, 25
vpermxor 29, 29, 18, 25
vpermxor 30, 30, 19, 25
xxlor 32+25, 0, 0
vadduwm 10, 10, 15
vadduwm 11, 11, 12
vadduwm 8, 8, 13
vadduwm 9, 9, 14
vadduwm 26, 26, 31
vadduwm 27, 27, 28
vadduwm 24, 24, 29
vadduwm 25, 25, 30
vxor 5, 5, 10
vxor 6, 6, 11
vxor 7, 7, 8
vxor 4, 4, 9
vxor 21, 21, 26
vxor 22, 22, 27
vxor 23, 23, 24
vxor 20, 20, 25
xxlor 0, 32+25, 32+25
xxlor 32+25, 21, 21
vrlw 5, 5, 25
vrlw 6, 6, 25
vrlw 7, 7, 25
vrlw 4, 4, 25
vrlw 21, 21, 25
vrlw 22, 22, 25
vrlw 23, 23, 25
vrlw 20, 20, 25
xxlor 32+25, 0, 0
vadduwm 0, 0, 5
vadduwm 1, 1, 6
vadduwm 2, 2, 7
vadduwm 3, 3, 4
vadduwm 16, 16, 21
vadduwm 17, 17, 22
vadduwm 18, 18, 23
vadduwm 19, 19, 20
xxlor 0, 32+25, 32+25
xxlor 32+25, 22, 22
vpermxor 15, 15, 0, 25
vpermxor 12, 12, 1, 25
vpermxor 13, 13, 2, 25
vpermxor 14, 14, 3, 25
vpermxor 31, 31, 16, 25
vpermxor 28, 28, 17, 25
vpermxor 29, 29, 18, 25
vpermxor 30, 30, 19, 25
xxlor 32+25, 0, 0
vadduwm 10, 10, 15
vadduwm 11, 11, 12
vadduwm 8, 8, 13
vadduwm 9, 9, 14
vadduwm 26, 26, 31
vadduwm 27, 27, 28
vadduwm 24, 24, 29
vadduwm 25, 25, 30
xxlor 0, 32+28, 32+28
xxlor 32+28, 23, 23
vxor 5, 5, 10
vxor 6, 6, 11
vxor 7, 7, 8
vxor 4, 4, 9
vxor 21, 21, 26
vxor 22, 22, 27
vxor 23, 23, 24
vxor 20, 20, 25
vrlw 5, 5, 28
vrlw 6, 6, 28
vrlw 7, 7, 28
vrlw 4, 4, 28
vrlw 21, 21, 28
vrlw 22, 22, 28
vrlw 23, 23, 28
vrlw 20, 20, 28
xxlor 32+28, 0, 0
.endm
.macro QT_loop_4x
# QR(v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
vadduwm 0, 0, 4
vadduwm 1, 1, 5
vadduwm 2, 2, 6
vadduwm 3, 3, 7
vpermxor 12, 12, 0, 20
vpermxor 13, 13, 1, 20
vpermxor 14, 14, 2, 20
vpermxor 15, 15, 3, 20
vadduwm 8, 8, 12
vadduwm 9, 9, 13
vadduwm 10, 10, 14
vadduwm 11, 11, 15
vxor 4, 4, 8
vxor 5, 5, 9
vxor 6, 6, 10
vxor 7, 7, 11
vrlw 4, 4, 21
vrlw 5, 5, 21
vrlw 6, 6, 21
vrlw 7, 7, 21
vadduwm 0, 0, 4
vadduwm 1, 1, 5
vadduwm 2, 2, 6
vadduwm 3, 3, 7
vpermxor 12, 12, 0, 22
vpermxor 13, 13, 1, 22
vpermxor 14, 14, 2, 22
vpermxor 15, 15, 3, 22
vadduwm 8, 8, 12
vadduwm 9, 9, 13
vadduwm 10, 10, 14
vadduwm 11, 11, 15
vxor 4, 4, 8
vxor 5, 5, 9
vxor 6, 6, 10
vxor 7, 7, 11
vrlw 4, 4, 23
vrlw 5, 5, 23
vrlw 6, 6, 23
vrlw 7, 7, 23
# QR(v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
vadduwm 0, 0, 5
vadduwm 1, 1, 6
vadduwm 2, 2, 7
vadduwm 3, 3, 4
vpermxor 15, 15, 0, 20
vpermxor 12, 12, 1, 20
vpermxor 13, 13, 2, 20
vpermxor 14, 14, 3, 20
vadduwm 10, 10, 15
vadduwm 11, 11, 12
vadduwm 8, 8, 13
vadduwm 9, 9, 14
vxor 5, 5, 10
vxor 6, 6, 11
vxor 7, 7, 8
vxor 4, 4, 9
vrlw 5, 5, 21
vrlw 6, 6, 21
vrlw 7, 7, 21
vrlw 4, 4, 21
vadduwm 0, 0, 5
vadduwm 1, 1, 6
vadduwm 2, 2, 7
vadduwm 3, 3, 4
vpermxor 15, 15, 0, 22
vpermxor 12, 12, 1, 22
vpermxor 13, 13, 2, 22
vpermxor 14, 14, 3, 22
vadduwm 10, 10, 15
vadduwm 11, 11, 12
vadduwm 8, 8, 13
vadduwm 9, 9, 14
vxor 5, 5, 10
vxor 6, 6, 11
vxor 7, 7, 8
vxor 4, 4, 9
vrlw 5, 5, 23
vrlw 6, 6, 23
vrlw 7, 7, 23
vrlw 4, 4, 23
.endm
# Transpose
.macro TP_4x a0 a1 a2 a3
xxmrghw 10, 32+\a0, 32+\a1 # a0, a1, b0, b1
xxmrghw 11, 32+\a2, 32+\a3 # a2, a3, b2, b3
xxmrglw 12, 32+\a0, 32+\a1 # c0, c1, d0, d1
xxmrglw 13, 32+\a2, 32+\a3 # c2, c3, d2, d3
xxpermdi 32+\a0, 10, 11, 0 # a0, a1, a2, a3
xxpermdi 32+\a1, 10, 11, 3 # b0, b1, b2, b3
xxpermdi 32+\a2, 12, 13, 0 # c0, c1, c2, c3
xxpermdi 32+\a3, 12, 13, 3 # d0, d1, d2, d3
.endm
# key stream = working state + state
.macro Add_state S
vadduwm \S+0, \S+0, 16-\S
vadduwm \S+4, \S+4, 17-\S
vadduwm \S+8, \S+8, 18-\S
vadduwm \S+12, \S+12, 19-\S
vadduwm \S+1, \S+1, 16-\S
vadduwm \S+5, \S+5, 17-\S
vadduwm \S+9, \S+9, 18-\S
vadduwm \S+13, \S+13, 19-\S
vadduwm \S+2, \S+2, 16-\S
vadduwm \S+6, \S+6, 17-\S
vadduwm \S+10, \S+10, 18-\S
vadduwm \S+14, \S+14, 19-\S
vadduwm \S+3, \S+3, 16-\S
vadduwm \S+7, \S+7, 17-\S
vadduwm \S+11, \S+11, 18-\S
vadduwm \S+15, \S+15, 19-\S
.endm
#
# write 256 bytes
#
.macro Write_256 S
add 9, 14, 5
add 16, 14, 4
lxvw4x 0, 0, 9
lxvw4x 1, 17, 9
lxvw4x 2, 18, 9
lxvw4x 3, 19, 9
lxvw4x 4, 20, 9
lxvw4x 5, 21, 9
lxvw4x 6, 22, 9
lxvw4x 7, 23, 9
lxvw4x 8, 24, 9
lxvw4x 9, 25, 9
lxvw4x 10, 26, 9
lxvw4x 11, 27, 9
lxvw4x 12, 28, 9
lxvw4x 13, 29, 9
lxvw4x 14, 30, 9
lxvw4x 15, 31, 9
xxlxor \S+32, \S+32, 0
xxlxor \S+36, \S+36, 1
xxlxor \S+40, \S+40, 2
xxlxor \S+44, \S+44, 3
xxlxor \S+33, \S+33, 4
xxlxor \S+37, \S+37, 5
xxlxor \S+41, \S+41, 6
xxlxor \S+45, \S+45, 7
xxlxor \S+34, \S+34, 8
xxlxor \S+38, \S+38, 9
xxlxor \S+42, \S+42, 10
xxlxor \S+46, \S+46, 11
xxlxor \S+35, \S+35, 12
xxlxor \S+39, \S+39, 13
xxlxor \S+43, \S+43, 14
xxlxor \S+47, \S+47, 15
stxvw4x \S+32, 0, 16
stxvw4x \S+36, 17, 16
stxvw4x \S+40, 18, 16
stxvw4x \S+44, 19, 16
stxvw4x \S+33, 20, 16
stxvw4x \S+37, 21, 16
stxvw4x \S+41, 22, 16
stxvw4x \S+45, 23, 16
stxvw4x \S+34, 24, 16
stxvw4x \S+38, 25, 16
stxvw4x \S+42, 26, 16
stxvw4x \S+46, 27, 16
stxvw4x \S+35, 28, 16
stxvw4x \S+39, 29, 16
stxvw4x \S+43, 30, 16
stxvw4x \S+47, 31, 16
.endm
#
# chacha20_p10le_8x(u32 *state, byte *dst, const byte *src, size_t len, int nrounds);
#
SYM_FUNC_START(chacha_p10le_8x)
.align 5
cmpdi 6, 0
ble Out_no_chacha
SAVE_REGS
# r17 - r31 mainly for Write_256 macro.
li 17, 16
li 18, 32
li 19, 48
li 20, 64
li 21, 80
li 22, 96
li 23, 112
li 24, 128
li 25, 144
li 26, 160
li 27, 176
li 28, 192
li 29, 208
li 30, 224
li 31, 240
mr 15, 6 # len
li 14, 0 # offset to inp and outp
lxvw4x 48, 0, 3 # vr16, constants
lxvw4x 49, 17, 3 # vr17, key 1
lxvw4x 50, 18, 3 # vr18, key 2
lxvw4x 51, 19, 3 # vr19, counter, nonce
# create (0, 1, 2, 3) counters
vspltisw 0, 0
vspltisw 1, 1
vspltisw 2, 2
vspltisw 3, 3
vmrghw 4, 0, 1
vmrglw 5, 2, 3
vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
vspltisw 21, 12
vspltisw 23, 7
addis 11, 2, permx@toc@ha
addi 11, 11, permx@toc@l
lxvw4x 32+20, 0, 11
lxvw4x 32+22, 17, 11
sradi 8, 7, 1
mtctr 8
# save constants to vsx
xxlor 16, 48, 48
xxlor 17, 49, 49
xxlor 18, 50, 50
xxlor 19, 51, 51
vspltisw 25, 4
vspltisw 26, 8
xxlor 25, 32+26, 32+26
xxlor 24, 32+25, 32+25
vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
xxlor 30, 32+30, 32+30
xxlor 31, 32+31, 32+31
xxlor 20, 32+20, 32+20
xxlor 21, 32+21, 32+21
xxlor 22, 32+22, 32+22
xxlor 23, 32+23, 32+23
cmpdi 6, 512
blt Loop_last
Loop_8x:
xxspltw 32+0, 16, 0
xxspltw 32+1, 16, 1
xxspltw 32+2, 16, 2
xxspltw 32+3, 16, 3
xxspltw 32+4, 17, 0
xxspltw 32+5, 17, 1
xxspltw 32+6, 17, 2
xxspltw 32+7, 17, 3
xxspltw 32+8, 18, 0
xxspltw 32+9, 18, 1
xxspltw 32+10, 18, 2
xxspltw 32+11, 18, 3
xxspltw 32+12, 19, 0
xxspltw 32+13, 19, 1
xxspltw 32+14, 19, 2
xxspltw 32+15, 19, 3
vadduwm 12, 12, 30 # increase counter
xxspltw 32+16, 16, 0
xxspltw 32+17, 16, 1
xxspltw 32+18, 16, 2
xxspltw 32+19, 16, 3
xxspltw 32+20, 17, 0
xxspltw 32+21, 17, 1
xxspltw 32+22, 17, 2
xxspltw 32+23, 17, 3
xxspltw 32+24, 18, 0
xxspltw 32+25, 18, 1
xxspltw 32+26, 18, 2
xxspltw 32+27, 18, 3
xxspltw 32+28, 19, 0
xxspltw 32+29, 19, 1
vadduwm 28, 28, 31 # increase counter
xxspltw 32+30, 19, 2
xxspltw 32+31, 19, 3
.align 5
quarter_loop_8x:
QT_loop_8x
bdnz quarter_loop_8x
xxlor 0, 32+30, 32+30
xxlor 32+30, 30, 30
vadduwm 12, 12, 30
xxlor 32+30, 0, 0
TP_4x 0, 1, 2, 3
TP_4x 4, 5, 6, 7
TP_4x 8, 9, 10, 11
TP_4x 12, 13, 14, 15
xxlor 0, 48, 48
xxlor 1, 49, 49
xxlor 2, 50, 50
xxlor 3, 51, 51
xxlor 48, 16, 16
xxlor 49, 17, 17
xxlor 50, 18, 18
xxlor 51, 19, 19
Add_state 0
xxlor 48, 0, 0
xxlor 49, 1, 1
xxlor 50, 2, 2
xxlor 51, 3, 3
Write_256 0
addi 14, 14, 256 # offset +=256
addi 15, 15, -256 # len -=256
xxlor 5, 32+31, 32+31
xxlor 32+31, 31, 31
vadduwm 28, 28, 31
xxlor 32+31, 5, 5
TP_4x 16+0, 16+1, 16+2, 16+3
TP_4x 16+4, 16+5, 16+6, 16+7
TP_4x 16+8, 16+9, 16+10, 16+11
TP_4x 16+12, 16+13, 16+14, 16+15
xxlor 32, 16, 16
xxlor 33, 17, 17
xxlor 34, 18, 18
xxlor 35, 19, 19
Add_state 16
Write_256 16
addi 14, 14, 256 # offset +=256
addi 15, 15, -256 # len +=256
xxlor 32+24, 24, 24
xxlor 32+25, 25, 25
xxlor 32+30, 30, 30
vadduwm 30, 30, 25
vadduwm 31, 30, 24
xxlor 30, 32+30, 32+30
xxlor 31, 32+31, 32+31
cmpdi 15, 0
beq Out_loop
cmpdi 15, 512
blt Loop_last
mtctr 8
b Loop_8x
Loop_last:
lxvw4x 48, 0, 3 # vr16, constants
lxvw4x 49, 17, 3 # vr17, key 1
lxvw4x 50, 18, 3 # vr18, key 2
lxvw4x 51, 19, 3 # vr19, counter, nonce
vspltisw 21, 12
vspltisw 23, 7
addis 11, 2, permx@toc@ha
addi 11, 11, permx@toc@l
lxvw4x 32+20, 0, 11
lxvw4x 32+22, 17, 11
sradi 8, 7, 1
mtctr 8
Loop_4x:
vspltw 0, 16, 0
vspltw 1, 16, 1
vspltw 2, 16, 2
vspltw 3, 16, 3
vspltw 4, 17, 0
vspltw 5, 17, 1
vspltw 6, 17, 2
vspltw 7, 17, 3
vspltw 8, 18, 0
vspltw 9, 18, 1
vspltw 10, 18, 2
vspltw 11, 18, 3
vspltw 12, 19, 0
vadduwm 12, 12, 30 # increase counter
vspltw 13, 19, 1
vspltw 14, 19, 2
vspltw 15, 19, 3
.align 5
quarter_loop:
QT_loop_4x
bdnz quarter_loop
vadduwm 12, 12, 30
TP_4x 0, 1, 2, 3
TP_4x 4, 5, 6, 7
TP_4x 8, 9, 10, 11
TP_4x 12, 13, 14, 15
Add_state 0
Write_256 0
addi 14, 14, 256 # offset += 256
addi 15, 15, -256 # len += 256
# Update state counter
vspltisw 25, 4
vadduwm 30, 30, 25
cmpdi 15, 0
beq Out_loop
cmpdi 15, 256
blt Out_loop
mtctr 8
b Loop_4x
Out_loop:
RESTORE_REGS
blr
Out_no_chacha:
li 3, 0
blr
SYM_FUNC_END(chacha_p10le_8x)
SYM_DATA_START_LOCAL(PERMX)
.align 5
permx:
.long 0x22330011, 0x66774455, 0xaabb8899, 0xeeffccdd
.long 0x11223300, 0x55667744, 0x99aabb88, 0xddeeffcc
SYM_DATA_END(PERMX)
arch/powerpc/crypto/poly1305-p10-glue.c
+186
View File
@@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Poly1305 authenticator algorithm, RFC7539.
*
* Copyright 2023- IBM Corp. All rights reserved.
*/
#include <crypto/algapi.h>
#include <linux/crypto.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/jump_label.h>
#include <crypto/internal/hash.h>
#include <crypto/internal/poly1305.h>
#include <crypto/internal/simd.h>
#include <linux/cpufeature.h>
#include <asm/unaligned.h>
#include <asm/simd.h>
#include <asm/switch_to.h>
asmlinkage void poly1305_p10le_4blocks(void *h, const u8 *m, u32 mlen);
asmlinkage void poly1305_64s(void *h, const u8 *m, u32 mlen, int highbit);
asmlinkage void poly1305_emit_64(void *h, void *s, u8 *dst);
static void vsx_begin(void)
{
preempt_disable();
enable_kernel_vsx();
}
static void vsx_end(void)
{
disable_kernel_vsx();
preempt_enable();
}
static int crypto_poly1305_p10_init(struct shash_desc *desc)
{
struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
poly1305_core_init(&dctx->h);
dctx->buflen = 0;
dctx->rset = 0;
dctx->sset = false;
return 0;
}
static unsigned int crypto_poly1305_setdctxkey(struct poly1305_desc_ctx *dctx,
const u8 *inp, unsigned int len)
{
unsigned int acc = 0;
if (unlikely(!dctx->sset)) {
if (!dctx->rset && len >= POLY1305_BLOCK_SIZE) {
struct poly1305_core_key *key = &dctx->core_r;
key->key.r64[0] = get_unaligned_le64(&inp[0]);
key->key.r64[1] = get_unaligned_le64(&inp[8]);
inp += POLY1305_BLOCK_SIZE;
len -= POLY1305_BLOCK_SIZE;
acc += POLY1305_BLOCK_SIZE;
dctx->rset = 1;
}
if (len >= POLY1305_BLOCK_SIZE) {
dctx->s[0] = get_unaligned_le32(&inp[0]);
dctx->s[1] = get_unaligned_le32(&inp[4]);
dctx->s[2] = get_unaligned_le32(&inp[8]);
dctx->s[3] = get_unaligned_le32(&inp[12]);
acc += POLY1305_BLOCK_SIZE;
dctx->sset = true;
}
}
return acc;
}
static int crypto_poly1305_p10_update(struct shash_desc *desc,
const u8 *src, unsigned int srclen)
{
struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
unsigned int bytes, used;
if (unlikely(dctx->buflen)) {
bytes = min(srclen, POLY1305_BLOCK_SIZE - dctx->buflen);
memcpy(dctx->buf + dctx->buflen, src, bytes);
src += bytes;
srclen -= bytes;
dctx->buflen += bytes;
if (dctx->buflen == POLY1305_BLOCK_SIZE) {
if (likely(!crypto_poly1305_setdctxkey(dctx, dctx->buf,
POLY1305_BLOCK_SIZE))) {
vsx_begin();
poly1305_64s(&dctx->h, dctx->buf,
POLY1305_BLOCK_SIZE, 1);
vsx_end();
}
dctx->buflen = 0;
}
}
if (likely(srclen >= POLY1305_BLOCK_SIZE)) {
bytes = round_down(srclen, POLY1305_BLOCK_SIZE);
used = crypto_poly1305_setdctxkey(dctx, src, bytes);
if (likely(used)) {
srclen -= used;
src += used;
}
if (crypto_simd_usable() && (srclen >= POLY1305_BLOCK_SIZE*4)) {
vsx_begin();
poly1305_p10le_4blocks(&dctx->h, src, srclen);
vsx_end();
src += srclen - (srclen % (POLY1305_BLOCK_SIZE * 4));
srclen %= POLY1305_BLOCK_SIZE * 4;
}
while (srclen >= POLY1305_BLOCK_SIZE) {
vsx_begin();
poly1305_64s(&dctx->h, src, POLY1305_BLOCK_SIZE, 1);
vsx_end();
srclen -= POLY1305_BLOCK_SIZE;
src += POLY1305_BLOCK_SIZE;
}
}
if (unlikely(srclen)) {
dctx->buflen = srclen;
memcpy(dctx->buf, src, srclen);
}
return 0;
}
static int crypto_poly1305_p10_final(struct shash_desc *desc, u8 *dst)
{
struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
if (unlikely(!dctx->sset))
return -ENOKEY;
if ((dctx->buflen)) {
dctx->buf[dctx->buflen++] = 1;
memset(dctx->buf + dctx->buflen, 0,
POLY1305_BLOCK_SIZE - dctx->buflen);
vsx_begin();
poly1305_64s(&dctx->h, dctx->buf, POLY1305_BLOCK_SIZE, 0);
vsx_end();
dctx->buflen = 0;
}
poly1305_emit_64(&dctx->h, &dctx->s, dst);
return 0;
}
static struct shash_alg poly1305_alg = {
.digestsize = POLY1305_DIGEST_SIZE,
.init = crypto_poly1305_p10_init,
.update = crypto_poly1305_p10_update,
.final = crypto_poly1305_p10_final,
.descsize = sizeof(struct poly1305_desc_ctx),
.base = {
.cra_name = "poly1305",
.cra_driver_name = "poly1305-p10",
.cra_priority = 300,
.cra_blocksize = POLY1305_BLOCK_SIZE,
.cra_module = THIS_MODULE,
},
};
static int __init poly1305_p10_init(void)
{
return crypto_register_shash(&poly1305_alg);
}
static void __exit poly1305_p10_exit(void)
{
crypto_unregister_shash(&poly1305_alg);
}
module_cpu_feature_match(PPC_MODULE_FEATURE_P10, poly1305_p10_init);
module_exit(poly1305_p10_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Danny Tsen <dtsen@linux.ibm.com>");
MODULE_DESCRIPTION("Optimized Poly1305 for P10");
MODULE_ALIAS_CRYPTO("poly1305");
MODULE_ALIAS_CRYPTO("poly1305-p10");
arch/powerpc/crypto/poly1305-p10le_64.S
+1075
View File
File diff suppressed because it is too large Load Diff
arch/x86/crypto/aesni-intel_glue.c
+9 -13
View File
@@ -229,10 +229,9 @@ static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
return (struct crypto_aes_ctx *)ALIGN(addr, align);
}
static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
static int aes_set_key_common(struct crypto_aes_ctx *ctx,
const u8 *in_key, unsigned int key_len)
{
struct crypto_aes_ctx *ctx = aes_ctx(raw_ctx);
int err;
if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
@@ -253,7 +252,8 @@ static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
unsigned int key_len)
{
return aes_set_key_common(tfm, crypto_tfm_ctx(tfm), in_key, key_len);
return aes_set_key_common(aes_ctx(crypto_tfm_ctx(tfm)), in_key,
key_len);
}
static void aesni_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
@@ -285,8 +285,7 @@ static void aesni_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
static int aesni_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key,
unsigned int len)
{
return aes_set_key_common(crypto_skcipher_tfm(tfm),
crypto_skcipher_ctx(tfm), key, len);
return aes_set_key_common(aes_ctx(crypto_skcipher_ctx(tfm)), key, len);
}
static int ecb_encrypt(struct skcipher_request *req)
@@ -627,8 +626,7 @@ static int common_rfc4106_set_key(struct crypto_aead *aead, const u8 *key,
memcpy(ctx->nonce, key + key_len, sizeof(ctx->nonce));
return aes_set_key_common(crypto_aead_tfm(aead),
&ctx->aes_key_expanded, key, key_len) ?:
return aes_set_key_common(&ctx->aes_key_expanded, key, key_len) ?:
rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
}
@@ -893,14 +891,13 @@ static int xts_aesni_setkey(struct crypto_skcipher *tfm, const u8 *key,
keylen /= 2;
/* first half of xts-key is for crypt */
err = aes_set_key_common(crypto_skcipher_tfm(tfm), ctx->raw_crypt_ctx,
key, keylen);
err = aes_set_key_common(aes_ctx(ctx->raw_crypt_ctx), key, keylen);
if (err)
return err;
/* second half of xts-key is for tweak */
return aes_set_key_common(crypto_skcipher_tfm(tfm), ctx->raw_tweak_ctx,
key + keylen, keylen);
return aes_set_key_common(aes_ctx(ctx->raw_tweak_ctx), key + keylen,
keylen);
}
static int xts_crypt(struct skcipher_request *req, bool encrypt)
@@ -1150,8 +1147,7 @@ static int generic_gcmaes_set_key(struct crypto_aead *aead, const u8 *key,
{
struct generic_gcmaes_ctx *ctx = generic_gcmaes_ctx_get(aead);
return aes_set_key_common(crypto_aead_tfm(aead),
&ctx->aes_key_expanded, key, key_len) ?:
return aes_set_key_common(&ctx->aes_key_expanded, key, key_len) ?:
rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
}
crypto/af_alg.c
+4
View File
@@ -320,18 +320,21 @@ static int alg_setkey_by_key_serial(struct alg_sock *ask, sockptr_t optval,
if (IS_ERR(ret)) {
up_read(&key->sem);
key_put(key);
return PTR_ERR(ret);
}
key_data = sock_kmalloc(&ask->sk, key_datalen, GFP_KERNEL);
if (!key_data) {
up_read(&key->sem);
key_put(key);
return -ENOMEM;
}
memcpy(key_data, ret, key_datalen);
up_read(&key->sem);
key_put(key);
err = type->setkey(ask->private, key_data, key_datalen);
@@ -1192,6 +1195,7 @@ struct af_alg_async_req *af_alg_alloc_areq(struct sock *sk,
areq->areqlen = areqlen;
areq->sk = sk;
areq->first_rsgl.sgl.sgt.sgl = areq->first_rsgl.sgl.sgl;
areq->last_rsgl = NULL;
INIT_LIST_HEAD(&areq->rsgl_list);
areq->tsgl = NULL;
crypto/algapi.c
+14 -2
View File
@@ -17,6 +17,7 @@
#include <linux/rtnetlink.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/workqueue.h>
#include "internal.h"
@@ -74,15 +75,26 @@ static void crypto_free_instance(struct crypto_instance *inst)
inst->alg.cra_type->free(inst);
}
static void crypto_destroy_instance(struct crypto_alg *alg)
static void crypto_destroy_instance_workfn(struct work_struct *w)
{
struct crypto_instance *inst = (void *)alg;
struct crypto_instance *inst = container_of(w, struct crypto_instance,
free_work);
struct crypto_template *tmpl = inst->tmpl;
crypto_free_instance(inst);
crypto_tmpl_put(tmpl);
}
static void crypto_destroy_instance(struct crypto_alg *alg)
{
struct crypto_instance *inst = container_of(alg,
struct crypto_instance,
alg);
INIT_WORK(&inst->free_work, crypto_destroy_instance_workfn);
schedule_work(&inst->free_work);
}
/*
* This function adds a spawn to the list secondary_spawns which
* will be used at the end of crypto_remove_spawns to unregister
crypto/asymmetric_keys/public_key.c
+4 -4
View File
@@ -42,7 +42,7 @@ static void public_key_describe(const struct key *asymmetric_key,
void public_key_free(struct public_key *key)
{
if (key) {
kfree(key->key);
kfree_sensitive(key->key);
kfree(key->params);
kfree(key);
}
@@ -263,7 +263,7 @@ error_free_tfm:
else
crypto_free_akcipher(tfm);
error_free_key:
kfree(key);
kfree_sensitive(key);
pr_devel("<==%s() = %d\n", __func__, ret);
return ret;
}
@@ -369,7 +369,7 @@ error_free_tfm:
else
crypto_free_akcipher(tfm);
error_free_key:
kfree(key);
kfree_sensitive(key);
pr_devel("<==%s() = %d\n", __func__, ret);
return ret;
}
@@ -441,7 +441,7 @@ int public_key_verify_signature(const struct public_key *pkey,
sig->digest, sig->digest_size);
error_free_key:
kfree(key);
kfree_sensitive(key);
error_free_tfm:
crypto_free_sig(tfm);
pr_devel("<==%s() = %d\n", __func__, ret);
crypto/asymmetric_keys/verify_pefile.c
+1 -1
View File
@@ -391,7 +391,7 @@ error_no_desc:
* verify_pefile_signature - Verify the signature on a PE binary image
* @pebuf: Buffer containing the PE binary image
* @pelen: Length of the binary image
* @trust_keys: Signing certificate(s) to use as starting points
* @trusted_keys: Signing certificate(s) to use as starting points
* @usage: The use to which the key is being put.
*
* Validate that the certificate chain inside the PKCS#7 message inside the PE
crypto/asymmetric_keys/x509_public_key.c
+5
View File
@@ -130,6 +130,11 @@ int x509_check_for_self_signed(struct x509_certificate *cert)
goto out;
}
if (cert->unsupported_sig) {
ret = 0;
goto out;
}
ret = public_key_verify_signature(cert->pub, cert->sig);
if (ret < 0) {
if (ret == -ENOPKG) {
crypto/crypto_engine.c
+197 -47
View File
@@ -7,15 +7,30 @@
* Author: Baolin Wang <baolin.wang@linaro.org>
*/
#include <crypto/internal/aead.h>
#include <crypto/internal/akcipher.h>
#include <crypto/internal/engine.h>
#include <crypto/internal/hash.h>
#include <crypto/internal/kpp.h>
#include <crypto/internal/skcipher.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <crypto/engine.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <uapi/linux/sched/types.h>
#include "internal.h"
#define CRYPTO_ENGINE_MAX_QLEN 10
/* Temporary algorithm flag used to indicate an updated driver. */
#define CRYPTO_ALG_ENGINE 0x200
struct crypto_engine_alg {
struct crypto_alg base;
struct crypto_engine_op op;
};
/**
* crypto_finalize_request - finalize one request if the request is done
* @engine: the hardware engine
@@ -26,9 +41,6 @@ static void crypto_finalize_request(struct crypto_engine *engine,
struct crypto_async_request *req, int err)
{
unsigned long flags;
bool finalize_req = false;
int ret;
struct crypto_engine_ctx *enginectx;
/*
* If hardware cannot enqueue more requests
@@ -38,21 +50,11 @@ static void crypto_finalize_request(struct crypto_engine *engine,
if (!engine->retry_support) {
spin_lock_irqsave(&engine->queue_lock, flags);
if (engine->cur_req == req) {
finalize_req = true;
engine->cur_req = NULL;
}
spin_unlock_irqrestore(&engine->queue_lock, flags);
}
if (finalize_req || engine->retry_support) {
enginectx = crypto_tfm_ctx(req->tfm);
if (enginectx->op.prepare_request &&
enginectx->op.unprepare_request) {
ret = enginectx->op.unprepare_request(engine, req);
if (ret)
dev_err(engine->dev, "failed to unprepare request\n");
}
}
lockdep_assert_in_softirq();
crypto_request_complete(req, err);
@@ -72,10 +74,11 @@ static void crypto_pump_requests(struct crypto_engine *engine,
bool in_kthread)
{
struct crypto_async_request *async_req, *backlog;
struct crypto_engine_alg *alg;
struct crypto_engine_op *op;
unsigned long flags;
bool was_busy = false;
int ret;
struct crypto_engine_ctx *enginectx;
spin_lock_irqsave(&engine->queue_lock, flags);
@@ -141,27 +144,21 @@ start_request:
ret = engine->prepare_crypt_hardware(engine);
if (ret) {
dev_err(engine->dev, "failed to prepare crypt hardware\n");
goto req_err_2;
goto req_err_1;
}
}
enginectx = crypto_tfm_ctx(async_req->tfm);
if (enginectx->op.prepare_request) {
ret = enginectx->op.prepare_request(engine, async_req);
if (ret) {
dev_err(engine->dev, "failed to prepare request: %d\n",
ret);
goto req_err_2;
}
}
if (!enginectx->op.do_one_request) {
if (async_req->tfm->__crt_alg->cra_flags & CRYPTO_ALG_ENGINE) {
alg = container_of(async_req->tfm->__crt_alg,
struct crypto_engine_alg, base);
op = &alg->op;
} else {
dev_err(engine->dev, "failed to do request\n");
ret = -EINVAL;
goto req_err_1;
}
ret = enginectx->op.do_one_request(engine, async_req);
ret = op->do_one_request(engine, async_req);
/* Request unsuccessfully executed by hardware */
if (ret < 0) {
@@ -177,18 +174,6 @@ start_request:
ret);
goto req_err_1;
}
/*
* If retry mechanism is supported,
* unprepare current request and
* enqueue it back into crypto-engine queue.
*/
if (enginectx->op.unprepare_request) {
ret = enginectx->op.unprepare_request(engine,
async_req);
if (ret)
dev_err(engine->dev,
"failed to unprepare request\n");
}
spin_lock_irqsave(&engine->queue_lock, flags);
/*
* If hardware was unable to execute request, enqueue it
@@ -204,13 +189,6 @@ start_request:
goto retry;
req_err_1:
if (enginectx->op.unprepare_request) {
ret = enginectx->op.unprepare_request(engine, async_req);
if (ret)
dev_err(engine->dev, "failed to unprepare request\n");
}
req_err_2:
crypto_request_complete(async_req, ret);
retry:
@@ -591,5 +569,177 @@ int crypto_engine_exit(struct crypto_engine *engine)
}
EXPORT_SYMBOL_GPL(crypto_engine_exit);
int crypto_engine_register_aead(struct aead_engine_alg *alg)
{
if (!alg->op.do_one_request)
return -EINVAL;
alg->base.base.cra_flags |= CRYPTO_ALG_ENGINE;
return crypto_register_aead(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_register_aead);
void crypto_engine_unregister_aead(struct aead_engine_alg *alg)
{
crypto_unregister_aead(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_aead);
int crypto_engine_register_aeads(struct aead_engine_alg *algs, int count)
{
int i, ret;
for (i = 0; i < count; i++) {
ret = crypto_engine_register_aead(&algs[i]);
if (ret)
goto err;
}
return 0;
err:
crypto_engine_unregister_aeads(algs, i);
return ret;
}
EXPORT_SYMBOL_GPL(crypto_engine_register_aeads);
void crypto_engine_unregister_aeads(struct aead_engine_alg *algs, int count)
{
int i;
for (i = count - 1; i >= 0; --i)
crypto_engine_unregister_aead(&algs[i]);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_aeads);
int crypto_engine_register_ahash(struct ahash_engine_alg *alg)
{
if (!alg->op.do_one_request)
return -EINVAL;
alg->base.halg.base.cra_flags |= CRYPTO_ALG_ENGINE;
return crypto_register_ahash(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_register_ahash);
void crypto_engine_unregister_ahash(struct ahash_engine_alg *alg)
{
crypto_unregister_ahash(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_ahash);
int crypto_engine_register_ahashes(struct ahash_engine_alg *algs, int count)
{
int i, ret;
for (i = 0; i < count; i++) {
ret = crypto_engine_register_ahash(&algs[i]);
if (ret)
goto err;
}
return 0;
err:
crypto_engine_unregister_ahashes(algs, i);
return ret;
}
EXPORT_SYMBOL_GPL(crypto_engine_register_ahashes);
void crypto_engine_unregister_ahashes(struct ahash_engine_alg *algs,
int count)
{
int i;
for (i = count - 1; i >= 0; --i)
crypto_engine_unregister_ahash(&algs[i]);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_ahashes);
int crypto_engine_register_akcipher(struct akcipher_engine_alg *alg)
{
if (!alg->op.do_one_request)
return -EINVAL;
alg->base.base.cra_flags |= CRYPTO_ALG_ENGINE;
return crypto_register_akcipher(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_register_akcipher);
void crypto_engine_unregister_akcipher(struct akcipher_engine_alg *alg)
{
crypto_unregister_akcipher(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_akcipher);
int crypto_engine_register_kpp(struct kpp_engine_alg *alg)
{
if (!alg->op.do_one_request)
return -EINVAL;
alg->base.base.cra_flags |= CRYPTO_ALG_ENGINE;
return crypto_register_kpp(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_register_kpp);
void crypto_engine_unregister_kpp(struct kpp_engine_alg *alg)
{
crypto_unregister_kpp(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_kpp);
int crypto_engine_register_skcipher(struct skcipher_engine_alg *alg)
{
if (!alg->op.do_one_request)
return -EINVAL;
alg->base.base.cra_flags |= CRYPTO_ALG_ENGINE;
return crypto_register_skcipher(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_register_skcipher);
void crypto_engine_unregister_skcipher(struct skcipher_engine_alg *alg)
{
return crypto_unregister_skcipher(&alg->base);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_skcipher);
int crypto_engine_register_skciphers(struct skcipher_engine_alg *algs,
int count)
{
int i, ret;
for (i = 0; i < count; i++) {
ret = crypto_engine_register_skcipher(&algs[i]);
if (ret)
goto err;
}
return 0;
err:
crypto_engine_unregister_skciphers(algs, i);
return ret;
}
EXPORT_SYMBOL_GPL(crypto_engine_register_skciphers);
void crypto_engine_unregister_skciphers(struct skcipher_engine_alg *algs,
int count)
{
int i;
for (i = count - 1; i >= 0; --i)
crypto_engine_unregister_skcipher(&algs[i]);
}
EXPORT_SYMBOL_GPL(crypto_engine_unregister_skciphers);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Crypto hardware engine framework");
crypto/jitterentropy.c
+7 -3
View File
@@ -89,10 +89,14 @@ struct rand_data {
unsigned int rct_count; /* Number of stuck values */
/* Intermittent health test failure threshold of 2^-30 */
#define JENT_RCT_CUTOFF 30 /* Taken from SP800-90B sec 4.4.1 */
#define JENT_APT_CUTOFF 325 /* Taken from SP800-90B sec 4.4.2 */
/* From an SP800-90B perspective, this RCT cutoff value is equal to 31. */
/* However, our RCT implementation starts at 1, so we subtract 1 here. */
#define JENT_RCT_CUTOFF (31 - 1) /* Taken from SP800-90B sec 4.4.1 */
#define JENT_APT_CUTOFF 325 /* Taken from SP800-90B sec 4.4.2 */
/* Permanent health test failure threshold of 2^-60 */
#define JENT_RCT_CUTOFF_PERMANENT 60
/* From an SP800-90B perspective, this RCT cutoff value is equal to 61. */
/* However, our RCT implementation starts at 1, so we subtract 1 here. */
#define JENT_RCT_CUTOFF_PERMANENT (61 - 1)
#define JENT_APT_CUTOFF_PERMANENT 355
#define JENT_APT_WINDOW_SIZE 512 /* Data window size */
/* LSB of time stamp to process */
crypto/lrw.c
+3 -3
View File
@@ -357,10 +357,10 @@ static int lrw_create(struct crypto_template *tmpl, struct rtattr **tb)
* cipher name.
*/
if (!strncmp(cipher_name, "ecb(", 4)) {
unsigned len;
int len;
len = strlcpy(ecb_name, cipher_name + 4, sizeof(ecb_name));
if (len < 2 || len >= sizeof(ecb_name))
len = strscpy(ecb_name, cipher_name + 4, sizeof(ecb_name));
if (len < 2)
goto err_free_inst;
if (ecb_name[len - 1] != ')')
crypto/sig.c
-5
View File
@@ -21,11 +21,6 @@
static const struct crypto_type crypto_sig_type;
static inline struct crypto_sig *__crypto_sig_tfm(struct crypto_tfm *tfm)
{
return container_of(tfm, struct crypto_sig, base);
}
static int crypto_sig_init_tfm(struct crypto_tfm *tfm)
{
if (tfm->__crt_alg->cra_type != &crypto_sig_type)
crypto/xts.c
+3 -3
View File
@@ -396,10 +396,10 @@ static int xts_create(struct crypto_template *tmpl, struct rtattr **tb)
* cipher name.
*/
if (!strncmp(cipher_name, "ecb(", 4)) {
unsigned len;
int len;
len = strlcpy(ctx->name, cipher_name + 4, sizeof(ctx->name));
if (len < 2 || len >= sizeof(ctx->name))
len = strscpy(ctx->name, cipher_name + 4, sizeof(ctx->name));
if (len < 2)
goto err_free_inst;
if (ctx->name[len - 1] != ')')
drivers/auxdisplay/hd44780_common.c
+9 -1
View File
@@ -82,7 +82,15 @@ int hd44780_common_clear_display(struct charlcd *lcd)
hdc->write_cmd(hdc, LCD_CMD_DISPLAY_CLEAR);
/* datasheet says to wait 1,64 milliseconds */
long_sleep(2);
return 0;
/*
* The Hitachi HD44780 controller (and compatible ones) reset the DDRAM
* address when executing the DISPLAY_CLEAR command, thus the
* following call is not required. However, other controllers do not
* (e.g. NewHaven NHD-0220DZW-AG5), thus move the cursor to home
* unconditionally to support both.
*/
return hd44780_common_home(lcd);
}
EXPORT_SYMBOL_GPL(hd44780_common_clear_display);
drivers/base/regmap/Kconfig
+11 -1
View File
@@ -4,7 +4,7 @@
# subsystems should select the appropriate symbols.
config REGMAP
bool "Register Map support" if KUNIT_ALL_TESTS
bool
default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SOUNDWIRE_MBQ || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM || REGMAP_MDIO || REGMAP_FSI)
select IRQ_DOMAIN if REGMAP_IRQ
select MDIO_BUS if REGMAP_MDIO
@@ -23,6 +23,16 @@ config REGMAP_KUNIT
default KUNIT_ALL_TESTS
select REGMAP_RAM
config REGMAP_BUILD
bool "Enable regmap build"
depends on KUNIT
select REGMAP
help
This option exists purely to allow the regmap KUnit tests to
be enabled without having to enable some driver that uses
regmap due to unfortunate issues with how KUnit tests are
normally enabled.
config REGMAP_AC97
tristate
drivers/base/regmap/regcache-maple.c
+8 -8
View File
@@ -74,7 +74,7 @@ static int regcache_maple_write(struct regmap *map, unsigned int reg,
rcu_read_unlock();
entry = kmalloc((last - index + 1) * sizeof(unsigned long),
GFP_KERNEL);
map->alloc_flags);
if (!entry)
return -ENOMEM;
@@ -92,7 +92,7 @@ static int regcache_maple_write(struct regmap *map, unsigned int reg,
mas_lock(&mas);
mas_set_range(&mas, index, last);
ret = mas_store_gfp(&mas, entry, GFP_KERNEL);
ret = mas_store_gfp(&mas, entry, map->alloc_flags);
mas_unlock(&mas);
@@ -134,7 +134,7 @@ static int regcache_maple_drop(struct regmap *map, unsigned int min,
lower = kmemdup(entry, ((min - mas.index) *
sizeof(unsigned long)),
GFP_KERNEL);
map->alloc_flags);
if (!lower) {
ret = -ENOMEM;
goto out_unlocked;
@@ -148,7 +148,7 @@ static int regcache_maple_drop(struct regmap *map, unsigned int min,
upper = kmemdup(&entry[max + 1],
((mas.last - max) *
sizeof(unsigned long)),
GFP_KERNEL);
map->alloc_flags);
if (!upper) {
ret = -ENOMEM;
goto out_unlocked;
@@ -162,7 +162,7 @@ static int regcache_maple_drop(struct regmap *map, unsigned int min,
/* Insert new nodes with the saved data */
if (lower) {
mas_set_range(&mas, lower_index, lower_last);
ret = mas_store_gfp(&mas, lower, GFP_KERNEL);
ret = mas_store_gfp(&mas, lower, map->alloc_flags);
if (ret != 0)
goto out;
lower = NULL;
@@ -170,7 +170,7 @@ static int regcache_maple_drop(struct regmap *map, unsigned int min,
if (upper) {
mas_set_range(&mas, upper_index, upper_last);
ret = mas_store_gfp(&mas, upper, GFP_KERNEL);
ret = mas_store_gfp(&mas, upper, map->alloc_flags);
if (ret != 0)
goto out;
upper = NULL;
@@ -320,7 +320,7 @@ static int regcache_maple_insert_block(struct regmap *map, int first,
unsigned long *entry;
int i, ret;
entry = kcalloc(last - first + 1, sizeof(unsigned long), GFP_KERNEL);
entry = kcalloc(last - first + 1, sizeof(unsigned long), map->alloc_flags);
if (!entry)
return -ENOMEM;
@@ -331,7 +331,7 @@ static int regcache_maple_insert_block(struct regmap *map, int first,
mas_set_range(&mas, map->reg_defaults[first].reg,
map->reg_defaults[last].reg);
ret = mas_store_gfp(&mas, entry, GFP_KERNEL);
ret = mas_store_gfp(&mas, entry, map->alloc_flags);
mas_unlock(&mas);
drivers/base/regmap/regcache-rbtree.c
+6 -6
View File
@@ -22,7 +22,7 @@ struct regcache_rbtree_node {
/* block of adjacent registers */
void *block;
/* Which registers are present */
long *cache_present;
unsigned long *cache_present;
/* base register handled by this block */
unsigned int base_reg;
/* number of registers available in the block */
@@ -277,7 +277,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map,
blk = krealloc(rbnode->block,
blklen * map->cache_word_size,
GFP_KERNEL);
map->alloc_flags);
if (!blk)
return -ENOMEM;
@@ -286,7 +286,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map,
if (BITS_TO_LONGS(blklen) > BITS_TO_LONGS(rbnode->blklen)) {
present = krealloc(rbnode->cache_present,
BITS_TO_LONGS(blklen) * sizeof(*present),
GFP_KERNEL);
map->alloc_flags);
if (!present)
return -ENOMEM;
@@ -320,7 +320,7 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg)
const struct regmap_range *range;
int i;
rbnode = kzalloc(sizeof(*rbnode), GFP_KERNEL);
rbnode = kzalloc(sizeof(*rbnode), map->alloc_flags);
if (!rbnode)
return NULL;
@@ -346,13 +346,13 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg)
}
rbnode->block = kmalloc_array(rbnode->blklen, map->cache_word_size,
GFP_KERNEL);
map->alloc_flags);
if (!rbnode->block)
goto err_free;
rbnode->cache_present = kcalloc(BITS_TO_LONGS(rbnode->blklen),
sizeof(*rbnode->cache_present),
GFP_KERNEL);
map->alloc_flags);
if (!rbnode->cache_present)
goto err_free_block;
drivers/base/regmap/regcache.c
+23 -15
View File
@@ -558,6 +558,29 @@ void regcache_cache_bypass(struct regmap *map, bool enable)
}
EXPORT_SYMBOL_GPL(regcache_cache_bypass);
/**
* regcache_reg_cached - Check if a register is cached
*
* @map: map to check
* @reg: register to check
*
* Reports if a register is cached.
*/
bool regcache_reg_cached(struct regmap *map, unsigned int reg)
{
unsigned int val;
int ret;
map->lock(map->lock_arg);
ret = regcache_read(map, reg, &val);
map->unlock(map->lock_arg);
return ret == 0;
}
EXPORT_SYMBOL_GPL(regcache_reg_cached);
void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
unsigned int val)
{
@@ -587,14 +610,6 @@ void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
cache[idx] = val;
break;
}
#ifdef CONFIG_64BIT
case 8: {
u64 *cache = base;
cache[idx] = val;
break;
}
#endif
default:
BUG();
}
@@ -627,13 +642,6 @@ unsigned int regcache_get_val(struct regmap *map, const void *base,
return cache[idx];
}
#ifdef CONFIG_64BIT
case 8: {
const u64 *cache = base;
return cache[idx];
}
#endif
default:
BUG();
}
drivers/base/regmap/regmap-kunit.c
+40
View File
@@ -836,6 +836,45 @@ static void cache_drop(struct kunit *test)
regmap_exit(map);
}
static void cache_present(struct kunit *test)
{
struct regcache_types *t = (struct regcache_types *)test->param_value;
struct regmap *map;
struct regmap_config config;
struct regmap_ram_data *data;
unsigned int val;
int i;
config = test_regmap_config;
config.cache_type = t->type;
map = gen_regmap(&config, &data);
KUNIT_ASSERT_FALSE(test, IS_ERR(map));
if (IS_ERR(map))
return;
for (i = 0; i < BLOCK_TEST_SIZE; i++)
data->read[i] = false;
/* No defaults so no registers cached. */
for (i = 0; i < BLOCK_TEST_SIZE; i++)
KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, i));
/* We didn't trigger any reads */
for (i = 0; i < BLOCK_TEST_SIZE; i++)
KUNIT_ASSERT_FALSE(test, data->read[i]);
/* Fill the cache */
for (i = 0; i < BLOCK_TEST_SIZE; i++)
KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &val));
/* Now everything should be cached */
for (i = 0; i < BLOCK_TEST_SIZE; i++)
KUNIT_ASSERT_TRUE(test, regcache_reg_cached(map, i));
regmap_exit(map);
}
struct raw_test_types {
const char *name;
@@ -1177,6 +1216,7 @@ static struct kunit_case regmap_test_cases[] = {
KUNIT_CASE_PARAM(cache_sync_readonly, real_cache_types_gen_params),
KUNIT_CASE_PARAM(cache_sync_patch, real_cache_types_gen_params),
KUNIT_CASE_PARAM(cache_drop, sparse_cache_types_gen_params),
KUNIT_CASE_PARAM(cache_present, sparse_cache_types_gen_params),
KUNIT_CASE_PARAM(raw_read_defaults_single, raw_test_types_gen_params),
KUNIT_CASE_PARAM(raw_read_defaults, raw_test_types_gen_params),
drivers/base/regmap/regmap-mmio.c
-24
View File
@@ -202,15 +202,6 @@ static int regmap_mmio_noinc_write(void *context, unsigned int reg,
writel(swab32(valp[i]), ctx->regs + reg);
goto out_clk;
}
#ifdef CONFIG_64BIT
case 8:
{
const u64 *valp = (const u64 *)val;
for (i = 0; i < val_count; i++)
writeq(swab64(valp[i]), ctx->regs + reg);
goto out_clk;
}
#endif
default:
ret = -EINVAL;
goto out_clk;
@@ -227,11 +218,6 @@ static int regmap_mmio_noinc_write(void *context, unsigned int reg,
case 4:
writesl(ctx->regs + reg, (const u32 *)val, val_count);
break;
#ifdef CONFIG_64BIT
case 8:
writesq(ctx->regs + reg, (const u64 *)val, val_count);
break;
#endif
default:
ret = -EINVAL;
break;
@@ -363,11 +349,6 @@ static int regmap_mmio_noinc_read(void *context, unsigned int reg,
case 4:
readsl(ctx->regs + reg, (u32 *)val, val_count);
break;
#ifdef CONFIG_64BIT
case 8:
readsq(ctx->regs + reg, (u64 *)val, val_count);
break;
#endif
default:
ret = -EINVAL;
goto out_clk;
@@ -387,11 +368,6 @@ static int regmap_mmio_noinc_read(void *context, unsigned int reg,
case 4:
swab32_array(val, val_count);
break;
#ifdef CONFIG_64BIT
case 8:
swab64_array(val, val_count);
break;
#endif
default:
ret = -EINVAL;
break;
drivers/base/regmap/regmap.c
-122
View File
@@ -311,26 +311,6 @@ static void regmap_format_32_native(void *buf, unsigned int val,
memcpy(buf, &v, sizeof(v));
}
#ifdef CONFIG_64BIT
static void regmap_format_64_be(void *buf, unsigned int val, unsigned int shift)
{
put_unaligned_be64((u64) val << shift, buf);
}
static void regmap_format_64_le(void *buf, unsigned int val, unsigned int shift)
{
put_unaligned_le64((u64) val << shift, buf);
}
static void regmap_format_64_native(void *buf, unsigned int val,
unsigned int shift)
{
u64 v = (u64) val << shift;
memcpy(buf, &v, sizeof(v));
}
#endif
static void regmap_parse_inplace_noop(void *buf)
{
}
@@ -411,40 +391,6 @@ static unsigned int regmap_parse_32_native(const void *buf)
return v;
}
#ifdef CONFIG_64BIT
static unsigned int regmap_parse_64_be(const void *buf)
{
return get_unaligned_be64(buf);
}
static unsigned int regmap_parse_64_le(const void *buf)
{
return get_unaligned_le64(buf);
}
static void regmap_parse_64_be_inplace(void *buf)
{
u64 v = get_unaligned_be64(buf);
memcpy(buf, &v, sizeof(v));
}
static void regmap_parse_64_le_inplace(void *buf)
{
u64 v = get_unaligned_le64(buf);
memcpy(buf, &v, sizeof(v));
}
static unsigned int regmap_parse_64_native(const void *buf)
{
u64 v;
memcpy(&v, buf, sizeof(v));
return v;
}
#endif
static void regmap_lock_hwlock(void *__map)
{
struct regmap *map = __map;
@@ -1005,24 +951,6 @@ struct regmap *__regmap_init(struct device *dev,
}
break;
#ifdef CONFIG_64BIT
case 64:
switch (reg_endian) {
case REGMAP_ENDIAN_BIG:
map->format.format_reg = regmap_format_64_be;
break;
case REGMAP_ENDIAN_LITTLE:
map->format.format_reg = regmap_format_64_le;
break;
case REGMAP_ENDIAN_NATIVE:
map->format.format_reg = regmap_format_64_native;
break;
default:
goto err_hwlock;
}
break;
#endif
default:
goto err_hwlock;
}
@@ -1086,28 +1014,6 @@ struct regmap *__regmap_init(struct device *dev,
goto err_hwlock;
}
break;
#ifdef CONFIG_64BIT
case 64:
switch (val_endian) {
case REGMAP_ENDIAN_BIG:
map->format.format_val = regmap_format_64_be;
map->format.parse_val = regmap_parse_64_be;
map->format.parse_inplace = regmap_parse_64_be_inplace;
break;
case REGMAP_ENDIAN_LITTLE:
map->format.format_val = regmap_format_64_le;
map->format.parse_val = regmap_parse_64_le;
map->format.parse_inplace = regmap_parse_64_le_inplace;
break;
case REGMAP_ENDIAN_NATIVE:
map->format.format_val = regmap_format_64_native;
map->format.parse_val = regmap_parse_64_native;
break;
default:
goto err_hwlock;
}
break;
#endif
}
if (map->format.format_write) {
@@ -2158,9 +2064,6 @@ static int regmap_noinc_readwrite(struct regmap *map, unsigned int reg,
u8 *u8p;
u16 *u16p;
u32 *u32p;
#ifdef CONFIG_64BIT
u64 *u64p;
#endif
int ret;
int i;
@@ -2180,13 +2083,6 @@ static int regmap_noinc_readwrite(struct regmap *map, unsigned int reg,
if (write)
lastval = (unsigned int)u32p[val_count - 1];
break;
#ifdef CONFIG_64BIT
case 8:
u64p = val;
if (write)
lastval = (unsigned int)u64p[val_count - 1];
break;
#endif
default:
return -EINVAL;
}
@@ -2224,11 +2120,6 @@ static int regmap_noinc_readwrite(struct regmap *map, unsigned int reg,
case 4:
pr_cont("%x", u32p[i]);
break;
#ifdef CONFIG_64BIT
case 8:
pr_cont("%llx", u64p[i]);
break;
#endif
default:
break;
}
@@ -2436,11 +2327,6 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
case 4:
ival = *(u32 *)(val + (i * val_bytes));
break;
#ifdef CONFIG_64BIT
case 8:
ival = *(u64 *)(val + (i * val_bytes));
break;
#endif
default:
ret = -EINVAL;
goto out;
@@ -3205,9 +3091,6 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
for (i = 0; i < val_count * val_bytes; i += val_bytes)
map->format.parse_inplace(val + i);
} else {
#ifdef CONFIG_64BIT
u64 *u64 = val;
#endif
u32 *u32 = val;
u16 *u16 = val;
u8 *u8 = val;
@@ -3223,11 +3106,6 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
goto out;
switch (map->format.val_bytes) {
#ifdef CONFIG_64BIT
case 8:
u64[i] = ival;
break;
#endif
case 4:
u32[i] = ival;
break;
drivers/char/hw_random/Kconfig
+19 -18
View File
@@ -37,7 +37,7 @@ config HW_RANDOM_TIMERIOMEM
config HW_RANDOM_INTEL
tristate "Intel HW Random Number Generator support"
depends on (X86 || IA64) && PCI
depends on (X86 || IA64 || COMPILE_TEST) && PCI
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -50,7 +50,8 @@ config HW_RANDOM_INTEL
config HW_RANDOM_AMD
tristate "AMD HW Random Number Generator support"
depends on (X86 || PPC_MAPLE) && PCI
depends on (X86 || PPC_MAPLE || COMPILE_TEST)
depends on PCI && HAS_IOPORT_MAP
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -63,7 +64,7 @@ config HW_RANDOM_AMD
config HW_RANDOM_ATMEL
tristate "Atmel Random Number Generator support"
depends on (ARCH_AT91 || COMPILE_TEST) && HAVE_CLK && OF
depends on (ARCH_AT91 || COMPILE_TEST)
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -113,7 +114,8 @@ config HW_RANDOM_IPROC_RNG200
config HW_RANDOM_GEODE
tristate "AMD Geode HW Random Number Generator support"
depends on X86_32 && PCI
depends on (X86_32 || COMPILE_TEST)
depends on PCI
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -205,7 +207,7 @@ config HW_RANDOM_OCTEON
config HW_RANDOM_PASEMI
tristate "PA Semi HW Random Number Generator support"
depends on PPC_PASEMI
depends on PPC_PASEMI || (PPC && COMPILE_TEST)
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -228,7 +230,7 @@ config HW_RANDOM_VIRTIO
config HW_RANDOM_MXC_RNGA
tristate "Freescale i.MX RNGA Random Number Generator"
depends on SOC_IMX31
depends on SOC_IMX31 || COMPILE_TEST
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -241,7 +243,7 @@ config HW_RANDOM_MXC_RNGA
config HW_RANDOM_IMX_RNGC
tristate "Freescale i.MX RNGC Random Number Generator"
depends on HAS_IOMEM && HAVE_CLK
depends on HAS_IOMEM
depends on SOC_IMX25 || SOC_IMX6SL || SOC_IMX6SLL || SOC_IMX6UL || COMPILE_TEST
default HW_RANDOM
help
@@ -256,8 +258,7 @@ config HW_RANDOM_IMX_RNGC
config HW_RANDOM_INGENIC_RNG
tristate "Ingenic Random Number Generator support"
depends on HW_RANDOM
depends on MACH_JZ4780 || MACH_X1000
depends on MACH_JZ4780 || MACH_X1000 || COMPILE_TEST
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number Generator
@@ -271,8 +272,7 @@ config HW_RANDOM_INGENIC_RNG
config HW_RANDOM_INGENIC_TRNG
tristate "Ingenic True Random Number Generator support"
depends on HW_RANDOM
depends on MACH_X1830
depends on MACH_X1830 || COMPILE_TEST
default HW_RANDOM
help
This driver provides kernel-side support for the True Random Number Generator
@@ -324,7 +324,7 @@ config HW_RANDOM_POWERNV
config HW_RANDOM_HISI
tristate "Hisilicon Random Number Generator support"
depends on HW_RANDOM && ARCH_HISI
depends on ARCH_HISI || COMPILE_TEST
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -348,7 +348,7 @@ config HW_RANDOM_HISTB
config HW_RANDOM_ST
tristate "ST Microelectronics HW Random Number Generator support"
depends on HW_RANDOM && (ARCH_STI || COMPILE_TEST)
depends on ARCH_STI || COMPILE_TEST
help
This driver provides kernel-side support for the Random Number
Generator hardware found on STi series of SoCs.
@@ -358,7 +358,7 @@ config HW_RANDOM_ST
config HW_RANDOM_XGENE
tristate "APM X-Gene True Random Number Generator (TRNG) support"
depends on HW_RANDOM && ARCH_XGENE
depends on ARCH_XGENE || COMPILE_TEST
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
@@ -371,7 +371,7 @@ config HW_RANDOM_XGENE
config HW_RANDOM_STM32
tristate "STMicroelectronics STM32 random number generator"
depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST)
depends on ARCH_STM32 || COMPILE_TEST
depends on HAS_IOMEM
default HW_RANDOM
help
@@ -385,8 +385,8 @@ config HW_RANDOM_STM32
config HW_RANDOM_PIC32
tristate "Microchip PIC32 Random Number Generator support"
depends on HW_RANDOM && MACH_PIC32
default y
depends on MACH_PIC32 || COMPILE_TEST
default HW_RANDOM if MACH_PIC32
help
This driver provides kernel-side support for the Random Number
Generator hardware found on a PIC32.
@@ -425,7 +425,8 @@ config HW_RANDOM_MESON
config HW_RANDOM_CAVIUM
tristate "Cavium ThunderX Random Number Generator support"
depends on HW_RANDOM && PCI && ARCH_THUNDER
depends on PCI
depends on ARCH_THUNDER || (ARM64 && COMPILE_TEST)
default HW_RANDOM
help
This driver provides kernel-side support for the Random Number
drivers/char/hw_random/amd-rng.c
+1
View File
@@ -26,6 +26,7 @@
#include <linux/delay.h>
#include <linux/hw_random.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
drivers/char/hw_random/arm_smccc_trng.c
-2
View File
@@ -105,8 +105,6 @@ static int smccc_trng_probe(struct platform_device *pdev)
trng->name = "smccc_trng";
trng->read = smccc_trng_read;
platform_set_drvdata(pdev, trng);
return devm_hwrng_register(&pdev->dev, trng);
}
drivers/char/hw_random/atmel-rng.c
+1 -1
View File
@@ -15,7 +15,7 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/hw_random.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
drivers/char/hw_random/ba431-rng.c
+3 -7
View File
@@ -189,13 +189,9 @@ static int ba431_trng_probe(struct platform_device *pdev)
ba431->rng.cleanup = ba431_trng_cleanup;
ba431->rng.read = ba431_trng_read;
platform_set_drvdata(pdev, ba431);
ret = devm_hwrng_register(&pdev->dev, &ba431->rng);
if (ret) {
dev_err(&pdev->dev, "BA431 registration failed (%d)\n", ret);
return ret;
}
if (ret)
return dev_err_probe(&pdev->dev, ret, "BA431 registration failed\n");
dev_info(&pdev->dev, "BA431 TRNG registered\n");
@@ -203,7 +199,7 @@ static int ba431_trng_probe(struct platform_device *pdev)
}
static const struct of_device_id ba431_trng_dt_ids[] = {
{ .compatible = "silex-insight,ba431-rng", .data = NULL },
{ .compatible = "silex-insight,ba431-rng" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ba431_trng_dt_ids);
drivers/char/hw_random/bcm2835-rng.c
+1 -2
View File
@@ -8,8 +8,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
#include <linux/clk.h>
drivers/char/hw_random/cctrng.c
+19 -74
View File
@@ -455,35 +455,6 @@ static void cc_trng_startwork_handler(struct work_struct *w)
cc_trng_hw_trigger(drvdata);
}
static int cc_trng_clk_init(struct cctrng_drvdata *drvdata)
{
struct clk *clk;
struct device *dev = &(drvdata->pdev->dev);
int rc = 0;
clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk),
"Error getting clock\n");
drvdata->clk = clk;
rc = clk_prepare_enable(drvdata->clk);
if (rc) {
dev_err(dev, "Failed to enable clock\n");
return rc;
}
return 0;
}
static void cc_trng_clk_fini(struct cctrng_drvdata *drvdata)
{
clk_disable_unprepare(drvdata->clk);
}
static int cctrng_probe(struct platform_device *pdev)
{
struct cctrng_drvdata *drvdata;
@@ -492,6 +463,10 @@ static int cctrng_probe(struct platform_device *pdev)
u32 val;
int irq;
/* Compile time assertion checks */
BUILD_BUG_ON(CCTRNG_DATA_BUF_WORDS < 6);
BUILD_BUG_ON((CCTRNG_DATA_BUF_WORDS & (CCTRNG_DATA_BUF_WORDS-1)) != 0);
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
@@ -510,10 +485,8 @@ static int cctrng_probe(struct platform_device *pdev)
drvdata->circ.buf = (char *)drvdata->data_buf;
drvdata->cc_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(drvdata->cc_base)) {
dev_err(dev, "Failed to ioremap registers");
return PTR_ERR(drvdata->cc_base);
}
if (IS_ERR(drvdata->cc_base))
return dev_err_probe(dev, PTR_ERR(drvdata->cc_base), "Failed to ioremap registers");
/* Then IRQ */
irq = platform_get_irq(pdev, 0);
@@ -522,16 +495,13 @@ static int cctrng_probe(struct platform_device *pdev)
/* parse sampling rate from device tree */
rc = cc_trng_parse_sampling_ratio(drvdata);
if (rc) {
dev_err(dev, "Failed to get legal sampling ratio for rosc\n");
return rc;
}
if (rc)
return dev_err_probe(dev, rc, "Failed to get legal sampling ratio for rosc\n");
rc = cc_trng_clk_init(drvdata);
if (rc) {
dev_err(dev, "cc_trng_clk_init failed\n");
return rc;
}
drvdata->clk = devm_clk_get_optional_enabled(dev, NULL);
if (IS_ERR(drvdata->clk))
return dev_err_probe(dev, PTR_ERR(drvdata->clk),
"Failed to get or enable the clock\n");
INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler);
INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler);
@@ -539,10 +509,8 @@ static int cctrng_probe(struct platform_device *pdev)
/* register the driver isr function */
rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata);
if (rc) {
dev_err(dev, "Could not register to interrupt %d\n", irq);
goto post_clk_err;
}
if (rc)
return dev_err_probe(dev, rc, "Could not register to interrupt %d\n", irq);
dev_dbg(dev, "Registered to IRQ: %d\n", irq);
/* Clear all pending interrupts */
@@ -557,17 +525,13 @@ static int cctrng_probe(struct platform_device *pdev)
/* init PM */
rc = cc_trng_pm_init(drvdata);
if (rc) {
dev_err(dev, "cc_trng_pm_init failed\n");
goto post_clk_err;
}
if (rc)
return dev_err_probe(dev, rc, "cc_trng_pm_init failed\n");
/* increment device's usage counter */
rc = cc_trng_pm_get(dev);
if (rc) {
dev_err(dev, "cc_trng_pm_get returned %x\n", rc);
goto post_pm_err;
}
if (rc)
return dev_err_probe(dev, rc, "cc_trng_pm_get returned %x\n", rc);
/* set pending_hw to verify that HW won't be triggered from read */
atomic_set(&drvdata->pending_hw, 1);
@@ -593,9 +557,6 @@ static int cctrng_probe(struct platform_device *pdev)
post_pm_err:
cc_trng_pm_fini(drvdata);
post_clk_err:
cc_trng_clk_fini(drvdata);
return rc;
}
@@ -608,8 +569,6 @@ static int cctrng_remove(struct platform_device *pdev)
cc_trng_pm_fini(drvdata);
cc_trng_clk_fini(drvdata);
dev_info(dev, "ARM cctrng device terminated\n");
return 0;
@@ -698,21 +657,7 @@ static struct platform_driver cctrng_driver = {
.remove = cctrng_remove,
};
static int __init cctrng_mod_init(void)
{
/* Compile time assertion checks */
BUILD_BUG_ON(CCTRNG_DATA_BUF_WORDS < 6);
BUILD_BUG_ON((CCTRNG_DATA_BUF_WORDS & (CCTRNG_DATA_BUF_WORDS-1)) != 0);
return platform_driver_register(&cctrng_driver);
}
module_init(cctrng_mod_init);
static void __exit cctrng_mod_exit(void)
{
platform_driver_unregister(&cctrng_driver);
}
module_exit(cctrng_mod_exit);
module_platform_driver(cctrng_driver);
/* Module description */
MODULE_DESCRIPTION("ARM CryptoCell TRNG Driver");
drivers/char/hw_random/cn10k-rng.c
+4 -14
View File
@@ -187,10 +187,8 @@ static int cn10k_rng_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_drvdata(pdev, rng);
rng->reg_base = pcim_iomap(pdev, 0, 0);
if (!rng->reg_base) {
dev_err(&pdev->dev, "Error while mapping CSRs, exiting\n");
return -ENOMEM;
}
if (!rng->reg_base)
return dev_err_probe(&pdev->dev, -ENOMEM, "Error while mapping CSRs, exiting\n");
rng->ops.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"cn10k-rng-%s", dev_name(&pdev->dev));
@@ -205,19 +203,12 @@ static int cn10k_rng_probe(struct pci_dev *pdev, const struct pci_device_id *id)
reset_rng_health_state(rng);
err = devm_hwrng_register(&pdev->dev, &rng->ops);
if (err) {
dev_err(&pdev->dev, "Could not register hwrng device.\n");
return err;
}
if (err)
return dev_err_probe(&pdev->dev, err, "Could not register hwrng device.\n");
return 0;
}
static void cn10k_rng_remove(struct pci_dev *pdev)
{
/* Nothing to do */
}
static const struct pci_device_id cn10k_rng_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA098) }, /* RNG PF */
{0,},
@@ -229,7 +220,6 @@ static struct pci_driver cn10k_rng_driver = {
.name = "cn10k_rng",
.id_table = cn10k_rng_id_table,
.probe = cn10k_rng_probe,
.remove = cn10k_rng_remove,
};
module_pci_driver(cn10k_rng_driver);
drivers/char/hw_random/core.c
+1 -2
View File
@@ -15,14 +15,13 @@
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/hw_random.h>
#include <linux/random.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/sched/signal.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/random.h>
#include <linux/sched.h>
#include <linux/sched/signal.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
drivers/char/hw_random/exynos-trng.c
+4 -4
View File
@@ -185,14 +185,14 @@ static int exynos_trng_remove(struct platform_device *pdev)
return 0;
}
static int __maybe_unused exynos_trng_suspend(struct device *dev)
static int exynos_trng_suspend(struct device *dev)
{
pm_runtime_put_sync(dev);
return 0;
}
static int __maybe_unused exynos_trng_resume(struct device *dev)
static int exynos_trng_resume(struct device *dev)
{
int ret;
@@ -205,7 +205,7 @@ static int __maybe_unused exynos_trng_resume(struct device *dev)
return 0;
}
static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
static DEFINE_SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
exynos_trng_resume);
static const struct of_device_id exynos_trng_dt_match[] = {
@@ -219,7 +219,7 @@ MODULE_DEVICE_TABLE(of, exynos_trng_dt_match);
static struct platform_driver exynos_trng_driver = {
.driver = {
.name = "exynos-trng",
.pm = &exynos_trng_pm_ops,
.pm = pm_sleep_ptr(&exynos_trng_pm_ops),
.of_match_table = exynos_trng_dt_match,
},
.probe = exynos_trng_probe,
drivers/char/hw_random/imx-rngc.c
+8 -16
View File
@@ -239,10 +239,8 @@ static int __init imx_rngc_probe(struct platform_device *pdev)
return PTR_ERR(rngc->base);
rngc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(rngc->clk)) {
dev_err(&pdev->dev, "Can not get rng_clk\n");
return PTR_ERR(rngc->clk);
}
if (IS_ERR(rngc->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(rngc->clk), "Cannot get rng_clk\n");
irq = platform_get_irq(pdev, 0);
if (irq < 0)
@@ -272,24 +270,18 @@ static int __init imx_rngc_probe(struct platform_device *pdev)
ret = devm_request_irq(&pdev->dev,
irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
if (ret) {
dev_err(rngc->dev, "Can't get interrupt working.\n");
return ret;
}
if (ret)
return dev_err_probe(&pdev->dev, ret, "Can't get interrupt working.\n");
if (self_test) {
ret = imx_rngc_self_test(rngc);
if (ret) {
dev_err(rngc->dev, "self test failed\n");
return ret;
}
if (ret)
return dev_err_probe(&pdev->dev, ret, "self test failed\n");
}
ret = devm_hwrng_register(&pdev->dev, &rngc->rng);
if (ret) {
dev_err(&pdev->dev, "hwrng registration failed\n");
return ret;
}
if (ret)
return dev_err_probe(&pdev->dev, ret, "hwrng registration failed\n");
dev_info(&pdev->dev,
"Freescale RNG%c registered (HW revision %d.%02d)\n",
drivers/char/hw_random/ingenic-rng.c
+1 -1
View File
@@ -95,7 +95,7 @@ static int ingenic_rng_probe(struct platform_device *pdev)
return PTR_ERR(priv->base);
}
priv->version = (enum ingenic_rng_version)of_device_get_match_data(&pdev->dev);
priv->version = (enum ingenic_rng_version)(uintptr_t)of_device_get_match_data(&pdev->dev);
priv->rng.name = pdev->name;
priv->rng.init = ingenic_rng_init;
drivers/char/hw_random/ingenic-trng.c
+12 -47
View File
@@ -11,8 +11,8 @@
#include <linux/hw_random.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -22,8 +22,6 @@
#define TRNG_REG_STATUS_OFFSET 0x08
/* bits within the CFG register */
#define CFG_RDY_CLR BIT(12)
#define CFG_INT_MASK BIT(11)
#define CFG_GEN_EN BIT(0)
/* bits within the STATUS register */
@@ -31,7 +29,6 @@
struct ingenic_trng {
void __iomem *base;
struct clk *clk;
struct hwrng rng;
};
@@ -79,6 +76,7 @@ static int ingenic_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait
static int ingenic_trng_probe(struct platform_device *pdev)
{
struct ingenic_trng *trng;
struct clk *clk;
int ret;
trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
@@ -86,60 +84,28 @@ static int ingenic_trng_probe(struct platform_device *pdev)
return -ENOMEM;
trng->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(trng->base)) {
pr_err("%s: Failed to map DTRNG registers\n", __func__);
ret = PTR_ERR(trng->base);
return PTR_ERR(trng->base);
}
if (IS_ERR(trng->base))
return dev_err_probe(&pdev->dev, PTR_ERR(trng->base),
"%s: Failed to map DTRNG registers\n", __func__);
trng->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(trng->clk)) {
ret = PTR_ERR(trng->clk);
pr_crit("%s: Cannot get DTRNG clock\n", __func__);
return PTR_ERR(trng->clk);
}
ret = clk_prepare_enable(trng->clk);
if (ret) {
pr_crit("%s: Unable to enable DTRNG clock\n", __func__);
return ret;
}
clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(&pdev->dev, PTR_ERR(clk),
"%s: Cannot get and enable DTRNG clock\n", __func__);
trng->rng.name = pdev->name;
trng->rng.init = ingenic_trng_init;
trng->rng.cleanup = ingenic_trng_cleanup;
trng->rng.read = ingenic_trng_read;
ret = hwrng_register(&trng->rng);
if (ret) {
dev_err(&pdev->dev, "Failed to register hwrng\n");
goto err_unprepare_clk;
}
ret = devm_hwrng_register(&pdev->dev, &trng->rng);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Failed to register hwrng\n");
platform_set_drvdata(pdev, trng);
dev_info(&pdev->dev, "Ingenic DTRNG driver registered\n");
return 0;
err_unprepare_clk:
clk_disable_unprepare(trng->clk);
return ret;
}
static int ingenic_trng_remove(struct platform_device *pdev)
{
struct ingenic_trng *trng = platform_get_drvdata(pdev);
unsigned int ctrl;
hwrng_unregister(&trng->rng);
ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET);
ctrl &= ~CFG_GEN_EN;
writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
clk_disable_unprepare(trng->clk);
return 0;
}
static const struct of_device_id ingenic_trng_of_match[] = {
@@ -150,7 +116,6 @@ MODULE_DEVICE_TABLE(of, ingenic_trng_of_match);
static struct platform_driver ingenic_trng_driver = {
.probe = ingenic_trng_probe,
.remove = ingenic_trng_remove,
.driver = {
.name = "ingenic-trng",
.of_match_table = ingenic_trng_of_match,
drivers/char/hw_random/iproc-rng200.c
+26 -2
View File
@@ -12,8 +12,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
@@ -182,6 +181,8 @@ static int iproc_rng200_probe(struct platform_device *pdev)
return PTR_ERR(priv->base);
}
dev_set_drvdata(dev, priv);
priv->rng.name = "iproc-rng200";
priv->rng.read = iproc_rng200_read;
priv->rng.init = iproc_rng200_init;
@@ -199,6 +200,28 @@ static int iproc_rng200_probe(struct platform_device *pdev)
return 0;
}
static int __maybe_unused iproc_rng200_suspend(struct device *dev)
{
struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
iproc_rng200_cleanup(&priv->rng);
return 0;
}
static int __maybe_unused iproc_rng200_resume(struct device *dev)
{
struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
iproc_rng200_init(&priv->rng);
return 0;
}
static const struct dev_pm_ops iproc_rng200_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(iproc_rng200_suspend, iproc_rng200_resume)
};
static const struct of_device_id iproc_rng200_of_match[] = {
{ .compatible = "brcm,bcm2711-rng200", },
{ .compatible = "brcm,bcm7211-rng200", },
@@ -212,6 +235,7 @@ static struct platform_driver iproc_rng200_driver = {
.driver = {
.name = "iproc-rng200",
.of_match_table = iproc_rng200_of_match,
.pm = &iproc_rng200_pm_ops,
},
.probe = iproc_rng200_probe,
};
drivers/char/hw_random/nomadik-rng.c
+5 -14
View File
@@ -13,8 +13,6 @@
#include <linux/clk.h>
#include <linux/err.h>
static struct clk *rng_clk;
static int nmk_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
{
void __iomem *base = (void __iomem *)rng->priv;
@@ -36,21 +34,17 @@ static struct hwrng nmk_rng = {
static int nmk_rng_probe(struct amba_device *dev, const struct amba_id *id)
{
struct clk *rng_clk;
void __iomem *base;
int ret;
rng_clk = devm_clk_get(&dev->dev, NULL);
if (IS_ERR(rng_clk)) {
dev_err(&dev->dev, "could not get rng clock\n");
ret = PTR_ERR(rng_clk);
return ret;
}
clk_prepare_enable(rng_clk);
rng_clk = devm_clk_get_enabled(&dev->dev, NULL);
if (IS_ERR(rng_clk))
return dev_err_probe(&dev->dev, PTR_ERR(rng_clk), "could not get rng clock\n");
ret = amba_request_regions(dev, dev->dev.init_name);
if (ret)
goto out_clk;
return ret;
ret = -ENOMEM;
base = devm_ioremap(&dev->dev, dev->res.start,
resource_size(&dev->res));
@@ -64,15 +58,12 @@ static int nmk_rng_probe(struct amba_device *dev, const struct amba_id *id)
out_release:
amba_release_regions(dev);
out_clk:
clk_disable_unprepare(rng_clk);
return ret;
}
static void nmk_rng_remove(struct amba_device *dev)
{
amba_release_regions(dev);
clk_disable_unprepare(rng_clk);
}
static const struct amba_id nmk_rng_ids[] = {

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