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BACKPORT: FROMLIST: KVM: arm64: smmu-v3: Setup command queue

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Map the command queue allocated by the host into the hypervisor address
space. When the host mappings are finalized, the queue is unmapped from
the host.

Link: https://lore.kernel.org/all/20241212180423.1578358-28-smostafa@google.com/

Bug: 357781595
Bug: 384432312

Change-Id: I191e9d99c02943f594c03bfaba69b1da3405a674
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
This commit is contained in:
Jean-Philippe Brucker
2024-12-12 18:03:51 +00:00
committed by Mostafa Saleh
parent b414161ca3
commit bd15feb317
2 changed files with 169 additions and 0 deletions
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arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c
+165
View File
@@ -41,6 +41,15 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
__ret; \
})
#define smmu_wait_event(_smmu, _cond) \
({ \
if ((_smmu)->features & ARM_SMMU_FEAT_SEV) { \
while (!(_cond)) \
wfe(); \
} \
smmu_wait(_cond); \
})
static int smmu_write_cr0(struct hyp_arm_smmu_v3_device *smmu, u32 val)
{
writel_relaxed(val, smmu->base + ARM_SMMU_CR0);
@@ -60,6 +69,123 @@ static void smmu_reclaim_pages(u64 phys, size_t size)
WARN_ON(__pkvm_hyp_donate_host(phys >> PAGE_SHIFT, size >> PAGE_SHIFT));
}
#define Q_WRAP(smmu, reg) ((reg) & (1 << (smmu)->cmdq_log2size))
#define Q_IDX(smmu, reg) ((reg) & ((1 << (smmu)->cmdq_log2size) - 1))
static bool smmu_cmdq_full(struct hyp_arm_smmu_v3_device *smmu)
{
u64 cons = readl_relaxed(smmu->base + ARM_SMMU_CMDQ_CONS);
return Q_IDX(smmu, smmu->cmdq_prod) == Q_IDX(smmu, cons) &&
Q_WRAP(smmu, smmu->cmdq_prod) != Q_WRAP(smmu, cons);
}
static bool smmu_cmdq_empty(struct hyp_arm_smmu_v3_device *smmu)
{
u64 cons = readl_relaxed(smmu->base + ARM_SMMU_CMDQ_CONS);
return Q_IDX(smmu, smmu->cmdq_prod) == Q_IDX(smmu, cons) &&
Q_WRAP(smmu, smmu->cmdq_prod) == Q_WRAP(smmu, cons);
}
static int smmu_add_cmd(struct hyp_arm_smmu_v3_device *smmu,
struct arm_smmu_cmdq_ent *ent)
{
int i;
int ret;
u64 cmd[CMDQ_ENT_DWORDS] = {};
int idx = Q_IDX(smmu, smmu->cmdq_prod);
u64 *slot = smmu->cmdq_base + idx * CMDQ_ENT_DWORDS;
if (smmu->iommu.power_is_off)
return -EPIPE;
ret = smmu_wait_event(smmu, !smmu_cmdq_full(smmu));
if (ret)
return ret;
cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);
switch (ent->opcode) {
case CMDQ_OP_CFGI_ALL:
cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);
break;
case CMDQ_OP_CFGI_CD:
cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);
fallthrough;
case CMDQ_OP_CFGI_STE:
cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);
break;
case CMDQ_OP_TLBI_NH_VA:
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);
cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
break;
case CMDQ_OP_TLBI_NSNH_ALL:
break;
case CMDQ_OP_TLBI_NH_ASID:
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
fallthrough;
case CMDQ_OP_TLBI_S12_VMALL:
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
break;
case CMDQ_OP_TLBI_S2_IPA:
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);
cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);
cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);
cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
break;
case CMDQ_OP_CMD_SYNC:
cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV);
break;
default:
return -EINVAL;
}
for (i = 0; i < CMDQ_ENT_DWORDS; i++)
slot[i] = cpu_to_le64(cmd[i]);
smmu->cmdq_prod++;
writel(Q_IDX(smmu, smmu->cmdq_prod) | Q_WRAP(smmu, smmu->cmdq_prod),
smmu->base + ARM_SMMU_CMDQ_PROD);
return 0;
}
static int smmu_sync_cmd(struct hyp_arm_smmu_v3_device *smmu)
{
int ret;
struct arm_smmu_cmdq_ent cmd = {
.opcode = CMDQ_OP_CMD_SYNC,
};
ret = smmu_add_cmd(smmu, &cmd);
if (ret)
return ret;
return smmu_wait_event(smmu, smmu_cmdq_empty(smmu));
}
__maybe_unused
static int smmu_send_cmd(struct hyp_arm_smmu_v3_device *smmu,
struct arm_smmu_cmdq_ent *cmd)
{
int ret = smmu_add_cmd(smmu, cmd);
if (ret)
return ret;
return smmu_sync_cmd(smmu);
}
static int smmu_init_registers(struct hyp_arm_smmu_v3_device *smmu)
{
u64 val, old;
@@ -94,6 +220,41 @@ static int smmu_init_registers(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
{
u64 cmdq_base;
size_t cmdq_nr_entries, cmdq_size;
int ret;
enum kvm_pgtable_prot prot = PAGE_HYP;
cmdq_base = readq_relaxed(smmu->base + ARM_SMMU_CMDQ_BASE);
if (cmdq_base & ~(Q_BASE_RWA | Q_BASE_ADDR_MASK | Q_BASE_LOG2SIZE))
return -EINVAL;
smmu->cmdq_log2size = cmdq_base & Q_BASE_LOG2SIZE;
cmdq_nr_entries = 1 << smmu->cmdq_log2size;
cmdq_size = cmdq_nr_entries * CMDQ_ENT_DWORDS * 8;
cmdq_base &= Q_BASE_ADDR_MASK;
if (!(smmu->features & ARM_SMMU_FEAT_COHERENCY))
prot |= KVM_PGTABLE_PROT_NORMAL_NC;
ret = ___pkvm_host_donate_hyp_prot(cmdq_base >> PAGE_SHIFT,
PAGE_ALIGN(cmdq_size) >> PAGE_SHIFT,
false, prot);
if (ret)
return ret;
smmu->cmdq_base = hyp_phys_to_virt(cmdq_base);
memset(smmu->cmdq_base, 0, cmdq_size);
writel_relaxed(0, smmu->base + ARM_SMMU_CMDQ_PROD);
writel_relaxed(0, smmu->base + ARM_SMMU_CMDQ_CONS);
return 0;
}
static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
{
int ret;
@@ -113,6 +274,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
if (ret)
return ret;
ret = smmu_init_cmdq(smmu);
if (ret)
return ret;
return kvm_iommu_init_device(&smmu->iommu);
}
include/kvm/arm_smmu_v3.h
+4
View File
@@ -16,8 +16,12 @@ struct hyp_arm_smmu_v3_device {
struct kvm_hyp_iommu iommu;
phys_addr_t mmio_addr;
size_t mmio_size;
unsigned long features;
void __iomem *base;
u32 cmdq_prod;
u64 *cmdq_base;
size_t cmdq_log2size;
};
extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);