BACKPORT: FROMLIST: KVM: arm64: smmu-v3: Initialize registers
Ensure all writable registers are properly initialized. We do not touch registers that will not be read by the SMMU due to disabled features. Link: https://lore.kernel.org/all/20241212180423.1578358-27-smostafa@google.com/ Bug: 357781595 Bug: 384432312 Change-Id: I2f8ed283765c3b9fe577239be96b84164a6a23f1 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Mostafa Saleh <smostafa@google.com>
This commit is contained in:
Jean-Philippe Brucker
committed by
Mostafa Saleh
Mostafa Saleh
parent
c16a84d8e6
commit
b414161ca3
@@ -4,16 +4,144 @@
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*
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* Copyright (C) 2022 Linaro Ltd.
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*/
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#include <asm/arm-smmu-v3-common.h>
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#include <asm/kvm_hyp.h>
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#include <kvm/arm_smmu_v3.h>
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#include <nvhe/iommu.h>
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#include <nvhe/mem_protect.h>
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#include <nvhe/mm.h>
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#include <nvhe/pkvm.h>
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#define ARM_SMMU_POLL_TIMEOUT_US 100000 /* 100ms arbitrary timeout */
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size_t __ro_after_init kvm_hyp_arm_smmu_v3_count;
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struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus;
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#define for_each_smmu(smmu) \
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for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \
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(smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \
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(smmu)++)
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/*
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* Wait until @cond is true.
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* Return 0 on success, or -ETIMEDOUT
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*/
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#define smmu_wait(_cond) \
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({ \
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int __i = 0; \
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int __ret = 0; \
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\
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while (!(_cond)) { \
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if (++__i > ARM_SMMU_POLL_TIMEOUT_US) { \
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__ret = -ETIMEDOUT; \
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break; \
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} \
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pkvm_udelay(1); \
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} \
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__ret; \
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})
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static int smmu_write_cr0(struct hyp_arm_smmu_v3_device *smmu, u32 val)
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{
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writel_relaxed(val, smmu->base + ARM_SMMU_CR0);
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return smmu_wait(readl_relaxed(smmu->base + ARM_SMMU_CR0ACK) == val);
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}
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/* Transfer ownership of structures from host to hyp */
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static int smmu_take_pages(u64 phys, size_t size)
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{
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WARN_ON(!PAGE_ALIGNED(phys) || !PAGE_ALIGNED(size));
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return __pkvm_host_donate_hyp(phys >> PAGE_SHIFT, size >> PAGE_SHIFT);
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}
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static void smmu_reclaim_pages(u64 phys, size_t size)
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{
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WARN_ON(!PAGE_ALIGNED(phys) || !PAGE_ALIGNED(size));
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WARN_ON(__pkvm_hyp_donate_host(phys >> PAGE_SHIFT, size >> PAGE_SHIFT));
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}
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static int smmu_init_registers(struct hyp_arm_smmu_v3_device *smmu)
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{
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u64 val, old;
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int ret;
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if (!(readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_ABORT))
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return -EINVAL;
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/* Initialize all RW registers that will be read by the SMMU */
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ret = smmu_write_cr0(smmu, 0);
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if (ret)
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return ret;
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val = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |
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FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |
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FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |
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FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |
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FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |
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FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);
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writel_relaxed(val, smmu->base + ARM_SMMU_CR1);
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writel_relaxed(CR2_PTM, smmu->base + ARM_SMMU_CR2);
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writel_relaxed(0, smmu->base + ARM_SMMU_IRQ_CTRL);
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val = readl_relaxed(smmu->base + ARM_SMMU_GERROR);
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old = readl_relaxed(smmu->base + ARM_SMMU_GERRORN);
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/* Service Failure Mode is fatal */
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if ((val ^ old) & GERROR_SFM_ERR)
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return -EIO;
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/* Clear pending errors */
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writel_relaxed(val, smmu->base + ARM_SMMU_GERRORN);
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return 0;
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}
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static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu)
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{
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int ret;
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if (!PAGE_ALIGNED(smmu->mmio_addr | smmu->mmio_size))
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return -EINVAL;
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ret = ___pkvm_host_donate_hyp(smmu->mmio_addr >> PAGE_SHIFT,
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smmu->mmio_size >> PAGE_SHIFT,
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/* accept_mmio */ true);
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if (ret)
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return ret;
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smmu->base = hyp_phys_to_virt(smmu->mmio_addr);
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ret = smmu_init_registers(smmu);
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if (ret)
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return ret;
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return kvm_iommu_init_device(&smmu->iommu);
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}
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static int smmu_init(void)
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{
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return -ENOSYS;
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int ret;
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struct hyp_arm_smmu_v3_device *smmu;
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size_t smmu_arr_size = PAGE_ALIGN(sizeof(*kvm_hyp_arm_smmu_v3_smmus) *
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kvm_hyp_arm_smmu_v3_count);
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phys_addr_t smmu_arr_phys;
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kvm_hyp_arm_smmu_v3_smmus = kern_hyp_va(kvm_hyp_arm_smmu_v3_smmus);
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smmu_arr_phys = hyp_virt_to_phys(kvm_hyp_arm_smmu_v3_smmus);
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ret = smmu_take_pages(smmu_arr_phys, smmu_arr_size);
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if (ret)
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return ret;
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for_each_smmu(smmu) {
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ret = smmu_init_device(smmu);
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if (ret)
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goto out_reclaim_smmu;
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}
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return 0;
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out_reclaim_smmu:
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smmu_reclaim_pages(smmu_arr_phys, smmu_arr_size);
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return ret;
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}
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/* Shared with the kernel driver in EL1 */
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@@ -5,8 +5,19 @@
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#include <asm/kvm_asm.h>
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#include <kvm/iommu.h>
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/*
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* Parameters from the trusted host:
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* @mmio_addr base address of the SMMU registers
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* @mmio_size size of the registers resource
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*
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* Other members are filled and used at runtime by the SMMU driver.
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*/
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struct hyp_arm_smmu_v3_device {
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struct kvm_hyp_iommu iommu;
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phys_addr_t mmio_addr;
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size_t mmio_size;
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void __iomem *base;
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};
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extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count);
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