Merge df86f912b4 ("Merge tag 'x86-urgent-2025-09-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip") into android-mainline
Steps on the way to v6.17-rc6 Change-Id: I0cc72f3232400cfb080566d71ae4dd2dd72c7cdf Signed-off-by: Carlos Llamas <cmllamas@google.com>
This commit is contained in:
commit
1cc0dafb17
10 files changed
+45
-34
No files matched your search
@@ -15755,13 +15755,6 @@ S: Supported
|
||||
W: http://www.melexis.com
|
||||
F: drivers/iio/temperature/mlx90635.c
|
||||
|
||||
MELFAS MIP4 TOUCHSCREEN DRIVER
|
||||
M: Sangwon Jee <jeesw@melfas.com>
|
||||
S: Supported
|
||||
W: http://www.melfas.com
|
||||
F: Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt
|
||||
F: drivers/input/touchscreen/melfas_mip4.c
|
||||
|
||||
MELLANOX BLUEFIELD I2C DRIVER
|
||||
M: Khalil Blaiech <kblaiech@nvidia.com>
|
||||
M: Asmaa Mnebhi <asmaa@nvidia.com>
|
||||
|
||||
@@ -175,27 +175,30 @@ static void topoext_fixup(struct topo_scan *tscan)
|
||||
|
||||
static void parse_topology_amd(struct topo_scan *tscan)
|
||||
{
|
||||
bool has_topoext = false;
|
||||
|
||||
/*
|
||||
* If the extended topology leaf 0x8000_001e is available
|
||||
* try to get SMT, CORE, TILE, and DIE shifts from extended
|
||||
* Try to get SMT, CORE, TILE, and DIE shifts from extended
|
||||
* CPUID leaf 0x8000_0026 on supported processors first. If
|
||||
* extended CPUID leaf 0x8000_0026 is not supported, try to
|
||||
* get SMT and CORE shift from leaf 0xb first, then try to
|
||||
* get the CORE shift from leaf 0x8000_0008.
|
||||
* get SMT and CORE shift from leaf 0xb. If either leaf is
|
||||
* available, cpu_parse_topology_ext() will return true.
|
||||
*/
|
||||
if (cpu_feature_enabled(X86_FEATURE_TOPOEXT))
|
||||
has_topoext = cpu_parse_topology_ext(tscan);
|
||||
bool has_xtopology = cpu_parse_topology_ext(tscan);
|
||||
|
||||
if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))
|
||||
tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);
|
||||
|
||||
if (!has_topoext && !parse_8000_0008(tscan))
|
||||
/*
|
||||
* If XTOPOLOGY leaves (0x26/0xb) are not available, try to
|
||||
* get the CORE shift from leaf 0x8000_0008 first.
|
||||
*/
|
||||
if (!has_xtopology && !parse_8000_0008(tscan))
|
||||
return;
|
||||
|
||||
/* Prefer leaf 0x8000001e if available */
|
||||
if (parse_8000_001e(tscan, has_topoext))
|
||||
/*
|
||||
* Prefer leaf 0x8000001e if available to get the SMT shift and
|
||||
* the initial APIC ID if XTOPOLOGY leaves are not available.
|
||||
*/
|
||||
if (parse_8000_001e(tscan, has_xtopology))
|
||||
return;
|
||||
|
||||
/* Try the NODEID MSR */
|
||||
|
||||
@@ -422,6 +422,7 @@ static const struct xpad_device {
|
||||
{ 0x3537, 0x1010, "GameSir G7 SE", 0, XTYPE_XBOXONE },
|
||||
{ 0x366c, 0x0005, "ByoWave Proteus Controller", MAP_SHARE_BUTTON, XTYPE_XBOXONE, FLAG_DELAY_INIT },
|
||||
{ 0x3767, 0x0101, "Fanatec Speedster 3 Forceshock Wheel", 0, XTYPE_XBOX },
|
||||
{ 0x37d7, 0x2501, "Flydigi Apex 5", 0, XTYPE_XBOX360 },
|
||||
{ 0x413d, 0x2104, "Black Shark Green Ghost Gamepad", 0, XTYPE_XBOX360 },
|
||||
{ 0xffff, 0xffff, "Chinese-made Xbox Controller", 0, XTYPE_XBOX },
|
||||
{ 0x0000, 0x0000, "Generic X-Box pad", 0, XTYPE_UNKNOWN }
|
||||
@@ -578,6 +579,7 @@ static const struct usb_device_id xpad_table[] = {
|
||||
XPAD_XBOX360_VENDOR(0x3537), /* GameSir Controllers */
|
||||
XPAD_XBOXONE_VENDOR(0x3537), /* GameSir Controllers */
|
||||
XPAD_XBOXONE_VENDOR(0x366c), /* ByoWave controllers */
|
||||
XPAD_XBOX360_VENDOR(0x37d7), /* Flydigi Controllers */
|
||||
XPAD_XBOX360_VENDOR(0x413d), /* Black Shark Green Ghost Controller */
|
||||
{ }
|
||||
};
|
||||
|
||||
@@ -55,6 +55,7 @@ struct mtk_pmic_regs {
|
||||
const struct mtk_pmic_keys_regs keys_regs[MTK_PMIC_MAX_KEY_COUNT];
|
||||
u32 pmic_rst_reg;
|
||||
u32 rst_lprst_mask; /* Long-press reset timeout bitmask */
|
||||
bool key_release_irq;
|
||||
};
|
||||
|
||||
static const struct mtk_pmic_regs mt6397_regs = {
|
||||
@@ -116,6 +117,7 @@ static const struct mtk_pmic_regs mt6358_regs = {
|
||||
MTK_PMIC_HOMEKEY_RST),
|
||||
.pmic_rst_reg = MT6358_TOP_RST_MISC,
|
||||
.rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
|
||||
.key_release_irq = true,
|
||||
};
|
||||
|
||||
static const struct mtk_pmic_regs mt6359_regs = {
|
||||
@@ -129,6 +131,7 @@ static const struct mtk_pmic_regs mt6359_regs = {
|
||||
MTK_PMIC_HOMEKEY_RST),
|
||||
.pmic_rst_reg = MT6359_TOP_RST_MISC,
|
||||
.rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
|
||||
.key_release_irq = true,
|
||||
};
|
||||
|
||||
struct mtk_pmic_keys_info {
|
||||
@@ -368,7 +371,7 @@ static int mtk_pmic_keys_probe(struct platform_device *pdev)
|
||||
if (keys->keys[index].irq < 0)
|
||||
return keys->keys[index].irq;
|
||||
|
||||
if (of_device_is_compatible(node, "mediatek,mt6358-keys")) {
|
||||
if (mtk_pmic_regs->key_release_irq) {
|
||||
keys->keys[index].irq_r = platform_get_irq_byname(pdev,
|
||||
irqnames_r[index]);
|
||||
|
||||
|
||||
@@ -2427,6 +2427,9 @@ static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
if (!iqs7222->kp_type[chan_index][i])
|
||||
continue;
|
||||
|
||||
if (!dev_desc->event_offset)
|
||||
continue;
|
||||
|
||||
|
||||
@@ -1155,6 +1155,20 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = {
|
||||
.driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS |
|
||||
SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP)
|
||||
},
|
||||
{
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_NAME, "XxHP4NAx"),
|
||||
},
|
||||
.driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS |
|
||||
SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP)
|
||||
},
|
||||
{
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_NAME, "XxKK4NAx_XxSP4NAx"),
|
||||
},
|
||||
.driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS |
|
||||
SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP)
|
||||
},
|
||||
/*
|
||||
* A lot of modern Clevo barebones have touchpad and/or keyboard issues
|
||||
* after suspend fixable with the forcenorestore quirk.
|
||||
|
||||
@@ -625,11 +625,11 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg)
|
||||
*/
|
||||
list_for_each_entry(d, &r->mon_domains, hdr.list) {
|
||||
if (d->ci_id == domid) {
|
||||
rr.ci_id = d->ci_id;
|
||||
cpu = cpumask_any(&d->hdr.cpu_mask);
|
||||
ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
|
||||
if (!ci)
|
||||
continue;
|
||||
rr.ci = ci;
|
||||
mon_event_read(&rr, r, NULL, rdtgrp,
|
||||
&ci->shared_cpu_map, evtid, false);
|
||||
goto checkresult;
|
||||
|
||||
@@ -98,7 +98,7 @@ struct mon_data {
|
||||
* domains in @r sharing L3 @ci.id
|
||||
* @evtid: Which monitor event to read.
|
||||
* @first: Initialize MBM counter when true.
|
||||
* @ci_id: Cacheinfo id for L3. Only set when @d is NULL. Used when summing domains.
|
||||
* @ci: Cacheinfo for L3. Only set when @d is NULL. Used when summing domains.
|
||||
* @err: Error encountered when reading counter.
|
||||
* @val: Returned value of event counter. If @rgrp is a parent resource group,
|
||||
* @val includes the sum of event counts from its child resource groups.
|
||||
@@ -112,7 +112,7 @@ struct rmid_read {
|
||||
struct rdt_mon_domain *d;
|
||||
enum resctrl_event_id evtid;
|
||||
bool first;
|
||||
unsigned int ci_id;
|
||||
struct cacheinfo *ci;
|
||||
int err;
|
||||
u64 val;
|
||||
void *arch_mon_ctx;
|
||||
|
||||
@@ -361,7 +361,6 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
struct rdt_mon_domain *d;
|
||||
struct cacheinfo *ci;
|
||||
struct mbm_state *m;
|
||||
int err, ret;
|
||||
u64 tval = 0;
|
||||
@@ -389,8 +388,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
|
||||
}
|
||||
|
||||
/* Summing domains that share a cache, must be on a CPU for that cache. */
|
||||
ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
|
||||
if (!ci || ci->id != rr->ci_id)
|
||||
if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
@@ -402,7 +400,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
|
||||
*/
|
||||
ret = -EINVAL;
|
||||
list_for_each_entry(d, &rr->r->mon_domains, hdr.list) {
|
||||
if (d->ci_id != rr->ci_id)
|
||||
if (d->ci_id != rr->ci->id)
|
||||
continue;
|
||||
err = resctrl_arch_rmid_read(rr->r, d, closid, rmid,
|
||||
rr->evtid, &tval, rr->arch_mon_ctx);
|
||||
|
||||
@@ -787,10 +787,10 @@ static void retrigger_next_event(void *arg)
|
||||
* of the next expiring timer is enough. The return from the SMP
|
||||
* function call will take care of the reprogramming in case the
|
||||
* CPU was in a NOHZ idle sleep.
|
||||
*
|
||||
* In periodic low resolution mode, the next softirq expiration
|
||||
* must also be updated.
|
||||
*/
|
||||
if (!hrtimer_hres_active(base) && !tick_nohz_active)
|
||||
return;
|
||||
|
||||
raw_spin_lock(&base->lock);
|
||||
hrtimer_update_base(base);
|
||||
if (hrtimer_hres_active(base))
|
||||
@@ -2295,11 +2295,6 @@ int hrtimers_cpu_dying(unsigned int dying_cpu)
|
||||
&new_base->clock_base[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* The migration might have changed the first expiring softirq
|
||||
* timer on this CPU. Update it.
|
||||
*/
|
||||
__hrtimer_get_next_event(new_base, HRTIMER_ACTIVE_SOFT);
|
||||
/* Tell the other CPU to retrigger the next event */
|
||||
smp_call_function_single(ncpu, retrigger_next_event, NULL, 0);
|
||||
|
||||
|
||||
Reference in new issue
Block a user