Merge tag 'x86-urgent-2025-09-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: "Fix a CPU topology parsing bug on AMD guests, and address a lockdep warning in the resctrl filesystem" * tag 'x86-urgent-2025-09-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: fs/resctrl: Eliminate false positive lockdep warning when reading SNC counters x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon
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@@ -175,27 +175,30 @@ static void topoext_fixup(struct topo_scan *tscan)
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static void parse_topology_amd(struct topo_scan *tscan)
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{
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bool has_topoext = false;
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/*
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* If the extended topology leaf 0x8000_001e is available
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* try to get SMT, CORE, TILE, and DIE shifts from extended
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* Try to get SMT, CORE, TILE, and DIE shifts from extended
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* CPUID leaf 0x8000_0026 on supported processors first. If
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* extended CPUID leaf 0x8000_0026 is not supported, try to
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* get SMT and CORE shift from leaf 0xb first, then try to
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* get the CORE shift from leaf 0x8000_0008.
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* get SMT and CORE shift from leaf 0xb. If either leaf is
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* available, cpu_parse_topology_ext() will return true.
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*/
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if (cpu_feature_enabled(X86_FEATURE_TOPOEXT))
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has_topoext = cpu_parse_topology_ext(tscan);
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bool has_xtopology = cpu_parse_topology_ext(tscan);
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if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))
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tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);
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if (!has_topoext && !parse_8000_0008(tscan))
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/*
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* If XTOPOLOGY leaves (0x26/0xb) are not available, try to
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* get the CORE shift from leaf 0x8000_0008 first.
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*/
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if (!has_xtopology && !parse_8000_0008(tscan))
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return;
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/* Prefer leaf 0x8000001e if available */
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if (parse_8000_001e(tscan, has_topoext))
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/*
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* Prefer leaf 0x8000001e if available to get the SMT shift and
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* the initial APIC ID if XTOPOLOGY leaves are not available.
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*/
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if (parse_8000_001e(tscan, has_xtopology))
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return;
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/* Try the NODEID MSR */
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@@ -625,11 +625,11 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg)
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*/
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list_for_each_entry(d, &r->mon_domains, hdr.list) {
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if (d->ci_id == domid) {
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rr.ci_id = d->ci_id;
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cpu = cpumask_any(&d->hdr.cpu_mask);
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ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
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if (!ci)
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continue;
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rr.ci = ci;
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mon_event_read(&rr, r, NULL, rdtgrp,
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&ci->shared_cpu_map, evtid, false);
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goto checkresult;
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@@ -98,7 +98,7 @@ struct mon_data {
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* domains in @r sharing L3 @ci.id
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* @evtid: Which monitor event to read.
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* @first: Initialize MBM counter when true.
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* @ci_id: Cacheinfo id for L3. Only set when @d is NULL. Used when summing domains.
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* @ci: Cacheinfo for L3. Only set when @d is NULL. Used when summing domains.
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* @err: Error encountered when reading counter.
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* @val: Returned value of event counter. If @rgrp is a parent resource group,
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* @val includes the sum of event counts from its child resource groups.
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@@ -112,7 +112,7 @@ struct rmid_read {
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struct rdt_mon_domain *d;
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enum resctrl_event_id evtid;
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bool first;
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unsigned int ci_id;
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struct cacheinfo *ci;
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int err;
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u64 val;
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void *arch_mon_ctx;
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@@ -361,7 +361,6 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
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{
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int cpu = smp_processor_id();
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struct rdt_mon_domain *d;
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struct cacheinfo *ci;
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struct mbm_state *m;
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int err, ret;
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u64 tval = 0;
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@@ -389,8 +388,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
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}
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/* Summing domains that share a cache, must be on a CPU for that cache. */
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ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
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if (!ci || ci->id != rr->ci_id)
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if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map))
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return -EINVAL;
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/*
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@@ -402,7 +400,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr)
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*/
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ret = -EINVAL;
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list_for_each_entry(d, &rr->r->mon_domains, hdr.list) {
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if (d->ci_id != rr->ci_id)
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if (d->ci_id != rr->ci->id)
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continue;
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err = resctrl_arch_rmid_read(rr->r, d, closid, rmid,
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rr->evtid, &tval, rr->arch_mon_ctx);
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