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Merge 82a2a51055 ("Merge tag 'sysctl-6.5-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux") into android-mainline

Browse Source 
Steps on the way to 6.5-rc1

Change-Id: I14b5c605ed8eb83066c2c307820b8acb1cb9de63
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-07-19 18:40:52 +00:00
parent 657450d968 82a2a51055
commit 09d894c76c
3725 changed files with 62870 additions and 13390 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/admin-guide/kernel-parameters.txt
+4 -4
View File
@@ -3720,8 +3720,8 @@
nohibernate [HIBERNATION] Disable hibernation and resume.
nohlt [ARM,ARM64,MICROBLAZE,SH] Forces the kernel to busy wait
in do_idle() and not use the arch_cpu_idle()
nohlt [ARM,ARM64,MICROBLAZE,MIPS,SH] Forces the kernel to
busy wait in do_idle() and not use the arch_cpu_idle()
implementation; requires CONFIG_GENERIC_IDLE_POLL_SETUP
to be effective. This is useful on platforms where the
sleep(SH) or wfi(ARM,ARM64) instructions do not work
@@ -3856,7 +3856,7 @@
nosmp [SMP] Tells an SMP kernel to act as a UP kernel,
and disable the IO APIC. legacy for "maxcpus=0".
nosmt [KNL,S390] Disable symmetric multithreading (SMT).
nosmt [KNL,MIPS,S390] Disable symmetric multithreading (SMT).
Equivalent to smt=1.
[KNL,X86] Disable symmetric multithreading (SMT).
@@ -5774,7 +5774,7 @@
1: Fast pin select (default)
2: ATC IRMode
smt= [KNL,S390] Set the maximum number of threads (logical
smt= [KNL,MIPS,S390] Set the maximum number of threads (logical
CPUs) to use per physical CPU on systems capable of
symmetric multithreading (SMT). Will be capped to the
actual hardware limit.
Documentation/devicetree/bindings/arm/amlogic.yaml
+8 -1
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/arm/amlogic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic MesonX
title: Amlogic SoC based Platforms
maintainers:
- Kevin Hilman <khilman@baylibre.com>
@@ -205,6 +205,13 @@ properties:
- amlogic,ad401
- const: amlogic,a1
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
- amlogic,aw409
- amlogic,aw419
- const: amlogic,c3
- description: Boards with the Amlogic Meson S4 S805X2 SoC
items:
- enum:
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
+5 -5
View File
@@ -122,14 +122,14 @@ properties:
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
arm,vexpress,dcc:
description: When describing tiles consisting of more than one DCC, its
number can be specified with this attribute.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
@@ -180,13 +180,13 @@ patternProperties:
- const: simple-bus
arm,v2m-memory-map:
description: This describes the memory map type.
$ref: '/schemas/types.yaml#/definitions/string'
$ref: /schemas/types.yaml#/definitions/string
enum:
- rs1
- rs2
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
@@ -197,7 +197,7 @@ patternProperties:
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
+8 -6
View File
@@ -25,13 +25,15 @@ properties:
- enum:
- asus,rt-ac56u
- asus,rt-ac68u
- buffalo,wzr-1166dhp
- buffalo,wzr-1166dhp2
- buffalo,wzr-1750dhp
- linksys,ea6300-v1
- linksys,ea6500-v2
- luxul,xap-1510v1
- luxul,xap-1510-v1
- luxul,xwc-1000
- netgear,r6250v1
- netgear,r6300v2
- netgear,r6250-v1
- netgear,r6300-v2
- smartrg,sr400ac
- brcm,bcm94708
- const: brcm,bcm4708
@@ -42,8 +44,8 @@ properties:
- asus,rt-n18u
- buffalo,wzr-600dhp2
- buffalo,wzr-900dhp
- luxul,xap-1410v1
- luxul,xwr-1200v1
- luxul,xap-1410-v1
- luxul,xwr-1200-v1
- tplink,archer-c5-v2
- const: brcm,bcm47081
- const: brcm,bcm4708
@@ -72,7 +74,7 @@ properties:
- luxul,xap-1610-v1
- luxul,xbr-4500-v1
- luxul,xwc-2000-v1
- luxul,xwr-3100v1
- luxul,xwr-3100-v1
- luxul,xwr-3150-v1
- netgear,r8500
- phicomm,k3
Documentation/devicetree/bindings/arm/cpus.yaml
+10 -9
View File
@@ -153,6 +153,7 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-r52
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
@@ -196,7 +197,7 @@ properties:
- qcom,scorpion
enable-method:
$ref: '/schemas/types.yaml#/definitions/string'
$ref: /schemas/types.yaml#/definitions/string
oneOf:
# On ARM v8 64-bit this property is required
- enum:
@@ -245,8 +246,8 @@ properties:
cpu-release-addr:
oneOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- $ref: '/schemas/types.yaml#/definitions/uint64'
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
description:
The DT specification defines this as 64-bit always, but some 32-bit Arm
systems have used a 32-bit value which must be supported.
@@ -254,7 +255,7 @@ properties:
property value of "spin-table".
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
@@ -270,7 +271,7 @@ properties:
cci-control-port: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
@@ -307,7 +308,7 @@ properties:
PM domain provider, must be "psci".
qcom,saw:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the SAW* node associated with this CPU.
@@ -317,7 +318,7 @@ properties:
* arm/msm/qcom,saw2.txt
qcom,acc:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the ACC* node associated with this CPU.
@@ -328,7 +329,7 @@ properties:
* arm/msm/qcom,kpss-acc.txt
rockchip,pmu:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the syscon node controlling the cpu core power domains.
@@ -338,7 +339,7 @@ properties:
the cpu-core power-domains.
secondary-boot-reg:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Required for systems that have an "enable-method" property value of
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
Documentation/devicetree/bindings/arm/fsl.yaml
+14
View File
@@ -726,6 +726,12 @@ properties:
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL DHCOR SoM based Boards
items:
- const: marantec,imx6ull-dhcor-maveo-box
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -901,6 +907,7 @@ properties:
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw7904
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
@@ -918,6 +925,12 @@ properties:
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
- description: Emtop i.MX8MM based Boards
items:
- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1
- const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module
- const: fsl,imx8mm
- description: Engicam i.Core MX8M Mini SoM based boards
items:
- enum:
@@ -1019,6 +1032,7 @@ properties:
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml
+30
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@@ -0,0 +1,30 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35 series SoC based platforms
maintainers:
- Jacky Huang <ychuang3@nuvoton.com>
description: |
Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
the following properties.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: MA35D1 based boards
items:
- enum:
- nuvoton,ma35d1-iot
- nuvoton,ma35d1-som
- const: nuvoton,ma35d1
additionalProperties: true
...
Documentation/devicetree/bindings/arm/npcm/npcm.yaml → Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml
+1 -1
View File
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NPCM Platforms
Documentation/devicetree/bindings/arm/psci.yaml
+1 -1
View File
@@ -100,7 +100,7 @@ properties:
patternProperties:
"^power-domain-":
$ref: "../power/power-domain.yaml#"
$ref: /schemas/power/power-domain.yaml#
type: object
description: |
Documentation/devicetree/bindings/arm/qcom.yaml
+28 -2
View File
@@ -40,6 +40,7 @@ description: |
msm8939
msm8953
msm8956
msm8960
msm8974
msm8976
msm8992
@@ -69,6 +70,7 @@ description: |
sdm845
sdx55
sdx65
sdx75
sm4250
sm6115
sm6115p
@@ -85,9 +87,15 @@ description: |
The 'board' element must be one of the following strings:
adp
ap-al02-c2
ap-al02-c6
ap-al02-c7
ap-al02-c8
ap-al02-c9
ap-mi01.2
ap-mi01.3
ap-mi01.6
ap-mi01.9
cdp
cp01-c1
dragonboard
@@ -191,6 +199,7 @@ properties:
- items:
- enum:
- qcom,msm8960-cdp
- samsung,expressatt
- const: qcom,msm8960
- items:
@@ -333,7 +342,9 @@ properties:
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
- qcom,ipq5332-ap-mi01.3
- qcom,ipq5332-ap-mi01.6
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
@@ -351,7 +362,11 @@ properties:
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
- description: Sierra Wireless MangOH Green with WP8548 Module
@@ -380,9 +395,9 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
- description: Qualcomm Technologies, Inc. SC7180 IDP
items:
- items:
- enum:
- acer,aspire1
- qcom,sc7180-idp
- const: qcom,sc7180
@@ -819,6 +834,11 @@ properties:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx75-idp
- const: qcom,sdx75
- items:
- enum:
- qcom,ipq6018-cp01
@@ -882,6 +902,11 @@ properties:
- const: qcom,qrb4210
- const: qcom,sm4250
- items:
- enum:
- fxtec,pro1x
- const: qcom,sm6115
- items:
- enum:
- lenovo,j606f
@@ -1042,6 +1067,7 @@ allOf:
- qcom,sdm845
- qcom,sdx55
- qcom,sdx65
- qcom,sdx75
- qcom,sm4250
- qcom,sm6115
- qcom,sm6125
Documentation/devicetree/bindings/arm/rockchip.yaml
+24
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@@ -40,6 +40,11 @@ properties:
- const: anbernic,rg353p
- const: rockchip,rk3566
- description: Anbernic RG353PS
items:
- const: anbernic,rg353ps
- const: rockchip,rk3566
- description: Anbernic RG353V
items:
- const: anbernic,rg353v
@@ -102,6 +107,12 @@ properties:
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- const: rockchip,rk3588
- description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
items:
- const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board
- const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
@@ -189,6 +200,7 @@ properties:
items:
- enum:
- friendlyarm,nanopi-r2c
- friendlyarm,nanopi-r2c-plus
- friendlyarm,nanopi-r2s
- const: rockchip,rk3328
@@ -534,6 +546,11 @@ properties:
- const: hugsun,x99
- const: rockchip,rk3399
- description: Indiedroid Nova SBC
items:
- const: indiedroid,nova
- const: rockchip,rk3588s
- description: Khadas Edge series boards
items:
- enum:
@@ -562,6 +579,13 @@ properties:
- const: leez,p710
- const: rockchip,rk3399
- description: Lunzn FastRhino R66S / R68S
items:
- enum:
- lunzn,fastrhino-r66s
- lunzn,fastrhino-r68s
- const: rockchip,rk3568
- description: mqmaker MiQi
items:
- const: mqmaker,miqi
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+10
View File
@@ -72,6 +72,16 @@ properties:
- const: samsung,exynos4210
- const: samsung,exynos4
- description: Samsung Galaxy Tab3 family boards
items:
- enum:
- samsung,t310 # Samsung Galaxy Tab 3 8.0 WiFi (SM-T310)
- samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311)
- samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315)
- const: samsung,tab3
- const: samsung,exynos4212
- const: samsung,exynos4
- description: Exynos4412 based boards
items:
- enum:
Documentation/devicetree/bindings/arm/socionext/synquacer.yaml
+28
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@@ -0,0 +1,28 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/synquacer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext Synquacer platform
maintainers:
- Masahisa Kojima <masahisa.kojima@linaro.org>
- Jassi Brar <jaswinder.singh@linaro.org>
description:
Socionext SC2A11B (Synquacer) SoC based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- socionext,developer-box
- const: socionext,synquacer
additionalProperties: true
...
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
+4 -3
View File
@@ -15,12 +15,13 @@ properties:
oneOf:
- items:
- enum:
- st,stm32mp157-syscfg
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
- st,stm32-syscfg
- st,stm32-tamp
- st,stm32f4-gcan
- st,stm32mp151-pwr-mcu
- st,stm32mp157-syscfg
- st,stm32mp25-syscfg
- const: syscon
- items:
- const: st,stm32-tamp
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+12
View File
@@ -155,6 +155,18 @@ properties:
- const: seeed,stm32mp157c-odyssey-som
- const: st,stm32mp157
- description: Phytec STM32MP1 SoM based Boards
items:
- const: phytec,phycore-stm32mp1-3
- const: phytec,phycore-stm32mp157c-som
- const: st,stm32mp157
- description: ST STM32MP257 based Boards
items:
- enum:
- st,stm32mp257f-ev1
- const: st,stm32mp257
additionalProperties: true
...
Documentation/devicetree/bindings/arm/sunxi.yaml
+6
View File
@@ -305,6 +305,12 @@ properties:
- const: allwinner,i12-tvbox
- const: allwinner,sun7i-a20
- description: ICnova A20 ADB4006
items:
- const: incircuit,icnova-a20-adb4006
- const: incircuit,icnova-a20
- const: allwinner,sun7i-a20
- description: ICNova A20 SWAC
items:
- const: incircuit,icnova-a20-swac
Documentation/devicetree/bindings/arm/tegra.yaml
+14
View File
@@ -167,6 +167,11 @@ properties:
- const: nvidia,p3737-0000+p3701-0000
- const: nvidia,p3701-0000
- const: nvidia,tegra234
- description: NVIDIA IGX Orin Development Kit
items:
- const: nvidia,p3740-0002+p3701-0008
- const: nvidia,p3701-0008
- const: nvidia,tegra234
- description: Jetson Orin NX
items:
- const: nvidia,p3767-0000
@@ -176,5 +181,14 @@ properties:
- const: nvidia,p3768-0000+p3767-0000
- const: nvidia,p3767-0000
- const: nvidia,tegra234
- description: Jetson Orin Nano
items:
- const: nvidia,p3767-0005
- const: nvidia,tegra234
- description: Jetson Orin Nano Developer Kit
items:
- const: nvidia,p3768-0000+p3767-0005
- const: nvidia,p3767-0005
- const: nvidia,tegra234
additionalProperties: true
Documentation/devicetree/bindings/arm/ti/k3.yaml
+26
View File
@@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
- const: phytec,am62-phycore-som
- const: ti,am625
- description: K3 AM625 SoC
items:
- enum:
@@ -33,6 +39,26 @@ properties:
- ti,am62-lp-sk
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
items:
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT
items:
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM642 SoC
items:
- enum:
Documentation/devicetree/bindings/arm/xilinx.yaml
+4 -4
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
@@ -61,10 +61,10 @@ properties:
- const: xlnx,zynqmp-zc1254
- const: xlnx,zynqmp
- description: Xilinx internal board zc1275
- description: Xilinx evaluation board zcu1275
items:
- const: xlnx,zynqmp-zc1275-revA
- const: xlnx,zynqmp-zc1275
- const: xlnx,zynqmp-zcu1275-revA
- const: xlnx,zynqmp-zcu1275
- const: xlnx,zynqmp
- description: Xilinx 96boards compatible board zcu100
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
- Piyush Mehta <piyush.mehta@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some
Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml
+1
View File
@@ -40,6 +40,7 @@ properties:
linux,keymap: true
linux,no-autorepeat:
type: boolean
description: Disable keyrepeat
default-brightness-level:
Documentation/devicetree/bindings/bus/ti-sysc.yaml
+1 -1
View File
@@ -97,7 +97,7 @@ properties:
- enum: [ ick, fck, sys_clk ]
- items:
- const: fck
- enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
- enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]
- items:
- const: fck
- const: phy-clk
Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml
+1 -1
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings
title: Broadcom BCM63268 Timer Clock and Reset
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
+1 -1
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP AudioMIX Block Control Binding
title: NXP i.MX8MP AudioMIX Block Control
maintainers:
- Marek Vasut <marex@denx.de>
Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+64
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@@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTMIPS SoCs System Controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
MediaTek MIPS and Ralink SoCs provides a system controller to allow
to access to system control registers. These registers include clock
and reset related ones so this node is both clock and reset provider
for the rest of the world.
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
reg:
maxItems: 1
'#clock-cells':
description:
The first cell indicates the clock number.
const: 1
'#reset-cells':
description:
The first cell indicates the reset bit within the register.
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
+63
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35D1 Clock Controller Module
maintainers:
- Chi-Fang Li <cfli0@nuvoton.com>
- Jacky Huang <ychuang3@nuvoton.com>
description: |
The MA35D1 clock controller generates clocks for the whole chip,
including system clocks and all peripheral clocks.
See also:
include/dt-bindings/clock/ma35d1-clk.h
properties:
compatible:
items:
- const: nuvoton,ma35d1-clk
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
nuvoton,pll-mode:
description:
A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
EPLL, and VPLL in sequential.
maxItems: 5
items:
enum:
- integer
- fractional
- spread-spectrum
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
clock-controller@40460200 {
compatible = "nuvoton,ma35d1-clk";
reg = <0x40460200 0x100>;
#clock-cells = <1>;
clocks = <&clk_hxt>;
};
...
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
+60
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@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
Qualcomm LPASS core and audio clock control module provides the clocks,
and reset on SC8280XP.
See also::
include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpass_audiocc: clock-controller@32a9000 {
compatible = "qcom,sc8280xp-lpassaudiocc";
reg = <0x032a9000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpasscc: clock-controller@33e0000 {
compatible = "qcom,sc8280xp-lpasscc";
reg = <0x033e0000 0x12000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
+65
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@@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SDX75
maintainers:
- Imran Shaik <quic_imrashai@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX75
See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
properties:
compatible:
const: qcom,sdx75-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC0 sgmiiphy rclk source
- description: EMAC0 sgmiiphy tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy rclk source
- description: EMAC1 sgmiiphy tclk source
- description: PCIE20 phy aux clock source
- description: PCIE_1 Pipe clock source
- description: PCIE_2 Pipe clock source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@80000 {
compatible = "qcom,sdx75-gcc";
reg = <0x80000 0x1f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+75
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@@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM8450
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d90000 {
compatible = "qcom,sm8450-gpucc";
reg = <0 0x03d90000 0 0xa000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+77
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@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
properties:
compatible:
const: qcom,sm8450-videocc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Video AHB clock from GCC
power-domains:
maxItems: 1
description:
MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8450-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
description:
The clocking wizard is a soft ip clocking block of Xilinx versal. It
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
+1 -3
View File
@@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
The clock controller is a hardware block of Xilinx versal clock tree. It
Documentation/devicetree/bindings/connector/usb-connector.yaml
+20
View File
@@ -168,6 +168,13 @@ properties:
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
port:
$ref: /schemas/graph.yaml#/properties/port
description: OF graph bindings modeling a data bus to the connector, e.g.
there is a single High Speed (HS) port present in this connector. If there
is more than one bus (several port, with 'reg' property), they can be grouped
under 'ports'.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: OF graph bindings modeling any data bus to the connector
@@ -322,6 +329,19 @@ examples:
};
};
# USB-C connector attached to SoC with a single High-Speed controller
- |
connector {
compatible = "usb-c-connector";
label = "USB-C";
port {
high_speed_ep: endpoint {
remote-endpoint = <&usb_hs_ep>;
};
};
};
# USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
# with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
# the output of MUX is connected to the SoC.
Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
+2 -2
View File
@@ -19,8 +19,8 @@ properties:
interrupts:
items:
- description: "Interrupt for flow 0"
- description: "Interrupt for flow 1"
- description: Interrupt for flow 0
- description: Interrupt for flow 1
clocks:
maxItems: 1
Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml
+6
View File
@@ -103,6 +103,12 @@ properties:
wakeup-source: true
linux,keycode:
$ref: /schemas/types.yaml#/definitions/uint32
default: 116
deprecated: true
linux,keycodes:
maxItems: 1
default: 116
required:
Documentation/devicetree/bindings/crypto/fsl-dcp.yaml
+9 -3
View File
@@ -11,9 +11,15 @@ maintainers:
properties:
compatible:
enum:
- fsl,imx23-dcp
- fsl,imx28-dcp
oneOf:
- enum:
- fsl,imx23-dcp
- fsl,imx28-dcp
- items:
- enum:
- fsl,imx6sl-dcp
- fsl,imx6ull-dcp
- const: fsl,imx28-dcp
reg:
maxItems: 1
Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
+3 -3
View File
@@ -2,8 +2,8 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx cryptographic engine
@@ -21,7 +21,7 @@ properties:
const: intel,ixp4xx-crypto
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to the NPE this crypto engine
Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
+2 -2
View File
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Kalyani Akula <kalyani.akula@amd.com>
- Michal Simek <michal.simek@amd.com>
description: |
The ZynqMP AES-GCM hardened cryptographic accelerator is used to
Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
+1
View File
@@ -26,6 +26,7 @@ properties:
const: dp
force-hpd:
type: boolean
description:
Indicate driver need force hpd when hpd detect failed, this
is used for some eDP screen which don not have a hpd signal.
Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml
+1
View File
@@ -20,6 +20,7 @@ properties:
maxItems: 1
video-ports:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x230145
maximum: 0xffffff
description:
Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
+3
View File
@@ -67,6 +67,7 @@ properties:
items:
- enum:
- sainsmart18
- shineworld,lh133k
- const: panel-mipi-dbi-spi
write-only:
@@ -86,6 +87,8 @@ properties:
Logic level supply for interface signals (Vddi).
No need to set if this is the same as power-supply.
spi-3wire: true
required:
- compatible
- reg
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
-2
View File
@@ -74,8 +74,6 @@ properties:
- const: 2
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- clocks
Documentation/devicetree/bindings/dvfs/performance-domain.yaml
+1 -1
View File
@@ -42,7 +42,7 @@ properties:
enum: [ 0, 1 ]
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.
Documentation/devicetree/bindings/eeprom/at25.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
- microchip,25lc040
- st,m95m02
- st,m95256
- st,m95640
- cypress,fm25
- const: atmel,at25
Documentation/devicetree/bindings/example-schema.yaml
+4 -2
View File
@@ -52,8 +52,7 @@ properties:
- vendor,soc4-ip
- vendor,soc3-ip
- vendor,soc2-ip
- enum:
- vendor,soc1-ip
- const: vendor,soc1-ip
# additionalItems being false is implied
# minItems/maxItems equal to 2 is implied
- items:
@@ -85,6 +84,9 @@ properties:
discouraged.
clock-names:
# For single-entry lists in clocks, resets etc., the xxx-names often do not
# bring any value, especially if they copy the IP block name. In such case
# just skip the xxx-names.
items:
- const: bus
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+8 -2
View File
@@ -34,6 +34,10 @@ properties:
- description: SCMI compliant firmware with ARM SMC/HVC transport
items:
- const: arm,scmi-smc
- description: SCMI compliant firmware with ARM SMC/HVC transport
with shmem address(4KB-page, offset) as parameters
items:
- const: arm,scmi-smc-param
- description: SCMI compliant firmware with SCMI Virtio transport.
The virtio transport only supports a single device.
items:
@@ -214,7 +218,7 @@ properties:
patternProperties:
'^regulator@[0-9a-f]+$':
type: object
$ref: "../regulator/regulator.yaml#"
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
@@ -299,7 +303,9 @@ else:
properties:
compatible:
contains:
const: arm,scmi-smc
enum:
- arm,scmi-smc
- arm,scmi-smc-param
then:
required:
- arm,smc-id
Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml
+39
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@@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family Secure Monitor bounce buffer
description:
A bounce buffer used for non-secure to secure communications.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
items:
- enum:
- brcm,bcm11351-smc
- brcm,bcm21664-smc
- brcm,bcm23550-smc
- const: brcm,kona-smc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
};
...
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+1
View File
@@ -51,6 +51,7 @@ properties:
- qcom,scm-sdm845
- qcom,scm-sdx55
- qcom,scm-sdx65
- qcom,scm-sdx75
- qcom,scm-sm6115
- qcom,scm-sm6125
- qcom,scm-sm6350
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx firmware driver
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: The zynqmp-firmware node describes the interface to platform
firmware. ZynqMP has an interface to communicate with secure firmware.
Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq FPGA Manager
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal FPGA driver.
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Device Tree Versal FPGA bindings for the Versal SoC, controlled
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
maintainers:
- Nava kishore Manne <navam@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq GPIO controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI GPIO controller
maintainers:
- Neeli Srinivas <srinivas.neeli@xilinx.com>
- Neeli Srinivas <srinivas.neeli@amd.com>
description:
The AXI GPIO design provides a general purpose input/output interface
Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
+1 -1
View File
@@ -12,7 +12,7 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
- Piyush Mehta <piyush.mehta@amd.com>
properties:
compatible:
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+1 -1
View File
@@ -86,7 +86,7 @@ properties:
const: 2
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
+1 -1
View File
@@ -92,7 +92,7 @@ properties:
dma-coherent: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
- rockchip,rk3228-mali
- samsung,exynos4210-mali
- stericsson,db8500-mali
- xlnx,zynqmp-mali
- const: arm,mali-400
- items:
- enum:
Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence I2C controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
+1 -1
View File
@@ -10,7 +10,7 @@ maintainers:
- Conor Culhane <conor.culhane@silvaco.com>
allOf:
- $ref: "i3c.yaml#"
- $ref: i3c.yaml#
properties:
compatible:
Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml
+1 -1
View File
@@ -55,7 +55,7 @@ patternProperties:
interrupt-names: true
linux-keycodes:
linux,keycodes:
maxItems: 1
wakeup-source: true
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
-38
View File
@@ -1,38 +0,0 @@
Amlogic meson GPIO interrupt controller
Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupt exposed depends on the SoC.
Required properties:
- compatible : must have "amlogic,meson8-gpio-intc" and either
"amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
"amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
"amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
"amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
are the hwirqs used on the parent interrupt controller.
Example:
gpio_interrupt: interrupt-controller@9880 {
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x9880 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson GPIO interrupt controller
maintainers:
- Heiner Kallweit <hkallweit1@gmail.com>
description: |
Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select
edge or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupts exposed depends on the SoC.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
oneOf:
- const: amlogic,meson-gpio-intc
- items:
- enum:
- amlogic,meson8-gpio-intc
- amlogic,meson8b-gpio-intc
- amlogic,meson-gxbb-gpio-intc
- amlogic,meson-gxl-gpio-intc
- amlogic,meson-axg-gpio-intc
- amlogic,meson-g12a-gpio-intc
- amlogic,meson-sm1-gpio-intc
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
- const: amlogic,meson-gpio-intc
reg:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
amlogic,channel-interrupts:
description: Array with the upstream hwirq numbers
minItems: 8
maxItems: 12
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- amlogic,channel-interrupts
additionalProperties: false
examples:
- |
interrupt-controller@9880 {
compatible = "amlogic,meson-gxbb-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x9880 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml → Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml
+1 -1
View File
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
$id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip External Interrupt Controller
Documentation/devicetree/bindings/interrupt-controller/ralink,rt2880-intc.yaml
+54
View File
@@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ralink,rt2880-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink SoCs Interrupt Controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
description:
This interrupt controller support a central point for interrupt aggregation
for platform related blocks.
properties:
compatible:
const: ralink,rt2880-intc
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@200 {
compatible = "ralink,rt2880-intc";
reg = <0x200 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
...
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+2 -1
View File
@@ -57,14 +57,15 @@ properties:
- const: andestech,nceplic100
- items:
- enum:
- canaan,k210-plic
- sifive,fu540-c000-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
- enum:
- allwinner,sun20i-d1-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:
- const: sifive,plic-1.0.0
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
+1 -1
View File
@@ -33,7 +33,7 @@ description: |
+------------------------------------------+
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
properties:
compatible:
Documentation/devicetree/bindings/media/rockchip-rga.yaml
+3 -1
View File
@@ -21,7 +21,9 @@ properties:
- const: rockchip,rk3288-rga
- const: rockchip,rk3399-rga
- items:
- const: rockchip,rk3228-rga
- enum:
- rockchip,rk3228-rga
- rockchip,rk3568-rga
- const: rockchip,rk3288-rga
reg:
Documentation/devicetree/bindings/media/s5p-mfc.txt
-78
View File
@@ -1,78 +0,0 @@
* Samsung Multi Format Codec (MFC)
Multi Format Codec (MFC) is the IP present in Samsung SoCs which
supports high resolution decoding and encoding functionalities.
The MFC device driver is a v4l2 driver which can encode/decode
video raw/elementary streams and has support for all popular
video codecs.
Required properties:
- compatible : value should be either one among the following
(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
(c) "samsung,exynos3250-mfc", "samsung,mfc-v7" for MFC v7
present in Exynos3250 SoC
(d) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
(e) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
(f) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
(g) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
- interrupts : MFC interrupt number to the CPU.
- clocks : from common clock binding: handle to mfc clock.
- clock-names : from common clock binding: must contain "mfc",
corresponding to entry in the clocks property.
Optional properties:
- power-domains : power-domain property defined with a phandle
to respective power domain.
- memory-region : from reserved memory binding: phandles to two reserved
memory regions, first is for "left" mfc memory bus interfaces,
second if for the "right" mfc memory bus, used when no SYSMMU
support is available; used only by MFC v5 present in Exynos4 SoCs
Obsolete properties:
- samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
property instead
Example:
SoC specific DT entry:
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
power-domains = <&pd_mfc>;
clocks = <&clock 273>;
clock-names = "mfc";
};
Reserved memory specific DT entry for given board (see reserved memory binding
for more information):
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mfc_left: region@51000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x51000000 0x800000>;
};
mfc_right: region@43000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x43000000 0x800000>;
};
};
Board specific DT entry:
codec@13400000 {
memory-region = <&mfc_left>, <&mfc_right>;
};
Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
+184
View File
@@ -0,0 +1,184 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos Multi Format Codec (MFC)
maintainers:
- Marek Szyprowski <m.szyprowski@samsung.com>
- Aakarsh Jain <aakarsh.jain@samsung.com>
description:
Multi Format Codec (MFC) is the IP present in Samsung SoCs which
supports high resolution decoding and encoding functionalities.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos5433-mfc # Exynos5433
- samsung,mfc-v5 # Exynos4
- samsung,mfc-v6 # Exynos5
- samsung,mfc-v7 # Exynos5420
- samsung,mfc-v8 # Exynos5800
- samsung,mfc-v10 # Exynos7880
- items:
- enum:
- samsung,exynos3250-mfc # Exynos3250
- const: samsung,mfc-v7 # Fall back for Exynos3250
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
iommus:
minItems: 1
maxItems: 2
iommu-names:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
memory-region:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos3250-mfc
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mfc
- const: sclk_mfc
iommus:
maxItems: 1
iommus-names: false
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5433-mfc
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v5
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mfc
- const: sclk_mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v6
- samsung,mfc-v8
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
- if:
properties:
compatible:
contains:
enum:
- samsung,mfc-v7
then:
properties:
clocks:
minItems: 1
maxItems: 2
iommus:
minItems: 1
maxItems: 2
examples:
- |
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
- Vishal Sagar <vishal.sagar@amd.com>
description: |
The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
+1 -1
View File
@@ -165,7 +165,7 @@ patternProperties:
const: 0
lpddr2:
$ref: "ddr/jedec,lpddr2.yaml#"
$ref: ddr/jedec,lpddr2.yaml#
type: object
patternProperties:
Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
+1 -2
View File
@@ -8,8 +8,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
+1 -1
View File
@@ -129,7 +129,7 @@ patternProperties:
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
$ref: "ti,gpmc-child.yaml"
$ref: ti,gpmc-child.yaml
required:
Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
+1 -2
View File
@@ -8,8 +8,7 @@ title: Zynq A05 DDR Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description:
The Zynq DDR ECC controller has an optional ECC support in half-bus width
Documentation/devicetree/bindings/mips/ralink.yaml
+1
View File
@@ -80,6 +80,7 @@ properties:
- enum:
- gnubee,gb-pc1
- gnubee,gb-pc2
- tplink,hc220-g5-v1
- const: mediatek,mt7621-soc
additionalProperties: true
Documentation/devicetree/bindings/misc/brcm,kona-smc.txt
-15
View File
@@ -1,15 +0,0 @@
Broadcom Secure Monitor Bounce buffer
-----------------------------------------------------
This binding defines the location of the bounce buffer
used for non-secure to secure communications.
Required properties:
- compatible : "brcm,kona-smc"
- DEPRECATED: compatible : "bcm,kona-smc"
- reg : Location and size of bounce buffer
Example:
smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; //1 KiB in SRAM
};
Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml
+3 -3
View File
@@ -36,7 +36,7 @@ properties:
description:
A list of channels tied to this function, used for matching
the function to a set of virtual channels.
$ref: "/schemas/types.yaml#/definitions/string-array"
$ref: /schemas/types.yaml#/definitions/string-array
items:
- const: fastrpcglink-apps-dsp
@@ -48,14 +48,14 @@ properties:
qcom,smd-channels:
description:
Channel name used for the RPM communication
$ref: "/schemas/types.yaml#/definitions/string-array"
$ref: /schemas/types.yaml#/definitions/string-array
items:
- const: fastrpcsmd-apps-dsp
qcom,vmids:
description:
Virtual machine IDs for remote processor.
$ref: "/schemas/types.yaml#/definitions/uint32-array"
$ref: /schemas/types.yaml#/definitions/uint32-array
"#address-cells":
const: 1
Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml
+53
View File
@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 ESM
maintainers:
- Neha Malcom Francis <n-francis@ti.com>
description:
The ESM (Error Signaling Module) is an IP block on TI K3 devices
that allows handling of safety events somewhat similar to what interrupt
controller would do. The safety signals have their separate paths within
the SoC, and they are handled by the ESM, which routes them to the proper
destination, which can be system reset, interrupt controller, etc. In the
simplest configuration the signals are just routed to reset the SoC.
properties:
compatible:
const: ti,j721e-esm
reg:
maxItems: 1
ti,esm-pins:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
integer array of ESM interrupt pins to route to external event pin
which can be used to reset the SoC.
minItems: 1
maxItems: 255
required:
- compatible
- reg
- ti,esm-pins
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
};
};
Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml
+3 -2
View File
@@ -24,11 +24,12 @@ properties:
- nxp,88w8997-bt
fw-init-baudrate:
$ref: /schemas/types.yaml#/definitions/uint32
default: 115200
description:
Chip baudrate after FW is downloaded and initialized.
This property depends on the module vendor's
configuration. If this property is not specified,
115200 is set as default.
configuration.
required:
- compatible
Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml
+2
View File
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,qca2066-bt
- qcom,qca6174-bt
- qcom,qca9377-bt
- qcom,wcn3990-bt
@@ -98,6 +99,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qca2066-bt
- qcom,qca6174-bt
then:
required:
Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
+5 -1
View File
@@ -15,6 +15,9 @@ description:
These chips also have a Bluetooth portion described in a separate
binding.
allOf:
- $ref: ieee80211.yaml#
properties:
compatible:
oneOf:
@@ -38,6 +41,7 @@ properties:
- brcm,bcm4354-fmac
- brcm,bcm4356-fmac
- brcm,bcm4359-fmac
- brcm,bcm4366-fmac
- cypress,cyw4373-fmac
- cypress,cyw43012-fmac
- const: brcm,bcm4329-fmac
@@ -120,7 +124,7 @@ required:
- compatible
- reg
additionalProperties: false
unevaluatedProperties: false
examples:
- |
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+3
View File
@@ -18,8 +18,11 @@ properties:
- enum:
- qcom,apq8064-qfprom
- qcom,apq8084-qfprom
- qcom,ipq5332-qfprom
- qcom,ipq6018-qfprom
- qcom,ipq8064-qfprom
- qcom,ipq8074-qfprom
- qcom,ipq9574-qfprom
- qcom,msm8916-qfprom
- qcom,msm8974-qfprom
- qcom,msm8976-qfprom
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+13 -3
View File
@@ -41,20 +41,24 @@ properties:
- const: config
clocks:
minItems: 5
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
- description: PIPE clock
clock-names:
minItems: 5
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
- const: pipe
msi-map: true
@@ -70,13 +74,19 @@ properties:
maxItems: 1
ranges:
maxItems: 2
minItems: 2
maxItems: 3
resets:
maxItems: 1
minItems: 1
maxItems: 2
reset-names:
const: pipe
oneOf:
- const: pipe
- items:
- const: pwr
- const: pipe
vpcie3v3-supply: true
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
- Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
+4
View File
@@ -24,6 +24,10 @@ properties:
- enum:
- mediatek,mt7623-mipi-tx
- const: mediatek,mt2701-mipi-tx
- items:
- enum:
- mediatek,mt6795-mipi-tx
- const: mediatek,mt8173-mipi-tx
- items:
- enum:
- mediatek,mt8365-mipi-tx
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+3 -1
View File
@@ -27,6 +27,8 @@ properties:
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl
- st,stm32mp257-pinctrl
- st,stm32mp257-z-pinctrl
'#address-cells':
const: 1
@@ -56,7 +58,7 @@ properties:
Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
patternProperties:
'^gpio@[0-9a-f]*$':
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+1 -2
View File
@@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt
-14
View File
@@ -1,14 +0,0 @@
Broadcom Kona Family Reset Manager
----------------------------------
The reset manager is used on the Broadcom BCM21664 SoC.
Required properties:
- compatible: brcm,bcm21664-resetmgr
- reg: memory address & range
Example:
brcm,resetmgr@35001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x35001f00 0x24>;
};
Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml
+31
View File
@@ -0,0 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/brcm,bcm21664-resetmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family reset manager
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
const: brcm,bcm21664-resetmgr
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
reset-controller@35001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x35001f00 0x24>;
};
...
Documentation/devicetree/bindings/power/reset/restart-handler.yaml
+1 -1
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/power/reset/restart-handler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Restart and shutdown handler generic binding
title: Restart and shutdown handler Common Properties
maintainers:
- Sebastian Reichel <sre@kernel.org>
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq MPSoC Power Management
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
The zynqmp-power node describes the power management configurations.
Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
+1 -1
View File
@@ -11,7 +11,7 @@ maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
allOf:
- $ref: "pwm.yaml#"
- $ref: pwm.yaml#
properties:
compatible:
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
+3 -1
View File
@@ -22,7 +22,9 @@ properties:
- mediatek,mt8173-disp-pwm
- mediatek,mt8183-disp-pwm
- items:
- const: mediatek,mt8167-disp-pwm
- enum:
- mediatek,mt6795-disp-pwm
- mediatek,mt8167-disp-pwm
- const: mediatek,mt8173-disp-pwm
- items:
- enum:
Documentation/devicetree/bindings/pwm/mxs-pwm.yaml
+1 -1
View File
@@ -25,7 +25,7 @@ properties:
const: 3
fsl,pwm-number:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: u32 value representing the number of PWM devices
required:
Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml
+1 -1
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common TI PRU Consumer Binding
title: TI PRU Consumer Common Properties
maintainers:
- Suman Anna <s-anna@ti.com>
Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml
+1 -1
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/reserved-memory/framebuffer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: /reserved-memory framebuffer node bindings
title: /reserved-memory framebuffer node
maintainers:
- devicetree-spec@vger.kernel.org
Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
+45
View File
@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35D1 Reset Controller
maintainers:
- Chi-Fang Li <cfli0@nuvoton.com>
- Jacky Huang <ychuang3@nuvoton.com>
description:
The system reset controller can be used to reset various peripheral
controllers in MA35D1 SoC.
properties:
compatible:
items:
- const: nuvoton,ma35d1-reset
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
# system reset controller node:
- |
system-management@40460000 {
compatible = "nuvoton,ma35d1-reset";
reg = <0x40460000 0x200>;
#reset-cells = <1>;
};
...
Documentation/devicetree/bindings/reset/oxnas,reset.txt
-32
View File
@@ -1,32 +0,0 @@
Oxford Semiconductor OXNAS SoC Family RESET Controller
================================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: For OX810SE, should be "oxsemi,ox810se-reset"
For OX820, should be "oxsemi,ox820-reset"
- #reset-cells: 1, see below
Parent node should have the following properties :
- compatible: For OX810SE, should be :
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
For OX820, should be :
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
Reset indices are in dt-bindings include files :
- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
- For OX820: include/dt-bindings/reset/oxsemi,ox820.h
example:
sys: sys-ctrl@000000 {
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
reg = <0x000000 0x100000>;
reset: reset-controller {
compatible = "oxsemi,ox810se-reset";
#reset-cells = <1>;
};
};

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