diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index a746b1d00d8d..485e5f13f27b 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3720,8 +3720,8 @@ nohibernate [HIBERNATION] Disable hibernation and resume. - nohlt [ARM,ARM64,MICROBLAZE,SH] Forces the kernel to busy wait - in do_idle() and not use the arch_cpu_idle() + nohlt [ARM,ARM64,MICROBLAZE,MIPS,SH] Forces the kernel to + busy wait in do_idle() and not use the arch_cpu_idle() implementation; requires CONFIG_GENERIC_IDLE_POLL_SETUP to be effective. This is useful on platforms where the sleep(SH) or wfi(ARM,ARM64) instructions do not work @@ -3856,7 +3856,7 @@ nosmp [SMP] Tells an SMP kernel to act as a UP kernel, and disable the IO APIC. legacy for "maxcpus=0". - nosmt [KNL,S390] Disable symmetric multithreading (SMT). + nosmt [KNL,MIPS,S390] Disable symmetric multithreading (SMT). Equivalent to smt=1. [KNL,X86] Disable symmetric multithreading (SMT). @@ -5774,7 +5774,7 @@ 1: Fast pin select (default) 2: ATC IRMode - smt= [KNL,S390] Set the maximum number of threads (logical + smt= [KNL,MIPS,S390] Set the maximum number of threads (logical CPUs) to use per physical CPU on systems capable of symmetric multithreading (SMT). Will be capped to the actual hardware limit. diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 274ee0890312..08d59842655c 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amlogic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic MesonX +title: Amlogic SoC based Platforms maintainers: - Kevin Hilman @@ -205,6 +205,13 @@ properties: - amlogic,ad401 - const: amlogic,a1 + - description: Boards with the Amlogic C3 C302X/C308L SoC + items: + - enum: + - amlogic,aw409 + - amlogic,aw419 + - const: amlogic,c3 + - description: Boards with the Amlogic Meson S4 S805X2 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 09c319f803ba..cdd65881fcdd 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -122,14 +122,14 @@ properties: arm,vexpress,position: description: When daughterboards are stacked on one site, their position in the stack be be described this attribute. - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 arm,vexpress,dcc: description: When describing tiles consisting of more than one DCC, its number can be specified with this attribute. - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3 @@ -180,13 +180,13 @@ patternProperties: - const: simple-bus arm,v2m-memory-map: description: This describes the memory map type. - $ref: '/schemas/types.yaml#/definitions/string' + $ref: /schemas/types.yaml#/definitions/string enum: - rs1 - rs2 arm,hbi: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: This indicates the ARM HBI (Hardware Board ID), this is ARM's unique board model ID, visible on the PCB's silkscreen. @@ -197,7 +197,7 @@ patternProperties: property, describing the physical location of the children nodes. 0 means motherboard site, while 1 and 2 are daughterboard sites, and 0xf means "sisterboard" which is the site containing the main CPU tile. - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 15 diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 454b0e93245d..5c3ac97e8728 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -25,13 +25,15 @@ properties: - enum: - asus,rt-ac56u - asus,rt-ac68u + - buffalo,wzr-1166dhp + - buffalo,wzr-1166dhp2 - buffalo,wzr-1750dhp - linksys,ea6300-v1 - linksys,ea6500-v2 - - luxul,xap-1510v1 + - luxul,xap-1510-v1 - luxul,xwc-1000 - - netgear,r6250v1 - - netgear,r6300v2 + - netgear,r6250-v1 + - netgear,r6300-v2 - smartrg,sr400ac - brcm,bcm94708 - const: brcm,bcm4708 @@ -42,8 +44,8 @@ properties: - asus,rt-n18u - buffalo,wzr-600dhp2 - buffalo,wzr-900dhp - - luxul,xap-1410v1 - - luxul,xwr-1200v1 + - luxul,xap-1410-v1 + - luxul,xwr-1200-v1 - tplink,archer-c5-v2 - const: brcm,bcm47081 - const: brcm,bcm4708 @@ -72,7 +74,7 @@ properties: - luxul,xap-1610-v1 - luxul,xbr-4500-v1 - luxul,xwc-2000-v1 - - luxul,xwr-3100v1 + - luxul,xwr-3100-v1 - luxul,xwr-3150-v1 - netgear,r8500 - phicomm,k3 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index ff272e517d57..9e6a45eea4e5 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -153,6 +153,7 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,cortex-r52 - arm,cortex-x1 - arm,cortex-x1c - arm,cortex-x2 @@ -196,7 +197,7 @@ properties: - qcom,scorpion enable-method: - $ref: '/schemas/types.yaml#/definitions/string' + $ref: /schemas/types.yaml#/definitions/string oneOf: # On ARM v8 64-bit this property is required - enum: @@ -245,8 +246,8 @@ properties: cpu-release-addr: oneOf: - - $ref: '/schemas/types.yaml#/definitions/uint32' - - $ref: '/schemas/types.yaml#/definitions/uint64' + - $ref: /schemas/types.yaml#/definitions/uint32 + - $ref: /schemas/types.yaml#/definitions/uint64 description: The DT specification defines this as 64-bit always, but some 32-bit Arm systems have used a 32-bit value which must be supported. @@ -254,7 +255,7 @@ properties: property value of "spin-table". cpu-idle-states: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 description: | @@ -270,7 +271,7 @@ properties: cci-control-port: true dynamic-power-coefficient: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: A u32 value that represents the running time dynamic power coefficient in units of uW/MHz/V^2. The @@ -307,7 +308,7 @@ properties: PM domain provider, must be "psci". qcom,saw: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Specifies the SAW* node associated with this CPU. @@ -317,7 +318,7 @@ properties: * arm/msm/qcom,saw2.txt qcom,acc: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Specifies the ACC* node associated with this CPU. @@ -328,7 +329,7 @@ properties: * arm/msm/qcom,kpss-acc.txt rockchip,pmu: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Specifies the syscon node controlling the cpu core power domains. @@ -338,7 +339,7 @@ properties: the cpu-core power-domains. secondary-boot-reg: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | Required for systems that have an "enable-method" property value of "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 15d411084065..2510eaa8906d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -726,6 +726,12 @@ properties: - const: dh,imx6ull-dhcor-som - const: fsl,imx6ull + - description: i.MX6ULL DHCOR SoM based Boards + items: + - const: marantec,imx6ull-dhcor-maveo-box + - const: dh,imx6ull-dhcor-som + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: @@ -901,6 +907,7 @@ properties: - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board + - fsl,imx8mm-evkb # i.MX8MM EVKB Board - gateworks,imx8mm-gw7904 - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit @@ -918,6 +925,12 @@ properties: - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm + - description: Emtop i.MX8MM based Boards + items: + - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 + - const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module + - const: fsl,imx8mm + - description: Engicam i.Core MX8M Mini SoM based boards items: - enum: @@ -1019,6 +1032,7 @@ properties: - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board + - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board - polyhex,imx8mp-debix # Polyhex Debix boards - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules diff --git a/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml new file mode 100644 index 000000000000..fb190db61525 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35 series SoC based platforms + +maintainers: + - Jacky Huang + +description: | + Boards with an ARMv8 based Nuvoton MA35 series SoC shall have + the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: MA35D1 based boards + items: + - enum: + - nuvoton,ma35d1-iot + - nuvoton,ma35d1-som + - const: nuvoton,ma35d1 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/npcm/npcm.yaml rename to Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml index 6871483947c5..d386744c8815 100644 --- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml# +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NPCM Platforms diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 3a2c908ff282..0c5381e081bd 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -100,7 +100,7 @@ properties: patternProperties: "^power-domain-": - $ref: "../power/power-domain.yaml#" + $ref: /schemas/power/power-domain.yaml# type: object description: | diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d9dd25695c3d..450f616774e0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -40,6 +40,7 @@ description: | msm8939 msm8953 msm8956 + msm8960 msm8974 msm8976 msm8992 @@ -69,6 +70,7 @@ description: | sdm845 sdx55 sdx65 + sdx75 sm4250 sm6115 sm6115p @@ -85,9 +87,15 @@ description: | The 'board' element must be one of the following strings: adp + ap-al02-c2 + ap-al02-c6 ap-al02-c7 + ap-al02-c8 + ap-al02-c9 ap-mi01.2 + ap-mi01.3 ap-mi01.6 + ap-mi01.9 cdp cp01-c1 dragonboard @@ -191,6 +199,7 @@ properties: - items: - enum: - qcom,msm8960-cdp + - samsung,expressatt - const: qcom,msm8960 - items: @@ -333,7 +342,9 @@ properties: - items: - enum: - qcom,ipq5332-ap-mi01.2 + - qcom,ipq5332-ap-mi01.3 - qcom,ipq5332-ap-mi01.6 + - qcom,ipq5332-ap-mi01.9 - const: qcom,ipq5332 - items: @@ -351,7 +362,11 @@ properties: - items: - enum: + - qcom,ipq9574-ap-al02-c2 + - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c8 + - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 - description: Sierra Wireless MangOH Green with WP8548 Module @@ -380,9 +395,9 @@ properties: - qcom,qru1000-idp - const: qcom,qru1000 - - description: Qualcomm Technologies, Inc. SC7180 IDP - items: + - items: - enum: + - acer,aspire1 - qcom,sc7180-idp - const: qcom,sc7180 @@ -819,6 +834,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + - items: - enum: - qcom,ipq6018-cp01 @@ -882,6 +902,11 @@ properties: - const: qcom,qrb4210 - const: qcom,sm4250 + - items: + - enum: + - fxtec,pro1x + - const: qcom,sm6115 + - items: - enum: - lenovo,j606f @@ -1042,6 +1067,7 @@ allOf: - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sdx75 - qcom,sm4250 - qcom,sm6115 - qcom,sm6125 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ec141c937b8b..ecdb72a519cb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -40,6 +40,11 @@ properties: - const: anbernic,rg353p - const: rockchip,rk3566 + - description: Anbernic RG353PS + items: + - const: anbernic,rg353ps + - const: rockchip,rk3566 + - description: Anbernic RG353V items: - const: anbernic,rg353v @@ -102,6 +107,12 @@ properties: - const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM - const: rockchip,rk3588 + - description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards + items: + - const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board + - const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM + - const: rockchip,rk3588 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 @@ -189,6 +200,7 @@ properties: items: - enum: - friendlyarm,nanopi-r2c + - friendlyarm,nanopi-r2c-plus - friendlyarm,nanopi-r2s - const: rockchip,rk3328 @@ -534,6 +546,11 @@ properties: - const: hugsun,x99 - const: rockchip,rk3399 + - description: Indiedroid Nova SBC + items: + - const: indiedroid,nova + - const: rockchip,rk3588s + - description: Khadas Edge series boards items: - enum: @@ -562,6 +579,13 @@ properties: - const: leez,p710 - const: rockchip,rk3399 + - description: Lunzn FastRhino R66S / R68S + items: + - enum: + - lunzn,fastrhino-r66s + - lunzn,fastrhino-r68s + - const: rockchip,rk3568 + - description: mqmaker MiQi items: - const: mqmaker,miqi diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index deb2cf971871..e3ffd8159ab6 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -72,6 +72,16 @@ properties: - const: samsung,exynos4210 - const: samsung,exynos4 + - description: Samsung Galaxy Tab3 family boards + items: + - enum: + - samsung,t310 # Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) + - samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311) + - samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315) + - const: samsung,tab3 + - const: samsung,exynos4212 + - const: samsung,exynos4 + - description: Exynos4412 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/socionext/synquacer.yaml b/Documentation/devicetree/bindings/arm/socionext/synquacer.yaml new file mode 100644 index 000000000000..72554a4f1c92 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/synquacer.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/synquacer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext Synquacer platform + +maintainers: + - Masahisa Kojima + - Jassi Brar + +description: + Socionext SC2A11B (Synquacer) SoC based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,developer-box + - const: socionext,synquacer + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ad8e51aa01b0..b63ff591ef8f 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -15,12 +15,13 @@ properties: oneOf: - items: - enum: - - st,stm32mp157-syscfg - - st,stm32mp151-pwr-mcu - - st,stm32-syscfg - st,stm32-power-config + - st,stm32-syscfg - st,stm32-tamp - st,stm32f4-gcan + - st,stm32mp151-pwr-mcu + - st,stm32mp157-syscfg + - st,stm32mp25-syscfg - const: syscon - items: - const: st,stm32-tamp diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 13e34241145b..4466b455bffa 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -155,6 +155,18 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 + - description: Phytec STM32MP1 SoM based Boards + items: + - const: phytec,phycore-stm32mp1-3 + - const: phytec,phycore-stm32mp157c-som + - const: st,stm32mp157 + + - description: ST STM32MP257 based Boards + items: + - enum: + - st,stm32mp257f-ev1 + - const: st,stm32mp257 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 013821f4a7b8..ee8fdd2da869 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -305,6 +305,12 @@ properties: - const: allwinner,i12-tvbox - const: allwinner,sun7i-a20 + - description: ICnova A20 ADB4006 + items: + - const: incircuit,icnova-a20-adb4006 + - const: incircuit,icnova-a20 + - const: allwinner,sun7i-a20 + - description: ICNova A20 SWAC items: - const: incircuit,icnova-a20-swac diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 0df41f5b7e2a..fcf956406168 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -167,6 +167,11 @@ properties: - const: nvidia,p3737-0000+p3701-0000 - const: nvidia,p3701-0000 - const: nvidia,tegra234 + - description: NVIDIA IGX Orin Development Kit + items: + - const: nvidia,p3740-0002+p3701-0008 + - const: nvidia,p3701-0008 + - const: nvidia,tegra234 - description: Jetson Orin NX items: - const: nvidia,p3767-0000 @@ -176,5 +181,14 @@ properties: - const: nvidia,p3768-0000+p3767-0000 - const: nvidia,p3767-0000 - const: nvidia,tegra234 + - description: Jetson Orin Nano + items: + - const: nvidia,p3767-0005 + - const: nvidia,tegra234 + - description: Jetson Orin Nano Developer Kit + items: + - const: nvidia,p3768-0000+p3767-0005 + - const: nvidia,p3767-0005 + - const: nvidia,tegra234 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e1183f90bb06..577eee95c893 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra + items: + - const: phytec,am625-phyboard-lyra-rdk + - const: phytec,am62-phycore-som + - const: ti,am625 + - description: K3 AM625 SoC items: - enum: @@ -33,6 +39,26 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia + - toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board + - toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia + - const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + - description: K3 AM642 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index 969cfe6dc434..f57ed0347894 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Platforms maintainers: - - Michal Simek + - Michal Simek description: | Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC @@ -61,10 +61,10 @@ properties: - const: xlnx,zynqmp-zc1254 - const: xlnx,zynqmp - - description: Xilinx internal board zc1275 + - description: Xilinx evaluation board zcu1275 items: - - const: xlnx,zynqmp-zc1275-revA - - const: xlnx,zynqmp-zc1275 + - const: xlnx,zynqmp-zcu1275-revA + - const: xlnx,zynqmp-zcu1275 - const: xlnx,zynqmp - description: Xilinx 96boards compatible board zcu100 diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 71364c6081ff..b29ce598f9aa 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ceva AHCI SATA Controller maintainers: - - Piyush Mehta + - Piyush Mehta description: | The Ceva SATA controller mostly conforms to the AHCI interface with some diff --git a/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml b/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml index 49304a1476ab..be95f6b97b41 100644 --- a/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml +++ b/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml @@ -40,6 +40,7 @@ properties: linux,keymap: true linux,no-autorepeat: + type: boolean description: Disable keyrepeat default-brightness-level: diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml index f089634f9466..6d7bca6c138e 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.yaml +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml @@ -97,7 +97,7 @@ properties: - enum: [ ick, fck, sys_clk ] - items: - const: fck - - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ] + - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ] - items: - const: fck - const: phy-clk diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml index 199818b2fb6d..cd0d763ce2f3 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings +title: Broadcom BCM63268 Timer Clock and Reset maintainers: - Álvaro Fernández Rojas diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml index ff9600474df2..0a6dc1a6e122 100644 --- a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NXP i.MX8MP AudioMIX Block Control Binding +title: NXP i.MX8MP AudioMIX Block Control maintainers: - Marek Vasut diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml new file mode 100644 index 000000000000..ba7ffc5b16a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MTMIPS SoCs System Controller + +maintainers: + - Sergio Paracuellos + +description: | + MediaTek MIPS and Ralink SoCs provides a system controller to allow + to access to system control registers. These registers include clock + and reset related ones so this node is both clock and reset provider + for the rest of the world. + + These SoCs have an XTAL from where the cpu clock is + provided as well as derived clocks for the bus and the peripherals. + +properties: + compatible: + items: + - enum: + - ralink,mt7620-sysc + - ralink,mt7628-sysc + - ralink,mt7688-sysc + - ralink,rt2880-sysc + - ralink,rt3050-sysc + - ralink,rt3052-sysc + - ralink,rt3352-sysc + - ralink,rt3883-sysc + - ralink,rt5350-sysc + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + description: + The first cell indicates the clock number. + const: 1 + + '#reset-cells': + description: + The first cell indicates the reset bit within the register. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + syscon@0 { + compatible = "ralink,rt5350-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..8f0c43683729 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. + maxItems: 5 + items: + enum: + - integer + - fractional + - spread-spectrum + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + + clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..3326dcd6766c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpassaudiocc + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml new file mode 100644 index 000000000000..98921fa236b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX75 + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX75 + + See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + +properties: + compatible: + const: qcom,sdx75-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC0 sgmiiphy rclk source + - description: EMAC0 sgmiiphy tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy rclk source + - description: EMAC1 sgmiiphy tclk source + - description: PCIE20 phy aux clock source + - description: PCIE_1 Pipe clock source + - description: PCIE_2 Pipe clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x80000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml new file mode 100644 index 000000000000..2320be920a5f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8450 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8550-gpucc.h + include/dt-bindings/reset/qcom,sm8450-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8450-gpucc + - qcom,sm8550-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml new file mode 100644 index 000000000000..fe1fda77b835 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8450 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + +properties: + compatible: + const: qcom,sm8450-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index c1f04830a832..02bd556bd91a 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx clocking wizard maintainers: - - Shubhrajyoti Datta + - Shubhrajyoti Datta description: The clocking wizard is a soft ip clocking block of Xilinx versal. It diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 229af98b1d30..5cbb34d0b61b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Versal clock controller maintainers: - - Michal Simek - - Jolly Shah - - Rajan Vaja + - Michal Simek description: | The clock controller is a hardware block of Xilinx versal clock tree. It diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml index ae515651fc6b..1c4d3eb87763 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -168,6 +168,13 @@ properties: offer the power, Capability Mismatch is set. Required for power sink and power dual role. + port: + $ref: /schemas/graph.yaml#/properties/port + description: OF graph bindings modeling a data bus to the connector, e.g. + there is a single High Speed (HS) port present in this connector. If there + is more than one bus (several port, with 'reg' property), they can be grouped + under 'ports'. + ports: $ref: /schemas/graph.yaml#/properties/ports description: OF graph bindings modeling any data bus to the connector @@ -322,6 +329,19 @@ examples: }; }; + # USB-C connector attached to SoC with a single High-Speed controller + - | + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + high_speed_ep: endpoint { + remote-endpoint = <&usb_hs_ep>; + }; + }; + }; + # USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220) # with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and # the output of MUX is connected to the SoC. diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml index ecf98a9e72b2..948e11ebe4ee 100644 --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml @@ -19,8 +19,8 @@ properties: interrupts: items: - - description: "Interrupt for flow 0" - - description: "Interrupt for flow 1" + - description: Interrupt for flow 0 + - description: Interrupt for flow 1 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml index 286dffa0671b..e879bc0be8e2 100644 --- a/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl,sec-v4.0-mon.yaml @@ -103,6 +103,12 @@ properties: wakeup-source: true linux,keycode: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 116 + deprecated: true + + linux,keycodes: + maxItems: 1 default: 116 required: diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml index 99be01539fcd..8dd36c2f76fd 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml @@ -11,9 +11,15 @@ maintainers: properties: compatible: - enum: - - fsl,imx23-dcp - - fsl,imx28-dcp + oneOf: + - enum: + - fsl,imx23-dcp + - fsl,imx28-dcp + - items: + - enum: + - fsl,imx6sl-dcp + - fsl,imx6ull-dcp + - const: fsl,imx28-dcp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml index e0fe63957888..a4006237aa89 100644 --- a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml @@ -2,8 +2,8 @@ # Copyright 2018 Linaro Ltd. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx cryptographic engine @@ -21,7 +21,7 @@ properties: const: intel,ixp4xx-crypto intel,npe-handle: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to the NPE this crypto engine diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml index 9e8fbd02b150..8aead97a585b 100644 --- a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx ZynqMP AES-GCM Hardware Accelerator maintainers: - - Kalyani Akula - - Michal Simek + - Kalyani Akula + - Michal Simek description: | The ZynqMP AES-GCM hardened cryptographic accelerator is used to diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml index c9b06885cc63..62f0521b0924 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml @@ -26,6 +26,7 @@ properties: const: dp force-hpd: + type: boolean description: Indicate driver need force hpd when hpd detect failed, this is used for some eDP screen which don not have a hpd signal. diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml index c4bf54397473..21d995f29a1e 100644 --- a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml @@ -20,6 +20,7 @@ properties: maxItems: 1 video-ports: + $ref: /schemas/types.yaml#/definitions/uint32 default: 0x230145 maximum: 0xffffff description: diff --git a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml index 9b701df5e9d2..2f0238b770eb 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml @@ -67,6 +67,7 @@ properties: items: - enum: - sainsmart18 + - shineworld,lh133k - const: panel-mipi-dbi-spi write-only: @@ -86,6 +87,8 @@ properties: Logic level supply for interface signals (Vddi). No need to set if this is the same as power-supply. + spi-3wire: true + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index c488308d7be1..53560052aaf0 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -74,8 +74,6 @@ properties: - const: 2 required: - - "#address-cells" - - "#size-cells" - compatible - reg - clocks diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml index 1dcb85a02a76..cc930660b794 100644 --- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -42,7 +42,7 @@ properties: enum: [ 0, 1 ] performance-domains: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array description: A phandle and performance domain specifier as defined by bindings of the performance controller/provider specified by phandle. diff --git a/Documentation/devicetree/bindings/eeprom/at25.yaml b/Documentation/devicetree/bindings/eeprom/at25.yaml index 11e2a95a7bcb..0e31bb36ebb1 100644 --- a/Documentation/devicetree/bindings/eeprom/at25.yaml +++ b/Documentation/devicetree/bindings/eeprom/at25.yaml @@ -33,6 +33,7 @@ properties: - microchip,25lc040 - st,m95m02 - st,m95256 + - st,m95640 - cypress,fm25 - const: atmel,at25 diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index f4eec4c42fb3..a41f9b9a196b 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -52,8 +52,7 @@ properties: - vendor,soc4-ip - vendor,soc3-ip - vendor,soc2-ip - - enum: - - vendor,soc1-ip + - const: vendor,soc1-ip # additionalItems being false is implied # minItems/maxItems equal to 2 is implied - items: @@ -85,6 +84,9 @@ properties: discouraged. clock-names: + # For single-entry lists in clocks, resets etc., the xxx-names often do not + # bring any value, especially if they copy the IP block name. In such case + # just skip the xxx-names. items: - const: bus diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 5824c43e9893..b138f3d23df8 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -34,6 +34,10 @@ properties: - description: SCMI compliant firmware with ARM SMC/HVC transport items: - const: arm,scmi-smc + - description: SCMI compliant firmware with ARM SMC/HVC transport + with shmem address(4KB-page, offset) as parameters + items: + - const: arm,scmi-smc-param - description: SCMI compliant firmware with SCMI Virtio transport. The virtio transport only supports a single device. items: @@ -214,7 +218,7 @@ properties: patternProperties: '^regulator@[0-9a-f]+$': type: object - $ref: "../regulator/regulator.yaml#" + $ref: /schemas/regulator/regulator.yaml# unevaluatedProperties: false properties: @@ -299,7 +303,9 @@ else: properties: compatible: contains: - const: arm,scmi-smc + enum: + - arm,scmi-smc + - arm,scmi-smc-param then: required: - arm,smc-id diff --git a/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml b/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml new file mode 100644 index 000000000000..684b15ba9ad0 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona family Secure Monitor bounce buffer + +description: + A bounce buffer used for non-secure to secure communications. + +maintainers: + - Florian Fainelli + +properties: + compatible: + items: + - enum: + - brcm,bcm11351-smc + - brcm,bcm21664-smc + - brcm,bcm23550-smc + - const: brcm,kona-smc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smc@3404c000 { + compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; + reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ + }; +... diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 83381f3a1341..bdbee58a542b 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -51,6 +51,7 @@ properties: - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 + - qcom,scm-sdx75 - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index f14f7b454f07..910bebe6cfa8 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx firmware driver maintainers: - - Nava kishore Manne + - Nava kishore Manne description: The zynqmp-firmware node describes the interface to platform firmware. ZynqMP has an interface to communicate with secure firmware. diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml index f47b6140a742..04dcadc2c20e 100644 --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq FPGA Manager maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml index ac6a207278d5..26f18834caa3 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Versal FPGA driver. maintainers: - - Nava kishore Manne + - Nava kishore Manne description: | Device Tree Versal FPGA bindings for the Versal SoC, controlled diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml index 00a8d92ff736..1390ae103b0b 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Ultrascale MPSoC FPGA Manager maintainers: - - Nava kishore Manne + - Nava kishore Manne description: | Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 572e1718f501..5e2496379a3c 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq GPIO controller maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml index f333ee2288e7..c1060e5fcef3 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx AXI GPIO controller maintainers: - - Neeli Srinivas + - Neeli Srinivas description: The AXI GPIO design provides a general purpose input/output interface diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml index 31c0fc345903..18e61aff2185 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -12,7 +12,7 @@ description: PS_MODE). Every pin can be configured as input/output. maintainers: - - Piyush Mehta + - Piyush Mehta properties: compatible: diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 0400a361875d..e796a1ff8c82 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -86,7 +86,7 @@ properties: const: 2 dynamic-power-coefficient: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: A u32 value that represents the running time dynamic power coefficient in units of uW/MHz/V^2. The diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 2a25384ca3ef..ca02baba5526 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -92,7 +92,7 @@ properties: dma-coherent: true dynamic-power-coefficient: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: A u32 value that represents the running time dynamic power coefficient in units of uW/MHz/V^2. The diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index 318122d95eb5..0fae1ef013be 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -33,6 +33,7 @@ properties: - rockchip,rk3228-mali - samsung,exynos4210-mali - stericsson,db8500-mali + - xlnx,zynqmp-mali - const: arm,mali-400 - items: - enum: diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml index cb24d7b3221c..ff57c5416ebc 100644 --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence I2C controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml index 32c821f97779..133855f11b4f 100644 --- a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml @@ -10,7 +10,7 @@ maintainers: - Conor Culhane allOf: - - $ref: "i3c.yaml#" + - $ref: i3c.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 037c3ae9f1c3..e34c9e78d38d 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -55,7 +55,7 @@ patternProperties: interrupt-names: true - linux-keycodes: + linux,keycodes: maxItems: 1 wakeup-source: true diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt deleted file mode 100644 index bde63f8f090e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ /dev/null @@ -1,38 +0,0 @@ -Amlogic meson GPIO interrupt controller - -Meson SoCs contains an interrupt controller which is able to watch the SoC -pads and generate an interrupt on edge or level. The controller is essentially -a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge -or level and polarity. It does not expose all 256 mux inputs because the -documentation shows that the upper part is not mapped to any pad. The actual -number of interrupt exposed depends on the SoC. - -Required properties: - -- compatible : must have "amlogic,meson8-gpio-intc" and either - "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or - "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or - "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or - "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) - "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) - "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) - "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) - "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2) -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. -- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These - are the hwirqs used on the parent interrupt controller. - -Example: - -gpio_interrupt: interrupt-controller@9880 { - compatible = "amlogic,meson-gxbb-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - meson,channel-interrupts = <64 65 66 67 68 69 70 71>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml new file mode 100644 index 000000000000..e84e4f33b358 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson GPIO interrupt controller + +maintainers: + - Heiner Kallweit + +description: | + Meson SoCs contains an interrupt controller which is able to watch the SoC + pads and generate an interrupt on edge or level. The controller is essentially + a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select + edge or level and polarity. It does not expose all 256 mux inputs because the + documentation shows that the upper part is not mapped to any pad. The actual + number of interrupts exposed depends on the SoC. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: amlogic,meson-gpio-intc + - items: + - enum: + - amlogic,meson8-gpio-intc + - amlogic,meson8b-gpio-intc + - amlogic,meson-gxbb-gpio-intc + - amlogic,meson-gxl-gpio-intc + - amlogic,meson-axg-gpio-intc + - amlogic,meson-g12a-gpio-intc + - amlogic,meson-sm1-gpio-intc + - amlogic,meson-a1-gpio-intc + - amlogic,meson-s4-gpio-intc + - const: amlogic,meson-gpio-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + amlogic,channel-interrupts: + description: Array with the upstream hwirq numbers + minItems: 8 + maxItems: 12 + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - amlogic,channel-interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml similarity index 98% rename from Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml rename to Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml index 50003880ee6f..d56ba65b17d1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip External Interrupt Controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/ralink,rt2880-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ralink,rt2880-intc.yaml new file mode 100644 index 000000000000..0fa952a9edfd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ralink,rt2880-intc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ralink,rt2880-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink SoCs Interrupt Controller + +maintainers: + - Sergio Paracuellos + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: + This interrupt controller support a central point for interrupt aggregation + for platform related blocks. + +properties: + compatible: + const: ralink,rt2880-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af..dc1f28e55266 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -57,14 +57,15 @@ properties: - const: andestech,nceplic100 - items: - enum: + - canaan,k210-plic - sifive,fu540-c000-plic - starfive,jh7100-plic - starfive,jh7110-plic - - canaan,k210-plic - const: sifive,plic-1.0.0 - items: - enum: - allwinner,sun20i-d1-plic + - thead,th1520-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml index 374ffe64016f..aeaddbf574b0 100644 --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml @@ -33,7 +33,7 @@ description: | +------------------------------------------+ maintainers: - - Shubhrajyoti Datta + - Shubhrajyoti Datta properties: compatible: diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml index dd645ddccb07..ea2342222408 100644 --- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml @@ -21,7 +21,9 @@ properties: - const: rockchip,rk3288-rga - const: rockchip,rk3399-rga - items: - - const: rockchip,rk3228-rga + - enum: + - rockchip,rk3228-rga + - rockchip,rk3568-rga - const: rockchip,rk3288-rga reg: diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index 8eb90c043d5d..e69de29bb2d1 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -1,78 +0,0 @@ -* Samsung Multi Format Codec (MFC) - -Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports high resolution decoding and encoding functionalities. -The MFC device driver is a v4l2 driver which can encode/decode -video raw/elementary streams and has support for all popular -video codecs. - -Required properties: - - compatible : value should be either one among the following - (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs - (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs - (c) "samsung,exynos3250-mfc", "samsung,mfc-v7" for MFC v7 - present in Exynos3250 SoC - (d) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC - (e) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC - (f) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - (g) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : MFC interrupt number to the CPU. - - clocks : from common clock binding: handle to mfc clock. - - clock-names : from common clock binding: must contain "mfc", - corresponding to entry in the clocks property. - -Optional properties: - - power-domains : power-domain property defined with a phandle - to respective power domain. - - memory-region : from reserved memory binding: phandles to two reserved - memory regions, first is for "left" mfc memory bus interfaces, - second if for the "right" mfc memory bus, used when no SYSMMU - support is available; used only by MFC v5 present in Exynos4 SoCs - -Obsolete properties: - - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region - property instead - - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock 273>; - clock-names = "mfc"; -}; - -Reserved memory specific DT entry for given board (see reserved memory binding -for more information): - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x800000>; - }; - - mfc_right: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x800000>; - }; -}; - -Board specific DT entry: - -codec@13400000 { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml new file mode 100644 index 000000000000..084b44582a43 --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Multi Format Codec (MFC) + +maintainers: + - Marek Szyprowski + - Aakarsh Jain + +description: + Multi Format Codec (MFC) is the IP present in Samsung SoCs which + supports high resolution decoding and encoding functionalities. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos5433-mfc # Exynos5433 + - samsung,mfc-v5 # Exynos4 + - samsung,mfc-v6 # Exynos5 + - samsung,mfc-v7 # Exynos5420 + - samsung,mfc-v8 # Exynos5800 + - samsung,mfc-v10 # Exynos7880 + - items: + - enum: + - samsung,exynos3250-mfc # Exynos3250 + - const: samsung,mfc-v7 # Fall back for Exynos3250 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + interrupts: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 2 + + iommu-names: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + memory-region: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-mfc + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: mfc + - const: sclk_mfc + iommus: + maxItems: 1 + iommus-names: false + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-mfc + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v5 + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: mfc + - const: sclk_mfc + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v6 + - samsung,mfc-v8 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: mfc + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v7 + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + iommus: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + #include + #include + #include + + codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml index 7d77823dbb7a..43daf837fc9f 100644 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx MIPI CSI-2 Receiver Subsystem maintainers: - - Vishal Sagar + - Vishal Sagar description: | The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml index 2fa44951cfde..f54e553e6c0e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -165,7 +165,7 @@ patternProperties: const: 0 lpddr2: - $ref: "ddr/jedec,lpddr2.yaml#" + $ref: ddr/jedec,lpddr2.yaml# type: object patternProperties: diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index e68c4306025a..87ff9ee098f5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -8,8 +8,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - - Michal Simek + - Michal Simek description: | Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml index bc9406929f6c..b049837ee669 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml @@ -129,7 +129,7 @@ patternProperties: The child device node represents the device connected to the GPMC bus. The device can be a NAND chip, SRAM device, NOR device or an ASIC. - $ref: "ti,gpmc-child.yaml" + $ref: ti,gpmc-child.yaml required: diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 8f72e2f8588a..75143db51411 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -8,8 +8,7 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - - Michal Simek + - Michal Simek description: The Zynq DDR ECC controller has an optional ECC support in half-bus width diff --git a/Documentation/devicetree/bindings/mips/ralink.yaml b/Documentation/devicetree/bindings/mips/ralink.yaml index 704b5b595127..53c1f6635377 100644 --- a/Documentation/devicetree/bindings/mips/ralink.yaml +++ b/Documentation/devicetree/bindings/mips/ralink.yaml @@ -80,6 +80,7 @@ properties: - enum: - gnubee,gb-pc1 - gnubee,gb-pc2 + - tplink,hc220-g5-v1 - const: mediatek,mt7621-soc additionalProperties: true diff --git a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt deleted file mode 100644 index 05b47232ed9e..000000000000 --- a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom Secure Monitor Bounce buffer ------------------------------------------------------ -This binding defines the location of the bounce buffer -used for non-secure to secure communications. - -Required properties: -- compatible : "brcm,kona-smc" -- DEPRECATED: compatible : "bcm,kona-smc" -- reg : Location and size of bounce buffer - -Example: - smc@3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; //1 KiB in SRAM - }; diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml index 1ab9588cdd89..2dc3e245fa5d 100644 --- a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml @@ -36,7 +36,7 @@ properties: description: A list of channels tied to this function, used for matching the function to a set of virtual channels. - $ref: "/schemas/types.yaml#/definitions/string-array" + $ref: /schemas/types.yaml#/definitions/string-array items: - const: fastrpcglink-apps-dsp @@ -48,14 +48,14 @@ properties: qcom,smd-channels: description: Channel name used for the RPM communication - $ref: "/schemas/types.yaml#/definitions/string-array" + $ref: /schemas/types.yaml#/definitions/string-array items: - const: fastrpcsmd-apps-dsp qcom,vmids: description: Virtual machine IDs for remote processor. - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: /schemas/types.yaml#/definitions/uint32-array "#address-cells": const: 1 diff --git a/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml new file mode 100644 index 000000000000..0c9a8444844c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 ESM + +maintainers: + - Neha Malcom Francis + +description: + The ESM (Error Signaling Module) is an IP block on TI K3 devices + that allows handling of safety events somewhat similar to what interrupt + controller would do. The safety signals have their separate paths within + the SoC, and they are handled by the ESM, which routes them to the proper + destination, which can be system reset, interrupt controller, etc. In the + simplest configuration the signals are just routed to reset the SoC. + +properties: + compatible: + const: ti,j721e-esm + + reg: + maxItems: 1 + + ti,esm-pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + integer array of ESM interrupt pins to route to external event pin + which can be used to reset the SoC. + minItems: 1 + maxItems: 255 + +required: + - compatible + - reg + - ti,esm-pins + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml index 57e4c87cb00b..f01a3988538c 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/nxp,88w8987-bt.yaml @@ -24,11 +24,12 @@ properties: - nxp,88w8997-bt fw-init-baudrate: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 115200 description: Chip baudrate after FW is downloaded and initialized. This property depends on the module vendor's - configuration. If this property is not specified, - 115200 is set as default. + configuration. required: - compatible diff --git a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml index 604985c8068e..56cbb42b5aea 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,qca2066-bt - qcom,qca6174-bt - qcom,qca9377-bt - qcom,wcn3990-bt @@ -98,6 +99,7 @@ allOf: compatible: contains: enum: + - qcom,qca2066-bt - qcom,qca6174-bt then: required: diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index fec1cc9b9a08..4aa521f1be8c 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -15,6 +15,9 @@ description: These chips also have a Bluetooth portion described in a separate binding. +allOf: + - $ref: ieee80211.yaml# + properties: compatible: oneOf: @@ -38,6 +41,7 @@ properties: - brcm,bcm4354-fmac - brcm,bcm4356-fmac - brcm,bcm4359-fmac + - brcm,bcm4366-fmac - cypress,cyw4373-fmac - cypress,cyw43012-fmac - const: brcm,bcm4329-fmac @@ -120,7 +124,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 8d8503dd934b..076566ef9cc8 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -18,8 +18,11 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,ipq5332-qfprom + - qcom,ipq6018-qfprom - qcom,ipq8064-qfprom - qcom,ipq8074-qfprom + - qcom,ipq9574-qfprom - qcom,msm8916-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 24c88942e59e..a4f61ced5e88 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -41,20 +41,24 @@ properties: - const: config clocks: + minItems: 5 items: - description: AHB clock for PCIe master - description: AHB clock for PCIe slave - description: AHB clock for PCIe dbi - description: APB clock for PCIe - description: Auxiliary clock for PCIe + - description: PIPE clock clock-names: + minItems: 5 items: - const: aclk_mst - const: aclk_slv - const: aclk_dbi - const: pclk - const: aux + - const: pipe msi-map: true @@ -70,13 +74,19 @@ properties: maxItems: 1 ranges: - maxItems: 2 + minItems: 2 + maxItems: 3 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - const: pipe + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe vpcie3v3-supply: true diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 24ddc2855b94..4734be456bde 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CPM Host Controller device tree for Xilinx Versal SoCs maintainers: - - Bharat Kumar Gogada + - Bharat Kumar Gogada allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 26f2b887cfc1..a9f78344efdb 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt6795-mipi-tx + - const: mediatek,mt8173-mipi-tx - items: - enum: - mediatek,mt8365-mipi-tx diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 1ab0f8dde477..2120ef71a78d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -27,6 +27,8 @@ properties: - st,stm32mp135-pinctrl - st,stm32mp157-pinctrl - st,stm32mp157-z-pinctrl + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl '#address-cells': const: 1 @@ -56,7 +58,7 @@ properties: Indicates the SOC package used. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] patternProperties: '^gpio@[0-9a-f]*$': diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml index 598a042850b8..b85f9e36ce4b 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Pinctrl maintainers: - - Sai Krishna Potthuri + - Sai Krishna Potthuri description: | Please refer to pinctrl-bindings.txt in this directory for details of the diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 2722dc7bb03d..24ad0614e61b 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx ZynqMP Pinctrl maintainers: - - Sai Krishna Potthuri - - Rajan Vaja + - Sai Krishna Potthuri description: | Please refer to pinctrl-bindings.txt in this directory for details of the diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt deleted file mode 100644 index 93f31ca1ef4b..000000000000 --- a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt +++ /dev/null @@ -1,14 +0,0 @@ -Broadcom Kona Family Reset Manager ----------------------------------- - -The reset manager is used on the Broadcom BCM21664 SoC. - -Required properties: - - compatible: brcm,bcm21664-resetmgr - - reg: memory address & range - -Example: - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml new file mode 100644 index 000000000000..3e28a59d718f --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/brcm,bcm21664-resetmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona family reset manager + +maintainers: + - Florian Fainelli + +properties: + compatible: + const: brcm,bcm21664-resetmgr + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + reset-controller@35001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x35001f00 0x24>; + }; +... diff --git a/Documentation/devicetree/bindings/power/reset/restart-handler.yaml b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml index 1f9a2aac53c0..f2ffdd29d52a 100644 --- a/Documentation/devicetree/bindings/power/reset/restart-handler.yaml +++ b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/power/reset/restart-handler.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Restart and shutdown handler generic binding +title: Restart and shutdown handler Common Properties maintainers: - Sebastian Reichel diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml index 11f1f98c1cdc..45792e216981 100644 --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq MPSoC Power Management maintainers: - - Michal Simek + - Michal Simek description: | The zynqmp-power node describes the power management configurations. diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml index ab45df80345d..d84268b59784 100644 --- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -11,7 +11,7 @@ maintainers: - Claudiu Beznea allOf: - - $ref: "pwm.yaml#" + - $ref: pwm.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..153e146df7d4 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -22,7 +22,9 @@ properties: - mediatek,mt8173-disp-pwm - mediatek,mt8183-disp-pwm - items: - - const: mediatek,mt8167-disp-pwm + - enum: + - mediatek,mt6795-disp-pwm + - mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm - items: - enum: diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml index a34cbc13f691..6ffbed204c25 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml @@ -25,7 +25,7 @@ properties: const: 3 fsl,pwm-number: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: u32 value representing the number of PWM devices required: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml index c6d86964b72a..35f0bb38f7b2 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Common TI PRU Consumer Binding +title: TI PRU Consumer Common Properties maintainers: - Suman Anna diff --git a/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml b/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml index 05b6648b3458..851ec24d6142 100644 --- a/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/framebuffer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reserved-memory/framebuffer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: /reserved-memory framebuffer node bindings +title: /reserved-memory framebuffer node maintainers: - devicetree-spec@vger.kernel.org diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 000000000000..34c5c1c08ec1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + items: + - const: nuvoton,ma35d1-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + + system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x40460000 0x200>; + #reset-cells = <1>; + }; +... + diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt deleted file mode 100644 index d27ccb5d04fc..000000000000 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,32 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-reset" - For OX820, should be "oxsemi,ox820-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be : - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be : - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -Reset indices are in dt-bindings include files : -- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h -- For OX820: include/dt-bindings/reset/oxsemi,ox820.h - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml new file mode 100644 index 000000000000..e62f6821372e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD SoC-based boards + +maintainers: + - Jisheng Zhang + +description: + T-HEAD SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A + items: + - enum: + - sipeed,lichee-pi-4a + - const: sipeed,lichee-module-4a + - const: thead,th1520 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml index 7ed0230f6c67..d1f5eb996dba 100644 --- a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -11,7 +11,7 @@ description: The RTC controller has separate IRQ lines for seconds and alarm. maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: rtc.yaml# diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index a8b323d7bf94..e35ad1109efc 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence UART Controller maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000000..a76af0f6009b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen + - Jacky Huang + +allOf: + - $ref: serial.yaml + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + }; +... diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml new file mode 100644 index 000000000000..1a952f569803 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm23550-cdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM23550 Cluster Dormant Control + +description: + The Cluster Dormant Control block keeps the CPU in idle state. A command + needs to be sent to this block to bring the CPU into running state. + +maintainers: + - Florian Fainelli + +properties: + compatible: + const: brcm,bcm23550-cdc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cdc@3fe0e000 { + compatible = "brcm,bcm23550-cdc"; + reg = <0x3fe0e000 0x78>; + }; +... diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 3fefd634bc69..a06ac2177444 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt2701-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap + - mediatek,mt6795-pwrap - mediatek,mt6797-pwrap - mediatek,mt6873-pwrap - mediatek,mt7622-pwrap diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml rename to Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml index 94e72f25b331..23e7e4ea01ff 100644 --- a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml +++ b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Global Control Registers block in Nuvoton SoCs diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index 798f15588ee2..9dc8e48c8af4 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -26,6 +26,7 @@ properties: items: - enum: - qcom,qdu1000-aoss-qmp + - qcom,sa8775p-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index 14dd29471c80..f2c5ec7e6437 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -55,9 +55,10 @@ additionalProperties: false examples: - | eud@88e0000 { - compatible = "qcom,sc7280-eud","qcom,eud"; + compatible = "qcom,sc7280-eud", "qcom,eud"; reg = <0x88e0000 0x2000>, <0x88e2000 0x1000>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -67,6 +68,7 @@ examples: remote-endpoint = <&usb2_role_switch>; }; }; + port@1 { reg = <1>; eud_con: endpoint { diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml new file mode 100644 index 000000000000..031800985b5e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm RPM (Resource Power Manager) architecture includes a concept + of "RPM Masters". They can be thought of as "the local gang leaders", usually + spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions + (particularly around entering hardware-driven low power modes: XO shutdown + and total system-wide power collapse) are first made at Master-level, and + only then aggregated for the entire system. + + The Master Stats provide a few useful bits that can be used to assess whether + our device has entered the desired low-power mode, how long it took to do so, + the duration of that residence, how long it took to come back online, + how many times a given sleep state was entered and which cores are actively + voting for staying awake. + + This scheme has been used on various SoCs in the 2013-2023 era, with some + newer or higher-end designs providing this information through an SMEM query. + +properties: + compatible: + const: qcom,rpm-master-stats + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to an RPM MSG RAM slice containing the master stats + minItems: 1 + maxItems: 5 + + qcom,master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + The name of the RPM Master which owns the MSG RAM slice where this + instance of Master Stats resides + minItems: 1 + maxItems: 5 + +required: + - compatible + - qcom,rpm-msg-ram + - qcom,master-names + +additionalProperties: false + +examples: + - | + stats { + compatible = "qcom,rpm-master-stats"; + qcom,rpm-msg-ram = <&apss_master_stats>, + <&mpss_master_stats>, + <&adsp_master_stats>, + <&cdsp_master_stats>, + <&tz_master_stats>; + qcom,master-names = "APSS", + "MPSS", + "ADSP", + "CDSP", + "TZ"; + }; +... diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index a4046ba60846..af632d0e0355 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -124,6 +124,7 @@ required: - qcom,tcs-offset - reg - reg-names + - power-domains additionalProperties: false @@ -179,6 +180,7 @@ examples: , , ; + power-domains = <&CLUSTER_PD>; }; - | diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index ea86569a40d3..65c02a7fef80 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -81,6 +81,7 @@ if: contains: enum: - qcom,rpm-apq8084 + - qcom,rpm-msm8226 - qcom,rpm-msm8916 - qcom,rpm-msm8936 - qcom,rpm-msm8974 diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 65a2d5a4f28d..e4fa6a07b4fa 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -24,6 +24,7 @@ properties: - rockchip,rk3588-bigcore1-grf - rockchip,rk3588-ioc - rockchip,rk3588-php-grf + - rockchip,rk3588-pipe-phy-grf - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf @@ -52,6 +53,7 @@ properties: - rockchip,rk3399-pmugrf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf + - rockchip,rk3588-usb2phy-grf - rockchip,rv1108-grf - rockchip,rv1108-pmugrf - rockchip,rv1126-grf @@ -119,7 +121,7 @@ allOf: usbphy: type: object - $ref: "/schemas/phy/rockchip-usb-phy.yaml#" + $ref: /schemas/phy/rockchip-usb-phy.yaml# unevaluatedProperties: false @@ -134,14 +136,14 @@ allOf: gpio: type: object - $ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#" + $ref: /schemas/gpio/rockchip,rk3328-grf-gpio.yaml# unevaluatedProperties: false power-controller: type: object - $ref: "/schemas/power/rockchip,power-controller.yaml#" + $ref: /schemas/power/rockchip,power-controller.yaml# unevaluatedProperties: false @@ -156,7 +158,7 @@ allOf: mipi-dphy-rx0: type: object - $ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#" + $ref: /schemas/phy/rockchip-mipi-dphy-rx0.yaml# unevaluatedProperties: false @@ -184,7 +186,7 @@ allOf: reboot-mode: type: object - $ref: "/schemas/power/reset/syscon-reboot-mode.yaml#" + $ref: /schemas/power/reset/syscon-reboot-mode.yaml# unevaluatedProperties: false @@ -199,6 +201,7 @@ allOf: - rockchip,rk3308-usb2phy-grf - rockchip,rk3328-usb2phy-grf - rockchip,rk3399-grf + - rockchip,rk3588-usb2phy-grf - rockchip,rv1108-grf then: @@ -238,7 +241,7 @@ allOf: io-domains: type: object - $ref: "/schemas/power/rockchip-io-domain.yaml#" + $ref: /schemas/power/rockchip-io-domain.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 5d8d9497f18e..e1d716df5dfa 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -17,6 +17,7 @@ select: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -36,6 +37,7 @@ properties: - enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -50,6 +52,7 @@ properties: - enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5420-pmu @@ -125,6 +128,7 @@ allOf: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5410-pmu @@ -143,6 +147,7 @@ allOf: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5420-pmu diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index b0f83b5c2cdd..b7552739b554 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence SPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml index 6bd83836eded..4beb3af0416d 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 226d8b493b57..e5199b109dad 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml index 83e8fb4a548d..7ea8fb42ce2c 100644 --- a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml @@ -14,7 +14,7 @@ allOf: - $ref: spi-controller.yaml# maintainers: - - Michal Simek + - Michal Simek # Everything else is described in the common file properties: diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..ac99883a3f29 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -14,13 +14,18 @@ description: |+ for multiple SoCs to control a single SPMI master. allOf: - - $ref: "spmi.yaml" + - $ref: spmi.yaml properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi reg: maxItems: 2 diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 0548e8e0d30b..8025a852bc9c 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -18,8 +18,10 @@ properties: items: - enum: - qcom,apq8064-imem + - qcom,msm8226-imem - qcom,msm8974-imem - qcom,qcs404-imem + - qcom,qdu1000-imem - qcom,sc7180-imem - qcom,sc7280-imem - qcom,sdm630-imem diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 993430be355b..0922d1f71ba8 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -94,6 +94,7 @@ patternProperties: - samsung,exynos4210-sysram - samsung,exynos4210-sysram-ns - socionext,milbeaut-smp-sram + - stericsson,u8500-esram reg: description: diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml index bc5e6f226295..dbba780c9b02 100644 --- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence TTC - Triple Timer Counter maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index 716c6afcca1f..dbe1267af06a 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -31,9 +31,13 @@ properties: - enum: - fsl,imx6sl-gpt - fsl,imx6sx-gpt + - fsl,imx8mp-gpt - fsl,imxrt1050-gpt - fsl,imxrt1170-gpt - const: fsl,imx6dl-gpt + - items: + - const: fsl,imx6ul-gpt + - const: fsl,imx6sx-gpt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1..a0185e15a42f 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -29,14 +29,15 @@ properties: oneOf: - items: - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - starfive,jh7110-clint - - canaan,k210-clint - - const: sifive,clint0 + - canaan,k210-clint # Canaan Kendryte K210 + - sifive,fu540-c000-clint # SiFive FU540 + - starfive,jh7100-clint # StarFive JH7100 + - starfive,jh7110-clint # StarFive JH7110 + - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 @@ -45,14 +46,9 @@ properties: description: For the QEMU virt machine only description: - Should be ",-clint" and "sifive,clint". - Supported compatible strings are - - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated - onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and - "sifive,clint0" for the SiFive CLINT v0 IP block with no chip - integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details + Should be ",-clint", followed by "sifive,clint" + when compatible with a SiFive CLINT. Please refer to + sifive-blocks-ip-versioning.txt for details regarding the latter. reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 246863a9bc7e..ba2bfb547909 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -139,6 +139,8 @@ properties: - infineon,ir38164 # Infineon IR38263 Voltage Regulator - infineon,ir38263 + # Infineon IRPS5401 Voltage Regulator (PMIC) + - infineon,irps5401 # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) - infineon,slb9635tt # Infineon SLB9645 I2C TPM (new protocol, max 400khz) diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 098b73134a1b..bb373eb025a5 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - - Manish Narani + - Piyush Mehta properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index e2270ce0c56b..c6e661e8915c 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -91,6 +91,7 @@ properties: phys: minItems: 1 + maxItems: 2 description: Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. @@ -99,13 +100,7 @@ properties: minItems: 1 items: - const: usb2-0 - - const: usb2-1 - - const: usb2-2 - - const: usb2-3 - const: usb3-0 - - const: usb3-1 - - const: usb3-2 - - const: usb3-3 avddio-usb-supply: description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml index 04c123c7252a..868dffe314bc 100644 --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx udc controller maintainers: - - Manish Narani + - Piyush Mehta properties: compatible: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 82d39ab0231b..af60bf1a6664 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -388,6 +388,8 @@ patternProperties: description: EDIMAX Technology Co., Ltd "^edt,.*": description: Emerging Display Technologies + "^ees,.*": + description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc "^einfochips,.*": @@ -617,6 +619,8 @@ patternProperties: description: Integrated Micro-Electronics Inc. "^incircuit,.*": description: In-Circuit GmbH + "^indiedroid,.*": + description: Indiedroid "^inet-tek,.*": description: Shenzhen iNet Mobile Internet Technology Co., Ltd "^infineon,.*": @@ -781,6 +785,8 @@ patternProperties: description: Nanjing Loongmasses Ltd. "^lsi,.*": description: LSI Corp. (LSI Logic) + "^lunzn,.*": + description: Shenzhen Lunzn Technology Co., Ltd. "^lwn,.*": description: Liebherr-Werk Nenzing GmbH "^lxa,.*": @@ -1189,6 +1195,8 @@ patternProperties: description: SHIFT GmbH "^shimafuji,.*": description: Shimafuji Electric, Inc. + "^shineworld,.*": + description: ShineWorld Innovations "^shiratech,.*": description: Shiratech Solutions "^si-en,.*": @@ -1267,6 +1275,8 @@ patternProperties: description: SpinalHDL "^sprd,.*": description: Spreadtrum Communications Inc. + "^square,.*": + description: Square "^ssi,.*": description: SSI Computer Corp "^sst,.*": @@ -1339,6 +1349,8 @@ patternProperties: description: Technologic Systems "^techstar,.*": description: Shenzhen Techstar Electronics Co., Ltd. + "^teejet,.*": + description: TeeJet "^teltonika,.*": description: Teltonika Networks "^tempo,.*": diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml index 8444c56dd602..dc1ff39d05a0 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx AXI/PLB softcore and window Watchdog Timer maintainers: - - Shubhrajyoti Datta - - Srinivas Neeli + - Shubhrajyoti Datta + - Srinivas Neeli description: The Timebase watchdog timer(WDT) is a free-running 32 bit counter. diff --git a/Documentation/filesystems/ext4/journal.rst b/Documentation/filesystems/ext4/journal.rst index a6bef5293a60..6e8fb2d4b46f 100644 --- a/Documentation/filesystems/ext4/journal.rst +++ b/Documentation/filesystems/ext4/journal.rst @@ -260,8 +260,13 @@ which is 1024 bytes long: - s_num_fc_blocks - Number of fast commit blocks in the journal. * - 0x58 + - __be32 + - s_head + - Block number of the head (first unused block) of the journal, only + up-to-date when the journal is empty. + * - 0x5C - __u32 - - s_padding[42] + - s_padding[40] - * - 0xFC - __be32 diff --git a/Documentation/filesystems/nfs/exporting.rst b/Documentation/filesystems/nfs/exporting.rst index 0e98edd353b5..3d97b8d8f735 100644 --- a/Documentation/filesystems/nfs/exporting.rst +++ b/Documentation/filesystems/nfs/exporting.rst @@ -122,8 +122,8 @@ are exportable by setting the s_export_op field in the struct super_block. This field must point to a "struct export_operations" struct which has the following members: - encode_fh (optional) - Takes a dentry and creates a filehandle fragment which can later be used + encode_fh (optional) + Takes a dentry and creates a filehandle fragment which may later be used to find or create a dentry for the same object. The default implementation creates a filehandle fragment that encodes a 32bit inode and generation number for the inode encoded, and if necessary the diff --git a/Documentation/process/maintainer-handbooks.rst b/Documentation/process/maintainer-handbooks.rst index d783060b4cc6..fe24cb665fb7 100644 --- a/Documentation/process/maintainer-handbooks.rst +++ b/Documentation/process/maintainer-handbooks.rst @@ -15,5 +15,6 @@ Contents: :numbered: :maxdepth: 2 - maintainer-tip maintainer-netdev + maintainer-soc + maintainer-tip diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst new file mode 100644 index 000000000000..49f08289d62c --- /dev/null +++ b/Documentation/process/maintainer-soc.rst @@ -0,0 +1,177 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============= +SoC Subsystem +============= + +Overview +-------- + +The SoC subsystem is a place of aggregation for SoC-specific code. +The main components of the subsystem are: + +* devicetrees for 32- & 64-bit ARM and RISC-V +* 32-bit ARM board files (arch/arm/mach*) +* 32- & 64-bit ARM defconfigs +* SoC-specific drivers across architectures, in particular for 32- & 64-bit + ARM, RISC-V and Loongarch + +These "SoC-specific drivers" do not include clock, GPIO etc drivers that have +other top-level maintainers. The drivers/soc/ directory is generally meant +for kernel-internal drivers that are used by other drivers to provide SoC- +specific functionality like identifying an SoC revision or interfacing with +power domains. + +The SoC subsystem also serves as an intermediate location for changes to +drivers/bus, drivers/firmware, drivers/reset and drivers/memory. The addition +of new platforms, or the removal of existing ones, often go through the SoC +tree as a dedicated branch covering multiple subsystems. + +The main SoC tree is housed on git.kernel.org: + https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/ + +Clearly this is quite a wide range of topics, which no one person, or even +small group of people are capable of maintaining. Instead, the SoC subsystem +is comprised of many submaintainers, each taking care of individual platforms +and driver subdirectories. +In this regard, "platform" usually refers to a series of SoCs from a given +vendor, for example, Nvidia's series of Tegra SoCs. Many submaintainers operate +on a vendor level, responsible for multiple product lines. For several reasons, +including acquisitions/different business units in a company, things vary +significantly here. The various submaintainers are documented in the +MAINTAINERS file. + +Most of these submaintainers have their own trees where they stage patches, +sending pull requests to the main SoC tree. These trees are usually, but not +always, listed in MAINTAINERS. The main SoC maintainers can be reached via the +alias soc@kernel.org if there is no platform-specific maintainer, or if they +are unresponsive. + +What the SoC tree is not, however, is a location for architecture-specific code +changes. Each architecture has its own maintainers that are responsible for +architectural details, CPU errata and the like. + +Information for (new) Submaintainers +------------------------------------ + +As new platforms spring up, they often bring with them new submaintainers, +many of whom work for the silicon vendor, and may not be familiar with the +process. + +Devicetree ABI Stability +~~~~~~~~~~~~~~~~~~~~~~~~ + +Perhaps one of the most important things to highlight is that dt-bindings +document the ABI between the devicetree and the kernel. +Please read Documentation/devicetree/bindings/ABI.rst. + +If changes are being made to a devicetree that are incompatible with old +kernels, the devicetree patch should not be applied until the driver is, or an +appropriate time later. Most importantly, any incompatible changes should be +clearly pointed out in the patch description and pull request, along with the +expected impact on existing users, such as bootloaders or other operating +systems. + +Driver Branch Dependencies +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A common problem is synchronizing changes between device drivers and devicetree +files. Even if a change is compatible in both directions, this may require +coordinating how the changes get merged through different maintainer trees. + +Usually the branch that includes a driver change will also include the +corresponding change to the devicetree binding description, to ensure they are +in fact compatible. This means that the devicetree branch can end up causing +warnings in the "make dtbs_check" step. If a devicetree change depends on +missing additions to a header file in include/dt-bindings/, it will fail the +"make dtbs" step and not get merged. + +There are multiple ways to deal with this: + +* Avoid defining custom macros in include/dt-bindings/ for hardware constants + that can be derived from a datasheet -- binding macros in header files should + only be used as a last resort if there is no natural way to define a binding + +* Use literal values in the devicetree file in place of macros even when a + header is required, and change them to the named representation in a + following release + +* Defer the devicetree changes to a release after the binding and driver have + already been merged + +* Change the bindings in a shared immutable branch that is used as the base for + both the driver change and the devicetree changes + +* Add duplicate defines in the devicetree file guarded by an #ifndef section, + removing them in a later release + +Devicetree Naming Convention +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The general naming scheme for devicetree files is as follows. The aspects of a +platform that are set at the SoC level, like CPU cores, are contained in a file +named $soc.dtsi, for example, jh7100.dtsi. Integration details, that will vary +from board to board, are described in $soc-$board.dts. An example of this is +jh7100-beaglev-starlight.dts. Often many boards are variations on a theme, and +frequently there are intermediate files, such as jh7100-common.dtsi, which sit +between the $soc.dtsi and $soc-$board.dts files, containing the descriptions of +common hardware. + +Some platforms also have System on Modules, containing an SoC, which are then +integrated into several different boards. For these platforms, $soc-$som.dtsi +and $soc-$som-$board.dts are typical. + +Directories are usually named after the vendor of the SoC at the time of its +inclusion, leading to some historical directory names in the tree. + +Validating Devicetree Files +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +``make dtbs_check`` can be used to validate that devicetree files are compliant +with the dt-bindings that describe the ABI. Please read the section +"Running checks" of Documentation/devicetree/bindings/writing-schema.rst for +more information on the validation of devicetrees. + +For new platforms, or additions to existing ones, ``make dtbs_check`` should not +add any new warnings. For RISC-V, as it has the advantage of being a newer +architecture, ``make dtbs_check W=1`` is required to not add any new warnings. +If in any doubt about a devicetree change, reach out to the devicetree +maintainers. + +Branches and Pull Requests +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Just as the main SoC tree has several branches, it is expected that +submaintainers will do the same. Driver, defconfig and devicetree changes should +all be split into separate branches and appear in separate pull requests to the +SoC maintainers. Each branch should be usable by itself and avoid +regressions that originate from dependencies on other branches. + +Small sets of patches can also be sent as separate emails to soc@kernel.org, +grouped into the same categories. + +If changes do not fit into the normal patterns, there can be additional +top-level branches, e.g. for a treewide rework, or the addition of new SoC +platforms including dts files and drivers. + +Branches with a lot of changes can benefit from getting split up into separate +topics branches, even if they end up getting merged into the same branch of the +SoC tree. An example here would be one branch for devicetree warning fixes, one +for a rework and one for newly added boards. + +Another common way to split up changes is to send an early pull request with the +majority of the changes at some point between rc1 and rc4, following up with one +or more smaller pull requests towards the end of the cycle that can add late +changes or address problems identified while testing the first set. + +While there is no cut-off time for late pull requests, it helps to only send +small branches as time gets closer to the merge window. + +Pull requests for bugfixes for the current release can be sent at any time, but +again having multiple smaller branches is better than trying to combine too many +patches into one pull request. + +The subject line of a pull request should begin with "[GIT PULL]" and made using +a signed tag, rather than a branch. This tag should contain a short description +summarising the changes in the pull request. For more detail on sending pull +requests, please see Documentation/maintainer/pull-requests.rst. diff --git a/MAINTAINERS b/MAINTAINERS index 833b0bcbfb7f..918940a20f3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1627,6 +1627,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained C: irc://irc.libera.chat/armlinux T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git +F: Documentation/process/maintainer-soc.rst F: arch/arm/boot/dts/Makefile F: arch/arm64/boot/dts/Makefile @@ -1658,9 +1659,9 @@ F: Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml F: Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml -F: arch/arm/boot/dts/arm-realview-* -F: arch/arm/boot/dts/integrator* -F: arch/arm/boot/dts/versatile* +F: arch/arm/boot/dts/arm/arm-realview-* +F: arch/arm/boot/dts/arm/integrator* +F: arch/arm/boot/dts/arm/versatile* F: arch/arm/mach-versatile/ F: drivers/bus/arm-integrator-lm.c F: drivers/clk/versatile/ @@ -1831,7 +1832,7 @@ F: Documentation/devicetree/bindings/net/actions,owl-emac.yaml F: Documentation/devicetree/bindings/pinctrl/actions,* F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt -F: arch/arm/boot/dts/owl-* +F: arch/arm/boot/dts/actions/ F: arch/arm/mach-actions/ F: arch/arm64/boot/dts/actions/ F: drivers/clk/actions/ @@ -1905,10 +1906,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-amlogic@lists.infradead.org S: Maintained W: http://linux-meson.com/ -F: arch/arm/boot/dts/meson* +F: Documentation/devicetree/bindings/phy/amlogic* +F: arch/arm/boot/dts/amlogic/ F: arch/arm/mach-meson/ F: arch/arm64/boot/dts/amlogic/ F: drivers/mmc/host/meson* +F: drivers/phy/amlogic/ F: drivers/pinctrl/meson/ F: drivers/rtc/rtc-meson* F: drivers/soc/amlogic/ @@ -1919,7 +1922,7 @@ M: Tsahee Zidenberg M: Antoine Tenart L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/alpine* +F: arch/arm/boot/dts/amazon/ F: arch/arm/mach-alpine/ F: arch/arm64/boot/dts/amazon/ F: drivers/*/*alpine* @@ -1990,7 +1993,7 @@ M: Lars Persson L: linux-arm-kernel@axis.com S: Maintained F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt -F: arch/arm/boot/dts/artpec6* +F: arch/arm/boot/dts/axis/ F: arch/arm/mach-artpec F: drivers/clk/axis F: drivers/crypto/axis @@ -2018,7 +2021,7 @@ S: Supported Q: https://patchwork.ozlabs.org/project/linux-aspeed/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git F: Documentation/devicetree/bindings/arm/aspeed/ -F: arch/arm/boot/dts/aspeed-* +F: arch/arm/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ N: aspeed @@ -2037,8 +2040,7 @@ ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/ecx-*.dts* -F: arch/arm/boot/dts/highbank.dts +F: arch/arm/boot/dts/calxeda/ F: arch/arm/mach-highbank/ ARM/CAVIUM THUNDER NETWORK DRIVER @@ -2086,7 +2088,7 @@ ARM/CONEXANT DIGICOLOR MACHINE SUPPORT M: Baruch Siach L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/cx92755* +F: arch/arm/boot/dts/cnxt/ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS @@ -2125,7 +2127,7 @@ F: Documentation/devicetree/bindings/arm/gemini.yaml F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.yaml -F: arch/arm/boot/dts/gemini* +F: arch/arm/boot/dts/gemini/ F: arch/arm/mach-gemini/ F: drivers/crypto/gemini/ F: drivers/net/ethernet/cortina/ @@ -2178,7 +2180,8 @@ R: NXP Linux Team L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm64/boot/dts/freescale/ +F: arch/arm/boot/dts/nxp/imx/ +F: arch/arm/boot/dts/nxp/mxs/ X: arch/arm64/boot/dts/freescale/fsl-* X: arch/arm64/boot/dts/freescale/qoriq-* X: drivers/media/i2c/ @@ -2191,7 +2194,7 @@ M: Li Yang L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/ls1021a* +F: arch/arm/boot/dts/nxp/ls/ F: arch/arm64/boot/dts/freescale/fsl-* F: arch/arm64/boot/dts/freescale/qoriq-* @@ -2203,7 +2206,7 @@ R: Stefan Agner L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/vf* +F: arch/arm/boot/dts/nxp/vf/ F: arch/arm/mach-imx/*vf610* ARM/GUMSTIX MACHINE SUPPORT @@ -2217,9 +2220,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.hisilicon.com T: git https://github.com/hisilicon/linux-hisi.git -F: arch/arm/boot/dts/hi3* -F: arch/arm/boot/dts/hip* -F: arch/arm/boot/dts/hisi* +F: arch/arm/boot/dts/hisilicon/ F: arch/arm/mach-hisi/ F: arch/arm64/boot/dts/hisilicon/ @@ -2241,8 +2242,7 @@ F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst -F: arch/arm/boot/dts/hpe-bmc* -F: arch/arm/boot/dts/hpe-gxp* +F: arch/arm/boot/dts/hpe/ F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c @@ -2256,7 +2256,7 @@ M: Javier Martinez Canillas L: linux-omap@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/omap3-igep* +F: arch/arm/boot/dts/ti/omap/omap3-igep* ARM/INTEL IXP4XX ARM ARCHITECTURE M: Linus Walleij @@ -2269,7 +2269,7 @@ F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml -F: arch/arm/boot/dts/intel-ixp* +F: arch/arm/boot/dts/intel/ixp/ F: arch/arm/mach-ixp4xx/ F: drivers/bus/intel-ixp4xx-eb.c F: drivers/clocksource/timer-ixp4xx.c @@ -2301,7 +2301,7 @@ M: Vladimir Zapolskiy L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt -F: arch/arm/boot/dts/lpc43* +F: arch/arm/boot/dts/nxp/lpc/lpc43* F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/controllers/nxp-spifi.c @@ -2314,7 +2314,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/vzapolskiy/linux-lpc32xx.git F: Documentation/devicetree/bindings/i2c/i2c-pnx.txt -F: arch/arm/boot/dts/lpc32* +F: arch/arm/boot/dts/nxp/lpc/lpc32* F: arch/arm/mach-lpc32xx/ F: drivers/i2c/busses/i2c-pnx.c F: drivers/net/ethernet/nxp/lpc_eth.c @@ -2332,8 +2332,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt F: Documentation/devicetree/bindings/soc/dove/ -F: arch/arm/boot/dts/dove* -F: arch/arm/boot/dts/orion5x* +F: arch/arm/boot/dts/marvell/dove* +F: arch/arm/boot/dts/marvell/orion5x* F: arch/arm/mach-dove/ F: arch/arm/mach-mv78xx0/ F: arch/arm/mach-orion5x/ @@ -2348,8 +2348,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ -F: arch/arm/boot/dts/armada* -F: arch/arm/boot/dts/kirkwood* +F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ F: arch/arm64/boot/dts/marvell/armada* @@ -2384,10 +2384,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained W: https://mtk.wiki.kernel.org/ C: irc://irc.libera.chat/linux-mediatek -F: arch/arm/boot/dts/mt2* -F: arch/arm/boot/dts/mt6* -F: arch/arm/boot/dts/mt7* -F: arch/arm/boot/dts/mt8* +F: arch/arm/boot/dts/mediatek/ F: arch/arm/mach-mediatek/ F: arch/arm64/boot/dts/mediatek/ F: drivers/soc/mediatek/ @@ -2411,10 +2408,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.linux4sam.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git -F: arch/arm/boot/dts/at91*.dts -F: arch/arm/boot/dts/at91*.dtsi -F: arch/arm/boot/dts/sama*.dts -F: arch/arm/boot/dts/sama*.dtsi +F: arch/arm/boot/dts/microchip/at91* +F: arch/arm/boot/dts/microchip/sama* F: arch/arm/include/debug/at91.S F: arch/arm/mach-at91/ F: drivers/memory/atmel* @@ -2451,7 +2446,7 @@ M: Taichi Sugaya M: Takao Orito L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/milbeaut* +F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut @@ -2465,7 +2460,7 @@ T: git git://github.com/linux-chenxing/linux.git F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml -F: arch/arm/boot/dts/mstar-* +F: arch/arm/boot/dts/sigmastar/ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c @@ -2484,7 +2479,7 @@ F: Documentation/devicetree/bindings/arm/ste-* F: Documentation/devicetree/bindings/arm/ux500.yaml F: Documentation/devicetree/bindings/arm/ux500/ F: Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml -F: arch/arm/boot/dts/ste-* +F: arch/arm/boot/dts/st/ste-* F: arch/arm/mach-nomadik/ F: arch/arm/mach-ux500/ F: drivers/clk/clk-nomadik.c @@ -2501,6 +2496,18 @@ F: drivers/rtc/rtc-ab8500.c F: drivers/rtc/rtc-pl031.c F: drivers/soc/ux500/ +ARM/NUVOTON MA35 ARCHITECTURE +M: Jacky Huang +M: Shan-Chun Hung +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/*/*ma35* +F: Documentation/devicetree/bindings/*/*ma35* +F: arch/arm64/boot/dts/nuvoton/*ma35* +F: drivers/*/*/*ma35* +F: drivers/*/*ma35* +K: ma35d1 + ARM/NUVOTON NPCM ARCHITECTURE M: Avi Fishman M: Tomer Maimon @@ -2512,9 +2519,8 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* -F: Documentation/devicetree/bindings/arm/npcm/* F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml -F: arch/arm/boot/dts/nuvoton-npcm* +F: arch/arm/boot/dts/nuvoton/nuvoton-npcm* F: arch/arm/mach-npcm/ F: arch/arm64/boot/dts/nuvoton/ F: drivers/*/*/*npcm* @@ -2529,7 +2535,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* -F: arch/arm/boot/dts/nuvoton-wpcm450* +F: arch/arm/boot/dts/nuvoton/nuvoton-wpcm450* F: arch/arm/configs/wpcm450_defconfig F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*/*wpcm* @@ -2570,14 +2576,13 @@ F: arch/arm64/boot/dts/qcom/sdm845-cheza* ARM/QUALCOMM SUPPORT M: Andy Gross M: Bjorn Andersson -R: Konrad Dybcio +M: Konrad Dybcio L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git F: Documentation/devicetree/bindings/*/qcom* F: Documentation/devicetree/bindings/soc/qcom/ -F: arch/arm/boot/dts/qcom-*.dts -F: arch/arm/boot/dts/qcom-*.dtsi +F: arch/arm/boot/dts/qcom/ F: arch/arm/configs/qcom_defconfig F: arch/arm/mach-qcom/ F: arch/arm64/boot/dts/qcom/ @@ -2620,7 +2625,7 @@ F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml -F: arch/arm/boot/dts/rda8810pl-* +F: arch/arm/boot/dts/unisoc/ F: drivers/clocksource/timer-rda.c F: drivers/gpio/gpio-rda.c F: drivers/irqchip/irq-rda-intc.c @@ -2632,7 +2637,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/realtek.yaml -F: arch/arm/boot/dts/rtd* +F: arch/arm/boot/dts/realtek/ F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ @@ -2646,13 +2651,7 @@ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml F: Documentation/devicetree/bindings/soc/renesas/ -F: arch/arm/boot/dts/emev2* -F: arch/arm/boot/dts/gr-peach* -F: arch/arm/boot/dts/iwg20d-q7* -F: arch/arm/boot/dts/r7s* -F: arch/arm/boot/dts/r8a* -F: arch/arm/boot/dts/r9a* -F: arch/arm/boot/dts/sh* +F: arch/arm/boot/dts/renesas/ F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ @@ -2685,8 +2684,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml -F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv11* +F: arch/arm/boot/dts/rockchip/ F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* @@ -2710,9 +2708,7 @@ F: Documentation/devicetree/bindings/arm/samsung/ F: Documentation/devicetree/bindings/hwinfo/samsung,* F: Documentation/devicetree/bindings/power/pd-samsung.yaml F: Documentation/devicetree/bindings/soc/samsung/ -F: arch/arm/boot/dts/exynos* -F: arch/arm/boot/dts/s3c* -F: arch/arm/boot/dts/s5p* +F: arch/arm/boot/dts/samsung/ F: arch/arm/mach-exynos*/ F: arch/arm/mach-s3c/ F: arch/arm/mach-s5p*/ @@ -2772,7 +2768,7 @@ M: Dinh Nguyen S: Maintained W: http://www.rocketboards.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git -F: arch/arm/boot/dts/socfpga* +F: arch/arm/boot/dts/intel/socfpga/ F: arch/arm/configs/socfpga_defconfig F: arch/arm/mach-socfpga/ F: arch/arm64/boot/dts/altera/ @@ -2805,7 +2801,7 @@ S: Maintained W: http://www.stlinux.com F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml -F: arch/arm/boot/dts/sti* +F: arch/arm/boot/dts/st/sti* F: arch/arm/mach-sti/ F: drivers/ata/ahci_st.c F: drivers/char/hw_random/st-rng.c @@ -2838,9 +2834,10 @@ L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-next -F: arch/arm/boot/dts/stm32* +F: arch/arm/boot/dts/st/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c +F: arch/arm64/boot/dts/st/ N: stm32 N: stm @@ -2853,7 +2850,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml -F: arch/arm/boot/dts/sunplus-sp7021*.dts* +F: arch/arm/boot/dts/sunplus/ F: arch/arm/configs/sp7021_*defconfig F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c @@ -2867,7 +2864,7 @@ M: Jisheng Zhang M: Sebastian Hesselbarth L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/berlin* +F: arch/arm/boot/dts/synaptics/ F: arch/arm/mach-berlin/ F: arch/arm64/boot/dts/synaptics/ @@ -2909,7 +2906,7 @@ M: Santosh Shilimkar L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -F: arch/arm/boot/dts/keystone-* +F: arch/arm/boot/dts/ti/keystone/ F: arch/arm/mach-keystone/ ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK @@ -2974,7 +2971,7 @@ F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml -F: arch/arm/boot/dts/uniphier* +F: arch/arm/boot/dts/socionext/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ F: arch/arm/mm/cache-uniphier.c @@ -2999,7 +2996,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: */*/*/vexpress* F: */*/vexpress* -F: arch/arm/boot/dts/vexpress* +F: arch/arm/boot/dts/arm/vexpress* F: arch/arm/mach-versatile/ F: arch/arm64/boot/dts/arm/ F: drivers/clk/versatile/clk-vexpress-osc.c @@ -3406,10 +3403,10 @@ AXENTIA ARM DEVICES M: Peter Rosin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/at91-linea.dtsi -F: arch/arm/boot/dts/at91-natte.dtsi -F: arch/arm/boot/dts/at91-nattis-2-natte-2.dts -F: arch/arm/boot/dts/at91-tse850-3.dts +F: arch/arm/boot/dts/microchip/at91-linea.dtsi +F: arch/arm/boot/dts/microchip/at91-natte.dtsi +F: arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts +F: arch/arm/boot/dts/microchip/at91-tse850-3.dts AXENTIA ASOC DRIVERS M: Peter Rosin @@ -3896,7 +3893,7 @@ S: Supported F: drivers/net/ethernet/broadcom/b44.* BROADCOM B53/SF2 ETHERNET SWITCH DRIVER -M: Florian Fainelli +M: Florian Fainelli L: netdev@vger.kernel.org L: openwrt-devel@lists.openwrt.org (subscribers-only) S: Supported @@ -3907,7 +3904,7 @@ F: include/linux/dsa/brcm.h F: include/linux/platform_data/b53.h BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -3921,7 +3918,7 @@ N: bcm283* N: raspberrypi BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli M: Ray Jui M: Scott Branden R: Broadcom internal kernel review list @@ -3960,25 +3957,26 @@ F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml F: drivers/pinctrl/bcm/pinctrl-bcm4908.c BROADCOM BCM5301X ARM ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli M: Hauke Mehrtens M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm470* -F: arch/arm/boot/dts/bcm5301* -F: arch/arm/boot/dts/bcm953012* +F: arch/arm/boot/dts/broadcom/bcm-ns.dtsi +F: arch/arm/boot/dts/broadcom/bcm470* +F: arch/arm/boot/dts/broadcom/bcm5301* +F: arch/arm/boot/dts/broadcom/bcm953012* F: arch/arm/mach-bcm/bcm_5301x.c BROADCOM BCM53573 ARM ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm47189* -F: arch/arm/boot/dts/bcm53573* +F: arch/arm/boot/dts/broadcom/bcm47189* +F: arch/arm/boot/dts/broadcom/bcm53573* BROADCOM BCM63XX/BCM33XX UDC DRIVER M: Kevin Cernekee @@ -3987,13 +3985,13 @@ S: Maintained F: drivers/usb/gadget/udc/bcm63xx_udc.* BROADCOM BCM7XXX ARM ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git https://github.com/broadcom/stblinux.git F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml -F: arch/arm/boot/dts/bcm7*.dts* +F: arch/arm/boot/dts/broadcom/bcm7*.dts* F: arch/arm/include/asm/hardware/cache-b15-rac.h F: arch/arm/mach-bcm/*brcmstb* F: arch/arm/mm/cache-b15-rac.c @@ -4007,7 +4005,7 @@ BROADCOM BCMBCA ARM ARCHITECTURE M: William Zhang M: Anand Gore M: Kursad Oney -M: Florian Fainelli +M: Florian Fainelli M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -4032,7 +4030,7 @@ N: bcm[9]?6858 N: bcm[9]?6878 BROADCOM BDC DRIVER -M: Justin Chen +M: Justin Chen M: Al Cooper R: Broadcom internal kernel review list L: linux-usb@vger.kernel.org @@ -4048,7 +4046,7 @@ S: Maintained F: drivers/cpufreq/bmips-cpufreq.c BROADCOM BMIPS MIPS ARCHITECTURE -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: linux-mips@vger.kernel.org S: Maintained @@ -4116,14 +4114,14 @@ F: drivers/net/wireless/broadcom/brcm80211/ BROADCOM BRCMSTB GPIO DRIVER M: Doug Berger -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list S: Supported F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml F: drivers/gpio/gpio-brcmstb.c BROADCOM BRCMSTB I2C DRIVER -M: Kamal Dasu +M: Kamal Dasu R: Broadcom internal kernel review list L: linux-i2c@vger.kernel.org S: Supported @@ -4139,7 +4137,7 @@ F: Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml F: drivers/tty/serial/8250/8250_bcm7271.c BROADCOM BRCMSTB USB EHCI DRIVER -M: Justin Chen +M: Justin Chen M: Al Cooper R: Broadcom internal kernel review list L: linux-usb@vger.kernel.org @@ -4156,7 +4154,7 @@ F: Documentation/devicetree/bindings/usb/brcm,usb-pinmap.yaml F: drivers/usb/misc/brcmstb-usb-pinmap.c BROADCOM BRCMSTB USB2 and USB3 PHY DRIVER -M: Justin Chen +M: Justin Chen M: Al Cooper R: Broadcom internal kernel review list L: linux-kernel@vger.kernel.org @@ -4175,7 +4173,7 @@ F: drivers/spi/spi-bcm63xx-hsspi.c F: drivers/spi/spi-bcmbca-hsspi.c BROADCOM ETHERNET PHY DRIVERS -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: netdev@vger.kernel.org S: Supported @@ -4186,7 +4184,7 @@ F: include/linux/brcmphy.h BROADCOM GENET ETHERNET DRIVER M: Doug Berger -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: netdev@vger.kernel.org S: Supported @@ -4270,7 +4268,7 @@ F: drivers/firmware/broadcom/* BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER M: Rafał Miłecki -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: linux-pm@vger.kernel.org S: Maintained @@ -4286,7 +4284,7 @@ F: drivers/bcma/ F: include/linux/bcma/ BROADCOM SPI DRIVER -M: Kamal Dasu +M: Kamal Dasu R: Broadcom internal kernel review list S: Maintained F: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml @@ -4320,7 +4318,7 @@ F: drivers/memory/brcmstb_dpfe.c BROADCOM STB NAND FLASH DRIVER M: Brian Norris -M: Kamal Dasu +M: Kamal Dasu R: Broadcom internal kernel review list L: linux-mtd@lists.infradead.org S: Maintained @@ -4330,7 +4328,7 @@ F: include/linux/platform_data/brcmnand.h BROADCOM STB PCIE DRIVER M: Jim Quinlan M: Nicolas Saenz Julienne -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: linux-pci@vger.kernel.org S: Maintained @@ -4338,7 +4336,7 @@ F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml F: drivers/pci/controller/pcie-brcmstb.c BROADCOM SYSTEMPORT ETHERNET DRIVER -M: Florian Fainelli +M: Florian Fainelli R: Broadcom internal kernel review list L: netdev@vger.kernel.org S: Supported @@ -6021,15 +6019,15 @@ DH ELECTRONICS IMX6 DHCOM/DHCOR BOARD SUPPORT M: Christoph Niedermaier L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/imx6*-dhcom-* -F: arch/arm/boot/dts/imx6*-dhcor-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcom-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcor-* DH ELECTRONICS STM32MP1 DHCOM/DHCOR BOARD SUPPORT M: Marek Vasut L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/stm32mp1*-dhcom-* -F: arch/arm/boot/dts/stm32mp1*-dhcor-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcom-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcor-* DIALOG SEMICONDUCTOR DRIVERS M: Support Opensource @@ -7111,7 +7109,6 @@ F: Documentation/gpu/xen-front.rst F: drivers/gpu/drm/xen/ DRM DRIVERS FOR XILINX -M: Hyun Kwon M: Laurent Pinchart L: dri-devel@lists.freedesktop.org S: Maintained @@ -11449,7 +11446,6 @@ F: tools/testing/selftests/kvm/aarch64/ KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips) M: Huacai Chen -M: Aleksandar Markovic L: linux-mips@vger.kernel.org L: kvm@vger.kernel.org S: Maintained @@ -11821,7 +11817,7 @@ LEGO MINDSTORMS EV3 R: David Lechner S: Maintained F: Documentation/devicetree/bindings/power/supply/lego,ev3-battery.yaml -F: arch/arm/boot/dts/da850-lego-ev3.dts +F: arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts F: drivers/power/supply/lego_ev3_battery.c LEGO USB Tower driver @@ -13338,6 +13334,12 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml F: drivers/i2c/busses/i2c-mt7621.c +MEDIATEK MTMIPS CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml +F: drivers/clk/ralink/clk-mtmips.c + MEDIATEK NAND CONTROLLER DRIVER L: linux-mtd@lists.infradead.org S: Orphan @@ -13815,6 +13817,7 @@ MICROCHIP EIC DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +F: Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml F: drivers/irqchip/irq-mchp-eic.c MICROCHIP I2C DRIVER @@ -14141,12 +14144,12 @@ MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT M: Luka Kovacic M: Luka Perkov S: Maintained -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER M: Sakari Ailus @@ -14249,7 +14252,7 @@ R: Lubomir Rintel L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd Fixes T: git git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp.git -F: arch/arm/boot/dts/mmp* +F: arch/arm/boot/dts/marvell/mmp* F: arch/arm/mach-mmp/ F: include/linux/soc/mmp/ @@ -15382,13 +15385,7 @@ M: Tony Lindgren L: linux-omap@vger.kernel.org L: devicetree@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/*am3* -F: arch/arm/boot/dts/*am4* -F: arch/arm/boot/dts/*am5* -F: arch/arm/boot/dts/*dra7* -F: arch/arm/boot/dts/*omap* -F: arch/arm/boot/dts/logicpd-som-lv* -F: arch/arm/boot/dts/logicpd-torpedo* +F: arch/arm/boot/dts/ti/omap/ OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) L: linux-omap@vger.kernel.org @@ -15496,7 +15493,7 @@ OMAP/NEWFLOW NANOBONE MACHINE SUPPORT M: Mark Jackson L: linux-omap@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/am335x-nano.dts +F: arch/arm/boot/dts/ti/omap/am335x-nano.dts OMAP1 SUPPORT M: Aaro Koskinen @@ -17245,7 +17242,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/hzhuang1/linux.git T: git git://github.com/rjarzmik/linux.git -F: arch/arm/boot/dts/pxa* +F: arch/arm/boot/dts/intel/pxa/ F: arch/arm/mach-pxa/ F: drivers/dma/pxa* F: drivers/pcmcia/pxa2xx* @@ -18284,6 +18281,8 @@ Q: https://patchwork.kernel.org/project/linux-riscv/list/ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ +X: arch/riscv/boot/dts/allwinner/ +X: arch/riscv/boot/dts/renesas/ RISC-V PMU DRIVERS M: Atish Patra @@ -18294,6 +18293,14 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +M: Guo Ren +M: Fu Wei +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang @@ -18877,7 +18884,7 @@ SANCLOUD BEAGLEBONE ENHANCED DEVICE TREE M: Paul Barker R: Marc Murphy S: Supported -F: arch/arm/boot/dts/am335x-sancloud* +F: arch/arm/boot/dts/ti/omap/am335x-sancloud* SC1200 WDT DRIVER M: Zwane Mwaikambo @@ -19032,7 +19039,7 @@ K: \bsecure_computing K: \bTIF_SECCOMP\b SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) Broadcom BRCMSTB DRIVER -M: Kamal Dasu +M: Kamal Dasu M: Al Cooper R: Broadcom internal kernel review list L: linux-mmc@vger.kernel.org @@ -19706,15 +19713,15 @@ F: include/uapi/linux/raid/ SOLIDRUN CLEARFOG SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/armada-388-clearfog* -F: arch/arm/boot/dts/armada-38x-solidrun-* +F: arch/arm/boot/dts/marvell/armada-388-clearfog* +F: arch/arm/boot/dts/marvell/armada-38x-solidrun-* SOLIDRUN CUBOX-I/HUMMINGBOARD SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/imx6*-cubox-i* -F: arch/arm/boot/dts/imx6*-hummingboard* -F: arch/arm/boot/dts/imx6*-sr-* +F: arch/arm/boot/dts/nxp/imx/imx6*-cubox-i* +F: arch/arm/boot/dts/nxp/imx/imx6*-hummingboard* +F: arch/arm/boot/dts/nxp/imx/imx6*-sr-* SONIC NETWORK DRIVER M: Thomas Bogendoerfer @@ -19999,7 +20006,7 @@ M: soc@kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://www.st.com/spear -F: arch/arm/boot/dts/spear* +F: arch/arm/boot/dts/st/spear* F: arch/arm/mach-spear/ F: drivers/clk/spear/ F: drivers/pinctrl/spear/ @@ -21213,7 +21220,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git F: Documentation/devicetree/bindings/i2c/i2c-davinci.txt -F: arch/arm/boot/dts/da850* +F: arch/arm/boot/dts/ti/davinci/ F: arch/arm/mach-davinci/ F: drivers/i2c/busses/i2c-davinci.c @@ -23268,7 +23275,7 @@ F: Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml F: drivers/iio/adc/xilinx-ams.c XILINX AXI ETHERNET DRIVER -M: Radhey Shyam Pandey +M: Radhey Shyam Pandey S: Maintained F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml F: drivers/net/ethernet/xilinx/xilinx_axienet* @@ -23288,8 +23295,8 @@ F: drivers/soc/xilinx/xlnx_event_manager.c F: include/linux/firmware/xlnx-event-manager.h XILINX GPIO DRIVER -M: Shubhrajyoti Datta -R: Srinivas Neeli +M: Shubhrajyoti Datta +R: Srinivas Neeli R: Michal Simek S: Maintained F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -23304,8 +23311,8 @@ F: drivers/pwm/pwm-xilinx.c F: include/clocksource/timer-xilinx.h XILINX SD-FEC IP CORES -M: Derek Kiernan -M: Dragan Cvetic +M: Derek Kiernan +M: Dragan Cvetic S: Maintained F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt F: Documentation/misc-devices/xilinx_sdfec.rst @@ -23321,7 +23328,6 @@ S: Maintained F: drivers/tty/serial/uartlite.c XILINX VIDEO IP CORES -M: Hyun Kwon M: Laurent Pinchart L: linux-media@vger.kernel.org S: Supported @@ -23350,7 +23356,6 @@ F: include/linux/dma/amd_xdma.h F: include/linux/platform_data/amd_xdma.h XILINX ZYNQMP DPDMA DRIVER -M: Hyun Kwon M: Laurent Pinchart L: dmaengine@vger.kernel.org S: Supported @@ -23366,7 +23371,6 @@ F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yam F: drivers/edac/zynqmp_edac.c XILINX ZYNQMP PSGTR PHY DRIVER -M: Anurag Kumar Vulisha M: Laurent Pinchart L: linux-kernel@vger.kernel.org S: Supported @@ -23375,7 +23379,7 @@ F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml F: drivers/phy/xilinx/phy-zynqmp.c XILINX ZYNQMP SHA3 DRIVER -M: Harsha +M: Harsha S: Maintained F: drivers/crypto/xilinx/zynqmp-sha.c diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig index 2f336d99a8cf..07c89281c2e3 100644 --- a/arch/arc/configs/axs103_smp_defconfig +++ b/arch/arc/configs/axs103_smp_defconfig @@ -13,7 +13,6 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arc/configs/haps_hs_defconfig b/arch/arc/configs/haps_hs_defconfig index 899b2fd5c71d..8c3ed5d6e6c3 100644 --- a/arch/arc/configs/haps_hs_defconfig +++ b/arch/arc/configs/haps_hs_defconfig @@ -14,7 +14,6 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs" CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/arc/configs/haps_hs_smp_defconfig b/arch/arc/configs/haps_hs_smp_defconfig index 0d32aac8069f..61107e8bac33 100644 --- a/arch/arc/configs/haps_hs_smp_defconfig +++ b/arch/arc/configs/haps_hs_smp_defconfig @@ -15,7 +15,6 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_SMP=y CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu" CONFIG_KPROBES=y diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig index d18378d2c2a6..4ee2a1507b57 100644 --- a/arch/arc/configs/hsdk_defconfig +++ b/arch/arc/configs/hsdk_defconfig @@ -13,7 +13,6 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_ARC_SOC_HSDK=y diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig index 6f0d2be9d926..941bbadd6bf2 100644 --- a/arch/arc/configs/tb10x_defconfig +++ b/arch/arc/configs/tb10x_defconfig @@ -19,7 +19,6 @@ CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_ISA_ARCOMPACT=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d60b73d93e03..7a27550ff3c1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1463,6 +1463,9 @@ config USE_OF help Include support for flattened device tree machine descriptions. +config ARCH_WANT_FLAT_DTB_INSTALL + def_bool y + config ATAGS bool "Support for the traditional ATAGS boot data passing" default y diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc90315..efe38eb25301 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,1672 +1,41 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine-db.dtb -dtb-$(CONFIG_MACH_ARTPEC6) += \ - artpec6-devboard.dtb -dtb-$(CONFIG_MACH_ASM9260) += \ - alphascale-asm9260-devkit.dtb -# Keep at91 dtb files sorted alphabetically for each SoC -dtb-$(CONFIG_SOC_AT91RM9200) += \ - at91rm9200ek.dtb \ - mpa1600.dtb -dtb-$(CONFIG_SOC_AT91SAM9) += \ - animeo_ip.dtb \ - at91-qil_a9260.dtb \ - aks-cdu.dtb \ - ethernut5.dtb \ - evk-pro3.dtb \ - tny_a9260.dtb \ - usb_a9260.dtb \ - at91sam9260ek.dtb \ - at91sam9261ek.dtb \ - at91sam9263ek.dtb \ - at91-sam9_l9260.dtb \ - tny_a9263.dtb \ - usb_a9263.dtb \ - at91-foxg20.dtb \ - at91-kizbox.dtb \ - at91-lmu5000.dtb \ - at91sam9g20ek.dtb \ - at91sam9g20ek_2mmc.dtb \ - tny_a9g20.dtb \ - usb_a9g20.dtb \ - usb_a9g20_lpw.dtb \ - at91sam9m10g45ek.dtb \ - pm9g45.dtb \ - at91sam9n12ek.dtb \ - at91sam9rlek.dtb \ - at91-ariag25.dtb \ - at91-ariettag25.dtb \ - at91-cosino_mega2560.dtb \ - at91-kizboxmini-base.dtb \ - at91-kizboxmini-mb.dtb \ - at91-kizboxmini-rd.dtb \ - at91-q5xr5.dtb \ - at91-smartkiz.dtb \ - at91-wb45n.dtb \ - at91sam9g15ek.dtb \ - at91sam9g25-gardena-smart-gateway.dtb \ - at91sam9g25ek.dtb \ - at91sam9g35ek.dtb \ - at91sam9x25ek.dtb \ - at91sam9x35ek.dtb -dtb-$(CONFIG_SOC_SAM9X60) += \ - at91-sam9x60_curiosity.dtb \ - at91-sam9x60ek.dtb -dtb-$(CONFIG_SOC_SAM_V7) += \ - at91-kizbox2-2.dtb \ - at91-kizbox3-hs.dtb \ - at91-nattis-2-natte-2.dtb \ - at91-sama5d27_som1_ek.dtb \ - at91-sama5d27_wlsom1_ek.dtb \ - at91-sama5d2_icp.dtb \ - at91-sama5d2_ptc_ek.dtb \ - at91-sama5d2_xplained.dtb \ - at91-sama5d3_eds.dtb \ - at91-sama5d3_ksz9477_evb.dtb \ - at91-sama5d3_xplained.dtb \ - at91-dvk_som60.dtb \ - at91-gatwick.dtb \ - at91-tse850-3.dtb \ - at91-wb50n.dtb \ - sama5d31ek.dtb \ - sama5d33ek.dtb \ - sama5d34ek.dtb \ - sama5d35ek.dtb \ - sama5d36ek.dtb \ - sama5d36ek_cmp.dtb \ - at91-sama5d4_ma5d4evk.dtb \ - at91-sama5d4_xplained.dtb \ - at91-sama5d4ek.dtb \ - at91-vinco.dtb -dtb-$(CONFIG_SOC_SAMA7G5) += \ - at91-sama7g5ek.dtb -dtb-$(CONFIG_SOC_SP7021) += \ - sunplus-sp7021-demo-v3.dtb -dtb-$(CONFIG_ARCH_AXXIA) += \ - axm5516-amarillo.dtb -dtb-$(CONFIG_ARCH_BCM2835) += \ - bcm2835-rpi-b.dtb \ - bcm2835-rpi-a.dtb \ - bcm2835-rpi-b-rev2.dtb \ - bcm2835-rpi-b-plus.dtb \ - bcm2835-rpi-a-plus.dtb \ - bcm2835-rpi-cm1-io1.dtb \ - bcm2836-rpi-2-b.dtb \ - bcm2837-rpi-3-a-plus.dtb \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb \ - bcm2837-rpi-zero-2-w.dtb \ - bcm2711-rpi-400.dtb \ - bcm2711-rpi-4-b.dtb \ - bcm2711-rpi-cm4-io.dtb \ - bcm2835-rpi-zero.dtb \ - bcm2835-rpi-zero-w.dtb -dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4708-asus-rt-ac56u.dtb \ - bcm4708-asus-rt-ac68u.dtb \ - bcm4708-buffalo-wzr-1750dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp2.dtb \ - bcm4708-linksys-ea6300-v1.dtb \ - bcm4708-linksys-ea6500-v2.dtb \ - bcm4708-luxul-xap-1510.dtb \ - bcm4708-luxul-xwc-1000.dtb \ - bcm4708-netgear-r6250.dtb \ - bcm4708-netgear-r6300-v2.dtb \ - bcm4708-smartrg-sr400ac.dtb \ - bcm47081-asus-rt-n18u.dtb \ - bcm47081-buffalo-wzr-600dhp2.dtb \ - bcm47081-buffalo-wzr-900dhp.dtb \ - bcm47081-luxul-xap-1410.dtb \ - bcm47081-luxul-xwr-1200.dtb \ - bcm47081-tplink-archer-c5-v2.dtb \ - bcm4709-asus-rt-ac87u.dtb \ - bcm4709-buffalo-wxr-1900dhp.dtb \ - bcm4709-linksys-ea9200.dtb \ - bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb \ - bcm4709-tplink-archer-c9-v1.dtb \ - bcm47094-asus-rt-ac88u.dtb \ - bcm47094-dlink-dir-885l.dtb \ - bcm47094-dlink-dir-890l.dtb \ - bcm47094-linksys-panamera.dtb \ - bcm47094-luxul-abr-4500.dtb \ - bcm47094-luxul-xap-1610.dtb \ - bcm47094-luxul-xbr-4500.dtb \ - bcm47094-luxul-xwc-2000.dtb \ - bcm47094-luxul-xwr-3100.dtb \ - bcm47094-luxul-xwr-3150-v1.dtb \ - bcm47094-netgear-r8500.dtb \ - bcm47094-phicomm-k3.dtb \ - bcm53015-meraki-mr26.dtb \ - bcm53016-dlink-dwl-8610ap.dtb \ - bcm53016-meraki-mr32.dtb \ - bcm94708.dtb \ - bcm94709.dtb \ - bcm953012er.dtb \ - bcm953012hr.dtb \ - bcm953012k.dtb -dtb-$(CONFIG_ARCH_BCM_53573) += \ - bcm47189-luxul-xap-1440.dtb \ - bcm47189-luxul-xap-810.dtb \ - bcm47189-tenda-ac9.dtb \ - bcm947189acdbmr.dtb -dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ - bcm911360_entphn.dtb \ - bcm911360k.dtb \ - bcm958300k.dtb \ - bcm958305k.dtb -dtb-$(CONFIG_ARCH_BCM_HR2) += \ - bcm53340-ubnt-unifi-switch8.dtb -dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ - bcm28155-ap.dtb \ - bcm21664-garnet.dtb \ - bcm23550-sparrow.dtb -dtb-$(CONFIG_ARCH_BCM_NSP) += \ - bcm958522er.dtb \ - bcm958525er.dtb \ - bcm958525xmc.dtb \ - bcm958622hr.dtb \ - bcm958623hr.dtb \ - bcm958625-meraki-mx64.dtb \ - bcm958625-meraki-mx64-a0.dtb \ - bcm958625-meraki-mx64w.dtb \ - bcm958625-meraki-mx64w-a0.dtb \ - bcm958625-meraki-mx65.dtb \ - bcm958625-meraki-mx65w.dtb \ - bcm958625hr.dtb \ - bcm988312hr.dtb \ - bcm958625k.dtb -dtb-$(CONFIG_ARCH_BERLIN) += \ - berlin2-sony-nsz-gs7.dtb \ - berlin2cd-google-chromecast.dtb \ - berlin2cd-valve-steamlink.dtb \ - berlin2q-marvell-dmp.dtb -dtb-$(CONFIG_ARCH_BRCMSTB) += \ - bcm7445-bcm97445svmb.dtb -dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb \ - bcm963138.dtb \ - bcm963138dvt.dtb \ - bcm963148.dtb \ - bcm963178.dtb \ - bcm96756.dtb \ - bcm96846.dtb \ - bcm96855.dtb \ - bcm96878.dtb -dtb-$(CONFIG_ARCH_CLPS711X) += \ - ep7211-edb7211.dtb -dtb-$(CONFIG_ARCH_DAVINCI) += \ - da850-lcdk.dtb \ - da850-enbw-cmc.dtb \ - da850-evm.dtb \ - da850-lego-ev3.dtb -dtb-$(CONFIG_ARCH_DIGICOLOR) += \ - cx92755_equinox.dtb -dtb-$(CONFIG_ARCH_AIROHA) += \ - en7523-evb.dtb -dtb-$(CONFIG_ARCH_EXYNOS3) += \ - exynos3250-artik5-eval.dtb \ - exynos3250-monk.dtb \ - exynos3250-rinato.dtb -dtb-$(CONFIG_ARCH_EXYNOS4) += \ - exynos4210-i9100.dtb \ - exynos4210-origen.dtb \ - exynos4210-smdkv310.dtb \ - exynos4210-trats.dtb \ - exynos4210-universal_c210.dtb \ - exynos4412-i9300.dtb \ - exynos4412-i9305.dtb \ - exynos4412-itop-elite.dtb \ - exynos4412-n710x.dtb \ - exynos4412-odroidu3.dtb \ - exynos4412-odroidx.dtb \ - exynos4412-odroidx2.dtb \ - exynos4412-origen.dtb \ - exynos4412-p4note-n8010.dtb \ - exynos4412-smdk4412.dtb \ - exynos4412-tiny4412.dtb \ - exynos4412-trats2.dtb -dtb-$(CONFIG_ARCH_EXYNOS5) += \ - exynos5250-arndale.dtb \ - exynos5250-smdk5250.dtb \ - exynos5250-snow.dtb \ - exynos5250-snow-rev5.dtb \ - exynos5250-spring.dtb \ - exynos5260-xyref5260.dtb \ - exynos5410-odroidxu.dtb \ - exynos5410-smdk5410.dtb \ - exynos5420-arndale-octa.dtb \ - exynos5420-peach-pit.dtb \ - exynos5420-smdk5420.dtb \ - exynos5420-chagall-wifi.dtb \ - exynos5420-klimt-wifi.dtb \ - exynos5422-odroidhc1.dtb \ - exynos5422-odroidxu3.dtb \ - exynos5422-odroidxu3-lite.dtb \ - exynos5422-odroidxu4.dtb \ - exynos5422-samsung-k3g.dtb \ - exynos5800-peach-pi.dtb -dtb-$(CONFIG_ARCH_GEMINI) += \ - gemini-dlink-dir-685.dtb \ - gemini-dlink-dns-313.dtb \ - gemini-nas4220b.dtb \ - gemini-ns2502.dtb \ - gemini-rut1xx.dtb \ - gemini-sl93512r.dtb \ - gemini-sq201.dtb \ - gemini-ssi1328.dtb \ - gemini-wbd111.dtb \ - gemini-wbd222.dtb -dtb-$(CONFIG_ARCH_HI3xxx) += \ - hi3620-hi4511.dtb -dtb-$(CONFIG_ARCH_HIGHBANK) += \ - highbank.dtb \ - ecx-2000.dtb -dtb-$(CONFIG_ARCH_HIP01) += \ - hip01-ca9x2.dtb -dtb-$(CONFIG_ARCH_HIP04) += \ - hip04-d01.dtb -dtb-$(CONFIG_ARCH_HISI) += \ - hi3519-demb.dtb -dtb-$(CONFIG_ARCH_HIX5HD2) += \ - hisi-x5hd2-dkb.dtb -dtb-$(CONFIG_ARCH_HPE_GXP) += \ - hpe-bmc-dl360gen10.dtb -dtb-$(CONFIG_ARCH_INTEGRATOR) += \ - integratorap.dtb \ - integratorap-im-pd1.dtb \ - integratorcp.dtb -dtb-$(CONFIG_ARCH_IXP4XX) += \ - intel-ixp42x-linksys-nslu2.dtb \ - intel-ixp42x-linksys-wrv54g.dtb \ - intel-ixp42x-freecom-fsg-3.dtb \ - intel-ixp42x-welltech-epbx100.dtb \ - intel-ixp42x-ixdp425.dtb \ - intel-ixp43x-kixrp435.dtb \ - intel-ixp46x-ixdp465.dtb \ - intel-ixp42x-adi-coyote.dtb \ - intel-ixp42x-ixdpg425.dtb \ - intel-ixp42x-goramo-multilink.dtb \ - intel-ixp42x-iomega-nas100d.dtb \ - intel-ixp42x-dlink-dsm-g600.dtb \ - intel-ixp42x-gateworks-gw2348.dtb \ - intel-ixp43x-gateworks-gw2358.dtb \ - intel-ixp42x-netgear-wg302v1.dtb \ - intel-ixp42x-arcom-vulcan.dtb \ - intel-ixp42x-gateway-7001.dtb -dtb-$(CONFIG_ARCH_KEYSTONE) += \ - keystone-k2hk-evm.dtb \ - keystone-k2l-evm.dtb \ - keystone-k2e-evm.dtb \ - keystone-k2g-evm.dtb \ - keystone-k2g-ice.dtb -dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-b3.dtb \ - kirkwood-blackarmor-nas220.dtb \ - kirkwood-c200-v1.dtb \ - kirkwood-cloudbox.dtb \ - kirkwood-d2net.dtb \ - kirkwood-db-88f6281.dtb \ - kirkwood-db-88f6282.dtb \ - kirkwood-dir665.dtb \ - kirkwood-dns320.dtb \ - kirkwood-dns325.dtb \ - kirkwood-dockstar.dtb \ - kirkwood-dreamplug.dtb \ - kirkwood-ds109.dtb \ - kirkwood-ds110jv10.dtb \ - kirkwood-ds111.dtb \ - kirkwood-ds112.dtb \ - kirkwood-ds209.dtb \ - kirkwood-ds210.dtb \ - kirkwood-ds212.dtb \ - kirkwood-ds212j.dtb \ - kirkwood-ds409.dtb \ - kirkwood-ds409slim.dtb \ - kirkwood-ds411.dtb \ - kirkwood-ds411j.dtb \ - kirkwood-ds411slim.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ - kirkwood-iconnect.dtb \ - kirkwood-iomega_ix2_200.dtb \ - kirkwood-is2.dtb \ - kirkwood-km_kirkwood.dtb \ - kirkwood-l-50.dtb \ - kirkwood-laplug.dtb \ - kirkwood-linkstation-lsqvl.dtb \ - kirkwood-linkstation-lsvl.dtb \ - kirkwood-linkstation-lswsxl.dtb \ - kirkwood-linkstation-lswvl.dtb \ - kirkwood-linkstation-lswxl.dtb \ - kirkwood-linksys-viper.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-lsxhl.dtb \ - kirkwood-mplcec4.dtb \ - kirkwood-mv88f6281gtw-ge.dtb \ - kirkwood-nas2big.dtb \ - kirkwood-net2big.dtb \ - kirkwood-net5big.dtb \ - kirkwood-netgear_readynas_duo_v2.dtb \ - kirkwood-netgear_readynas_nv+_v2.dtb \ - kirkwood-ns2.dtb \ - kirkwood-ns2lite.dtb \ - kirkwood-ns2max.dtb \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310.dtb \ - kirkwood-nsa310a.dtb \ - kirkwood-nsa310s.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-pogoplug-series-4.dtb \ - kirkwood-rd88f6192.dtb \ - kirkwood-rd88f6281-z0.dtb \ - kirkwood-rd88f6281-a.dtb \ - kirkwood-rs212.dtb \ - kirkwood-rs409.dtb \ - kirkwood-rs411.dtb \ - kirkwood-sheevaplug.dtb \ - kirkwood-sheevaplug-esata.dtb \ - kirkwood-t5325.dtb \ - kirkwood-topkick.dtb \ - kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb \ - kirkwood-ts419-6281.dtb \ - kirkwood-ts419-6282.dtb -dtb-$(CONFIG_ARCH_LPC18XX) += \ - lpc4337-ciaa.dtb \ - lpc4350-hitex-eval.dtb \ - lpc4357-ea4357-devkit.dtb \ - lpc4357-myd-lpc4357.dtb -dtb-$(CONFIG_ARCH_LPC32XX) += \ - lpc3250-ea3250.dtb \ - lpc3250-phy3250.dtb -dtb-$(CONFIG_ARCH_WPCM450) += \ - nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb -dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm730-gsj.dtb \ - nuvoton-npcm730-gbs.dtb \ - nuvoton-npcm730-kudo.dtb \ - nuvoton-npcm750-evb.dtb \ - nuvoton-npcm750-runbmc-olympus.dtb -dtb-$(CONFIG_MACH_MESON6) += \ - meson6-atv1200.dtb -dtb-$(CONFIG_MACH_MESON8) += \ - meson8-minix-neo-x8.dtb \ - meson8b-ec100.dtb \ - meson8b-mxq.dtb \ - meson8b-odroidc1.dtb \ - meson8m2-mxiii-plus.dtb -dtb-$(CONFIG_ARCH_MMP) += \ - pxa168-aspenite.dtb \ - pxa910-dkb.dtb \ - mmp2-brownstone.dtb \ - mmp2-olpc-xo-1-75.dtb \ - mmp3-dell-ariel.dtb -dtb-$(CONFIG_ARCH_MPS2) += \ - mps2-an385.dtb \ - mps2-an399.dtb -dtb-$(CONFIG_ARCH_MOXART) += \ - moxart-uc7112lx.dtb -dtb-$(CONFIG_ARCH_SD5203) += \ - sd5203.dtb -dtb-$(CONFIG_SOC_IMX1) += \ - imx1-ads.dtb \ - imx1-apf9328.dtb -dtb-$(CONFIG_SOC_IMX25) += \ - imx25-eukrea-mbimxsd25-baseboard.dtb \ - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ - imx25-karo-tx25.dtb \ - imx25-pdk.dtb -dtb-$(CONFIG_SOC_IMX27) += \ - imx27-apf27.dtb \ - imx27-apf27dev.dtb \ - imx27-eukrea-mbimxsd27-baseboard.dtb \ - imx27-pdk.dtb \ - imx27-phytec-phycore-rdk.dtb \ - imx27-phytec-phycard-s-rdk.dtb -dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb \ - imx31-lite.dtb -dtb-$(CONFIG_SOC_IMX35) += \ - imx35-eukrea-mbimxsd35-baseboard.dtb \ - imx35-pdk.dtb -dtb-$(CONFIG_SOC_IMX50) += \ - imx50-evk.dtb \ - imx50-kobo-aura.dtb -dtb-$(CONFIG_SOC_IMX51) += \ - imx51-apf51.dtb \ - imx51-apf51dev.dtb \ - imx51-babbage.dtb \ - imx51-digi-connectcore-jsk.dtb \ - imx51-eukrea-mbimxsd51-baseboard.dtb \ - imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb \ - imx51-zii-scu2-mezz.dtb \ - imx51-zii-scu3-esb.dtb -dtb-$(CONFIG_SOC_IMX53) += \ - imx53-ard.dtb \ - imx53-cx9020.dtb \ - imx53-kp-ddc.dtb \ - imx53-kp-hsc.dtb \ - imx53-m53evk.dtb \ - imx53-m53menlo.dtb \ - imx53-mba53.dtb \ - imx53-ppd.dtb \ - imx53-qsb.dtb \ - imx53-qsrb.dtb \ - imx53-sk-imx53.dtb \ - imx53-smd.dtb \ - imx53-tx53-x03x.dtb \ - imx53-tx53-x13x.dtb \ - imx53-usbarmory.dtb \ - imx53-voipac-bsb.dtb -dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-alti6p.dtb \ - imx6dl-apf6dev.dtb \ - imx6dl-aristainetos_4.dtb \ - imx6dl-aristainetos_7.dtb \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-colibri-aster.dtb \ - imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-iris.dtb \ - imx6dl-colibri-iris-v2.dtb \ - imx6dl-cubox-i.dtb \ - imx6dl-cubox-i-emmc-som-v15.dtb \ - imx6dl-cubox-i-som-v15.dtb \ - imx6dl-dfi-fs700-m60.dtb \ - imx6dl-dhcom-picoitx.dtb \ - imx6dl-eckelmann-ci4x10.dtb \ - imx6dl-emcon-avari.dtb \ - imx6dl-gw51xx.dtb \ - imx6dl-gw52xx.dtb \ - imx6dl-gw53xx.dtb \ - imx6dl-gw54xx.dtb \ - imx6dl-gw551x.dtb \ - imx6dl-gw552x.dtb \ - imx6dl-gw553x.dtb \ - imx6dl-gw560x.dtb \ - imx6dl-gw5903.dtb \ - imx6dl-gw5904.dtb \ - imx6dl-gw5907.dtb \ - imx6dl-gw5910.dtb \ - imx6dl-gw5912.dtb \ - imx6dl-gw5913.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-hummingboard-emmc-som-v15.dtb \ - imx6dl-hummingboard-som-v15.dtb \ - imx6dl-hummingboard2.dtb \ - imx6dl-hummingboard2-emmc-som-v15.dtb \ - imx6dl-hummingboard2-som-v15.dtb \ - imx6dl-icore.dtb \ - imx6dl-icore-mipi.dtb \ - imx6dl-icore-rqs.dtb \ - imx6dl-lanmcu.dtb \ - imx6dl-mamoj.dtb \ - imx6dl-mba6a.dtb \ - imx6dl-mba6b.dtb \ - imx6dl-nit6xlite.dtb \ - imx6dl-nitrogen6x.dtb \ - imx6dl-phytec-mira-rdk-nand.dtb \ - imx6dl-phytec-pbab01.dtb \ - imx6dl-pico-dwarf.dtb \ - imx6dl-pico-hobbit.dtb \ - imx6dl-pico-nymph.dtb \ - imx6dl-pico-pi.dtb \ - imx6dl-plybas.dtb \ - imx6dl-plym2m.dtb \ - imx6dl-prtmvt.dtb \ - imx6dl-prtrvt.dtb \ - imx6dl-prtvt7.dtb \ - imx6dl-rex-basic.dtb \ - imx6dl-riotboard.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabrelite.dtb \ - imx6dl-sabresd.dtb \ - imx6dl-savageboard.dtb \ - imx6dl-skov-revc-lt2.dtb \ - imx6dl-skov-revc-lt6.dtb \ - imx6dl-solidsense.dtb \ - imx6dl-ts4900.dtb \ - imx6dl-ts7970.dtb \ - imx6dl-tx6dl-comtft.dtb \ - imx6dl-tx6s-8034.dtb \ - imx6dl-tx6s-8034-mb7.dtb \ - imx6dl-tx6s-8035.dtb \ - imx6dl-tx6s-8035-mb7.dtb \ - imx6dl-tx6u-801x.dtb \ - imx6dl-tx6u-80xx-mb7.dtb \ - imx6dl-tx6u-8033.dtb \ - imx6dl-tx6u-8033-mb7.dtb \ - imx6dl-tx6u-811x.dtb \ - imx6dl-tx6u-81xx-mb7.dtb \ - imx6dl-udoo.dtb \ - imx6dl-victgo.dtb \ - imx6dl-vicut1.dtb \ - imx6dl-wandboard.dtb \ - imx6dl-wandboard-revb1.dtb \ - imx6dl-wandboard-revd1.dtb \ - imx6dl-yapp4-draco.dtb \ - imx6dl-yapp4-hydra.dtb \ - imx6dl-yapp4-lynx.dtb \ - imx6dl-yapp4-orion.dtb \ - imx6dl-yapp4-phoenix.dtb \ - imx6dl-yapp4-ursa.dtb \ - imx6q-apalis-eval.dtb \ - imx6q-apalis-ixora.dtb \ - imx6q-apalis-ixora-v1.1.dtb \ - imx6q-apalis-ixora-v1.2.dtb \ - imx6q-apf6dev.dtb \ - imx6q-arm2.dtb \ - imx6q-b450v3.dtb \ - imx6q-b650v3.dtb \ - imx6q-b850v3.dtb \ - imx6q-bosch-acc.dtb \ - imx6q-cm-fx6.dtb \ - imx6q-cubox-i.dtb \ - imx6q-cubox-i-emmc-som-v15.dtb \ - imx6q-cubox-i-som-v15.dtb \ - imx6q-dfi-fs700-m60.dtb \ - imx6q-dhcom-pdk2.dtb \ - imx6q-display5-tianma-tm070-1280x768.dtb \ - imx6q-dmo-edmqmx6.dtb \ - imx6q-dms-ba16.dtb \ - imx6q-ds.dtb \ - imx6q-emcon-avari.dtb \ - imx6q-evi.dtb \ - imx6dl-b105pv2.dtb \ - imx6dl-b105v2.dtb \ - imx6dl-b125v2.dtb \ - imx6dl-b125pv2.dtb \ - imx6dl-b155v2.dtb \ - imx6q-gk802.dtb \ - imx6q-gw51xx.dtb \ - imx6q-gw52xx.dtb \ - imx6q-gw53xx.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ - imx6q-gw551x.dtb \ - imx6q-gw552x.dtb \ - imx6q-gw553x.dtb \ - imx6q-gw560x.dtb \ - imx6q-gw5903.dtb \ - imx6q-gw5904.dtb \ - imx6q-gw5907.dtb \ - imx6q-gw5910.dtb \ - imx6q-gw5912.dtb \ - imx6q-gw5913.dtb \ - imx6q-h100.dtb \ - imx6q-hummingboard.dtb \ - imx6q-hummingboard-emmc-som-v15.dtb \ - imx6q-hummingboard-som-v15.dtb \ - imx6q-hummingboard2.dtb \ - imx6q-hummingboard2-emmc-som-v15.dtb \ - imx6q-hummingboard2-som-v15.dtb \ - imx6q-icore.dtb \ - imx6q-icore-mipi.dtb \ - imx6q-icore-ofcap10.dtb \ - imx6q-icore-ofcap12.dtb \ - imx6q-icore-rqs.dtb \ - imx6q-kp-tpc.dtb \ - imx6q-logicpd.dtb \ - imx6q-marsboard.dtb \ - imx6q-mba6a.dtb \ - imx6q-mba6b.dtb \ - imx6q-mccmon6.dtb \ - imx6q-nitrogen6x.dtb \ - imx6q-nitrogen6_max.dtb \ - imx6q-nitrogen6_som2.dtb \ - imx6q-novena.dtb \ - imx6q-phytec-mira-rdk-emmc.dtb \ - imx6q-phytec-mira-rdk-nand.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-pico-dwarf.dtb \ - imx6q-pico-hobbit.dtb \ - imx6q-pico-nymph.dtb \ - imx6q-pico-pi.dtb \ - imx6q-pistachio.dtb \ - imx6q-prti6q.dtb \ - imx6q-prtwd2.dtb \ - imx6q-rex-pro.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ - imx6q-savageboard.dtb \ - imx6q-sbc6x.dtb \ - imx6q-skov-revc-lt2.dtb \ - imx6q-skov-revc-lt6.dtb \ - imx6q-skov-reve-mi1010ait-1cp1.dtb \ - imx6q-solidsense.dtb \ - imx6q-tbs2910.dtb \ - imx6q-ts4900.dtb \ - imx6q-ts7970.dtb \ - imx6q-tx6q-1010.dtb \ - imx6q-tx6q-1010-comtft.dtb \ - imx6q-tx6q-1020.dtb \ - imx6q-tx6q-1020-comtft.dtb \ - imx6q-tx6q-1036.dtb \ - imx6q-tx6q-1036-mb7.dtb \ - imx6q-tx6q-10x0-mb7.dtb \ - imx6q-tx6q-1110.dtb \ - imx6q-tx6q-11x0-mb7.dtb \ - imx6q-udoo.dtb \ - imx6q-utilite-pro.dtb \ - imx6q-var-dt6customboard.dtb \ - imx6q-vicut1.dtb \ - imx6q-wandboard.dtb \ - imx6q-wandboard-revb1.dtb \ - imx6q-wandboard-revd1.dtb \ - imx6q-yapp4-crux.dtb \ - imx6q-yapp4-pegasus.dtb \ - imx6q-zii-rdu2.dtb \ - imx6qp-mba6b.dtb \ - imx6qp-nitrogen6_max.dtb \ - imx6qp-nitrogen6_som2.dtb \ - imx6qp-phytec-mira-rdk-nand.dtb \ - imx6qp-prtwd3.dtb \ - imx6qp-sabreauto.dtb \ - imx6qp-sabresd.dtb \ - imx6qp-tx6qp-8037.dtb \ - imx6qp-tx6qp-8037-mb7.dtb \ - imx6qp-tx6qp-8137.dtb \ - imx6qp-tx6qp-8137-mb7.dtb \ - imx6qp-vicutp.dtb \ - imx6qp-wandboard-revd1.dtb \ - imx6qp-yapp4-crux-plus.dtb \ - imx6qp-yapp4-pegasus-plus.dtb \ - imx6qp-zii-rdu2.dtb \ - imx6s-dhcom-drc02.dtb -dtb-$(CONFIG_SOC_IMX6SL) += \ - imx6sl-evk.dtb \ - imx6sl-kobo-aura2.dtb \ - imx6sl-tolino-shine2hd.dtb \ - imx6sl-tolino-shine3.dtb \ - imx6sl-tolino-vision.dtb \ - imx6sl-tolino-vision5.dtb \ - imx6sl-warp.dtb -dtb-$(CONFIG_SOC_IMX6SLL) += \ - imx6sll-evk.dtb \ - imx6sll-kobo-clarahd.dtb \ - imx6sll-kobo-librah2o.dtb -dtb-$(CONFIG_SOC_IMX6SX) += \ - imx6sx-nitrogen6sx.dtb \ - imx6sx-sabreauto.dtb \ - imx6sx-sdb-reva.dtb \ - imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb \ - imx6sx-sdb-mqs.dtb \ - imx6sx-softing-vining-2000.dtb \ - imx6sx-udoo-neo-basic.dtb \ - imx6sx-udoo-neo-extended.dtb \ - imx6sx-udoo-neo-full.dtb -dtb-$(CONFIG_SOC_IMX6UL) += \ - imx6ul-14x14-evk.dtb \ - imx6ul-ccimx6ulsbcexpress.dtb \ - imx6ul-ccimx6ulsbcpro.dtb \ - imx6ul-geam.dtb \ - imx6ul-isiot-emmc.dtb \ - imx6ul-isiot-nand.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ul-kontron-bl-43.dtb \ - imx6ul-liteboard.dtb \ - imx6ul-tqma6ul1-mba6ulx.dtb \ - imx6ul-tqma6ul2-mba6ulx.dtb \ - imx6ul-tqma6ul2l-mba6ulx.dtb \ - imx6ul-opos6uldev.dtb \ - imx6ul-pico-dwarf.dtb \ - imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-phytec-segin-ff-rdk-emmc.dtb \ - imx6ul-phytec-segin-ff-rdk-nand.dtb \ - imx6ul-prti6g.dtb \ - imx6ul-tx6ul-0010.dtb \ - imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb \ - imx6ull-14x14-evk.dtb \ - imx6ull-colibri-aster.dtb \ - imx6ull-colibri-emmc-aster.dtb \ - imx6ull-colibri-emmc-eval-v3.dtb \ - imx6ull-colibri-emmc-iris.dtb \ - imx6ull-colibri-emmc-iris-v2.dtb \ - imx6ull-colibri-eval-v3.dtb \ - imx6ull-colibri-iris.dtb \ - imx6ull-colibri-iris-v2.dtb \ - imx6ull-colibri-wifi-aster.dtb \ - imx6ull-colibri-wifi-eval-v3.dtb \ - imx6ull-colibri-wifi-iris.dtb \ - imx6ull-colibri-wifi-iris-v2.dtb \ - imx6ull-dhcom-drc02.dtb \ - imx6ull-dhcom-pdk2.dtb \ - imx6ull-dhcom-picoitx.dtb \ - imx6ull-jozacp.dtb \ - imx6ull-kontron-bl.dtb \ - imx6ull-myir-mys-6ulx-eval.dtb \ - imx6ull-opos6uldev.dtb \ - imx6ull-phytec-segin-ff-rdk-nand.dtb \ - imx6ull-phytec-segin-ff-rdk-emmc.dtb \ - imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ull-phytec-tauri-emmc.dtb \ - imx6ull-phytec-tauri-nand.dtb \ - imx6ull-tarragon-master.dtb \ - imx6ull-tarragon-micro.dtb \ - imx6ull-tarragon-slave.dtb \ - imx6ull-tarragon-slavext.dtb \ - imx6ull-tqma6ull2-mba6ulx.dtb \ - imx6ull-tqma6ull2l-mba6ulx.dtb \ - imx6ulz-14x14-evk.dtb \ - imx6ulz-bsh-smm-m2.dtb -dtb-$(CONFIG_SOC_IMX7D) += \ - imx7d-cl-som-imx7.dtb \ - imx7d-colibri-aster.dtb \ - imx7d-colibri-emmc-aster.dtb \ - imx7d-colibri-emmc-iris.dtb \ - imx7d-colibri-emmc-iris-v2.dtb \ - imx7d-colibri-emmc-eval-v3.dtb \ - imx7d-colibri-eval-v3.dtb \ - imx7d-colibri-iris.dtb \ - imx7d-colibri-iris-v2.dtb \ - imx7d-flex-concentrator.dtb \ - imx7d-flex-concentrator-mfg.dtb \ - imx7d-mba7.dtb \ - imx7d-meerkat96.dtb \ - imx7d-nitrogen7.dtb \ - imx7d-pico-dwarf.dtb \ - imx7d-pico-hobbit.dtb \ - imx7d-pico-nymph.dtb \ - imx7d-pico-pi.dtb \ - imx7d-remarkable2.dtb \ - imx7d-sbc-imx7.dtb \ - imx7d-sdb.dtb \ - imx7d-sdb-reva.dtb \ - imx7d-sdb-sht11.dtb \ - imx7d-smegw01.dtb \ - imx7d-zii-rmu2.dtb \ - imx7d-zii-rpu2.dtb \ - imx7s-colibri-aster.dtb \ - imx7s-colibri-eval-v3.dtb \ - imx7s-colibri-iris.dtb \ - imx7s-colibri-iris-v2.dtb \ - imx7s-mba7.dtb \ - imx7s-warp.dtb -dtb-$(CONFIG_SOC_IMX7ULP) += \ - imx7ulp-com.dtb \ - imx7ulp-evk.dtb -dtb-$(CONFIG_SOC_IMXRT) += \ - imxrt1050-evk.dtb -dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ - lan966x-kontron-kswitch-d10-mmt-8g.dtb \ - lan966x-pcb8290.dtb \ - lan966x-pcb8291.dtb \ - lan966x-pcb8309.dtb -dtb-$(CONFIG_SOC_LS1021A) += \ - ls1021a-iot.dtb \ - ls1021a-moxa-uc-8410a.dtb \ - ls1021a-qds.dtb \ - ls1021a-tsn.dtb \ - ls1021a-twr.dtb -dtb-$(CONFIG_SOC_VF610) += \ - vf500-colibri-eval-v3.dtb \ - vf610-bk4.dtb \ - vf610-colibri-eval-v3.dtb \ - vf610m4-colibri.dtb \ - vf610-cosmic.dtb \ - vf610m4-cosmic.dtb \ - vf610-twr.dtb \ - vf610-zii-cfu1.dtb \ - vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb \ - vf610-zii-scu4-aib.dtb \ - vf610-zii-spb4.dtb \ - vf610-zii-ssmb-dtu.dtb \ - vf610-zii-ssmb-spu3.dtb -dtb-$(CONFIG_ARCH_MXS) += \ - imx23-evk.dtb \ - imx23-olinuxino.dtb \ - imx23-sansa.dtb \ - imx23-stmp378x_devb.dtb \ - imx23-xfi3.dtb \ - imx28-apf28.dtb \ - imx28-apf28dev.dtb \ - imx28-apx4devkit.dtb \ - imx28-cfa10036.dtb \ - imx28-cfa10037.dtb \ - imx28-cfa10049.dtb \ - imx28-cfa10055.dtb \ - imx28-cfa10056.dtb \ - imx28-cfa10057.dtb \ - imx28-cfa10058.dtb \ - imx28-duckbill-2-485.dtb \ - imx28-duckbill-2.dtb \ - imx28-duckbill-2-enocean.dtb \ - imx28-duckbill-2-spi.dtb \ - imx28-duckbill.dtb \ - imx28-eukrea-mbmx283lc.dtb \ - imx28-eukrea-mbmx287lc.dtb \ - imx28-evk.dtb \ - imx28-m28cu3.dtb \ - imx28-m28evk.dtb \ - imx28-sps1.dtb \ - imx28-ts4600.dtb \ - imx28-tx28.dtb \ - imx28-xea.dtb -dtb-$(CONFIG_ARCH_NOMADIK) += \ - ste-nomadik-s8815.dtb \ - ste-nomadik-nhk15.dtb -dtb-$(CONFIG_ARCH_NSPIRE) += \ - nspire-cx.dtb \ - nspire-tp.dtb \ - nspire-clp.dtb -dtb-$(CONFIG_ARCH_OMAP2) += \ - omap2420-h4.dtb \ - omap2420-n800.dtb \ - omap2420-n810.dtb \ - omap2420-n810-wimax.dtb \ - omap2430-sdp.dtb -dtb-$(CONFIG_ARCH_OMAP3) += \ - am3517-craneboard.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ - logicpd-torpedo-37xx-devkit.dtb \ - logicpd-som-lv-37xx-devkit.dtb \ - omap3430-sdp.dtb \ - omap3-beagle.dtb \ - omap3-beagle-ab4.dtb \ - omap3-beagle-xm.dtb \ - omap3-beagle-xm-ab.dtb \ - omap3-cm-t3517.dtb \ - omap3-cm-t3530.dtb \ - omap3-cm-t3730.dtb \ - omap3-devkit8000.dtb \ - omap3-devkit8000-lcd43.dtb \ - omap3-devkit8000-lcd70.dtb \ - omap3-echo.dtb \ - omap3-evm.dtb \ - omap3-evm-37xx.dtb \ - omap3-gta04a3.dtb \ - omap3-gta04a4.dtb \ - omap3-gta04a5.dtb \ - omap3-gta04a5one.dtb \ - omap3-ha.dtb \ - omap3-ha-lcd.dtb \ - omap3-igep0020.dtb \ - omap3-igep0020-rev-f.dtb \ - omap3-igep0030.dtb \ - omap3-igep0030-rev-g.dtb \ - omap3-ldp.dtb \ - omap3-lilly-dbb056.dtb \ - omap3-n900.dtb \ - omap3-n9.dtb \ - omap3-n950.dtb \ - omap3-overo-alto35.dtb \ - omap3-overo-chestnut43.dtb \ - omap3-overo-gallop43.dtb \ - omap3-overo-palo35.dtb \ - omap3-overo-palo43.dtb \ - omap3-overo-storm-alto35.dtb \ - omap3-overo-storm-chestnut43.dtb \ - omap3-overo-storm-gallop43.dtb \ - omap3-overo-storm-palo35.dtb \ - omap3-overo-storm-palo43.dtb \ - omap3-overo-storm-summit.dtb \ - omap3-overo-storm-tobi.dtb \ - omap3-overo-storm-tobiduo.dtb \ - omap3-overo-summit.dtb \ - omap3-overo-tobi.dtb \ - omap3-overo-tobiduo.dtb \ - omap3-pandora-600mhz.dtb \ - omap3-pandora-1ghz.dtb \ - omap3-sbc-t3517.dtb \ - omap3-sbc-t3530.dtb \ - omap3-sbc-t3730.dtb \ - omap3-sniper.dtb \ - omap3-thunder.dtb \ - omap3-zoom3.dtb -dtb-$(CONFIG_SOC_TI81XX) += \ - am3874-iceboard.dtb \ - dm8148-evm.dtb \ - dm8148-t410.dtb \ - dm8168-evm.dtb \ - dra62x-j5eco-evm.dtb -dtb-$(CONFIG_SOC_AM33XX) += \ - am335x-baltos-ir2110.dtb \ - am335x-baltos-ir3220.dtb \ - am335x-baltos-ir5221.dtb \ - am335x-base0033.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-boneblack-wireless.dtb \ - am335x-boneblue.dtb \ - am335x-bonegreen.dtb \ - am335x-bonegreen-wireless.dtb \ - am335x-chiliboard.dtb \ - am335x-cm-t335.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-guardian.dtb \ - am335x-icev2.dtb \ - am335x-lxm.dtb \ - am335x-moxa-uc-2101.dtb \ - am335x-moxa-uc-8100-me-t.dtb \ - am335x-myirtech-myd.dtb \ - am335x-nano.dtb \ - am335x-netcan-plus-1xx.dtb \ - am335x-netcom-plus-2xx.dtb \ - am335x-netcom-plus-8xx.dtb \ - am335x-pdu001.dtb \ - am335x-pepper.dtb \ - am335x-phycore-rdk.dtb \ - am335x-pocketbeagle.dtb \ - am335x-regor-rdk.dtb \ - am335x-sancloud-bbe.dtb \ - am335x-sancloud-bbe-lite.dtb \ - am335x-sancloud-bbe-extended-wifi.dtb \ - am335x-shc.dtb \ - am335x-sbc-t335.dtb \ - am335x-sl50.dtb \ - am335x-wega-rdk.dtb \ - am335x-osd3358-sm-red.dtb -dtb-$(CONFIG_ARCH_OMAP4) += \ - omap4-droid-bionic-xt875.dtb \ - omap4-droid4-xt894.dtb \ - omap4-duovero-parlor.dtb \ - omap4-kc1.dtb \ - omap4-panda.dtb \ - omap4-panda-a4.dtb \ - omap4-panda-es.dtb \ - omap4-sdp.dtb \ - omap4-sdp-es23plus.dtb \ - omap4-var-dvk-om44.dtb \ - omap4-var-stk-om44.dtb -dtb-$(CONFIG_SOC_AM43XX) += \ - am43x-epos-evm.dtb \ - am437x-cm-t43.dtb \ - am437x-gp-evm.dtb \ - am437x-idk-evm.dtb \ - am437x-sbc-t43.dtb \ - am437x-sk-evm.dtb -dtb-$(CONFIG_SOC_OMAP5) += \ - omap5-cm-t54.dtb \ - omap5-igep0050.dtb \ - omap5-sbc-t54.dtb \ - omap5-uevm.dtb -am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo -am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo -dtb-$(CONFIG_SOC_DRA7XX) += \ - am57xx-beagle-x15.dtb \ - am57xx-beagle-x15-revb1.dtb \ - am57xx-beagle-x15-revc.dtb \ - am57xx-evm.dtb \ - am57xx-evm-reva3.dtb \ - am5729-beagleboneai.dtb \ - am57xx-cl-som-am57x.dtb \ - am57xx-sbc-am57x.dtb \ - am572x-idk.dtb \ - am572x-idk-touchscreen.dtbo \ - am571x-idk.dtb \ - am571x-idk-touchscreen.dtbo \ - am574x-idk.dtb \ - am57xx-idk-lcd-osd101t2045.dtbo \ - am57xx-idk-lcd-osd101t2587.dtbo \ - dra7-evm.dtb \ - dra72-evm.dtb \ - dra72-evm-revc.dtb \ - dra71-evm.dtb \ - dra76-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-kuroboxpro.dtb \ - orion5x-lacie-d2-network.dtb \ - orion5x-lacie-ethernet-disk-mini-v2.dtb \ - orion5x-linkstation-lsgl.dtb \ - orion5x-linkstation-lswtgl.dtb \ - orion5x-linkstation-lschl.dtb \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-netgear-wnr854t.dtb \ - orion5x-rd88f5182-nas.dtb -dtb-$(CONFIG_ARCH_ACTIONS) += \ - owl-s500-cubieboard6.dtb \ - owl-s500-guitar-bb-rev-b.dtb \ - owl-s500-labrador-base-m.dtb \ - owl-s500-roseapplepi.dtb \ - owl-s500-sparky.dtb -dtb-$(CONFIG_ARCH_PXA) += \ - pxa300-raumfeld-connector.dtb \ - pxa300-raumfeld-controller.dtb \ - pxa300-raumfeld-speaker-l.dtb \ - pxa300-raumfeld-speaker-m.dtb \ - pxa300-raumfeld-speaker-one.dtb \ - pxa300-raumfeld-speaker-s.dtb -dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8016-sbc.dtb \ - qcom-apq8026-asus-sparrow.dtb \ - qcom-apq8026-huawei-sturgeon.dtb \ - qcom-apq8026-lg-lenok.dtb \ - qcom-apq8026-samsung-matisse-wifi.dtb \ - qcom-apq8060-dragonboard.dtb \ - qcom-apq8064-cm-qs600.dtb \ - qcom-apq8064-ifc6410.dtb \ - qcom-apq8064-sony-xperia-lagan-yuga.dtb \ - qcom-apq8064-asus-nexus7-flo.dtb \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ - qcom-ipq4018-ap120c-ac.dtb \ - qcom-ipq4018-ap120c-ac-bit.dtb \ - qcom-ipq4018-jalapeno.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-ipq8064-rb3011.dtb \ - qcom-msm8226-samsung-s3ve3g.dtb \ - qcom-msm8660-surf.dtb \ - qcom-msm8916-samsung-e5.dtb \ - qcom-msm8916-samsung-e7.dtb \ - qcom-msm8916-samsung-grandmax.dtb \ - qcom-msm8916-samsung-serranove.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-rhine-amami.dtb \ - qcom-msm8974-sony-xperia-rhine-honami.dtb \ - qcom-msm8974pro-fairphone-fp2.dtb \ - qcom-msm8974pro-oneplus-bacon.dtb \ - qcom-msm8974pro-samsung-klte.dtb \ - qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ - qcom-mdm9615-wp8548-mangoh-green.dtb \ - qcom-sdx55-mtp.dtb \ - qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb \ - qcom-sdx65-mtp.dtb -dtb-$(CONFIG_ARCH_RDA) += \ - rda8810pl-orangepi-2g-iot.dtb \ - rda8810pl-orangepi-i96.dtb -dtb-$(CONFIG_ARCH_REALTEK) += \ - rtd1195-horseradish.dtb \ - rtd1195-mele-x1000.dtb -dtb-$(CONFIG_ARCH_REALVIEW) += \ - arm-realview-pb1176.dtb \ - arm-realview-pb11mp.dtb \ - arm-realview-eb.dtb \ - arm-realview-eb-bbrevd.dtb \ - arm-realview-eb-11mp.dtb \ - arm-realview-eb-11mp-bbrevd.dtb \ - arm-realview-eb-11mp-ctrevb.dtb \ - arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ - arm-realview-eb-a9mp.dtb \ - arm-realview-eb-a9mp-bbrevd.dtb \ - arm-realview-pba8.dtb \ - arm-realview-pbx-a9.dtb -dtb-$(CONFIG_ARCH_RENESAS) += \ - emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ - r7s72100-gr-peach.dtb \ - r7s72100-rskrza1.dtb \ - r7s9210-rza2mevb.dtb \ - r8a73a4-ape6evm.dtb \ - r8a7740-armadillo800eva.dtb \ - r8a7742-iwg21d-q7.dtb \ - r8a7742-iwg21d-q7-dbcm-ca.dtb \ - r8a7743-iwg20d-q7.dtb \ - r8a7743-iwg20d-q7-dbcm-ca.dtb \ - r8a7743-sk-rzg1m.dtb \ - r8a7744-iwg20d-q7.dtb \ - r8a7744-iwg20d-q7-dbcm-ca.dtb \ - r8a7745-iwg22d-sodimm.dtb \ - r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ - r8a7745-sk-rzg1e.dtb \ - r8a77470-iwg23s-sbc.dtb \ - r8a7778-bockw.dtb \ - r8a7779-marzen.dtb \ - r8a7790-lager.dtb \ - r8a7790-stout.dtb \ - r8a7791-koelsch.dtb \ - r8a7791-porter.dtb \ - r8a7792-blanche.dtb \ - r8a7792-wheat.dtb \ - r8a7793-gose.dtb \ - r8a7794-alt.dtb \ - r8a7794-silk.dtb \ - r9a06g032-rzn1d400-db.dtb \ - sh73a0-kzm9g.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rv1108-elgin-r1.dtb \ - rv1108-evb.dtb \ - rv1126-edgeble-neu2-io.dtb \ - rk3036-evb.dtb \ - rk3036-kylin.dtb \ - rk3066a-bqcurie2.dtb \ - rk3066a-marsboard.dtb \ - rk3066a-mk808.dtb \ - rk3066a-rayeager.dtb \ - rk3128-evb.dtb \ - rk3188-bqedison2qc.dtb \ - rk3188-px3-evb.dtb \ - rk3188-radxarock.dtb \ - rk3228-evb.dtb \ - rk3229-evb.dtb \ - rk3229-xms6.dtb \ - rk3288-evb-act8846.dtb \ - rk3288-evb-rk808.dtb \ - rk3288-firefly-beta.dtb \ - rk3288-firefly.dtb \ - rk3288-firefly-reload.dtb \ - rk3288-miqi.dtb \ - rk3288-phycore-rdk.dtb \ - rk3288-popmetal.dtb \ - rk3288-r89.dtb \ - rk3288-rock2-square.dtb \ - rk3288-rock-pi-n8.dtb \ - rk3288-tinker.dtb \ - rk3288-tinker-s.dtb \ - rk3288-veyron-brain.dtb \ - rk3288-veyron-fievel.dtb \ - rk3288-veyron-jaq.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-mighty.dtb \ - rk3288-veyron-minnie.dtb \ - rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb \ - rk3288-veyron-tiger.dtb \ - rk3288-vyasa.dtb -dtb-$(CONFIG_ARCH_S3C64XX) += \ - s3c6410-mini6410.dtb \ - s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_S5PV210) += \ - s5pv210-aquila.dtb \ - s5pv210-fascinate4g.dtb \ - s5pv210-galaxys.dtb \ - s5pv210-goni.dtb \ - s5pv210-smdkc110.dtb \ - s5pv210-smdkv210.dtb \ - s5pv210-torbreck.dtb -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ - socfpga_arria5_socdk.dtb \ - socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ - socfpga_arria10_socdk_nand.dtb \ - socfpga_arria10_socdk_qspi.dtb \ - socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_cyclone5_chameleon96.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sodia.dtb \ - socfpga_cyclone5_vining_fpga.dtb \ - socfpga_vt.dtb -dtb-$(CONFIG_ARCH_SPEAR13XX) += \ - spear1310-evb.dtb \ - spear1340-evb.dtb -dtb-$(CONFIG_ARCH_SPEAR3XX) += \ - spear300-evb.dtb \ - spear310-evb.dtb \ - spear320-evb.dtb \ - spear320-hmi.dtb -dtb-$(CONFIG_ARCH_SPEAR6XX) += \ - spear600-evb.dtb -dtb-$(CONFIG_ARCH_STI) += \ - stih407-b2120.dtb \ - stih410-b2120.dtb \ - stih410-b2260.dtb \ - stih418-b2199.dtb \ - stih418-b2264.dtb -dtb-$(CONFIG_ARCH_STM32) += \ - stm32f429-disco.dtb \ - stm32f469-disco.dtb \ - stm32f746-disco.dtb \ - stm32f769-disco.dtb \ - stm32429i-eval.dtb \ - stm32746g-eval.dtb \ - stm32h743i-eval.dtb \ - stm32h743i-disco.dtb \ - stm32h750i-art-pi.dtb \ - stm32mp135f-dk.dtb \ - stm32mp151a-prtt1a.dtb \ - stm32mp151a-prtt1c.dtb \ - stm32mp151a-prtt1s.dtb \ - stm32mp151a-dhcor-testbench.dtb \ - stm32mp153c-dhcom-drc02.dtb \ - stm32mp153c-dhcor-drc-compact.dtb \ - stm32mp157a-avenger96.dtb \ - stm32mp157a-dhcor-avenger96.dtb \ - stm32mp157a-dk1.dtb \ - stm32mp157a-dk1-scmi.dtb \ - stm32mp157a-iot-box.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ - stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ - stm32mp157a-stinger96.dtb \ - stm32mp157c-dhcom-pdk2.dtb \ - stm32mp157c-dhcom-picoitx.dtb \ - stm32mp157c-dk2.dtb \ - stm32mp157c-dk2-scmi.dtb \ - stm32mp157c-ed1.dtb \ - stm32mp157c-ed1-scmi.dtb \ - stm32mp157c-emsbc-argon.dtb \ - stm32mp157c-ev1.dtb \ - stm32mp157c-ev1-scmi.dtb \ - stm32mp157c-lxa-mc1.dtb \ - stm32mp157c-odyssey.dtb -dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ - sun4i-a10-ba10-tvbox.dtb \ - sun4i-a10-chuwi-v7-cw0825.dtb \ - sun4i-a10-cubieboard.dtb \ - sun4i-a10-dserve-dsrv9703c.dtb \ - sun4i-a10-gemei-g9.dtb \ - sun4i-a10-hackberry.dtb \ - sun4i-a10-hyundai-a7hd.dtb \ - sun4i-a10-inet1.dtb \ - sun4i-a10-inet97fv2.dtb \ - sun4i-a10-inet9f-rev03.dtb \ - sun4i-a10-itead-iteaduino-plus.dtb \ - sun4i-a10-jesurun-q5.dtb \ - sun4i-a10-marsboard.dtb \ - sun4i-a10-mini-xplus.dtb \ - sun4i-a10-mk802.dtb \ - sun4i-a10-mk802ii.dtb \ - sun4i-a10-olinuxino-lime.dtb \ - sun4i-a10-pcduino.dtb \ - sun4i-a10-pcduino2.dtb \ - sun4i-a10-pov-protab2-ips9.dtb \ - sun4i-a10-topwise-a721.dtb -dtb-$(CONFIG_MACH_SUN5I) += \ - sun5i-a10s-auxtek-t003.dtb \ - sun5i-a10s-auxtek-t004.dtb \ - sun5i-a10s-mk802.dtb \ - sun5i-a10s-olinuxino-micro.dtb \ - sun5i-a10s-r7-tv-dongle.dtb \ - sun5i-a10s-wobo-i5.dtb \ - sun5i-a13-difrnce-dit4350.dtb \ - sun5i-a13-empire-electronix-d709.dtb \ - sun5i-a13-empire-electronix-m712.dtb \ - sun5i-a13-hsg-h702.dtb \ - sun5i-a13-inet-98v-rev2.dtb \ - sun5i-a13-licheepi-one.dtb \ - sun5i-a13-olinuxino.dtb \ - sun5i-a13-olinuxino-micro.dtb \ - sun5i-a13-pocketbook-touch-lux-3.dtb \ - sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb \ - sun5i-gr8-chip-pro.dtb \ - sun5i-gr8-evb.dtb \ - sun5i-r8-chip.dtb -dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-app4-evb1.dtb \ - sun6i-a31-colombus.dtb \ - sun6i-a31-hummingbird.dtb \ - sun6i-a31-i7.dtb \ - sun6i-a31-m9.dtb \ - sun6i-a31-mele-a1000g-quad.dtb \ - sun6i-a31s-colorfly-e708-q1.dtb \ - sun6i-a31s-cs908.dtb \ - sun6i-a31s-inet-q972.dtb \ - sun6i-a31s-primo81.dtb \ - sun6i-a31s-sina31s.dtb \ - sun6i-a31s-sinovoip-bpi-m2.dtb \ - sun6i-a31s-yones-toptech-bs1078-v2.dtb -dtb-$(CONFIG_MACH_SUN7I) += \ - sun7i-a20-bananapi.dtb \ - sun7i-a20-bananapi-m1-plus.dtb \ - sun7i-a20-bananapro.dtb \ - sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-haoyu-marsboard.dtb \ - sun7i-a20-hummingbird.dtb \ - sun7i-a20-itead-ibox.dtb \ - sun7i-a20-i12-tvbox.dtb \ - sun7i-a20-icnova-swac.dtb \ - sun7i-a20-lamobo-r1.dtb \ - sun7i-a20-linutronix-testbox-v2.dtb \ - sun7i-a20-m3.dtb \ - sun7i-a20-mk808c.dtb \ - sun7i-a20-olimex-som-evb.dtb \ - sun7i-a20-olimex-som-evb-emmc.dtb \ - sun7i-a20-olimex-som204-evb.dtb \ - sun7i-a20-olimex-som204-evb-emmc.dtb \ - sun7i-a20-olinuxino-lime.dtb \ - sun7i-a20-olinuxino-lime-emmc.dtb \ - sun7i-a20-olinuxino-lime2.dtb \ - sun7i-a20-olinuxino-lime2-emmc.dtb \ - sun7i-a20-olinuxino-micro.dtb \ - sun7i-a20-olinuxino-micro-emmc.dtb \ - sun7i-a20-orangepi.dtb \ - sun7i-a20-orangepi-mini.dtb \ - sun7i-a20-pcduino3.dtb \ - sun7i-a20-pcduino3-nano.dtb \ - sun7i-a20-wexler-tab7200.dtb \ - sun7i-a20-wits-pro-a20-dkt.dtb -dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a23-evb.dtb \ - sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-inet86dz.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ - sun8i-a23-polaroid-mid2407pxe03.dtb \ - sun8i-a23-polaroid-mid2809pxe04.dtb \ - sun8i-a23-q8-tablet.dtb \ - sun8i-a33-et-q8-v1.6.dtb \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-inet-d978-rev2.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-bananapi-m2-plus-v1.2.dtb \ - sun8i-h3-beelink-x2.dtb \ - sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-mapleboard-mp130.dtb \ - sun8i-h3-nanopi-duo2.dtb \ - sun8i-h3-nanopi-m1.dtb \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ - sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ - sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-zeropi.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ - sun8i-r16-parrot.dtb \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-r40-oka40i-c.dtb \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-lichee-zero-plus.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-t113s-mangopi-mq-r-t113.dtb \ - sun8i-t3-cqa3t-bv3.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb \ - sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ - sun9i-a80-cubieboard4.dtb -dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb \ - suniv-f1c200s-lctech-pi.dtb \ - suniv-f1c200s-popstick-v1.1.dtb -dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ - tegra20-acer-a500-picasso.dtb \ - tegra20-asus-tf101.dtb \ - tegra20-harmony.dtb \ - tegra20-colibri-eval-v3.dtb \ - tegra20-colibri-iris.dtb \ - tegra20-medcom-wide.dtb \ - tegra20-paz00.dtb \ - tegra20-plutux.dtb \ - tegra20-seaboard.dtb \ - tegra20-tec.dtb \ - tegra20-trimslice.dtb \ - tegra20-ventana.dtb -dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ - tegra30-apalis-eval.dtb \ - tegra30-apalis-v1.1-eval.dtb \ - tegra30-asus-nexus7-grouper-PM269.dtb \ - tegra30-asus-nexus7-grouper-E1565.dtb \ - tegra30-asus-nexus7-tilapia-E1565.dtb \ - tegra30-asus-tf201.dtb \ - tegra30-asus-tf300t.dtb \ - tegra30-asus-tf300tg.dtb \ - tegra30-asus-tf700t.dtb \ - tegra30-beaver.dtb \ - tegra30-cardhu-a02.dtb \ - tegra30-cardhu-a04.dtb \ - tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb \ - tegra30-pegatron-chagall.dtb -dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ - tegra114-asus-tf701t.dtb \ - tegra114-dalmore.dtb \ - tegra114-roth.dtb \ - tegra114-tn7.dtb -dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ - tegra124-apalis-eval.dtb \ - tegra124-apalis-v1.2-eval.dtb \ - tegra124-jetson-tk1.dtb \ - tegra124-nyan-big.dtb \ - tegra124-nyan-big-fhd.dtb \ - tegra124-nyan-blaze.dtb \ - tegra124-venice2.dtb -dtb-$(CONFIG_ARCH_U8500) += \ - ste-snowball.dtb \ - ste-hrefprev60-stuib.dtb \ - ste-hrefprev60-tvk.dtb \ - ste-hrefv60plus-stuib.dtb \ - ste-hrefv60plus-tvk.dtb \ - ste-href520-tvk.dtb \ - ste-ux500-samsung-golden.dtb \ - ste-ux500-samsung-janice.dtb \ - ste-ux500-samsung-gavini.dtb \ - ste-ux500-samsung-codina.dtb \ - ste-ux500-samsung-codina-tmo.dtb \ - ste-ux500-samsung-skomer.dtb \ - ste-ux500-samsung-kyle.dtb -dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ld4-ref.dtb \ - uniphier-ld6b-ref.dtb \ - uniphier-pro4-ace.dtb \ - uniphier-pro4-ref.dtb \ - uniphier-pro4-sanji.dtb \ - uniphier-pro5-epcore.dtb \ - uniphier-pro5-proex.dtb \ - uniphier-pxs2-gentil.dtb \ - uniphier-pxs2-vodka.dtb \ - uniphier-sld8-ref.dtb -dtb-$(CONFIG_ARCH_VERSATILE) += \ - versatile-ab.dtb \ - versatile-ab-ib2.dtb \ - versatile-pb.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += \ - vexpress-v2p-ca5s.dtb \ - vexpress-v2p-ca9.dtb \ - vexpress-v2p-ca15-tc1.dtb \ - vexpress-v2p-ca15_a7.dtb -dtb-$(CONFIG_ARCH_VIRT) += \ - xenvm-4.2.dtb -dtb-$(CONFIG_ARCH_VT8500) += \ - vt8500-bv07.dtb \ - wm8505-ref.dtb \ - wm8650-mid.dtb \ - wm8750-apc8750.dtb \ - wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += \ - zynq-cc108.dtb \ - zynq-ebaz4205.dtb \ - zynq-microzed.dtb \ - zynq-parallella.dtb \ - zynq-zc702.dtb \ - zynq-zc706.dtb \ - zynq-zc770-xm010.dtb \ - zynq-zc770-xm011.dtb \ - zynq-zc770-xm012.dtb \ - zynq-zc770-xm013.dtb \ - zynq-zed.dtb \ - zynq-zturn.dtb \ - zynq-zturn-v5.dtb \ - zynq-zybo.dtb \ - zynq-zybo-z7.dtb -dtb-$(CONFIG_MACH_ARMADA_370) += \ - armada-370-c200-v2.dtb \ - armada-370-db.dtb \ - armada-370-dlink-dns327l.dtb \ - armada-370-mirabox.dtb \ - armada-370-netgear-rn102.dtb \ - armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb \ - armada-370-seagate-nas-2bay.dtb \ - armada-370-seagate-nas-4bay.dtb \ - armada-370-seagate-personal-cloud.dtb \ - armada-370-seagate-personal-cloud-2bay.dtb \ - armada-370-synology-ds213j.dtb -dtb-$(CONFIG_MACH_ARMADA_375) += \ - armada-375-db.dtb -dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-381-netgear-gs110emx.dtb \ - armada-382-rd-ac3x-48g4x2xl.dtb \ - armada-385-atl-x530.dtb\ - armada-385-clearfog-gtr-s4.dtb \ - armada-385-clearfog-gtr-l8.dtb \ - armada-385-db-88f6820-amc.dtb \ - armada-385-db-ap.dtb \ - armada-385-linksys-caiman.dtb \ - armada-385-linksys-cobra.dtb \ - armada-385-linksys-rango.dtb \ - armada-385-linksys-shelby.dtb \ - armada-385-synology-ds116.dtb \ - armada-385-turris-omnia.dtb \ - armada-388-clearfog.dtb \ - armada-388-clearfog-base.dtb \ - armada-388-clearfog-pro.dtb \ - armada-388-db.dtb \ - armada-388-gp.dtb \ - armada-388-helios4.dtb \ - armada-388-rd.dtb -dtb-$(CONFIG_MACH_ARMADA_39X) += \ - armada-398-db.dtb -dtb-$(CONFIG_MACH_ARMADA_XP) += \ - armada-xp-axpwifiap.dtb \ - armada-xp-crs305-1g-4s.dtb \ - armada-xp-crs305-1g-4s-bit.dtb \ - armada-xp-crs326-24g-2s.dtb \ - armada-xp-crs326-24g-2s-bit.dtb \ - armada-xp-crs328-4c-20s-4s.dtb \ - armada-xp-crs328-4c-20s-4s-bit.dtb \ - armada-xp-db.dtb \ - armada-xp-db-dxbc2.dtb \ - armada-xp-db-xc3-24g4xg.dtb \ - armada-xp-gp.dtb \ - armada-xp-lenovo-ix4-300d.dtb \ - armada-xp-linksys-mamba.dtb \ - armada-xp-matrix.dtb \ - armada-xp-netgear-rn2120.dtb \ - armada-xp-openblocks-ax3-4.dtb \ - armada-xp-synology-ds414.dtb -dtb-$(CONFIG_MACH_DOVE) += \ - dove-cubox.dtb \ - dove-cubox-es.dtb \ - dove-d2plug.dtb \ - dove-d3plug.dtb \ - dove-dove-db.dtb \ - dove-sbc-a510.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt2701-evb.dtb \ - mt6580-evbp1.dtb \ - mt6589-aquaris5.dtb \ - mt6589-fairphone-fp1.dtb \ - mt6592-evb.dtb \ - mt7623a-rfb-emmc.dtb \ - mt7623a-rfb-nand.dtb \ - mt7623n-rfb-emmc.dtb \ - mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ - mt8127-moose.dtb \ - mt8135-evbp1.dtb -dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb -dtb-$(CONFIG_ARCH_MSTARV7) += \ - mstar-infinity-msc313-breadbee_crust.dtb \ - mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ - mstar-infinity2m-ssd202d-miyoo-mini.dtb \ - mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ - mstar-infinity2m-ssd202d-ssd201htv2.dtb \ - mstar-infinity2m-ssd202d-unitv2.dtb \ - mstar-infinity3-msc313e-breadbee.dtb \ - mstar-mercury5-ssc8336n-midrived08.dtb -dtb-$(CONFIG_ARCH_ASPEED) += \ - aspeed-ast2500-evb.dtb \ - aspeed-ast2600-evb-a1.dtb \ - aspeed-ast2600-evb.dtb \ - aspeed-bmc-amd-daytonax.dtb \ - aspeed-bmc-amd-ethanolx.dtb \ - aspeed-bmc-ampere-mtjade.dtb \ - aspeed-bmc-ampere-mtmitchell.dtb \ - aspeed-bmc-arm-stardragon4800-rep2.dtb \ - aspeed-bmc-asrock-e3c246d4i.dtb \ - aspeed-bmc-asrock-romed8hm3.dtb \ - aspeed-bmc-bytedance-g220a.dtb \ - aspeed-bmc-delta-ahe50dc.dtb \ - aspeed-bmc-facebook-bletchley.dtb \ - aspeed-bmc-facebook-cloudripper.dtb \ - aspeed-bmc-facebook-cmm.dtb \ - aspeed-bmc-facebook-elbert.dtb \ - aspeed-bmc-facebook-fuji.dtb \ - aspeed-bmc-facebook-galaxy100.dtb \ - aspeed-bmc-facebook-greatlakes.dtb \ - aspeed-bmc-facebook-minipack.dtb \ - aspeed-bmc-facebook-tiogapass.dtb \ - aspeed-bmc-facebook-wedge40.dtb \ - aspeed-bmc-facebook-wedge100.dtb \ - aspeed-bmc-facebook-wedge400.dtb \ - aspeed-bmc-facebook-yamp.dtb \ - aspeed-bmc-facebook-yosemitev2.dtb \ - aspeed-bmc-ibm-bonnell.dtb \ - aspeed-bmc-ibm-everest.dtb \ - aspeed-bmc-ibm-rainier.dtb \ - aspeed-bmc-ibm-rainier-1s4u.dtb \ - aspeed-bmc-ibm-rainier-4u.dtb \ - aspeed-bmc-intel-s2600wf.dtb \ - aspeed-bmc-inspur-fp5280g2.dtb \ - aspeed-bmc-inspur-nf5280m6.dtb \ - aspeed-bmc-lenovo-hr630.dtb \ - aspeed-bmc-lenovo-hr855xg2.dtb \ - aspeed-bmc-microsoft-olympus.dtb \ - aspeed-bmc-opp-lanyang.dtb \ - aspeed-bmc-opp-mowgli.dtb \ - aspeed-bmc-opp-nicole.dtb \ - aspeed-bmc-opp-palmetto.dtb \ - aspeed-bmc-opp-romulus.dtb \ - aspeed-bmc-opp-swift.dtb \ - aspeed-bmc-opp-tacoma.dtb \ - aspeed-bmc-opp-vesnin.dtb \ - aspeed-bmc-opp-witherspoon.dtb \ - aspeed-bmc-opp-zaius.dtb \ - aspeed-bmc-portwell-neptune.dtb \ - aspeed-bmc-qcom-dc-scm-v1.dtb \ - aspeed-bmc-quanta-q71l.dtb \ - aspeed-bmc-quanta-s6q.dtb \ - aspeed-bmc-supermicro-x11spi.dtb \ - aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb \ - aspeed-bmc-tyan-s8036.dtb \ - aspeed-bmc-ufispace-ncplite.dtb \ - aspeed-bmc-vegman-n110.dtb \ - aspeed-bmc-vegman-rx20.dtb \ - aspeed-bmc-vegman-sx20.dtb +subdir-y += actions +subdir-y += airoha +subdir-y += allwinner +subdir-y += alphascale +subdir-y += amazon +subdir-y += amlogic +subdir-y += arm +subdir-y += aspeed +subdir-y += axis +subdir-y += broadcom +subdir-y += calxeda +subdir-y += cirrus +subdir-y += cnxt +subdir-y += gemini +subdir-y += hisilicon +subdir-y += hpe +subdir-y += intel +subdir-y += marvell +subdir-y += mediatek +subdir-y += microchip +subdir-y += moxa +subdir-y += nspire +subdir-y += nuvoton +subdir-y += nvidia +subdir-y += nxp +subdir-y += qcom +subdir-y += realtek +subdir-y += renesas +subdir-y += rockchip +subdir-y += samsung +subdir-y += sigmastar +subdir-y += socionext +subdir-y += st +subdir-y += sunplus +subdir-y += synaptics +subdir-y += ti +subdir-y += unisoc +subdir-y += vt8500 +subdir-y += xen +subdir-y += xilinx diff --git a/arch/arm/boot/dts/actions/Makefile b/arch/arm/boot/dts/actions/Makefile new file mode 100644 index 000000000000..f384e4a48e6f --- /dev/null +++ b/arch/arm/boot/dts/actions/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ACTIONS) += \ + owl-s500-cubieboard6.dtb \ + owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-labrador-base-m.dtb \ + owl-s500-roseapplepi.dtb \ + owl-s500-sparky.dtb diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-cubieboard6.dts rename to arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts rename to arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts diff --git a/arch/arm/boot/dts/owl-s500-guitar.dtsi b/arch/arm/boot/dts/actions/owl-s500-guitar.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500-guitar.dtsi rename to arch/arm/boot/dts/actions/owl-s500-guitar.dtsi diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-labrador-base-m.dts rename to arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500-labrador-v2.dtsi rename to arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-roseapplepi.dts rename to arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/actions/owl-s500-sparky.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-sparky.dts rename to arch/arm/boot/dts/actions/owl-s500-sparky.dts diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/actions/owl-s500.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500.dtsi rename to arch/arm/boot/dts/actions/owl-s500.dtsi diff --git a/arch/arm/boot/dts/airoha/Makefile b/arch/arm/boot/dts/airoha/Makefile new file mode 100644 index 000000000000..00c31389f622 --- /dev/null +++ b/arch/arm/boot/dts/airoha/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/airoha/en7523-evb.dts similarity index 100% rename from arch/arm/boot/dts/en7523-evb.dts rename to arch/arm/boot/dts/airoha/en7523-evb.dts diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/airoha/en7523.dtsi similarity index 99% rename from arch/arm/boot/dts/en7523.dtsi rename to arch/arm/boot/dts/airoha/en7523.dtsi index 7f839331a777..b523a868c4ad 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/airoha/en7523.dtsi @@ -81,6 +81,8 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..589a1ce1120a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb\ + \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb diff --git a/arch/arm/boot/dts/axp152.dtsi b/arch/arm/boot/dts/allwinner/axp152.dtsi similarity index 100% rename from arch/arm/boot/dts/axp152.dtsi rename to arch/arm/boot/dts/allwinner/axp152.dtsi diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/allwinner/axp209.dtsi similarity index 96% rename from arch/arm/boot/dts/axp209.dtsi rename to arch/arm/boot/dts/allwinner/axp209.dtsi index ca240cd6f6c3..469d0f7d5185 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/allwinner/axp209.dtsi @@ -48,6 +48,13 @@ * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf */ +/ { + pmic-temp { + compatible = "iio-hwmon"; + io-channels = <&axp_adc 4>; /* Internal temperature */ + }; +}; + &axp209 { compatible = "x-powers,axp209"; interrupt-controller; diff --git a/arch/arm/boot/dts/axp223.dtsi b/arch/arm/boot/dts/allwinner/axp223.dtsi similarity index 100% rename from arch/arm/boot/dts/axp223.dtsi rename to arch/arm/boot/dts/allwinner/axp223.dtsi diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/allwinner/axp22x.dtsi similarity index 100% rename from arch/arm/boot/dts/axp22x.dtsi rename to arch/arm/boot/dts/allwinner/axp22x.dtsi diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/allwinner/axp809.dtsi similarity index 100% rename from arch/arm/boot/dts/axp809.dtsi rename to arch/arm/boot/dts/allwinner/axp809.dtsi diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi similarity index 100% rename from arch/arm/boot/dts/axp81x.dtsi rename to arch/arm/boot/dts/allwinner/axp81x.dtsi diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-a1000.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-cubieboard.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-gemei-g9.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-hackberry.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet1.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet97fv2.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-marsboard.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mini-xplus.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mk802.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mk802ii.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pcduino.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pcduino2.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts diff --git a/arch/arm/boot/dts/sun4i-a10-topwise-a721.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-topwise-a721.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi similarity index 100% rename from arch/arm/boot/dts/sun4i-a10.dtsi rename to arch/arm/boot/dts/allwinner/sun4i-a10.dtsi diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-mk802.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-hsg-h702.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-licheepi-one.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-olinuxino.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts diff --git a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-utoo-p66.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-a13.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-a13.dtsi diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8-chip-pro.dts rename to arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8-evb.dts rename to arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts similarity index 97% rename from arch/arm/boot/dts/sun5i-r8-chip.dts rename to arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts index fd37bd1f3920..4192c23848c3 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts @@ -255,6 +255,12 @@ pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + }; }; &usb_otg { diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-r8.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-r8.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-r8.dtsi diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi similarity index 98% rename from arch/arm/boot/dts/sun5i.dtsi rename to arch/arm/boot/dts/allwinner/sun5i.dtsi index 250d6b87ab4d..d7c7b454a11a 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi @@ -286,7 +286,7 @@ clock-names = "ahb", "tcon-ch0", "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; status = "disabled"; @@ -517,6 +517,15 @@ bias-pull-up; }; + /omit-if-no-ref/ + mmc2_4bit_pe_pins: mmc2-4bit-pe-pins { + pins = "PE4", "PE5", "PE6", "PE7", + "PE8", "PE9"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-app4-evb1.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-colombus.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-hummingbird.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-i7.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-m9.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-cs908.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-inet-q972.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-primo81.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sina31s.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapi.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapro.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-cubieboard2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-cubietruck.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts diff --git a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-hummingbird.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts new file mode 100644 index 000000000000..577ead1d02a0 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +/dts-v1/; + +#include "sun7i-a20-icnova-a20.dtsi" + +#include +#include + +/ { + model = "In-Circuit ICnova A20 ADB4006"; + compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +&ac_power_supply { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi new file mode 100644 index 000000000000..46616c6bc899 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-icnova-swac.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-itead-ibox.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts diff --git a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-m3.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-mk808c.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-orangepi.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-pcduino3.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi similarity index 100% rename from arch/arm/boot/dts/sun7i-a20.dtsi rename to arch/arm/boot/dts/allwinner/sun7i-a20.dtsi diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi similarity index 99% rename from arch/arm/boot/dts/sun8i-a23-a33.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi index 4aa9d88c9ea3..cd4bf60dbb3c 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi @@ -190,7 +190,7 @@ clock-names = "ahb", "tcon-ch0", "lvds-alt"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_LCD>, <&ccu RST_BUS_LVDS>; diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-evb.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-inet86dz.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a23.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a23.dtsi diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-olinuxino.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a33.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a33.dtsi diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi similarity index 99% rename from arch/arm/boot/dts/sun8i-a83t.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index 82fdb04122ca..94eb3bfc989e 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -456,7 +456,7 @@ interrupts = ; clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-beelink-x2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi similarity index 82% rename from arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi index eedd5da5dc2f..35e71f46c197 100644 --- a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun8i-h3.dtsi" -#include +#include "sunxi-h3-h5-emlid-neutis.dtsi" diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-one.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-zeropi.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-h3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-q8-common.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-parrot.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts rename to arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-feta40i.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-oka40i-c.dts rename to arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40.dtsi diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-elimo-initium.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-pinecube.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts rename to arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-t113s.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts rename to arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts diff --git a/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts diff --git a/arch/arm/boot/dts/sun8i-v3-sl631.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-v3-sl631.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-v3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3.dtsi diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi similarity index 99% rename from arch/arm/boot/dts/sun8i-v3s.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index b001251644f7..3b9a282c2746 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -191,7 +191,7 @@ <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>; reset-names = "lcd"; diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts rename to arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts similarity index 100% rename from arch/arm/boot/dts/sun9i-a80-cubieboard4.dts rename to arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts similarity index 100% rename from arch/arm/boot/dts/sun9i-a80-optimus.dts rename to arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi similarity index 100% rename from arch/arm/boot/dts/sun9i-a80.dtsi rename to arch/arm/boot/dts/allwinner/sun9i-a80.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi similarity index 100% rename from arch/arm/boot/dts/suniv-f1c100s.dtsi rename to arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-common-regulators.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-h3-h5.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-itead-core-common.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/alphascale/Makefile b/arch/arm/boot/dts/alphascale/Makefile new file mode 100644 index 000000000000..8d1314fc79d0 --- /dev/null +++ b/arch/arm/boot/dts/alphascale/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb diff --git a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts similarity index 100% rename from arch/arm/boot/dts/alphascale-asm9260-devkit.dts rename to arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi similarity index 100% rename from arch/arm/boot/dts/alphascale-asm9260.dtsi rename to arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi diff --git a/arch/arm/boot/dts/amazon/Makefile b/arch/arm/boot/dts/amazon/Makefile new file mode 100644 index 000000000000..58af5c4846ef --- /dev/null +++ b/arch/arm/boot/dts/amazon/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/amazon/alpine-db.dts similarity index 100% rename from arch/arm/boot/dts/alpine-db.dts rename to arch/arm/boot/dts/amazon/alpine-db.dts diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/amazon/alpine.dtsi similarity index 100% rename from arch/arm/boot/dts/alpine.dtsi rename to arch/arm/boot/dts/amazon/alpine.dtsi diff --git a/arch/arm/boot/dts/amlogic/Makefile b/arch/arm/boot/dts/amlogic/Makefile new file mode 100644 index 000000000000..a84310780ea3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_MESON6) += \ + meson6-atv1200.dtb +dtb-$(CONFIG_MACH_MESON8) += \ + meson8-minix-neo-x8.dtb \ + meson8b-ec100.dtb \ + meson8b-mxq.dtb \ + meson8b-odroidc1.dtb \ + meson8m2-mxiii-plus.dtb diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi similarity index 100% rename from arch/arm/boot/dts/meson.dtsi rename to arch/arm/boot/dts/amlogic/meson.dtsi diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/amlogic/meson6-atv1200.dts similarity index 100% rename from arch/arm/boot/dts/meson6-atv1200.dts rename to arch/arm/boot/dts/amlogic/meson6-atv1200.dts diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/amlogic/meson6.dtsi similarity index 100% rename from arch/arm/boot/dts/meson6.dtsi rename to arch/arm/boot/dts/amlogic/meson6.dtsi diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts similarity index 100% rename from arch/arm/boot/dts/meson8-minix-neo-x8.dts rename to arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi similarity index 99% rename from arch/arm/boot/dts/meson8.dtsi rename to arch/arm/boot/dts/amlogic/meson8.dtsi index 4f22ab451aae..59932fbfd5d5 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -769,13 +769,13 @@ &uart_B { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; &uart_C { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-ec100.dts rename to arch/arm/boot/dts/amlogic/meson8b-ec100.dts diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-mxq.dts rename to arch/arm/boot/dts/amlogic/meson8b-mxq.dts diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-odroidc1.dts rename to arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi similarity index 99% rename from arch/arm/boot/dts/meson8b.dtsi rename to arch/arm/boot/dts/amlogic/meson8b.dtsi index 5979209fe91e..5198f5177c2c 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -740,13 +740,13 @@ &uart_B { compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; &uart_C { compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts similarity index 100% rename from arch/arm/boot/dts/meson8m2-mxiii-plus.dts rename to arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi similarity index 100% rename from arch/arm/boot/dts/meson8m2.dtsi rename to arch/arm/boot/dts/amlogic/meson8m2.dtsi diff --git a/arch/arm/boot/dts/arm/Makefile b/arch/arm/boot/dts/arm/Makefile new file mode 100644 index 000000000000..07ebb64e2cd0 --- /dev/null +++ b/arch/arm/boot/dts/arm/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEGRATOR) += \ + integratorap.dtb \ + integratorap-im-pd1.dtb \ + integratorcp.dtb +dtb-$(CONFIG_ARCH_MPS2) += \ + mps2-an385.dtb \ + mps2-an399.dtb +dtb-$(CONFIG_ARCH_REALVIEW) += \ + arm-realview-pb1176.dtb \ + arm-realview-pb11mp.dtb \ + arm-realview-eb.dtb \ + arm-realview-eb-bbrevd.dtb \ + arm-realview-eb-11mp.dtb \ + arm-realview-eb-11mp-bbrevd.dtb \ + arm-realview-eb-11mp-ctrevb.dtb \ + arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ + arm-realview-eb-a9mp.dtb \ + arm-realview-eb-a9mp-bbrevd.dtb \ + arm-realview-pba8.dtb \ + arm-realview-pbx-a9.dtb +dtb-$(CONFIG_ARCH_VERSATILE) += \ + versatile-ab.dtb \ + versatile-ab-ib2.dtb \ + versatile-pb.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += \ + vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb \ + vexpress-v2p-ca15-tc1.dtb \ + vexpress-v2p-ca15_a7.dtb diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-a9mp.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-mp.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm/arm-realview-eb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb.dtsi diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pb1176.dts rename to arch/arm/boot/dts/arm/arm-realview-pb1176.dts diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pb11mp.dts rename to arch/arm/boot/dts/arm/arm-realview-pb11mp.dts diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm/arm-realview-pba8.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pba8.dts rename to arch/arm/boot/dts/arm/arm-realview-pba8.dts diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pbx-a9.dts rename to arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-pbx.dtsi rename to arch/arm/boot/dts/arm/arm-realview-pbx.dtsi diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/arm/integrator.dtsi similarity index 100% rename from arch/arm/boot/dts/integrator.dtsi rename to arch/arm/boot/dts/arm/integrator.dtsi diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts similarity index 100% rename from arch/arm/boot/dts/integratorap-im-pd1.dts rename to arch/arm/boot/dts/arm/integratorap-im-pd1.dts diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts similarity index 100% rename from arch/arm/boot/dts/integratorap.dts rename to arch/arm/boot/dts/arm/integratorap.dts diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/arm/integratorcp.dts similarity index 100% rename from arch/arm/boot/dts/integratorcp.dts rename to arch/arm/boot/dts/arm/integratorcp.dts diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/arm/mps2-an385.dts similarity index 100% rename from arch/arm/boot/dts/mps2-an385.dts rename to arch/arm/boot/dts/arm/mps2-an385.dts diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/arm/mps2-an399.dts similarity index 100% rename from arch/arm/boot/dts/mps2-an399.dts rename to arch/arm/boot/dts/arm/mps2-an399.dts diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi similarity index 99% rename from arch/arm/boot/dts/mps2.dtsi rename to arch/arm/boot/dts/arm/mps2.dtsi index b99577d411b1..ce308820765b 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -42,7 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" / { #address-cells = <1>; diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/arm/versatile-ab-ib2.dts similarity index 100% rename from arch/arm/boot/dts/versatile-ab-ib2.dts rename to arch/arm/boot/dts/arm/versatile-ab-ib2.dts diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts similarity index 100% rename from arch/arm/boot/dts/versatile-ab.dts rename to arch/arm/boot/dts/arm/versatile-ab.dts diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/arm/versatile-pb.dts similarity index 100% rename from arch/arm/boot/dts/versatile-pb.dts rename to arch/arm/boot/dts/arm/versatile-pb.dts diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi similarity index 100% rename from arch/arm/boot/dts/vexpress-v2m-rs1.dtsi rename to arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi similarity index 100% rename from arch/arm/boot/dts/vexpress-v2m.dtsi rename to arch/arm/boot/dts/arm/vexpress-v2m.dtsi diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca5s.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca9.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile new file mode 100644 index 000000000000..c68984322a86 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ + aspeed-ast2600-evb.dtb \ + aspeed-bmc-amd-daytonax.dtb \ + aspeed-bmc-amd-ethanolx.dtb \ + aspeed-bmc-ampere-mtjade.dtb \ + aspeed-bmc-ampere-mtmitchell.dtb \ + aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-romed8hm3.dtb \ + aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ + aspeed-bmc-facebook-cloudripper.dtb \ + aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-elbert.dtb \ + aspeed-bmc-facebook-fuji.dtb \ + aspeed-bmc-facebook-galaxy100.dtb \ + aspeed-bmc-facebook-greatlakes.dtb \ + aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-tiogapass.dtb \ + aspeed-bmc-facebook-wedge40.dtb \ + aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400.dtb \ + aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-facebook-yosemitev2.dtb \ + aspeed-bmc-ibm-bonnell.dtb \ + aspeed-bmc-ibm-everest.dtb \ + aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-1s4u.dtb \ + aspeed-bmc-ibm-rainier-4u.dtb \ + aspeed-bmc-intel-s2600wf.dtb \ + aspeed-bmc-inspur-fp5280g2.dtb \ + aspeed-bmc-inspur-nf5280m6.dtb \ + aspeed-bmc-inspur-on5263m5.dtb \ + aspeed-bmc-lenovo-hr630.dtb \ + aspeed-bmc-lenovo-hr855xg2.dtb \ + aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-opp-lanyang.dtb \ + aspeed-bmc-opp-mowgli.dtb \ + aspeed-bmc-opp-nicole.dtb \ + aspeed-bmc-opp-palmetto.dtb \ + aspeed-bmc-opp-romulus.dtb \ + aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-tacoma.dtb \ + aspeed-bmc-opp-vesnin.dtb \ + aspeed-bmc-opp-witherspoon.dtb \ + aspeed-bmc-opp-zaius.dtb \ + aspeed-bmc-portwell-neptune.dtb \ + aspeed-bmc-qcom-dc-scm-v1.dtb \ + aspeed-bmc-quanta-q71l.dtb \ + aspeed-bmc-quanta-s6q.dtb \ + aspeed-bmc-supermicro-x11spi.dtb \ + aspeed-bmc-inventec-transformers.dtb \ + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ + aspeed-bmc-ufispace-ncplite.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2500-evb.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2600-evb.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-swift.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g4.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g4.dtsi diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g5.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g5.dtsi diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g6.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g6.dtsi diff --git a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi similarity index 100% rename from arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi rename to arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi similarity index 100% rename from arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi rename to arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi similarity index 100% rename from arch/arm/boot/dts/ibm-power9-dual.dtsi rename to arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-128.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-64.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi diff --git a/arch/arm/boot/dts/axis/Makefile b/arch/arm/boot/dts/axis/Makefile new file mode 100644 index 000000000000..2cab41451281 --- /dev/null +++ b/arch/arm/boot/dts/axis/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/axis/artpec6-devboard.dts similarity index 100% rename from arch/arm/boot/dts/artpec6-devboard.dts rename to arch/arm/boot/dts/axis/artpec6-devboard.dts diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi similarity index 100% rename from arch/arm/boot/dts/artpec6.dtsi rename to arch/arm/boot/dts/axis/artpec6.dtsi diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts deleted file mode 100644 index cd03fa0c2aae..000000000000 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2014 Broadcom Corporation - -/dts-v1/; - -#include - -#include "bcm21664.dtsi" - -/ { - model = "BCM21664 Garnet board"; - compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - serial@3e000000 { - status = "okay"; - }; - - sdio1: sdio@3f180000 { - max-frequency = <48000000>; - status = "okay"; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - usbotg: usb@3f120000 { - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile new file mode 100644 index 000000000000..95b0ef2a4215 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays +DTC_FLAGS_bcm2835-rpi-b := -@ +DTC_FLAGS_bcm2835-rpi-a := -@ +DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ +DTC_FLAGS_bcm2835-rpi-b-plus := -@ +DTC_FLAGS_bcm2835-rpi-a-plus := -@ +DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ +DTC_FLAGS_bcm2836-rpi-2-b := -@ +DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ +DTC_FLAGS_bcm2837-rpi-3-b := -@ +DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ +DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ +DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ +DTC_FLAGS_bcm2711-rpi-400 := -@ +DTC_FLAGS_bcm2711-rpi-4-b := -@ +DTC_FLAGS_bcm2711-rpi-cm4-io := -@ +DTC_FLAGS_bcm2835-rpi-zero := -@ +DTC_FLAGS_bcm2835-rpi-zero-w := -@ +dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-a.dtb \ + bcm2835-rpi-b-rev2.dtb \ + bcm2835-rpi-b-plus.dtb \ + bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-cm1-io1.dtb \ + bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb \ + bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-cm4-io.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb \ + bcm963138.dtb \ + bcm963138dvt.dtb \ + bcm963148.dtb \ + bcm963178.dtb \ + bcm96756.dtb \ + bcm96846.dtb \ + bcm96855.dtb \ + bcm96878.dtb +dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ + bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-linksys-ea6500-v2.dtb \ + bcm4708-luxul-xap-1510.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ + bcm4708-smartrg-sr400ac.dtb \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm47081-luxul-xap-1410.dtb \ + bcm47081-luxul-xwr-1200.dtb \ + bcm47081-tplink-archer-c5-v2.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-linksys-ea9200.dtb \ + bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ + bcm47094-asus-rt-ac88u.dtb \ + bcm47094-dlink-dir-885l.dtb \ + bcm47094-dlink-dir-890l.dtb \ + bcm47094-linksys-panamera.dtb \ + bcm47094-luxul-abr-4500.dtb \ + bcm47094-luxul-xap-1610.dtb \ + bcm47094-luxul-xbr-4500.dtb \ + bcm47094-luxul-xwc-2000.dtb \ + bcm47094-luxul-xwr-3100.dtb \ + bcm47094-luxul-xwr-3150-v1.dtb \ + bcm47094-netgear-r8500.dtb \ + bcm47094-phicomm-k3.dtb \ + bcm53015-meraki-mr26.dtb \ + bcm53016-dlink-dwl-8610ap.dtb \ + bcm53016-meraki-mr32.dtb \ + bcm94708.dtb \ + bcm94709.dtb \ + bcm953012er.dtb \ + bcm953012hr.dtb \ + bcm953012k.dtb +dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-luxul-xap-1440.dtb \ + bcm47189-luxul-xap-810.dtb \ + bcm47189-tenda-ac9.dtb \ + bcm947189acdbmr.dtb +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ + bcm911360_entphn.dtb \ + bcm911360k.dtb \ + bcm958300k.dtb \ + bcm958305k.dtb +dtb-$(CONFIG_ARCH_BCM_HR2) += \ + bcm53340-ubnt-unifi-switch8.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ + bcm28155-ap.dtb \ + bcm21664-garnet.dtb \ + bcm23550-sparrow.dtb +dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958522er.dtb \ + bcm958525er.dtb \ + bcm958525xmc.dtb \ + bcm958622hr.dtb \ + bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ + bcm958625hr.dtb \ + bcm988312hr.dtb \ + bcm958625k.dtb +dtb-$(CONFIG_ARCH_BRCMSTB) += \ + bcm7445-bcm97445svmb.dtb diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-cygnus-clock.dtsi rename to arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-cygnus.dtsi rename to arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-hr2.dtsi rename to arch/arm/boot/dts/broadcom/bcm-hr2.dtsi diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi similarity index 71% rename from arch/arm/boot/dts/bcm5301x.dtsi rename to arch/arm/boot/dts/broadcom/bcm-ns.dtsi index 5fc1b847f4aa..dae9c47ace76 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Broadcom BCM470X / BCM5301X ARM platform code. - * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, - * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs - * * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. */ #include @@ -15,9 +10,9 @@ #include / { + interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&gic>; chipcommon-a-bus@18000000 { compatible = "simple-bus"; @@ -50,13 +45,6 @@ #address-cells = <1>; #size-cells = <1>; - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - scu@20000 { compatible = "arm,cortex-a9-scu"; reg = <0x20000 0x100>; @@ -77,14 +65,6 @@ clocks = <&periph_clk>; }; - watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - gic: interrupt-controller@21000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -105,49 +85,6 @@ }; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -157,7 +94,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = + interrupt-map = /* ChipCommon */ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, @@ -239,14 +176,23 @@ pcie0: pcie@12000 { reg = <0x00012000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie1: pcie@13000 { reg = <0x00013000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie2: pcie@14000 { reg = <0x00014000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@21000 { @@ -259,8 +205,6 @@ interrupt-parent = <&gic>; ehci: usb@21000 { - #usb-cells = <0>; - compatible = "generic-ehci"; reg = <0x00021000 0x1000>; interrupts = ; @@ -281,8 +225,6 @@ }; ohci: usb@22000 { - #usb-cells = <0>; - compatible = "generic-ohci"; reg = <0x00022000 0x1000>; interrupts = ; @@ -312,8 +254,6 @@ interrupt-parent = <&gic>; xhci: usb@23000 { - #usb-cells = <0>; - compatible = "generic-xhci"; reg = <0x00023000 0x1000>; interrupts = ; @@ -362,33 +302,63 @@ #address-cells = <1>; }; - mdio-mux@18003000 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x18003000 0x4>; - mux-mask = <0x200>; + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; - mdio@0 { - reg = <0x0>; + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + ports { #address-cells = <1>; #size-cells = <0>; - usb3_phy: usb3-phy@10 { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - status = "disabled"; + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + ethernet = <&gmac0>; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; }; }; - usb3_dmp: syscon@18105000 { - reg = <0x18105000 0x1000>; - }; - uart2: serial@18008000 { compatible = "ns16550a"; reg = <0x18008000 0x20>; @@ -398,16 +368,6 @@ status = "disabled"; }; - i2c0: i2c@18009000 { - compatible = "brcm,iproc-i2c"; - reg = <0x18009000 0x50>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - status = "disabled"; - }; - dmu-bus@1800c000 { compatible = "simple-bus"; ranges = <0 0x1800c000 0x1000>; @@ -421,26 +381,6 @@ #address-cells = <1>; #size-cells = <1>; - lcpll0: clock-controller@100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", - "sdio", "ddr_phy"; - }; - - genpll: clock-controller@140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", - "ethernetclk", - "usbclk", "iprocfast", - "sata1", "sata2"; - }; - usb2_phy: phy@164 { compatible = "brcm,ns-usb2-phy"; reg = <0x164 0x4>; @@ -490,24 +430,6 @@ }; }; - srab: ethernet-switch@18007000 { - compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - - status = "disabled"; - - /* ports are defined in board DTS */ - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - rng: rng@18004000 { - compatible = "brcm,bcm5301x-rng"; - reg = <0x18004000 0x14>; - }; - nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; @@ -520,45 +442,6 @@ brcm,nand-has-wp; }; - spi@18029200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x18029200 0x184>, - <0x18029000 0x124>, - <0x1811b408 0x004>, - <0x180293a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overread"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - - spi_nor: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - status = "disabled"; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; - }; - }; - thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-nsp-ax.dtsi rename to arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-nsp.dtsi rename to arch/arm/boot/dts/broadcom/bcm-nsp.dtsi diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/broadcom/bcm11351.dtsi similarity index 96% rename from arch/arm/boot/dts/bcm11351.dtsi rename to arch/arm/boot/dts/broadcom/bcm11351.dtsi index ba75784d66a9..b271a9bf06a9 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm11351.dtsi @@ -1,11 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2012-2013 Broadcom Corporation +#include #include #include -#include "dt-bindings/clock/bcm281xx.h" - / { #address-cells = <1>; #size-cells = <1>; @@ -50,44 +49,44 @@ reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; - serial@3e000000 { + uartb: serial@3e000000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e000000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; - serial@3e001000 { + uartb2: serial@3e001000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e001000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; - serial@3e002000 { + uartb3: serial@3e002000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e002000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; - serial@3e003000 { + uartb4: serial@3e003000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e003000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; L2: l2-cache@3ff20000 { @@ -125,7 +124,7 @@ interrupt-controller; }; - sdio1: sdio@3f180000 { + sdio1: mmc@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; interrupts = ; @@ -133,7 +132,7 @@ status = "disabled"; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; interrupts = ; @@ -141,7 +140,7 @@ status = "disabled"; }; - sdio3: sdio@3f1a0000 { + sdio3: mmc@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; interrupts = ; @@ -149,7 +148,7 @@ status = "disabled"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; interrupts = ; @@ -162,7 +161,7 @@ reg = <0x35004800 0x430>; }; - i2c@3e016000 { + bsc1: i2c@3e016000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e016000 0x80>; interrupts = ; @@ -172,7 +171,7 @@ status = "disabled"; }; - i2c@3e017000 { + bsc2: i2c@3e017000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e017000 0x80>; interrupts = ; @@ -182,7 +181,7 @@ status = "disabled"; }; - i2c@3e018000 { + bsc3: i2c@3e018000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e018000 0x80>; interrupts = ; @@ -192,7 +191,7 @@ status = "disabled"; }; - i2c@3500d000 { + pmu_bsc: i2c@3500d000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3500d000 0x80>; interrupts = ; diff --git a/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts b/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts new file mode 100644 index 000000000000..8789fae178bf --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Broadcom Corporation + +/dts-v1/; + +#include + +#include "bcm21664.dtsi" + +/ { + model = "BCM21664 Garnet board"; + compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; + +&sdio1 { + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio2 { + non-removable; + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uartb { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/broadcom/bcm21664.dtsi similarity index 94% rename from arch/arm/boot/dts/bcm21664.dtsi rename to arch/arm/boot/dts/broadcom/bcm21664.dtsi index ed4de031e48e..2eb7f5b0c1dc 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm21664.dtsi @@ -1,11 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014 Broadcom Corporation +#include #include #include -#include "dt-bindings/clock/bcm21664.h" - / { #address-cells = <1>; #size-cells = <1>; @@ -50,34 +49,34 @@ reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ }; - serial@3e000000 { + uartb: serial@3e000000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e000000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; - serial@3e001000 { + uartb2: serial@3e001000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e001000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; - serial@3e002000 { + uartb3: serial@3e002000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e002000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; L2: cache-controller@3ff20000 { @@ -113,7 +112,7 @@ interrupt-controller; }; - sdio1: sdio@3f180000 { + sdio1: mmc@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x801c>; interrupts = ; @@ -121,7 +120,7 @@ status = "disabled"; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x801c>; interrupts = ; @@ -129,7 +128,7 @@ status = "disabled"; }; - sdio3: sdio@3f1a0000 { + sdio3: mmc@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x801c>; interrupts = ; @@ -137,7 +136,7 @@ status = "disabled"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x801c>; interrupts = ; @@ -145,7 +144,7 @@ status = "disabled"; }; - i2c@3e016000 { + bsc1: i2c@3e016000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e016000 0x70>; interrupts = ; @@ -155,7 +154,7 @@ status = "disabled"; }; - i2c@3e017000 { + bsc2: i2c@3e017000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e017000 0x70>; interrupts = ; @@ -165,7 +164,7 @@ status = "disabled"; }; - i2c@3e018000 { + bsc3: i2c@3e018000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e018000 0x70>; interrupts = ; @@ -175,7 +174,7 @@ status = "disabled"; }; - i2c@3e01c000 { + bsc4: i2c@3e01c000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e01c000 0x70>; interrupts = ; @@ -286,21 +285,21 @@ }; root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; + compatible = "brcm,bcm21664-root-ccu"; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; + compatible = "brcm,bcm21664-aon-ccu"; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; + compatible = "brcm,bcm21664-master-ccu"; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; clock-output-names = "sdio1", @@ -314,7 +313,7 @@ }; slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + compatible = "brcm,bcm21664-slave-ccu"; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; clock-output-names = "uartb", diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts similarity index 100% rename from arch/arm/boot/dts/bcm23550-sparrow.dts rename to arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/broadcom/bcm23550.dtsi similarity index 95% rename from arch/arm/boot/dts/bcm23550.dtsi rename to arch/arm/boot/dts/broadcom/bcm23550.dtsi index a36c9b1d23c8..445eadb8d871 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm23550.dtsi @@ -30,12 +30,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* BCM23550 and BCM21664 have almost identical clocks */ +#include #include #include -/* BCM23550 and BCM21664 have almost identical clocks */ -#include "dt-bindings/clock/bcm21664.h" - / { #address-cells = <1>; #size-cells = <1>; @@ -130,36 +129,36 @@ uartb: serial@0 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00000000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uartb2: serial@1000 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00001000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uartb3: serial@2000 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00002000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; bsc1: i2c@16000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00016000 0x70>; interrupts = ; #address-cells = <1>; @@ -169,7 +168,7 @@ }; bsc2: i2c@17000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00017000 0x70>; interrupts = ; #address-cells = <1>; @@ -179,7 +178,7 @@ }; bsc3: i2c@18000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00018000 0x70>; interrupts = ; #address-cells = <1>; @@ -189,7 +188,7 @@ }; bsc4: i2c@1c000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x0001c000 0x70>; interrupts = ; #address-cells = <1>; @@ -224,7 +223,7 @@ status = "disabled"; }; - sdio1: sdio@e80000 { + sdio1: mmc@e80000 { compatible = "brcm,kona-sdhci"; reg = <0x00e80000 0x801c>; interrupts = ; @@ -232,7 +231,7 @@ status = "disabled"; }; - sdio2: sdio@e90000 { + sdio2: mmc@e90000 { compatible = "brcm,kona-sdhci"; reg = <0x00e90000 0x801c>; interrupts = ; @@ -240,7 +239,7 @@ status = "disabled"; }; - sdio3: sdio@ea0000 { + sdio3: mmc@ea0000 { compatible = "brcm,kona-sdhci"; reg = <0x00ea0000 0x801c>; interrupts = ; @@ -248,7 +247,7 @@ status = "disabled"; }; - sdio4: sdio@eb0000 { + sdio4: mmc@eb0000 { compatible = "brcm,kona-sdhci"; reg = <0x00eb0000 0x801c>; interrupts = ; @@ -372,21 +371,21 @@ }; root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; + compatible = "brcm,bcm21664-root-ccu"; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; + compatible = "brcm,bcm21664-aon-ccu"; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + compatible = "brcm,bcm21664-slave-ccu"; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; clock-output-names = "uartb", @@ -399,7 +398,7 @@ }; master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; + compatible = "brcm,bcm21664-master-ccu"; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; clock-output-names = "sdio1", diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-4-b.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-400.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711.dtsi diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts similarity index 97% rename from arch/arm/boot/dts/bcm28155-ap.dts rename to arch/arm/boot/dts/broadcom/bcm28155-ap.dts index 60c8ab8a2855..0a8ad1d673d8 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts @@ -21,30 +21,30 @@ }; i2c@3e016000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3e017000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3e018000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3500d000 { - status = "okay"; clock-frequency = <100000>; + status = "okay"; pmu: pmu@8 { reg = <0x08>; }; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { non-removable; max-frequency = <48000000>; vmmc-supply = <&camldo1_reg>; @@ -52,7 +52,7 @@ status = "okay"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { max-frequency = <48000000>; cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; vmmc-supply = <&sdldo_reg>; diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-common.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-a-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-a.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-zero-w.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-zero.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/broadcom/bcm2835.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835.dtsi diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2836-rpi-2-b.dts rename to arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2836-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/broadcom/bcm2836.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2836.dtsi rename to arch/arm/boot/dts/broadcom/bcm2836.dtsi diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-b.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/broadcom/bcm2837.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2837.dtsi rename to arch/arm/boot/dts/broadcom/bcm2837.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x.dtsi diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts rename to arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts rename to arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi similarity index 95% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi index e583b9cbf07c..42bcbf10957c 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -16,8 +16,8 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; @@ -159,34 +159,27 @@ ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts similarity index 97% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts index 43c698a0a7c3..95ef6ca7210b 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts @@ -28,8 +28,8 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts rename to arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts similarity index 81% rename from arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts rename to arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts index 6de7fe204b0c..e04d2e5ea51a 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts @@ -8,7 +8,7 @@ #include "bcm4708.dtsi" / { - compatible = "luxul,xap-1510v1", "brcm,bcm4708"; + compatible = "luxul,xap-1510-v1", "brcm,bcm4708"; model = "Luxul XAP-1510 V1"; chosen { @@ -20,6 +20,14 @@ reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -53,6 +61,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -62,19 +75,15 @@ ports { port@0 { - reg = <0>; label = "poe"; }; port@4 { - reg = <4>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts similarity index 86% rename from arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts rename to arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts index f5b75ba93512..a399800139d9 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts @@ -24,6 +24,14 @@ reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + nand_controller: nand-controller@18028000 { nand@0 { partitions { @@ -60,6 +68,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -69,14 +82,11 @@ ports { port@4 { - reg = <4>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts similarity index 92% rename from arch/arm/boot/dts/bcm4708-netgear-r6250.dts rename to arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts index 89155caf50be..fad3473810a2 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts @@ -13,7 +13,7 @@ #include "bcm5301x-nand-cs0-bch8.dtsi" / { - compatible = "netgear,r6250v1", "brcm,bcm4708"; + compatible = "netgear,r6250-v1", "brcm,bcm4708"; model = "Netgear R6250 V1 (BCM4708)"; chosen { @@ -100,34 +100,27 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts similarity index 96% rename from arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts index 57d00a0b4765..77396730bdd3 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts @@ -12,7 +12,7 @@ #include "bcm5301x-nand-cs0-bch8.dtsi" / { - compatible = "netgear,r6300v2", "brcm,bcm4708"; + compatible = "netgear,r6300-v2", "brcm,bcm4708"; model = "Netgear R6300 V2 (BCM4708)"; chosen { diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts similarity index 96% rename from arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts rename to arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts index 26cdeb5cc337..5b2b7b8b3b12 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts @@ -123,34 +123,27 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/broadcom/bcm4708.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm4708.dtsi rename to arch/arm/boot/dts/broadcom/bcm4708.dtsi diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts rename to arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts similarity index 93% rename from arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts rename to arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts index 407319cb5c0d..d0a26b643b82 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts @@ -28,8 +28,8 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; @@ -123,34 +123,27 @@ ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts similarity index 96% rename from arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts rename to arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts index f8622ecce6a2..7655e4ff2d1c 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts @@ -28,8 +28,8 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts similarity index 80% rename from arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts rename to arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts index 76c9b30b868d..9f21d6d6d35b 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts @@ -8,7 +8,7 @@ #include "bcm47081.dtsi" / { - compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708"; + compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708"; model = "Luxul XAP-1410 V1"; chosen { @@ -20,6 +20,14 @@ reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -53,6 +61,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -62,14 +75,11 @@ ports { port@4 { - reg = <4>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts similarity index 89% rename from arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts rename to arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts index 6ef0c0788e62..256107291702 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts @@ -9,7 +9,7 @@ #include "bcm5301x-nand-cs0-bch4.dtsi" / { - compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708"; + compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708"; model = "Luxul XWR-1200 V1"; chosen { @@ -24,6 +24,10 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -106,6 +110,11 @@ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -115,34 +124,29 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts rename to arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/broadcom/bcm47081.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm47081.dtsi rename to arch/arm/boot/dts/broadcom/bcm47081.dtsi diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts rename to arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-linksys-ea9200.dts rename to arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-netgear-r7000.dts rename to arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts similarity index 89% rename from arch/arm/boot/dts/bcm4709-netgear-r8000.dts rename to arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts index 14303ab521ea..707c561703ed 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts @@ -137,8 +137,10 @@ #size-cells = <2>; wifi@0,1,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5735000 5835000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; }; @@ -159,6 +161,19 @@ #address-cells = <3>; #size-cells = <2>; + bridge@1,0 { + reg = <0x800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + bridge@1,2,2 { reg = <0x1000 0 0 0 0>; @@ -166,8 +181,10 @@ #size-cells = <2>; wifi@1,4,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5170000 5730000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; }; @@ -191,39 +208,27 @@ ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts rename to arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/broadcom/bcm4709.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm4709.dtsi rename to arch/arm/boot/dts/broadcom/bcm4709.dtsi diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts similarity index 95% rename from arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts rename to arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts index a50ff686b557..4d5747aa5dc8 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts @@ -181,32 +181,28 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; sw0_p5: port@5 { - reg = <5>; + /delete-property/ethernet; + label = "extsw"; phy-mode = "rgmii"; @@ -218,8 +214,6 @@ }; port@7 { - reg = <7>; - ethernet = <&gmac1>; label = "cpu"; fixed-link { @@ -229,14 +223,7 @@ }; port@8 { - reg = <8>; - ethernet = <&gmac2>; label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts similarity index 93% rename from arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts rename to arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts index 555fbe41dd8f..51ce510b3e3a 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts @@ -124,39 +124,27 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts similarity index 96% rename from arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts rename to arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts index d945a20b06e0..60744f82c2b7 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts @@ -172,40 +172,28 @@ ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts similarity index 95% rename from arch/arm/boot/dts/bcm47094-linksys-panamera.dts rename to arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts index d9a16a820e7f..8036c04d81cb 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts @@ -207,29 +207,32 @@ dsa,member = <0 0>; ports { + sw0_p0: port@0 { + label = "extsw"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@1 { - reg = <1>; label = "lan7"; }; port@2 { - reg = <2>; label = "lan4"; }; port@3 { - reg = <3>; label = "lan8"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; - ethernet = <&gmac0>; label = "cpu"; status = "disabled"; @@ -240,8 +243,6 @@ }; port@7 { - reg = <7>; - ethernet = <&gmac1>; label = "cpu"; status = "disabled"; @@ -252,24 +253,7 @@ }; port@8 { - reg = <8>; - ethernet = <&gmac2>; label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sw0_p0: port@0 { - reg = <0>; - label = "extsw"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts similarity index 87% rename from arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts index 41a0722fa64a..e8991d4e248c 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts @@ -25,6 +25,10 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -61,6 +65,11 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -74,34 +83,29 @@ ports { port@0 { - reg = <0>; label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@1 { - reg = <1>; label = "lan4"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan2"; }; port@4 { - reg = <4>; label = "lan1"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts similarity index 84% rename from arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts index c56c7e366848..6875625869d9 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts @@ -20,6 +20,14 @@ reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -51,6 +59,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -60,19 +73,15 @@ ports { port@0 { - reg = <0>; label = "poe"; }; port@1 { - reg = <1>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts similarity index 87% rename from arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts index 1b5c91a524ac..7cfa4607ef31 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts @@ -25,6 +25,10 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -61,6 +65,11 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -74,34 +83,29 @@ ports { port@0 { - reg = <0>; label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@1 { - reg = <1>; label = "lan4"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan2"; }; port@4 { - reg = <4>; label = "lan1"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts similarity index 83% rename from arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts index 739063b77b1f..d55e10095eae 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts @@ -22,6 +22,14 @@ <0x88000000 0x18000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -47,6 +55,11 @@ status = "okay"; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -56,14 +69,11 @@ ports { port@0 { - reg = <0>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts similarity index 88% rename from arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts index 7afc68d5d2c2..ccf031c0e276 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts @@ -9,7 +9,7 @@ #include "bcm5301x-nand-cs0-bch4.dtsi" / { - compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; + compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708"; model = "Luxul XWR-3100 V1"; chosen { @@ -25,6 +25,10 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -101,6 +105,11 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -114,34 +123,29 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts similarity index 93% rename from arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts index 60a2c441d5bd..789dd2a3d226 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts @@ -27,6 +27,7 @@ reg = <0x1eff0000 0x10000>; et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; }; }; @@ -76,7 +77,7 @@ }; &gmac0 { - nvmem-cells = <&et0macaddr>; + nvmem-cells = <&et0macaddr 0>; nvmem-cell-names = "mac-address"; }; @@ -97,34 +98,29 @@ ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-netgear-r8500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-phicomm-k3.dts rename to arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/broadcom/bcm47094.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm47094.dtsi rename to arch/arm/boot/dts/broadcom/bcm47094.dtsi diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts rename to arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-luxul-xap-810.dts rename to arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-tenda-ac9.dts rename to arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/broadcom/bcm47622.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm47622.dtsi rename to arch/arm/boot/dts/broadcom/bcm47622.dtsi index cd25ed2757b7..7cd38de118c3 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47622.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts similarity index 94% rename from arch/arm/boot/dts/bcm53015-meraki-mr26.dts rename to arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts index 14f58033efeb..03ad614e6b72 100644 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts @@ -39,8 +39,6 @@ keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; key-restart { label = "Reset"; @@ -74,8 +72,6 @@ }; &nandcs { - nand-ecc-algo = "hw"; - partitions { compatible = "fixed-partitions"; #address-cells = <0x1>; @@ -117,18 +113,15 @@ ports { port@0 { - reg = <0>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; fixed-link { speed = <1000>; - duplex-full; + full-duplex; }; }; }; diff --git a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts similarity index 100% rename from arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts rename to arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts similarity index 94% rename from arch/arm/boot/dts/bcm53016-meraki-mr32.dts rename to arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts index 46c2c93b01d8..26c12bfb0bdd 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts @@ -125,8 +125,6 @@ }; &nandcs { - nand-ecc-algo = "hw"; - partitions { /* * The partition autodetection does not work for this device. @@ -140,31 +138,31 @@ #address-cells = <0x1>; #size-cells = <0x1>; - partition0@0 { + partition@0 { label = "u-boot"; reg = <0x0 0x100000>; read-only; }; - partition1@100000 { + partition@100000 { label = "bootkernel1"; reg = <0x100000 0x300000>; read-only; }; - partition2@400000 { + partition@400000 { label = "nvram"; reg = <0x400000 0x100000>; read-only; }; - partition3@500000 { + partition@500000 { label = "bootkernel2"; reg = <0x500000 0x300000>; read-only; }; - partition4@800000 { + partition@800000 { label = "ubi"; reg = <0x800000 0x7780000>; }; @@ -176,18 +174,15 @@ ports { port@0 { - reg = <0>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; fixed-link { speed = <1000>; - duplex-full; + full-duplex; }; }; }; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi diff --git a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi new file mode 100644 index 000000000000..600a1b54f2ae --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi @@ -0,0 +1,170 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "bcm-ns.dtsi" + +/ { + mpcore-bus@19000000 { + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + cru-bus@100 { + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + }; + }; + + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, + <0x18029000 0x124>, + <0x1811b408 0x004>, + <0x180293a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "disabled"; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts similarity index 100% rename from arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts rename to arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/broadcom/bcm53573.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm53573.dtsi rename to arch/arm/boot/dts/broadcom/bcm53573.dtsi diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/broadcom/bcm59056.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm59056.dtsi rename to arch/arm/boot/dts/broadcom/bcm59056.dtsi diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm63138.dtsi rename to arch/arm/boot/dts/broadcom/bcm63138.dtsi diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm63148.dtsi rename to arch/arm/boot/dts/broadcom/bcm63148.dtsi index ba7f265db121..24431de1810e 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/broadcom/bcm63178.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm63178.dtsi rename to arch/arm/boot/dts/broadcom/bcm63178.dtsi index d8268a1e889b..3f9aed96babf 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm63178.dtsi @@ -44,6 +44,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/broadcom/bcm6756.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm6756.dtsi rename to arch/arm/boot/dts/broadcom/bcm6756.dtsi index 49ecc1f0c18c..1d8d957d65dd 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6756.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm6846.dtsi rename to arch/arm/boot/dts/broadcom/bcm6846.dtsi index fbc7d3a5dc5f..cf92cf8c4693 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm6855.dtsi rename to arch/arm/boot/dts/broadcom/bcm6855.dtsi index 5e0fe26530f1..52d6bc89f9f8 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi @@ -44,6 +44,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi similarity index 99% rename from arch/arm/boot/dts/bcm6878.dtsi rename to arch/arm/boot/dts/broadcom/bcm6878.dtsi index 96529d3d4dc2..2c5d706bac7e 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts similarity index 100% rename from arch/arm/boot/dts/bcm7445-bcm97445svmb.dts rename to arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/broadcom/bcm7445.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm7445.dtsi rename to arch/arm/boot/dts/broadcom/bcm7445.dtsi diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/broadcom/bcm911360_entphn.dts similarity index 100% rename from arch/arm/boot/dts/bcm911360_entphn.dts rename to arch/arm/boot/dts/broadcom/bcm911360_entphn.dts diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/broadcom/bcm911360k.dts similarity index 100% rename from arch/arm/boot/dts/bcm911360k.dts rename to arch/arm/boot/dts/broadcom/bcm911360k.dts diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/broadcom/bcm94708.dts similarity index 100% rename from arch/arm/boot/dts/bcm94708.dts rename to arch/arm/boot/dts/broadcom/bcm94708.dts diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/broadcom/bcm94709.dts similarity index 100% rename from arch/arm/boot/dts/bcm94709.dts rename to arch/arm/boot/dts/broadcom/bcm94709.dts diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts similarity index 100% rename from arch/arm/boot/dts/bcm947189acdbmr.dts rename to arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/broadcom/bcm947622.dts similarity index 100% rename from arch/arm/boot/dts/bcm947622.dts rename to arch/arm/boot/dts/broadcom/bcm947622.dts diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/broadcom/bcm953012er.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012er.dts rename to arch/arm/boot/dts/broadcom/bcm953012er.dts diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/broadcom/bcm953012hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012hr.dts rename to arch/arm/boot/dts/broadcom/bcm953012hr.dts diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/broadcom/bcm953012k.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012k.dts rename to arch/arm/boot/dts/broadcom/bcm953012k.dts diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/broadcom/bcm958300k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958300k.dts rename to arch/arm/boot/dts/broadcom/bcm958300k.dts diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/broadcom/bcm958305k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958305k.dts rename to arch/arm/boot/dts/broadcom/bcm958305k.dts diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/broadcom/bcm958522er.dts similarity index 100% rename from arch/arm/boot/dts/bcm958522er.dts rename to arch/arm/boot/dts/broadcom/bcm958522er.dts diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/broadcom/bcm958525er.dts similarity index 100% rename from arch/arm/boot/dts/bcm958525er.dts rename to arch/arm/boot/dts/broadcom/bcm958525er.dts diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts similarity index 100% rename from arch/arm/boot/dts/bcm958525xmc.dts rename to arch/arm/boot/dts/broadcom/bcm958525xmc.dts diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/broadcom/bcm958622hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958622hr.dts rename to arch/arm/boot/dts/broadcom/bcm958622hr.dts diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/broadcom/bcm958623hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958623hr.dts rename to arch/arm/boot/dts/broadcom/bcm958623hr.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64w.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx65.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx65w.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/broadcom/bcm958625hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625hr.dts rename to arch/arm/boot/dts/broadcom/bcm958625hr.dts diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/broadcom/bcm958625k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625k.dts rename to arch/arm/boot/dts/broadcom/bcm958625k.dts diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/broadcom/bcm963138.dts similarity index 100% rename from arch/arm/boot/dts/bcm963138.dts rename to arch/arm/boot/dts/broadcom/bcm963138.dts diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/broadcom/bcm963138dvt.dts similarity index 100% rename from arch/arm/boot/dts/bcm963138dvt.dts rename to arch/arm/boot/dts/broadcom/bcm963138dvt.dts diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/broadcom/bcm963148.dts similarity index 100% rename from arch/arm/boot/dts/bcm963148.dts rename to arch/arm/boot/dts/broadcom/bcm963148.dts diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/broadcom/bcm963178.dts similarity index 100% rename from arch/arm/boot/dts/bcm963178.dts rename to arch/arm/boot/dts/broadcom/bcm963178.dts diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/broadcom/bcm96756.dts similarity index 100% rename from arch/arm/boot/dts/bcm96756.dts rename to arch/arm/boot/dts/broadcom/bcm96756.dts diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/broadcom/bcm96846.dts similarity index 100% rename from arch/arm/boot/dts/bcm96846.dts rename to arch/arm/boot/dts/broadcom/bcm96846.dts diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/broadcom/bcm96855.dts similarity index 100% rename from arch/arm/boot/dts/bcm96855.dts rename to arch/arm/boot/dts/broadcom/bcm96855.dts diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/broadcom/bcm96878.dts similarity index 100% rename from arch/arm/boot/dts/bcm96878.dts rename to arch/arm/boot/dts/broadcom/bcm96878.dts diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/broadcom/bcm988312hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm988312hr.dts rename to arch/arm/boot/dts/broadcom/bcm988312hr.dts diff --git a/arch/arm/boot/dts/bcm9hmidc.dtsi b/arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm9hmidc.dtsi rename to arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi diff --git a/arch/arm/boot/dts/calxeda/Makefile b/arch/arm/boot/dts/calxeda/Makefile new file mode 100644 index 000000000000..f5126b6d26ad --- /dev/null +++ b/arch/arm/boot/dts/calxeda/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/calxeda/ecx-2000.dts similarity index 100% rename from arch/arm/boot/dts/ecx-2000.dts rename to arch/arm/boot/dts/calxeda/ecx-2000.dts diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/calxeda/ecx-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ecx-common.dtsi rename to arch/arm/boot/dts/calxeda/ecx-common.dtsi diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/calxeda/highbank.dts similarity index 100% rename from arch/arm/boot/dts/highbank.dts rename to arch/arm/boot/dts/calxeda/highbank.dts diff --git a/arch/arm/boot/dts/cirrus/Makefile b/arch/arm/boot/dts/cirrus/Makefile new file mode 100644 index 000000000000..e944d3e2129d --- /dev/null +++ b/arch/arm/boot/dts/cirrus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/cirrus/ep7209.dtsi similarity index 100% rename from arch/arm/boot/dts/ep7209.dtsi rename to arch/arm/boot/dts/cirrus/ep7209.dtsi diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts similarity index 100% rename from arch/arm/boot/dts/ep7211-edb7211.dts rename to arch/arm/boot/dts/cirrus/ep7211-edb7211.dts diff --git a/arch/arm/boot/dts/ep7211.dtsi b/arch/arm/boot/dts/cirrus/ep7211.dtsi similarity index 100% rename from arch/arm/boot/dts/ep7211.dtsi rename to arch/arm/boot/dts/cirrus/ep7211.dtsi diff --git a/arch/arm/boot/dts/cnxt/Makefile b/arch/arm/boot/dts/cnxt/Makefile new file mode 100644 index 000000000000..d49df53f65a1 --- /dev/null +++ b/arch/arm/boot/dts/cnxt/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cnxt/cx92755.dtsi similarity index 100% rename from arch/arm/boot/dts/cx92755.dtsi rename to arch/arm/boot/dts/cnxt/cx92755.dtsi diff --git a/arch/arm/boot/dts/cx92755_equinox.dts b/arch/arm/boot/dts/cnxt/cx92755_equinox.dts similarity index 100% rename from arch/arm/boot/dts/cx92755_equinox.dts rename to arch/arm/boot/dts/cnxt/cx92755_equinox.dts diff --git a/arch/arm/boot/dts/gemini/Makefile b/arch/arm/boot/dts/gemini/Makefile new file mode 100644 index 000000000000..f9f63ce3eb49 --- /dev/null +++ b/arch/arm/boot/dts/gemini/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_GEMINI) += \ + gemini-dlink-dir-685.dtb \ + gemini-dlink-dns-313.dtb \ + gemini-nas4220b.dtb \ + gemini-ns2502.dtb \ + gemini-rut1xx.dtb \ + gemini-sl93512r.dtb \ + gemini-sq201.dtb \ + gemini-ssi1328.dtb \ + gemini-wbd111.dtb \ + gemini-wbd222.dtb diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts similarity index 100% rename from arch/arm/boot/dts/gemini-dlink-dir-685.dts rename to arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts similarity index 100% rename from arch/arm/boot/dts/gemini-dlink-dns-313.dts rename to arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts similarity index 100% rename from arch/arm/boot/dts/gemini-nas4220b.dts rename to arch/arm/boot/dts/gemini/gemini-nas4220b.dts diff --git a/arch/arm/boot/dts/gemini-ns2502.dts b/arch/arm/boot/dts/gemini/gemini-ns2502.dts similarity index 100% rename from arch/arm/boot/dts/gemini-ns2502.dts rename to arch/arm/boot/dts/gemini/gemini-ns2502.dts diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts similarity index 100% rename from arch/arm/boot/dts/gemini-rut1xx.dts rename to arch/arm/boot/dts/gemini/gemini-rut1xx.dts diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts similarity index 100% rename from arch/arm/boot/dts/gemini-sl93512r.dts rename to arch/arm/boot/dts/gemini/gemini-sl93512r.dts diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini/gemini-sq201.dts similarity index 100% rename from arch/arm/boot/dts/gemini-sq201.dts rename to arch/arm/boot/dts/gemini/gemini-sq201.dts diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini/gemini-ssi1328.dts similarity index 100% rename from arch/arm/boot/dts/gemini-ssi1328.dts rename to arch/arm/boot/dts/gemini/gemini-ssi1328.dts diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini/gemini-wbd111.dts similarity index 100% rename from arch/arm/boot/dts/gemini-wbd111.dts rename to arch/arm/boot/dts/gemini/gemini-wbd111.dts diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini/gemini-wbd222.dts similarity index 100% rename from arch/arm/boot/dts/gemini-wbd222.dts rename to arch/arm/boot/dts/gemini/gemini-wbd222.dts diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini/gemini.dtsi similarity index 100% rename from arch/arm/boot/dts/gemini.dtsi rename to arch/arm/boot/dts/gemini/gemini.dtsi diff --git a/arch/arm/boot/dts/hisilicon/Makefile b/arch/arm/boot/dts/hisilicon/Makefile new file mode 100644 index 000000000000..5ce0512c0010 --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HI3xxx) += \ + hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HIP01) += \ + hip01-ca9x2.dtb +dtb-$(CONFIG_ARCH_HIP04) += \ + hip04-d01.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += \ + hisi-x5hd2-dkb.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hisilicon/hi3519-demb.dts similarity index 100% rename from arch/arm/boot/dts/hi3519-demb.dts rename to arch/arm/boot/dts/hisilicon/hi3519-demb.dts diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hisilicon/hi3519.dtsi similarity index 100% rename from arch/arm/boot/dts/hi3519.dtsi rename to arch/arm/boot/dts/hisilicon/hi3519.dtsi diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts similarity index 88% rename from arch/arm/boot/dts/hi3620-hi4511.dts rename to arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts index d7f5daecc9dc..f1c816a1d7cf 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts @@ -66,119 +66,119 @@ pinctrl-names = "default"; pinctrl-0 = <&board_pmx_pins>; - board_pmx_pins: board_pmx_pins { + board_pmx_pins: board-pins { pinctrl-single,pins = < 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x0f0 0x0 0x0f4 0x0 /* UART0_RX & UART0_TX */ >; }; - uart0_pmx_idle: uart0_pmx_idle { + uart0_pmx_idle: uart0-idle-pins { pinctrl-single,pins = < /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ 0x0f4 0x1 /* UART0_RX & UART0_TX */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ >; }; - uart1_pmx_idle: uart1_pmx_idle { + uart1_pmx_idle: uart1-idle-pins { pinctrl-single,pins = < 0x0f8 0x1 /* GPIO (IOMG61) */ 0x0fc 0x1 /* GPIO (IOMG62) */ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x104 0x2 /* UART2_RXD (IOMG96) */ 0x108 0x2 /* UART2_TXD (IOMG64) */ >; }; - uart2_pmx_idle: uart2_pmx_idle { + uart2_pmx_idle: uart2-idle-pins { pinctrl-single,pins = < 0x104 0x1 /* GPIO (IOMG96) */ 0x108 0x1 /* GPIO (IOMG64) */ >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ >; }; - uart3_pmx_idle: uart3_pmx_idle { + uart3_pmx_idle: uart3-idle-pins { pinctrl-single,pins = < 0x160 0x1 /* GPIO (IOMG85) */ 0x164 0x1 /* GPIO (IOMG86) */ >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ 0x16c 0x0 /* UART4_RXD (IOMG88) */ 0x170 0x0 /* UART4_TXD (IOMG93) */ >; }; - uart4_pmx_idle: uart4_pmx_idle { + uart4_pmx_idle: uart4-idle-pins { pinctrl-single,pins = < 0x168 0x1 /* GPIO (IOMG87) */ 0x16c 0x1 /* GPIO (IOMG88) */ 0x170 0x1 /* GPIO (IOMG93) */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ >; }; - i2c0_pmx_idle: i2c0_pmx_idle { + i2c0_pmx_idle: i2c0-idle-pins { pinctrl-single,pins = < 0x0b4 0x1 /* GPIO (IOMG45) */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ >; }; - i2c1_pmx_idle: i2c1_pmx_idle { + i2c1_pmx_idle: i2c1-idle-pins { pinctrl-single,pins = < 0x0b8 0x1 /* GPIO (IOMG46) */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0x068 0x0 /* I2C2_SCL (IOMG26) */ 0x06c 0x0 /* I2C2_SDA (IOMG27) */ >; }; - i2c2_pmx_idle: i2c2_pmx_idle { + i2c2_pmx_idle: i2c2-idle-pins { pinctrl-single,pins = < 0x068 0x1 /* GPIO (IOMG26) */ 0x06c 0x1 /* GPIO (IOMG27) */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x050 0x2 /* I2C3_SCL (IOMG20) */ 0x054 0x2 /* I2C3_SDA (IOMG21) */ >; }; - i2c3_pmx_idle: i2c3_pmx_idle { + i2c3_pmx_idle: i2c3-idle-pins { pinctrl-single,pins = < 0x050 0x1 /* GPIO (IOMG20) */ 0x054 0x1 /* GPIO (IOMG21) */ >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ @@ -187,7 +187,7 @@ 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ >; }; - spi0_pmx_idle: spi0_pmx_idle { + spi0_pmx_idle: spi0-idle-pins { pinctrl-single,pins = < 0x0d4 0x1 /* GPIO (IOMG53) */ 0x0d8 0x1 /* GPIO (IOMG54) */ @@ -196,21 +196,21 @@ 0x0e4 0x1 /* GPIO (IOMG57) */ >; }; - spi1_pmx_func: spi1_pmx_func { + spi1_pmx_func: spi1-pins { pinctrl-single,pins = < 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ 0x0e8 0x0 /* SPI1_DO (IOMG58) */ 0x0ec 0x0 /* SPI1_CS (IOMG95) */ >; }; - spi1_pmx_idle: spi1_pmx_idle { + spi1_pmx_idle: spi1-idle-pins { pinctrl-single,pins = < 0x184 0x1 /* GPIO (IOMG98) */ 0x0e8 0x1 /* GPIO (IOMG58) */ 0x0ec 0x1 /* GPIO (IOMG95) */ >; }; - kpc_pmx_func: kpc_pmx_func { + kpc_pmx_func: kpc-pins { pinctrl-single,pins = < 0x12c 0x0 /* KEY_IN0 (IOMG73) */ 0x130 0x0 /* KEY_IN1 (IOMG74) */ @@ -220,7 +220,7 @@ 0x114 0x0 /* KEY_OUT2 (IOMG67) */ >; }; - kpc_pmx_idle: kpc_pmx_idle { + kpc_pmx_idle: kpc-idle-pins { pinctrl-single,pins = < 0x12c 0x1 /* GPIO (IOMG73) */ 0x130 0x1 /* GPIO (IOMG74) */ @@ -230,13 +230,13 @@ 0x114 0x1 /* GPIO (IOMG67) */ >; }; - gpio_key_func: gpio_key_func { + gpio_key_func: gpio-key-pins { pinctrl-single,pins = < 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ >; }; - emmc_pmx_func: emmc_pmx_func { + emmc_pmx_func: emmc-pins { pinctrl-single,pins = < 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ 0x018 0x0 /* NAND_CS3_N (IOMG6) */ @@ -245,7 +245,7 @@ 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ >; }; - emmc_pmx_idle: emmc_pmx_idle { + emmc_pmx_idle: emmc-idle-pins { pinctrl-single,pins = < 0x030 0x0 /* GPIO (IOMG12) */ 0x018 0x1 /* GPIO (IOMG6) */ @@ -254,19 +254,19 @@ 0x02c 0x1 /* GPIO (IOMG10) */ >; }; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ >; }; - sd_pmx_idle: sd_pmx_idle { + sd_pmx_idle: sd-idle-pins { pinctrl-single,pins = < 0x0bc 0x1 /* GPIO (IOMG47) */ 0x0c0 0x1 /* GPIO (IOMG48) */ >; }; - nand_pmx_func: nand_pmx_func { + nand_pmx_func: nand-pins { pinctrl-single,pins = < 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ 0x010 0x0 /* NAND_CS1_N (IOMG4) */ @@ -279,7 +279,7 @@ 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ >; }; - nand_pmx_idle: nand_pmx_idle { + nand_pmx_idle: nand-idle-pins { pinctrl-single,pins = < 0x00c 0x1 /* GPIO (IOMG3) */ 0x010 0x1 /* GPIO (IOMG4) */ @@ -292,17 +292,17 @@ 0x02c 0x1 /* GPIO (IOMG10) */ >; }; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ >; }; - sdio_pmx_idle: sdio_pmx_idle { + sdio_pmx_idle: sdio-idle-pins { pinctrl-single,pins = < 0x0c4 0x1 /* GPIO (IOMG49) */ >; }; - audio_out_pmx_func: audio_out_pmx_func { + audio_out_pmx_func: audio-out-pins { pinctrl-single,pins = < 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ >; @@ -314,7 +314,7 @@ pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins &board_np_pins &board_ps_pins &kpc_cfg_func &audio_out_cfg_func>; - board_pu_pins: board_pu_pins { + board_pu_pins: board-pu-pins { pinctrl-single,pins = < 0x014 0 /* GPIO_158 (IOCFG2) */ 0x018 0 /* GPIO_159 (IOCFG3) */ @@ -324,7 +324,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <1 1 0 1>; }; - board_pd_pins: board_pd_pins { + board_pd_pins: board-pd-pins { pinctrl-single,pins = < 0x038 0 /* eFUSE_DOUT (IOCFG11) */ 0x150 0 /* ISP_GPIO8 (IOCFG93) */ @@ -333,7 +333,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - board_pd_ps_pins: board_pd_ps_pins { + board_pd_ps_pins: board-pd-ps-pins { pinctrl-single,pins = < 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ @@ -342,21 +342,21 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - board_np_pins: board_np_pins { + board_np_pins: board-np-pins { pinctrl-single,pins = < 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ >; pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - board_ps_pins: board_ps_pins { + board_ps_pins: board-ps-pins { pinctrl-single,pins = < 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ >; pinctrl-single,drive-strength = <0x30 0xf0>; }; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x208 0 /* UART0_RXD (IOCFG138) */ 0x20c 0 /* UART0_TXD (IOCFG139) */ @@ -364,7 +364,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart0_cfg_idle: uart0_cfg_idle { + uart0_cfg_idle: uart0-cfg-idle-pins { pinctrl-single,pins = < 0x208 0 /* UART0_RXD (IOCFG138) */ 0x20c 0 /* UART0_TXD (IOCFG139) */ @@ -372,7 +372,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart1_cfg_func: uart1_cfg_func { + uart1_cfg_func: uart1-cfg-pins { pinctrl-single,pins = < 0x210 0 /* UART1_CTS (IOCFG140) */ 0x214 0 /* UART1_RTS (IOCFG141) */ @@ -382,7 +382,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart1_cfg_idle: uart1_cfg_idle { + uart1_cfg_idle: uart1-cfg-idle-pins { pinctrl-single,pins = < 0x210 0 /* UART1_CTS (IOCFG140) */ 0x214 0 /* UART1_RTS (IOCFG141) */ @@ -392,7 +392,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x220 0 /* UART2_CTS (IOCFG144) */ 0x224 0 /* UART2_RTS (IOCFG145) */ @@ -402,7 +402,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart2_cfg_idle: uart2_cfg_idle { + uart2_cfg_idle: uart2-cfg-idle-pins { pinctrl-single,pins = < 0x220 0 /* GPIO (IOCFG144) */ 0x224 0 /* GPIO (IOCFG145) */ @@ -412,7 +412,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x294 0 /* UART3_CTS (IOCFG173) */ 0x298 0 /* UART3_RTS (IOCFG174) */ @@ -422,7 +422,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart3_cfg_idle: uart3_cfg_idle { + uart3_cfg_idle: uart3-cfg-idle-pins { pinctrl-single,pins = < 0x294 0 /* UART3_CTS (IOCFG173) */ 0x298 0 /* UART3_RTS (IOCFG174) */ @@ -432,7 +432,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x2a4 0 /* UART4_CTS (IOCFG177) */ 0x2a8 0 /* UART4_RTS (IOCFG178) */ @@ -442,7 +442,7 @@ pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x17c 0 /* I2C0_SCL (IOCFG103) */ 0x180 0 /* I2C0_SDA (IOCFG104) */ @@ -451,7 +451,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x184 0 /* I2C1_SCL (IOCFG105) */ 0x188 0 /* I2C1_SDA (IOCFG106) */ @@ -460,7 +460,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0x118 0 /* I2C2_SCL (IOCFG79) */ 0x11c 0 /* I2C2_SDA (IOCFG80) */ @@ -469,7 +469,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x100 0 /* I2C3_SCL (IOCFG73) */ 0x104 0 /* I2C3_SDA (IOCFG74) */ @@ -478,7 +478,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi0_cfg_func1: spi0_cfg_func1 { + spi0_cfg_func1: spi0-cfg-func1-pins { pinctrl-single,pins = < 0x1d4 0 /* SPI0_CLK (IOCFG125) */ 0x1d8 0 /* SPI0_DI (IOCFG126) */ @@ -488,7 +488,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi0_cfg_func2: spi0_cfg_func2 { + spi0_cfg_func2: spi0-cfg-func2-pins { pinctrl-single,pins = < 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ @@ -499,7 +499,7 @@ pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi1_cfg_func1: spi1_cfg_func1 { + spi1_cfg_func1: spi1-cfg-func1-pins { pinctrl-single,pins = < 0x1f0 0 /* SPI1_CLK (IOCFG132) */ 0x1f4 0 /* SPI1_DI (IOCFG133) */ @@ -509,7 +509,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi1_cfg_func2: spi1_cfg_func2 { + spi1_cfg_func2: spi1-cfg-func2-pins { pinctrl-single,pins = < 0x1fc 0 /* SPI1_CS (IOCFG135) */ >; @@ -517,7 +517,7 @@ pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - kpc_cfg_func: kpc_cfg_func { + kpc_cfg_func: kpc-cfg-pins { pinctrl-single,pins = < 0x250 0 /* KEY_IN0 (IOCFG156) */ 0x254 0 /* KEY_IN1 (IOCFG157) */ @@ -529,7 +529,7 @@ pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - emmc_cfg_func: emmc_cfg_func { + emmc_cfg_func: emmc-cfg-pins { pinctrl-single,pins = < 0x0ac 0 /* eMMC_CMD (IOCFG40) */ 0x0b0 0 /* eMMC_CLK (IOCFG41) */ @@ -549,7 +549,7 @@ pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sd_cfg_func1: sd_cfg_func1 { + sd_cfg_func1: sd-cfg-func1-pins { pinctrl-single,pins = < 0x18c 0 /* SD_CLK (IOCFG107) */ 0x190 0 /* SD_CMD (IOCFG108) */ @@ -558,7 +558,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sd_cfg_func2: sd_cfg_func2 { + sd_cfg_func2: sd-cfg-func2-pins { pinctrl-single,pins = < 0x194 0 /* SD_DATA0 (IOCFG109) */ 0x198 0 /* SD_DATA1 (IOCFG110) */ @@ -569,7 +569,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x70 0xf0>; }; - nand_cfg_func1: nand_cfg_func1 { + nand_cfg_func1: nand-cfg-func1-pins { pinctrl-single,pins = < 0x03c 0 /* NAND_ALE (IOCFG12) */ 0x040 0 /* NAND_CLE (IOCFG13) */ @@ -594,7 +594,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - nand_cfg_func2: nand_cfg_func2 { + nand_cfg_func2: nand-cfg-func2-pins { pinctrl-single,pins = < 0x044 0 /* NAND_RE_N (IOCFG14) */ 0x048 0 /* NAND_WE_N (IOCFG15) */ @@ -611,7 +611,7 @@ pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x1a4 0 /* SDIO0_CLK (IOCG113) */ 0x1a8 0 /* SDIO0_CMD (IOCG114) */ @@ -624,7 +624,7 @@ pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - audio_out_cfg_func: audio_out_cfg_func { + audio_out_cfg_func: audio-out-cfg-pins { pinctrl-single,pins = < 0x200 0 /* GPIO (IOCFG136) */ 0x204 0 /* GPIO (IOCFG137) */ diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hisilicon/hi3620.dtsi similarity index 99% rename from arch/arm/boot/dts/hi3620.dtsi rename to arch/arm/boot/dts/hisilicon/hi3620.dtsi index cf48ec14af43..a254ec009296 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hisilicon/hi3620.dtsi @@ -545,10 +545,9 @@ compatible = "pinctrl-single"; reg = <0x803000 0x188>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; #gpio-range-cells = <3>; - ranges; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <7>; @@ -567,9 +566,8 @@ compatible = "pinconf-single"; reg = <0x803800 0x2dc>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; - ranges; pinctrl-single,register-width = <32>; }; diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts similarity index 100% rename from arch/arm/boot/dts/hip01-ca9x2.dts rename to arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hisilicon/hip01.dtsi similarity index 100% rename from arch/arm/boot/dts/hip01.dtsi rename to arch/arm/boot/dts/hisilicon/hip01.dtsi diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hisilicon/hip04-d01.dts similarity index 100% rename from arch/arm/boot/dts/hip04-d01.dts rename to arch/arm/boot/dts/hisilicon/hip04-d01.dts diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hisilicon/hip04.dtsi similarity index 100% rename from arch/arm/boot/dts/hip04.dtsi rename to arch/arm/boot/dts/hisilicon/hip04.dtsi diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts similarity index 100% rename from arch/arm/boot/dts/hisi-x5hd2-dkb.dts rename to arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi similarity index 100% rename from arch/arm/boot/dts/hisi-x5hd2.dtsi rename to arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/hisilicon/sd5203.dts similarity index 100% rename from arch/arm/boot/dts/sd5203.dts rename to arch/arm/boot/dts/hisilicon/sd5203.dts diff --git a/arch/arm/boot/dts/hpe/Makefile b/arch/arm/boot/dts/hpe/Makefile new file mode 100644 index 000000000000..e175b1732cdb --- /dev/null +++ b/arch/arm/boot/dts/hpe/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HPE_GXP) += \ + hpe-bmc-dl360gen10.dtb diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts similarity index 100% rename from arch/arm/boot/dts/hpe-bmc-dl360gen10.dts rename to arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi similarity index 100% rename from arch/arm/boot/dts/hpe-gxp.dtsi rename to arch/arm/boot/dts/hpe/hpe-gxp.dtsi diff --git a/arch/arm/boot/dts/intel/Makefile b/arch/arm/boot/dts/intel/Makefile new file mode 100644 index 000000000000..c5fc845deb61 --- /dev/null +++ b/arch/arm/boot/dts/intel/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += axm +subdir-y += ixp +subdir-y += pxa +subdir-y += socfpga diff --git a/arch/arm/boot/dts/intel/axm/Makefile b/arch/arm/boot/dts/intel/axm/Makefile new file mode 100644 index 000000000000..7c7dc679964d --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts similarity index 100% rename from arch/arm/boot/dts/axm5516-amarillo.dts rename to arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/axm5516-cpus.dtsi rename to arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/intel/axm/axm55xx.dtsi similarity index 100% rename from arch/arm/boot/dts/axm55xx.dtsi rename to arch/arm/boot/dts/intel/axm/axm55xx.dtsi diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile new file mode 100644 index 000000000000..1a25ce3cf84f --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-linksys-wrv54g.dtb \ + intel-ixp42x-freecom-fsg-3.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ + intel-ixp42x-ixdp425.dtb \ + intel-ixp43x-kixrp435.dtb \ + intel-ixp46x-ixdp465.dtb \ + intel-ixp42x-adi-coyote.dtb \ + intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ + intel-ixp42x-iomega-nas100d.dtb \ + intel-ixp42x-dlink-dsm-g600.dtb \ + intel-ixp42x-gateworks-gw2348.dtb \ + intel-ixp43x-gateworks-gw2358.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-ixdp425.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x-kixrp435.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp46x-ixdp465.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp4xx.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi diff --git a/arch/arm/boot/dts/intel/pxa/Makefile b/arch/arm/boot/dts/intel/pxa/Makefile new file mode 100644 index 000000000000..24d5240f08e7 --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PXA) += \ + pxa300-raumfeld-connector.dtb \ + pxa300-raumfeld-controller.dtb \ + pxa300-raumfeld-speaker-l.dtb \ + pxa300-raumfeld-speaker-m.dtb \ + pxa300-raumfeld-speaker-one.dtb \ + pxa300-raumfeld-speaker-s.dtb diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa25x.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa25x.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa25x.dtsi diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa27x.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa27x.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa27x.dtsi diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa2xx.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-common.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi diff --git a/arch/arm/boot/dts/pxa300-raumfeld-connector.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-connector.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-controller.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa3xx.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile new file mode 100644 index 000000000000..c467828aeb4b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ + socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_pe1.dtb \ + socfpga_arria10_socdk_nand.dtb \ + socfpga_arria10_socdk_qspi.dtb \ + socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ + socfpga_cyclone5_mcvevk.dtb \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_vt.dtb diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria5.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria5_socdk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_socdk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_sockit.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_socrates.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_sodia.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_vt.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile new file mode 100644 index 000000000000..1e0f5ff492f7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/Makefile @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MMP) += \ + pxa168-aspenite.dtb \ + pxa910-dkb.dtb \ + mmp2-brownstone.dtb \ + mmp2-olpc-xo-1-75.dtb \ + mmp3-dell-ariel.dtb +dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-kuroboxpro.dtb \ + orion5x-lacie-d2-network.dtb \ + orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-linkstation-lsgl.dtb \ + orion5x-linkstation-lswtgl.dtb \ + orion5x-linkstation-lschl.dtb \ + orion5x-lswsgl.dtb \ + orion5x-maxtor-shared-storage-2.dtb \ + orion5x-netgear-wnr854t.dtb \ + orion5x-rd88f5182-nas.dtb +dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-c200-v2.dtb \ + armada-370-db.dtb \ + armada-370-dlink-dns327l.dtb \ + armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ + armada-370-rd.dtb \ + armada-370-seagate-nas-2bay.dtb \ + armada-370-seagate-nas-4bay.dtb \ + armada-370-seagate-personal-cloud.dtb \ + armada-370-seagate-personal-cloud-2bay.dtb \ + armada-370-synology-ds213j.dtb +dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb +dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-381-netgear-gs110emx.dtb \ + armada-382-rd-ac3x-48g4x2xl.dtb \ + armada-385-atl-x530.dtb \ + armada-385-clearfog-gtr-s4.dtb \ + armada-385-clearfog-gtr-l8.dtb \ + armada-385-db-88f6820-amc.dtb \ + armada-385-db-ap.dtb \ + armada-385-linksys-caiman.dtb \ + armada-385-linksys-cobra.dtb \ + armada-385-linksys-rango.dtb \ + armada-385-linksys-shelby.dtb \ + armada-385-synology-ds116.dtb \ + armada-385-turris-omnia.dtb \ + armada-388-clearfog.dtb \ + armada-388-clearfog-base.dtb \ + armada-388-clearfog-pro.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-helios4.dtb \ + armada-388-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-390-db.dtb \ + armada-395-gp.dtb \ + armada-398-db.dtb +dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ + armada-xp-db.dtb \ + armada-xp-db-dxbc2.dtb \ + armada-xp-db-xc3-24g4xg.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ + armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb \ + armada-xp-synology-ds414.dtb +dtb-$(CONFIG_MACH_DOVE) += \ + dove-cubox.dtb \ + dove-cubox-es.dtb \ + dove-d2plug.dtb \ + dove-d3plug.dtb \ + dove-dove-db.dtb \ + dove-sbc-a510.dtb +dtb-$(CONFIG_MACH_KIRKWOOD) += \ + kirkwood-4i-edge-200.dtb \ + kirkwood-b3.dtb \ + kirkwood-blackarmor-nas220.dtb \ + kirkwood-c200-v1.dtb \ + kirkwood-cloudbox.dtb \ + kirkwood-d2net.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ + kirkwood-dir665.dtb \ + kirkwood-dns320.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-ds110jv10.dtb \ + kirkwood-ds111.dtb \ + kirkwood-ds112.dtb \ + kirkwood-ds209.dtb \ + kirkwood-ds210.dtb \ + kirkwood-ds212.dtb \ + kirkwood-ds212j.dtb \ + kirkwood-ds409.dtb \ + kirkwood-ds409slim.dtb \ + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-iomega_ix2_200.dtb \ + kirkwood-is2.dtb \ + kirkwood-km_fixedeth.dtb \ + kirkwood-km_kirkwood.dtb \ + kirkwood-l-50.dtb \ + kirkwood-laplug.dtb \ + kirkwood-linkstation-lsqvl.dtb \ + kirkwood-linkstation-lsvl.dtb \ + kirkwood-linkstation-lswsxl.dtb \ + kirkwood-linkstation-lswvl.dtb \ + kirkwood-linkstation-lswxl.dtb \ + kirkwood-linksys-viper.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-mplcec4.dtb \ + kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ + kirkwood-net2big.dtb \ + kirkwood-net5big.dtb \ + kirkwood-netgear_readynas_duo_v2.dtb \ + kirkwood-netgear_readynas_nv+_v2.dtb \ + kirkwood-ns2.dtb \ + kirkwood-ns2lite.dtb \ + kirkwood-ns2max.dtb \ + kirkwood-ns2mini.dtb \ + kirkwood-nsa310.dtb \ + kirkwood-nsa310a.dtb \ + kirkwood-nsa310s.dtb \ + kirkwood-nsa320.dtb \ + kirkwood-nsa325.dtb \ + kirkwood-openblocks_a6.dtb \ + kirkwood-openblocks_a7.dtb \ + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ + kirkwood-pogo_e02.dtb \ + kirkwood-pogoplug-series-4.dtb \ + kirkwood-rd88f6192.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ + kirkwood-rs212.dtb \ + kirkwood-rs409.dtb \ + kirkwood-rs411.dtb \ + kirkwood-sheevaplug.dtb \ + kirkwood-sheevaplug-esata.dtb \ + kirkwood-t5325.dtb \ + kirkwood-topkick.dtb \ + kirkwood-ts219-6281.dtb \ + kirkwood-ts219-6282.dtb \ + kirkwood-ts419-6281.dtb \ + kirkwood-ts419-6282.dtb diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/marvell/armada-370-c200-v2.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-c200-v2.dts rename to arch/arm/boot/dts/marvell/armada-370-c200-v2.dts diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/marvell/armada-370-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-db.dts rename to arch/arm/boot/dts/marvell/armada-370-db.dts diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-dlink-dns327l.dts rename to arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/marvell/armada-370-mirabox.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-mirabox.dts rename to arch/arm/boot/dts/marvell/armada-370-mirabox.dts diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-netgear-rn102.dts rename to arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-netgear-rn104.dts rename to arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/marvell/armada-370-rd.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-rd.dts rename to arch/arm/boot/dts/marvell/armada-370-rd.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-synology-ds213j.dts rename to arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-xp.dtsi rename to arch/arm/boot/dts/marvell/armada-370-xp.dtsi diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/marvell/armada-370.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370.dtsi rename to arch/arm/boot/dts/marvell/armada-370.dtsi diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/marvell/armada-375-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-375-db.dts rename to arch/arm/boot/dts/marvell/armada-375-db.dts diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-375.dtsi rename to arch/arm/boot/dts/marvell/armada-375.dtsi diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-380.dtsi rename to arch/arm/boot/dts/marvell/armada-380.dtsi diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts similarity index 100% rename from arch/arm/boot/dts/armada-381-netgear-gs110emx.dts rename to arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts diff --git a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts similarity index 100% rename from arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts rename to arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts similarity index 96% rename from arch/arm/boot/dts/armada-385-atl-x530.dts rename to arch/arm/boot/dts/marvell/armada-385-atl-x530.dts index 241f5d7c80e9..5a9ab8410b7b 100644 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts @@ -179,19 +179,19 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@u-boot { + partition@0 { reg = <0x00000000 0x00100000>; label = "u-boot"; }; - partition@u-boot-env { + partition@100000 { reg = <0x00100000 0x00040000>; label = "u-boot-env"; }; - partition@unused { + partition@140000 { reg = <0x00140000 0x00e80000>; label = "unused"; }; - partition@idprom { + partition@fc0000 { reg = <0x00fc0000 0x00040000>; label = "idprom"; }; @@ -216,16 +216,16 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@user { + partition@0 { reg = <0x00000000 0x0f000000>; label = "user"; }; - partition@errlog { + partition@f000000 { /* Maximum mtdoops size is 8MB, so set to that. */ reg = <0x0f000000 0x00800000>; label = "errlog"; }; - partition@nand-bbt { + partition@f800000 { reg = <0x0f800000 0x00800000>; label = "nand-bbt"; }; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-db-88f6820-amc.dts rename to arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/marvell/armada-385-db-ap.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-db-ap.dts rename to arch/arm/boot/dts/marvell/armada-385-db-ap.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-caiman.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-cobra.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-rango.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-shelby.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys.dtsi rename to arch/arm/boot/dts/marvell/armada-385-linksys.dtsi diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-synology-ds116.dts rename to arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-turris-omnia.dts rename to arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/marvell/armada-385.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385.dtsi rename to arch/arm/boot/dts/marvell/armada-385.dtsi diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog-base.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog-pro.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts similarity index 97% rename from arch/arm/boot/dts/armada-388-clearfog.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog.dts index 95299167dcf5..32c569df142f 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -47,6 +47,8 @@ ð1 { /* ethernet@30000 */ + phy-mode = "1000base-x"; + fixed-link { speed = <1000>; full-duplex; @@ -129,8 +131,9 @@ port@5 { reg = <5>; - label = "cpu"; ethernet = <ð1>; + phy-mode = "1000base-x"; + fixed-link { speed = <1000>; full-duplex; @@ -141,6 +144,8 @@ /* 88E1512 external phy */ reg = <6>; label = "lan6"; + phy-mode = "rgmii-id"; + fixed-link { speed = <1000>; full-duplex; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog.dtsi rename to arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/marvell/armada-388-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-db.dts rename to arch/arm/boot/dts/marvell/armada-388-db.dts diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/marvell/armada-388-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-gp.dts rename to arch/arm/boot/dts/marvell/armada-388-gp.dts diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-helios4.dts rename to arch/arm/boot/dts/marvell/armada-388-helios4.dts diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/marvell/armada-388-rd.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-rd.dts rename to arch/arm/boot/dts/marvell/armada-388-rd.dts diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/marvell/armada-388.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-388.dtsi rename to arch/arm/boot/dts/marvell/armada-388.dtsi diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi rename to arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-38x.dtsi rename to arch/arm/boot/dts/marvell/armada-38x.dtsi diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/marvell/armada-390-db.dts similarity index 99% rename from arch/arm/boot/dts/armada-390-db.dts rename to arch/arm/boot/dts/marvell/armada-390-db.dts index 792d0a0184e8..20f518dbac97 100644 --- a/arch/arm/boot/dts/armada-390-db.dts +++ b/arch/arm/boot/dts/marvell/armada-390-db.dts @@ -81,7 +81,7 @@ pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - flash@1 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/marvell/armada-390.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-390.dtsi rename to arch/arm/boot/dts/marvell/armada-390.dtsi diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/marvell/armada-395-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-395-gp.dts rename to arch/arm/boot/dts/marvell/armada-395-gp.dts diff --git a/arch/arm/boot/dts/armada-395.dtsi b/arch/arm/boot/dts/marvell/armada-395.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-395.dtsi rename to arch/arm/boot/dts/marvell/armada-395.dtsi diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/marvell/armada-398-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-398-db.dts rename to arch/arm/boot/dts/marvell/armada-398-db.dts diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/marvell/armada-398.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-398.dtsi rename to arch/arm/boot/dts/marvell/armada-398.dtsi diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-39x.dtsi rename to arch/arm/boot/dts/marvell/armada-39x.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx3236.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx3336.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx4251.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-axpwifiap.dts rename to arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db-dxbc2.dts rename to arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts rename to arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/marvell/armada-xp-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db.dts rename to arch/arm/boot/dts/marvell/armada-xp-db.dts diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/marvell/armada-xp-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-gp.dts rename to arch/arm/boot/dts/marvell/armada-xp-gp.dts diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts similarity index 98% rename from arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts rename to arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts index 0dad95ea26c2..21b95578fe95 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts @@ -167,8 +167,8 @@ spi-3 { compatible = "spi-gpio"; status = "okay"; - gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ + sck-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + mosi-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-linksys-mamba.dts rename to arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/marvell/armada-xp-matrix.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-matrix.dts rename to arch/arm/boot/dts/marvell/armada-xp-matrix.dts diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78230.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78260.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78460.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-netgear-rn2120.dts rename to arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts rename to arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-synology-ds414.dts rename to arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/marvell/armada-xp.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp.dtsi rename to arch/arm/boot/dts/marvell/armada-xp.dtsi diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi similarity index 100% rename from arch/arm/boot/dts/dove-cm-a510.dtsi rename to arch/arm/boot/dts/marvell/dove-cm-a510.dtsi diff --git a/arch/arm/boot/dts/dove-cubox-es.dts b/arch/arm/boot/dts/marvell/dove-cubox-es.dts similarity index 100% rename from arch/arm/boot/dts/dove-cubox-es.dts rename to arch/arm/boot/dts/marvell/dove-cubox-es.dts diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts similarity index 100% rename from arch/arm/boot/dts/dove-cubox.dts rename to arch/arm/boot/dts/marvell/dove-cubox.dts diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/marvell/dove-d2plug.dts similarity index 100% rename from arch/arm/boot/dts/dove-d2plug.dts rename to arch/arm/boot/dts/marvell/dove-d2plug.dts diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/marvell/dove-d3plug.dts similarity index 100% rename from arch/arm/boot/dts/dove-d3plug.dts rename to arch/arm/boot/dts/marvell/dove-d3plug.dts diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/marvell/dove-dove-db.dts similarity index 100% rename from arch/arm/boot/dts/dove-dove-db.dts rename to arch/arm/boot/dts/marvell/dove-dove-db.dts diff --git a/arch/arm/boot/dts/dove-sbc-a510.dts b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts similarity index 100% rename from arch/arm/boot/dts/dove-sbc-a510.dts rename to arch/arm/boot/dts/marvell/dove-sbc-a510.dts diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/marvell/dove.dtsi similarity index 100% rename from arch/arm/boot/dts/dove.dtsi rename to arch/arm/boot/dts/marvell/dove.dtsi diff --git a/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts b/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts new file mode 100644 index 000000000000..b1749d3f60b7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Endian 4i Edge 200 Board Description + * Note: Endian UTM Mini is hardware clone of Endian Edge 200 + * Copyright 2021-2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "Endian 4i Edge 200"; + compatible = "endian,4i-edge-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_SD; + color = ; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + speed = <1000>; + duplex = <1>; +}; + +ð1 { + status = "okay"; +}; + +ð1port { + phy-handle = <ðphyb>; +}; + +&mdio { + status = "okay"; + + ethphyb: ethernet-phy@b { + reg = <0x0b>; + + marvell,reg-init = + /* link-activity, bi-color mode 4 */ + <3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */ + }; + + switch0: switch@11 { + compatible = "marvell,mv88e6085"; + reg = <0x11>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "port4"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot-env"; + reg = <0x000a0000 0x00060000>; + read-only; + }; + + partition@100000 { + label = "kernel"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "ubi"; + reg = <0x00500000 0x1fb00000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_sysrst>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp34", "mpp35", "mpp49"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&sdio { + pinctrl-0 = <&pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio0 28 9>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6192.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6192.dtsi diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6282.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6282.dtsi diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-98dx4122.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/marvell/kirkwood-b3.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-b3.dts rename to arch/arm/boot/dts/marvell/kirkwood-b3.dts diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts rename to arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts diff --git a/arch/arm/boot/dts/kirkwood-c200-v1.dts b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-c200-v1.dts rename to arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-cloudbox.dts rename to arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-d2net.dts rename to arch/arm/boot/dts/marvell/kirkwood-d2net.dts diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-db-88f6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-db-88f6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-db.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-db.dtsi diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dir665.dts rename to arch/arm/boot/dts/marvell/kirkwood-dir665.dts diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dns320.dts rename to arch/arm/boot/dts/marvell/kirkwood-dns320.dts diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dns325.dts rename to arch/arm/boot/dts/marvell/kirkwood-dns325.dts diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-dnskw.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dockstar.dts rename to arch/arm/boot/dts/marvell/kirkwood-dockstar.dts diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dreamplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/marvell/kirkwood-ds109.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds109.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds109.dts diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds110jv10.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/marvell/kirkwood-ds111.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds111.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds111.dts diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/marvell/kirkwood-ds112.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds112.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds112.dts diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/marvell/kirkwood-ds209.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds209.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds209.dts diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/marvell/kirkwood-ds210.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds210.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds210.dts diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds212.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds212.dts diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212j.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds212j.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds212j.dts diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds409.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds409.dts diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds409slim.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411j.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411j.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411j.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411slim.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-goflexnet.dts rename to arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts rename to arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ib62x0.dts rename to arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-iconnect.dts rename to arch/arm/boot/dts/marvell/kirkwood-iconnect.dts diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts rename to arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/marvell/kirkwood-is2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-is2.dts rename to arch/arm/boot/dts/marvell/kirkwood-is2.dts diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_fixedeth.dts rename to arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_kirkwood.dts rename to arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-l-50.dts rename to arch/arm/boot/dts/marvell/kirkwood-l-50.dts diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-laplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-laplug.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linksys-viper.dts rename to arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-lschlv2.dts rename to arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-lsxhl.dts rename to arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-lsxl.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-mplcec4.dts rename to arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts rename to arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/marvell/kirkwood-nas2big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nas2big.dts rename to arch/arm/boot/dts/marvell/kirkwood-nas2big.dts diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/marvell/kirkwood-net2big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-net2big.dts rename to arch/arm/boot/dts/marvell/kirkwood-net2big.dts diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/marvell/kirkwood-net5big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-net5big.dts rename to arch/arm/boot/dts/marvell/kirkwood-net5big.dts diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts rename to arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts rename to arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-netxbig.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2lite.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2max.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2max.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2max.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2mini.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310a.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310s.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa320.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa320.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa325.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa325.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openblocks_a6.dts rename to arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openblocks_a7.dts rename to arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-base.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-client.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-ultimate.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-pogo_e02.dts rename to arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts rename to arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6192.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281-a.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/marvell/kirkwood-rs212.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs212.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs212.dts diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/marvell/kirkwood-rs409.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs409.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs409.dts diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/marvell/kirkwood-rs411.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs411.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs411.dts diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-synology.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-synology.dtsi diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-t5325.dts rename to arch/arm/boot/dts/marvell/kirkwood-t5325.dts diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/marvell/kirkwood-topkick.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-topkick.dts rename to arch/arm/boot/dts/marvell/kirkwood-topkick.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219-6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219-6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419-6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419-6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/marvell/kirkwood.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood.dtsi rename to arch/arm/boot/dts/marvell/kirkwood.dtsi diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts similarity index 100% rename from arch/arm/boot/dts/mmp2-brownstone.dts rename to arch/arm/boot/dts/marvell/mmp2-brownstone.dts diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts similarity index 100% rename from arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts rename to arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/marvell/mmp2.dtsi similarity index 100% rename from arch/arm/boot/dts/mmp2.dtsi rename to arch/arm/boot/dts/marvell/mmp2.dtsi diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts similarity index 100% rename from arch/arm/boot/dts/mmp3-dell-ariel.dts rename to arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/marvell/mmp3.dtsi similarity index 100% rename from arch/arm/boot/dts/mmp3.dtsi rename to arch/arm/boot/dts/marvell/mmp3.dtsi diff --git a/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi similarity index 100% rename from arch/arm/boot/dts/mvebu-linkstation-fan.dtsi rename to arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi diff --git a/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi similarity index 100% rename from arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi rename to arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi diff --git a/arch/arm/boot/dts/orion5x-kuroboxpro.dts b/arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-kuroboxpro.dts rename to arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lacie-d2-network.dts rename to arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts rename to arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lschl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lsgl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation.dtsi rename to arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lswsgl.dts rename to arch/arm/boot/dts/marvell/orion5x-lswsgl.dts diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts rename to arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-mv88f5181.dtsi rename to arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-mv88f5182.dtsi rename to arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-netgear-wnr854t.dts rename to arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-rd88f5182-nas.dts rename to arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/marvell/orion5x.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x.dtsi rename to arch/arm/boot/dts/marvell/orion5x.dtsi diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/marvell/pxa168-aspenite.dts similarity index 100% rename from arch/arm/boot/dts/pxa168-aspenite.dts rename to arch/arm/boot/dts/marvell/pxa168-aspenite.dts diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/marvell/pxa168.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa168.dtsi rename to arch/arm/boot/dts/marvell/pxa168.dtsi diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/marvell/pxa910-dkb.dts similarity index 100% rename from arch/arm/boot/dts/pxa910-dkb.dts rename to arch/arm/boot/dts/marvell/pxa910-dkb.dts diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/marvell/pxa910.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa910.dtsi rename to arch/arm/boot/dts/marvell/pxa910.dtsi diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile new file mode 100644 index 000000000000..1957947cb41c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt2701-evb.dtb \ + mt6580-evbp1.dtb \ + mt6582-prestigio-pmt5008-3g.dtb \ + mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ + mt6592-evb.dtb \ + mt7623a-rfb-emmc.dtb \ + mt7623a-rfb-nand.dtb \ + mt7623n-rfb-emmc.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts similarity index 100% rename from arch/arm/boot/dts/mt2701-evb.dts rename to arch/arm/boot/dts/mediatek/mt2701-evb.dts diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mediatek/mt2701-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/mt2701-pinfunc.h rename to arch/arm/boot/dts/mediatek/mt2701-pinfunc.h diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi similarity index 100% rename from arch/arm/boot/dts/mt2701.dtsi rename to arch/arm/boot/dts/mediatek/mt2701.dtsi diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6323.dtsi rename to arch/arm/boot/dts/mediatek/mt6323.dtsi diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mediatek/mt6580-evbp1.dts similarity index 100% rename from arch/arm/boot/dts/mt6580-evbp1.dts rename to arch/arm/boot/dts/mediatek/mt6580-evbp1.dts diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mediatek/mt6580.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6580.dtsi rename to arch/arm/boot/dts/mediatek/mt6580.dtsi diff --git a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts similarity index 100% rename from arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts rename to arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts diff --git a/arch/arm/boot/dts/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6582.dtsi rename to arch/arm/boot/dts/mediatek/mt6582.dtsi diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts similarity index 100% rename from arch/arm/boot/dts/mt6589-aquaris5.dts rename to arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts similarity index 100% rename from arch/arm/boot/dts/mt6589-fairphone-fp1.dts rename to arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6589.dtsi rename to arch/arm/boot/dts/mediatek/mt6589.dtsi diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mediatek/mt6592-evb.dts similarity index 100% rename from arch/arm/boot/dts/mt6592-evb.dts rename to arch/arm/boot/dts/mediatek/mt6592-evb.dts diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mediatek/mt6592.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6592.dtsi rename to arch/arm/boot/dts/mediatek/mt6592.dtsi diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi similarity index 99% rename from arch/arm/boot/dts/mt7623.dtsi rename to arch/arm/boot/dts/mediatek/mt7623.dtsi index 11379c3e6b4c..f0b4a09004b3 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -980,6 +980,18 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + status = "disabled"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; }; crypto: crypto@1b240000 { diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts similarity index 79% rename from arch/arm/boot/dts/mt7623a-rfb-emmc.dts rename to arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts index e8b4b6d30d19..5654284bab01 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ b/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts @@ -112,75 +112,31 @@ status = "okay"; }; -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; }; - }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; + port@1 { + status = "okay"; + label = "lan1"; + }; - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; + port@2 { + status = "okay"; + label = "lan2"; + }; - ports { - #address-cells = <1>; - #size-cells = <0>; + port@3 { + status = "okay"; + label = "lan3"; + }; - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; + port@4 { + status = "okay"; + label = "wan"; }; }; }; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts similarity index 81% rename from arch/arm/boot/dts/mt7623a-rfb-nand.dts rename to arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts index 61f5da68d4b0..afd177b3b516 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ b/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts @@ -116,75 +116,31 @@ status = "okay"; }; -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; }; - }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; + port@1 { + status = "okay"; + label = "lan1"; + }; - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; + port@2 { + status = "okay"; + label = "lan2"; + }; - ports { - #address-cells = <1>; - #size-cells = <0>; + port@3 { + status = "okay"; + label = "lan3"; + }; - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; + port@4 { + status = "okay"; + label = "wan"; }; }; }; diff --git a/arch/arm/boot/dts/mediatek/mt7623a.dtsi b/arch/arm/boot/dts/mediatek/mt7623a.dtsi new file mode 100644 index 000000000000..bcf909d58a1c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt7623a.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: Sean Wang + * + */ + +/dts-v1/; +#include +#include "mt7623.dtsi" + +&afe { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&crypto { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +ð { + status = "okay"; + power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@1f { + compatible = "mediatek,mt7530"; + reg = <0x1f>; + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "swp0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "swp1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "swp2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "swp3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "swp4"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&nandc { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&pcie { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; + +&scpsys { + compatible = "mediatek,mt7623a-scpsys"; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "ethif"; +}; + +&usb0 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; +}; + +&usb1 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; + +&usb2 { + power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; +}; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts similarity index 93% rename from arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts rename to arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts index ece61a6a7a89..a37f3fa223c7 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts @@ -171,28 +171,38 @@ }; }; +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + ð { status = "okay"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { + mdio-bus { #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; @@ -226,6 +236,19 @@ label = "lan3"; }; + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts similarity index 95% rename from arch/arm/boot/dts/mt7623n-rfb-emmc.dts rename to arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts index bf67a8e9be59..34994f3f5a4b 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts @@ -156,28 +156,26 @@ }; }; +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy5>; +}; + ð { status = "okay"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -187,9 +185,9 @@ phy-mode = "rgmii-rxid"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; @@ -232,6 +230,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mediatek/mt7623n.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7623n.dtsi rename to arch/arm/boot/dts/mediatek/mt7623n.dtsi diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts similarity index 100% rename from arch/arm/boot/dts/mt7629-rfb.dts rename to arch/arm/boot/dts/mediatek/mt7629-rfb.dts diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mediatek/mt7629.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7629.dtsi rename to arch/arm/boot/dts/mediatek/mt7629.dtsi diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mediatek/mt8127-moose.dts similarity index 100% rename from arch/arm/boot/dts/mt8127-moose.dts rename to arch/arm/boot/dts/mediatek/mt8127-moose.dts diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mediatek/mt8127.dtsi similarity index 100% rename from arch/arm/boot/dts/mt8127.dtsi rename to arch/arm/boot/dts/mediatek/mt8127.dtsi diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mediatek/mt8135-evbp1.dts similarity index 100% rename from arch/arm/boot/dts/mt8135-evbp1.dts rename to arch/arm/boot/dts/mediatek/mt8135-evbp1.dts diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mediatek/mt8135.dtsi similarity index 100% rename from arch/arm/boot/dts/mt8135.dtsi rename to arch/arm/boot/dts/mediatek/mt8135.dtsi diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..0f5193d05a31 --- /dev/null +++ b/arch/arm/boot/dts/microchip/Makefile @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_AT91RM9200) += \ + at91rm9200ek.dtb \ + mpa1600.dtb +dtb-$(CONFIG_SOC_AT91SAM9) += \ + animeo_ip.dtb \ + at91-qil_a9260.dtb \ + aks-cdu.dtb \ + ethernut5.dtb \ + evk-pro3.dtb \ + tny_a9260.dtb \ + usb_a9260.dtb \ + at91sam9260ek.dtb \ + at91sam9261ek.dtb \ + at91sam9263ek.dtb \ + at91-sam9_l9260.dtb \ + tny_a9263.dtb \ + usb_a9263.dtb \ + at91-foxg20.dtb \ + at91-kizbox.dtb \ + at91-lmu5000.dtb \ + at91sam9g20ek.dtb \ + at91sam9g20ek_2mmc.dtb \ + tny_a9g20.dtb \ + usb_a9g20.dtb \ + usb_a9g20_lpw.dtb \ + at91sam9m10g45ek.dtb \ + pm9g45.dtb \ + at91sam9n12ek.dtb \ + at91sam9rlek.dtb \ + at91-ariag25.dtb \ + at91-ariettag25.dtb \ + at91-cosino_mega2560.dtb \ + at91-kizboxmini-base.dtb \ + at91-kizboxmini-mb.dtb \ + at91-kizboxmini-rd.dtb \ + at91-q5xr5.dtb \ + at91-smartkiz.dtb \ + at91-wb45n.dtb \ + at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +dtb-$(CONFIG_SOC_SAM9X60) += \ + at91-sam9x60_curiosity.dtb \ + at91-sam9x60ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +dtb-$(CONFIG_SOC_SAM_V7) += \ + at91-kizbox2-2.dtb \ + at91-kizbox3-hs.dtb \ + at91-nattis-2-natte-2.dtb \ + at91-sama5d27_som1_ek.dtb \ + at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d2_icp.dtb \ + at91-sama5d2_ptc_ek.dtb \ + at91-sama5d2_xplained.dtb \ + at91-sama5d3_eds.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ + at91-sama5d3_xplained.dtb \ + at91-dvk_som60.dtb \ + at91-gatwick.dtb \ + at91-tse850-3.dtb \ + at91-wb50n.dtb \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb \ + at91-sama5d4_ma5d4evk.dtb \ + at91-sama5d4_xplained.dtb \ + at91-sama5d4ek.dtb \ + at91-vinco.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_SAMA7G5) += \ + at91-sama7g5ek.dtb + +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb \ + lan966x-pcb8290.dtb \ + lan966x-pcb8291.dtb \ + lan966x-pcb8309.dtb diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/microchip/aks-cdu.dts similarity index 100% rename from arch/arm/boot/dts/aks-cdu.dts rename to arch/arm/boot/dts/microchip/aks-cdu.dts diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/microchip/animeo_ip.dts similarity index 100% rename from arch/arm/boot/dts/animeo_ip.dts rename to arch/arm/boot/dts/microchip/animeo_ip.dts diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/microchip/at91-ariag25.dts similarity index 100% rename from arch/arm/boot/dts/at91-ariag25.dts rename to arch/arm/boot/dts/microchip/at91-ariag25.dts diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/microchip/at91-ariettag25.dts similarity index 100% rename from arch/arm/boot/dts/at91-ariettag25.dts rename to arch/arm/boot/dts/microchip/at91-ariettag25.dts diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/microchip/at91-cosino.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-cosino.dtsi rename to arch/arm/boot/dts/microchip/at91-cosino.dtsi diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts similarity index 100% rename from arch/arm/boot/dts/at91-cosino_mega2560.dts rename to arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts diff --git a/arch/arm/boot/dts/at91-dvk_som60.dts b/arch/arm/boot/dts/microchip/at91-dvk_som60.dts similarity index 100% rename from arch/arm/boot/dts/at91-dvk_som60.dts rename to arch/arm/boot/dts/microchip/at91-dvk_som60.dts diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-dvk_su60_somc.dtsi rename to arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi rename to arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/microchip/at91-foxg20.dts similarity index 100% rename from arch/arm/boot/dts/at91-foxg20.dts rename to arch/arm/boot/dts/microchip/at91-foxg20.dts diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/microchip/at91-gatwick.dts similarity index 100% rename from arch/arm/boot/dts/at91-gatwick.dts rename to arch/arm/boot/dts/microchip/at91-gatwick.dts diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/microchip/at91-kizbox.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizbox.dts rename to arch/arm/boot/dts/microchip/at91-kizbox.dts diff --git a/arch/arm/boot/dts/at91-kizbox2-2.dts b/arch/arm/boot/dts/microchip/at91-kizbox2-2.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizbox2-2.dts rename to arch/arm/boot/dts/microchip/at91-kizbox2-2.dts diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-kizbox2-common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts similarity index 99% rename from arch/arm/boot/dts/at91-kizbox3-hs.dts rename to arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts index 7075df6549e9..fec7269088d1 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts @@ -225,7 +225,7 @@ pinctrl_pio_io_reset: gpio_io_reset { pinmux = ; bias-disable; - drive-open-drain = <1>; + drive-open-drain; output-low; }; pinctrl_pio_input: gpio_input { diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi similarity index 99% rename from arch/arm/boot/dts/at91-kizbox3_common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi index abe27adfa4d6..465664628419 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi @@ -211,7 +211,7 @@ pinmux = , //DATA ; //CLK bias-disable; - drive-open-drain = <1>; + drive-open-drain; }; pinctrl_pwm0 { diff --git a/arch/arm/boot/dts/at91-kizboxmini-base.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-base.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi diff --git a/arch/arm/boot/dts/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-mb.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts diff --git a/arch/arm/boot/dts/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-rd.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/microchip/at91-linea.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-linea.dtsi rename to arch/arm/boot/dts/microchip/at91-linea.dtsi diff --git a/arch/arm/boot/dts/at91-lmu5000.dts b/arch/arm/boot/dts/microchip/at91-lmu5000.dts similarity index 100% rename from arch/arm/boot/dts/at91-lmu5000.dts rename to arch/arm/boot/dts/microchip/at91-lmu5000.dts diff --git a/arch/arm/boot/dts/at91-natte.dtsi b/arch/arm/boot/dts/microchip/at91-natte.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-natte.dtsi rename to arch/arm/boot/dts/microchip/at91-natte.dtsi diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts similarity index 100% rename from arch/arm/boot/dts/at91-nattis-2-natte-2.dts rename to arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/microchip/at91-q5xr5.dts similarity index 100% rename from arch/arm/boot/dts/at91-q5xr5.dts rename to arch/arm/boot/dts/microchip/at91-q5xr5.dts diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts similarity index 99% rename from arch/arm/boot/dts/at91-qil_a9260.dts rename to arch/arm/boot/dts/microchip/at91-qil_a9260.dts index 9d26f9996348..5ccb3c139592 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts @@ -108,7 +108,7 @@ status = "okay"; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9_l9260.dts rename to arch/arm/boot/dts/microchip/at91-sam9_l9260.dts diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9x60_curiosity.dts rename to arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9x60ek.dts rename to arch/arm/boot/dts/microchip/at91-sam9x60ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_som1.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts similarity index 99% rename from arch/arm/boot/dts/at91-sama5d27_som1_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts index 52ddd0571f1c..d0a6dbd377df 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts @@ -139,7 +139,7 @@ }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d2_icp.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts similarity index 99% rename from arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts index bf1c9ca72a9f..200b20515ab1 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts @@ -204,7 +204,7 @@ }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; input@0 { diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts similarity index 99% rename from arch/arm/boot/dts/at91-sama5d2_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts index 2d53c47d7cc8..6680031387e8 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts @@ -348,7 +348,7 @@ }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_eds.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4ek.dts diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama7g5ek.dts rename to arch/arm/boot/dts/microchip/at91-sama7g5ek.dts diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/microchip/at91-smartkiz.dts similarity index 100% rename from arch/arm/boot/dts/at91-smartkiz.dts rename to arch/arm/boot/dts/microchip/at91-smartkiz.dts diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/microchip/at91-som60.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-som60.dtsi rename to arch/arm/boot/dts/microchip/at91-som60.dtsi diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/microchip/at91-tse850-3.dts similarity index 78% rename from arch/arm/boot/dts/at91-tse850-3.dts rename to arch/arm/boot/dts/microchip/at91-tse850-3.dts index b99a4fb44a36..9d58a3931207 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/microchip/at91-tse850-3.dts @@ -300,3 +300,63 @@ dmas = <0>, <0>; /* Do not use DMA for dbgu */ }; + +&pioA { + gpio-line-names = + /* 0 */ "SUP-A", "SUP-B", "SUP-C", "SIGLIN", + /* 28 */ "RXD", "TXD", "BRX", "BTX"; +}; + +&pioC { + gpio-line-names = + /* 0 */ "ETX0", "ETX1", "ERX0", "ERX1", + /* 4 */ "ETXEN", "ECRSDV", "ERXER", "EREFCK", + /* 8 */ "EMDC", "EMDIO", "", "", + /* 12 */ "", "", "", "/ILIM", + /* 16 */ "BCK", "LRCK", "DIN", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "VBUS"; +}; + +&pioD { + gpio-line-names = + /* 0 */ "I1", "I2", "O1", "EXTVEN", + /* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL", + /* 8 */ "STEREO", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", ">LIN", "LIN>", "", + /* 20 */ "VREFEN", "", "", "", + /* 24 */ "", "", "VINOK", "", + /* 28 */ "POEOK", "USBON", "POELOAD", ""; +}; + +&pioE { + gpio-line-names = + /* 0 */ "", "", "", "", + /* 4 */ "", "", "", "", + /* 8 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "ALE", "CLE", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "/ETHINT"; +}; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts similarity index 100% rename from arch/arm/boot/dts/at91-vinco.dts rename to arch/arm/boot/dts/microchip/at91-vinco.dts diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/microchip/at91-wb45n.dts similarity index 100% rename from arch/arm/boot/dts/at91-wb45n.dts rename to arch/arm/boot/dts/microchip/at91-wb45n.dts diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/microchip/at91-wb45n.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-wb45n.dtsi rename to arch/arm/boot/dts/microchip/at91-wb45n.dtsi diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/microchip/at91-wb50n.dts similarity index 100% rename from arch/arm/boot/dts/at91-wb50n.dts rename to arch/arm/boot/dts/microchip/at91-wb50n.dts diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/microchip/at91-wb50n.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-wb50n.dtsi rename to arch/arm/boot/dts/microchip/at91-wb50n.dtsi diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi similarity index 99% rename from arch/arm/boot/dts/at91rm9200.dtsi rename to arch/arm/boot/dts/microchip/at91rm9200.dtsi index 6f9004ebf424..37b500f6f395 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -102,7 +102,7 @@ reg = <0xffffff00 0x100>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi similarity index 100% rename from arch/arm/boot/dts/at91rm9200_pqfp.dtsi rename to arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts similarity index 100% rename from arch/arm/boot/dts/at91rm9200ek.dts rename to arch/arm/boot/dts/microchip/at91rm9200ek.dts diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9260.dtsi rename to arch/arm/boot/dts/microchip/at91sam9260.dtsi index 789fe356dbf6..35a007365b6a 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -115,7 +115,7 @@ reg = <0xffffee00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9260-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -130,7 +130,7 @@ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/microchip/at91sam9260ek.dts similarity index 99% rename from arch/arm/boot/dts/at91sam9260ek.dts rename to arch/arm/boot/dts/microchip/at91sam9260ek.dts index bb72f050a4fe..720c15472c4a 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9260ek.dts @@ -112,7 +112,7 @@ }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9261.dtsi rename to arch/arm/boot/dts/microchip/at91sam9261.dtsi index ee0bd1aceb3f..528ffc6f6f96 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -599,7 +599,7 @@ }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9261-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -614,7 +614,7 @@ clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/microchip/at91sam9261ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9261ek.dts rename to arch/arm/boot/dts/microchip/at91sam9261ek.dts diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9263.dtsi rename to arch/arm/boot/dts/microchip/at91sam9263.dtsi index 3ce9ea987312..75d8ff2d12c8 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi @@ -101,7 +101,7 @@ atmel,external-irqs = <30 31>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9263-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -158,7 +158,7 @@ clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9263ek.dts rename to arch/arm/boot/dts/microchip/at91sam9263ek.dts diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/microchip/at91sam9g15.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g15.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g15.dtsi diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/microchip/at91sam9g15ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g15ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g15ek.dts diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20.dtsi similarity index 96% rename from arch/arm/boot/dts/at91sam9g20.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g20.dtsi index 708e1646b7f4..738a43ffd228 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g20.dtsi @@ -41,7 +41,7 @@ atmel,adc-startup-time = <40>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g20ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g20ek.dts diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g20ek_2mmc.dts rename to arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9g20ek_common.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi index 024af2db638e..565b99e79c52 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi @@ -126,7 +126,7 @@ }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts rename to arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/microchip/at91sam9g25.dtsi similarity index 95% rename from arch/arm/boot/dts/at91sam9g25.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g25.dtsi index d2f13afb35ea..ec3c77221881 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g25.dtsi @@ -26,7 +26,7 @@ >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/microchip/at91sam9g25ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g25ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g25ek.dts diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/microchip/at91sam9g35.dtsi similarity index 95% rename from arch/arm/boot/dts/at91sam9g35.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g35.dtsi index 48c2bc4a7753..c9cfb93092ee 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g35.dtsi @@ -25,7 +25,7 @@ >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/microchip/at91sam9g35ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g35ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g35ek.dts diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9g45.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g45.dtsi index 95f5d76234db..7cccc606e36c 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -129,7 +129,7 @@ reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -152,7 +152,7 @@ }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9rl-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; @@ -923,7 +923,7 @@ status = "disabled"; }; - clk32k: sckc@fffffd50 { + clk32k: clock-controller@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9m10g45ek.dts rename to arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi similarity index 97% rename from arch/arm/boot/dts/at91sam9n12.dtsi rename to arch/arm/boot/dts/microchip/at91sam9n12.dtsi index 83114d26f10d..8dc04e9031a6 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi @@ -118,7 +118,7 @@ reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; #clock-cells = <2>; @@ -140,34 +140,17 @@ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - shdwc@fffffe10 { + poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; }; - sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; mmc0: mmc@f0008000 { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9n12ek.dts rename to arch/arm/boot/dts/microchip/at91sam9n12ek.dts diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9rl.dtsi rename to arch/arm/boot/dts/microchip/at91sam9rl.dtsi index 364a2ff0a763..3d089ffbe162 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi @@ -763,7 +763,7 @@ }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9rl-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -778,7 +778,7 @@ clocks = <&clk32k>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; @@ -799,7 +799,7 @@ status = "disabled"; }; - clk32k: sckc@fffffd50 { + clk32k: clock-controller@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/microchip/at91sam9rlek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9rlek.dts rename to arch/arm/boot/dts/microchip/at91sam9rlek.dts diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/microchip/at91sam9x25.dtsi similarity index 96% rename from arch/arm/boot/dts/at91sam9x25.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x25.dtsi index 0fe8802e1242..7036f5f04571 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x25.dtsi @@ -27,7 +27,7 @@ >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/microchip/at91sam9x25ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9x25ek.dts rename to arch/arm/boot/dts/microchip/at91sam9x25ek.dts diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/microchip/at91sam9x35.dtsi similarity index 95% rename from arch/arm/boot/dts/at91sam9x35.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x35.dtsi index 0bfa21f18f87..eb03b0497e37 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x35.dtsi @@ -26,7 +26,7 @@ >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/microchip/at91sam9x35ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9x35ek.dts rename to arch/arm/boot/dts/microchip/at91sam9x35ek.dts diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi similarity index 99% rename from arch/arm/boot/dts/at91sam9x5.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5.dtsi index 0c26c925761b..a1fed912f2ee 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -126,7 +126,7 @@ reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x5-pmc", "syscon"; reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -141,7 +141,7 @@ clocks = <&clk32k>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -154,7 +154,7 @@ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_can.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_isi.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_lcd.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_macb0.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_macb1.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_usart3.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5cm.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5dm.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5ek.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/microchip/at91sam9xe.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9xe.dtsi rename to arch/arm/boot/dts/microchip/at91sam9xe.dtsi diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/microchip/ethernut5.dts similarity index 100% rename from arch/arm/boot/dts/ethernut5.dts rename to arch/arm/boot/dts/microchip/ethernut5.dts diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/microchip/evk-pro3.dts similarity index 100% rename from arch/arm/boot/dts/evk-pro3.dts rename to arch/arm/boot/dts/microchip/evk-pro3.dts diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/microchip/ge863-pro3.dtsi similarity index 100% rename from arch/arm/boot/dts/ge863-pro3.dtsi rename to arch/arm/boot/dts/microchip/ge863-pro3.dtsi diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts similarity index 86% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts index 5feef9a59a79..ad5d8b56e6fa 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts +++ b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -15,10 +15,12 @@ &mdio0 { phy2: ethernet-phy@3 { reg = <3>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; }; phy3: ethernet-phy@4 { reg = <4>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi similarity index 83% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi index 0097e72e3fb2..426893750d51 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -18,6 +18,8 @@ gpio-restart { compatible = "gpio-restart"; + pinctrl-0 = <&reset_pins>; + pinctrl-names = "default"; gpios = <&gpio 56 GPIO_ACTIVE_LOW>; priority = <200>; }; @@ -39,7 +41,7 @@ status = "okay"; spi3: spi@400 { - pinctrl-0 = <&fc3_b_pins>; + pinctrl-0 = <&fc3_b_pins>, <&spi3_cs_pins>; pinctrl-names = "default"; status = "okay"; cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; @@ -47,6 +49,9 @@ }; &gpio { + pinctrl-0 = <&phy_int_pins>; + pinctrl-names = "default"; + fc3_b_pins: fc3-b-pins { /* SCK, MISO, MOSI */ pins = "GPIO_51", "GPIO_52", "GPIO_53"; @@ -59,6 +64,18 @@ function = "miim_c"; }; + phy_int_pins: phy-int-pins { + /* PHY_INT# */ + pins = "GPIO_24"; + function = "gpio"; + }; + + reset_pins: reset-pins { + /* SYS_RST# */ + pins = "GPIO_56"; + function = "gpio"; + }; + sgpio_a_pins: sgpio-a-pins { /* SCK, D0, D1 */ pins = "GPIO_32", "GPIO_33", "GPIO_34"; @@ -71,6 +88,12 @@ function = "sgpio_b"; }; + spi3_cs_pins: spi3-cs-pins { + /* CS# */ + pins = "GPIO_46"; + function = "gpio"; + }; + usart0_pins: usart0-pins { /* RXD, TXD */ pins = "GPIO_25", "GPIO_26"; @@ -93,21 +116,25 @@ phy4: ethernet-phy@5 { reg = <5>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy5: ethernet-phy@6 { reg = <6>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy6: ethernet-phy@7 { reg = <7>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy7: ethernet-phy@8 { reg = <8>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; }; diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-pcb8290.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8290.dts diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-pcb8291.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8291.dts diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts similarity index 93% rename from arch/arm/boot/dts/lan966x-pcb8309.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8309.dts index c436cd20d4b4..0cb505f79ba1 100644 --- a/arch/arm/boot/dts/lan966x-pcb8309.dts +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts @@ -144,6 +144,18 @@ function = "fc4_b"; }; + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_39"; + function = "ptpsync_4"; + }; + sgpio_a_pins: sgpio-a-pins { /* SCK, D0, D1, LD */ pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; @@ -212,5 +224,7 @@ }; &switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/microchip/lan966x.dtsi similarity index 100% rename from arch/arm/boot/dts/lan966x.dtsi rename to arch/arm/boot/dts/microchip/lan966x.dtsi diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/microchip/mpa1600.dts similarity index 100% rename from arch/arm/boot/dts/mpa1600.dts rename to arch/arm/boot/dts/microchip/mpa1600.dts diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/microchip/pm9g45.dts similarity index 100% rename from arch/arm/boot/dts/pm9g45.dts rename to arch/arm/boot/dts/microchip/pm9g45.dts diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi similarity index 99% rename from arch/arm/boot/dts/sam9x60.dtsi rename to arch/arm/boot/dts/microchip/sam9x60.dtsi index e67ede940071..8b53997675e7 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -1282,7 +1282,7 @@ }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "microchip,sam9x60-pmc", "syscon"; reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1297,7 +1297,7 @@ clocks = <&clk32k 0>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "microchip,sam9x60-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k 0>; @@ -1322,7 +1322,7 @@ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "microchip,sam9x60-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/sama5d2-pinfunc.h rename to arch/arm/boot/dts/microchip/sama5d2-pinfunc.h diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi similarity index 99% rename from arch/arm/boot/dts/sama5d2.dtsi rename to arch/arm/boot/dts/microchip/sama5d2.dtsi index 14c35c12a115..daeeb24e5f4d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -284,7 +284,7 @@ clock-names = "dma_clk"; }; - pmc: pmc@f0014000 { + pmc: clock-controller@f0014000 { compatible = "atmel,sama5d2-pmc", "syscon"; reg = <0xf0014000 0x160>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; @@ -680,7 +680,7 @@ clocks = <&clk32k>; }; - shutdown_controller: shdwc@f8048010 { + shutdown_controller: poweroff@f8048010 { compatible = "atmel,sama5d2-shdwc"; reg = <0xf8048010 0x10>; clocks = <&clk32k>; @@ -704,10 +704,9 @@ status = "disabled"; }; - clk32k: sckc@f8048050 { + clk32k: clock-controller@f8048050 { compatible = "atmel,sama5d4-sckc"; reg = <0xf8048050 0x4>; - clocks = <&slow_xtal>; #clock-cells = <0>; }; diff --git a/arch/arm/boot/dts/sama5d29.dtsi b/arch/arm/boot/dts/microchip/sama5d29.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d29.dtsi rename to arch/arm/boot/dts/microchip/sama5d29.dtsi diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi similarity index 99% rename from arch/arm/boot/dts/sama5d3.dtsi rename to arch/arm/boot/dts/microchip/sama5d3.dtsi index bde8e92d60bb..d9e66700d1c2 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -1001,7 +1001,7 @@ }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,sama5d3-pmc", "syscon"; reg = <0xfffffc00 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1016,7 +1016,7 @@ clocks = <&clk32k>; }; - shutdown_controller: shutdown-controller@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -1040,7 +1040,7 @@ status = "disabled"; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,sama5d3-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/microchip/sama5d31.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d31.dtsi rename to arch/arm/boot/dts/microchip/sama5d31.dtsi diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/microchip/sama5d31ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d31ek.dts rename to arch/arm/boot/dts/microchip/sama5d31ek.dts diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/microchip/sama5d33.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d33.dtsi rename to arch/arm/boot/dts/microchip/sama5d33.dtsi diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/microchip/sama5d33ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d33ek.dts rename to arch/arm/boot/dts/microchip/sama5d33ek.dts diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/microchip/sama5d34.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d34.dtsi rename to arch/arm/boot/dts/microchip/sama5d34.dtsi diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/microchip/sama5d34ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d34ek.dts rename to arch/arm/boot/dts/microchip/sama5d34ek.dts diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/microchip/sama5d35.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d35.dtsi rename to arch/arm/boot/dts/microchip/sama5d35.dtsi diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/microchip/sama5d35ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d35ek.dts rename to arch/arm/boot/dts/microchip/sama5d35ek.dts diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/microchip/sama5d36.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d36.dtsi rename to arch/arm/boot/dts/microchip/sama5d36.dtsi diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/microchip/sama5d36ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d36ek.dts rename to arch/arm/boot/dts/microchip/sama5d36ek.dts diff --git a/arch/arm/boot/dts/sama5d36ek_cmp.dts b/arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts similarity index 100% rename from arch/arm/boot/dts/sama5d36ek_cmp.dts rename to arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_can.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_can.dtsi diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi similarity index 98% rename from arch/arm/boot/dts/sama5d3_emac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_emac.dtsi index 45226108850d..5d7ce13de8cc 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi @@ -30,7 +30,7 @@ }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { }; macb1: ethernet@f802c000 { diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_gmac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_lcd.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_mci2.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_tcb1.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/microchip/sama5d3_uart.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_uart.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_uart.dtsi diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xcm.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xcm.dtsi diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xcm_cmp.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xdm.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xdm.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xdm.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_cmp.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_emac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_gmac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi similarity index 99% rename from arch/arm/boot/dts/sama5d4.dtsi rename to arch/arm/boot/dts/microchip/sama5d4.dtsi index af62157ae214..41284e013f53 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -250,7 +250,7 @@ clock-names = "dma_clk"; }; - pmc: pmc@f0018000 { + pmc: clock-controller@f0018000 { compatible = "atmel,sama5d4-pmc", "syscon"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -740,7 +740,7 @@ clocks = <&clk32k>; }; - shutdown_controller: shdwc@fc068610 { + shutdown_controller: poweroff@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; clocks = <&clk32k>; @@ -761,7 +761,7 @@ status = "disabled"; }; - clk32k: sckc@fc068650 { + clk32k: clock-controller@fc068650 { compatible = "atmel,sama5d4-sckc"; reg = <0xfc068650 0x4>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/sama7g5-pinfunc.h rename to arch/arm/boot/dts/microchip/sama7g5-pinfunc.h diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi similarity index 99% rename from arch/arm/boot/dts/sama7g5.dtsi rename to arch/arm/boot/dts/microchip/sama7g5.dtsi index 929ba73702e9..9642a42d84e6 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -241,7 +241,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; }; - pmc: pmc@e0018000 { + pmc: clock-controller@e0018000 { compatible = "microchip,sama7g5-pmc", "syscon"; reg = <0xe0018000 0x200>; interrupts = ; @@ -257,7 +257,7 @@ clocks = <&clk32k 0>; }; - shdwc: shdwc@e001d010 { + shdwc: poweroff@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/microchip/tny_a9260.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9260.dts rename to arch/arm/boot/dts/microchip/tny_a9260.dts diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi similarity index 100% rename from arch/arm/boot/dts/tny_a9260_common.dtsi rename to arch/arm/boot/dts/microchip/tny_a9260_common.dtsi diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9263.dts rename to arch/arm/boot/dts/microchip/tny_a9263.dts diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/microchip/tny_a9g20.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9g20.dts rename to arch/arm/boot/dts/microchip/tny_a9g20.dts diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts similarity index 95% rename from arch/arm/boot/dts/usb_a9260.dts rename to arch/arm/boot/dts/microchip/usb_a9260.dts index 6cfa83921ac2..66f8da89007d 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -22,7 +22,7 @@ ahb { apb { - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9260_common.dtsi rename to arch/arm/boot/dts/microchip/usb_a9260_common.dtsi diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts similarity index 99% rename from arch/arm/boot/dts/usb_a9263.dts rename to arch/arm/boot/dts/microchip/usb_a9263.dts index b6cb9cdf8197..45745915b2e1 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -67,7 +67,7 @@ }; }; - shdwc@fffffd10 { + poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi rename to arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9g20.dts rename to arch/arm/boot/dts/microchip/usb_a9g20.dts diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9g20_common.dtsi rename to arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9g20_lpw.dts rename to arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts diff --git a/arch/arm/boot/dts/moxa/Makefile b/arch/arm/boot/dts/moxa/Makefile new file mode 100644 index 000000000000..d61ce8d4e732 --- /dev/null +++ b/arch/arm/boot/dts/moxa/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MOXART) += \ + moxart-uc7112lx.dtb diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxa/moxart-uc7112lx.dts similarity index 100% rename from arch/arm/boot/dts/moxart-uc7112lx.dts rename to arch/arm/boot/dts/moxa/moxart-uc7112lx.dts diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxa/moxart.dtsi similarity index 100% rename from arch/arm/boot/dts/moxart.dtsi rename to arch/arm/boot/dts/moxa/moxart.dtsi diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi deleted file mode 100644 index d304b62d24b5..000000000000 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623.dtsi" - -&afe { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&crypto { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; -}; - -ð { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; -}; - -&nandc { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&pcie { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&scpsys { - compatible = "mediatek,mt7623a-scpsys"; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "ethif"; -}; - -&usb0 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&usb2 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; diff --git a/arch/arm/boot/dts/nspire/Makefile b/arch/arm/boot/dts/nspire/Makefile new file mode 100644 index 000000000000..82a2515bdd46 --- /dev/null +++ b/arch/arm/boot/dts/nspire/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NSPIRE) += \ + nspire-cx.dtb \ + nspire-tp.dtb \ + nspire-clp.dtb diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi similarity index 100% rename from arch/arm/boot/dts/nspire-classic.dtsi rename to arch/arm/boot/dts/nspire/nspire-classic.dtsi diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire/nspire-clp.dts similarity index 100% rename from arch/arm/boot/dts/nspire-clp.dts rename to arch/arm/boot/dts/nspire/nspire-clp.dts diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts similarity index 100% rename from arch/arm/boot/dts/nspire-cx.dts rename to arch/arm/boot/dts/nspire/nspire-cx.dts diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire/nspire-tp.dts similarity index 100% rename from arch/arm/boot/dts/nspire-tp.dts rename to arch/arm/boot/dts/nspire/nspire-tp.dts diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi similarity index 100% rename from arch/arm/boot/dts/nspire.dtsi rename to arch/arm/boot/dts/nspire/nspire.dtsi diff --git a/arch/arm/boot/dts/nuvoton/Makefile b/arch/arm/boot/dts/nuvoton/Makefile new file mode 100644 index 000000000000..89c157dad312 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NPCM7XX) += \ + nuvoton-npcm730-gsj.dtb \ + nuvoton-npcm730-gbs.dtb \ + nuvoton-npcm730-kudo.dtb \ + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm750-runbmc-olympus.dtb +dtb-$(CONFIG_ARCH_WPCM450) += \ + nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gbs.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gsj.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-kudo.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-evb.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-wpcm450.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile new file mode 100644 index 000000000000..60091bf7e48b --- /dev/null +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ + tegra114-dalmore.dtb \ + tegra114-roth.dtb \ + tegra114-tn7.dtb +dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ + tegra124-apalis-eval.dtb \ + tegra124-apalis-v1.2-eval.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ + tegra124-nyan-blaze.dtb \ + tegra124-venice2.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ + tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ + tegra20-harmony.dtb \ + tegra20-colibri-eval-v3.dtb \ + tegra20-colibri-iris.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ + tegra30-apalis-eval.dtb \ + tegra30-apalis-v1.1-eval.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu-a02.dtb \ + tegra30-cardhu-a04.dtb \ + tegra30-colibri-eval-v3.dtb \ + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-asus-tf701t.dts rename to arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-dalmore.dts rename to arch/arm/boot/dts/nvidia/tegra114-dalmore.dts diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/nvidia/tegra114-roth.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-roth.dts rename to arch/arm/boot/dts/nvidia/tegra114-roth.dts diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-tn7.dts rename to arch/arm/boot/dts/nvidia/tegra114-tn7.dts diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra114.dtsi rename to arch/arm/boot/dts/nvidia/tegra114.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-eval.dts rename to arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts rename to arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-jetson-tk1.dts rename to arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big-fhd.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-blaze.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi similarity index 99% rename from arch/arm/boot/dts/tegra124-nyan.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index 56952333ae28..0c35ca2e9121 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -833,4 +833,4 @@ }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts similarity index 99% rename from arch/arm/boot/dts/tegra124-venice2.dts rename to arch/arm/boot/dts/nvidia/tegra124-venice2.dts index 7e739879c00c..c697301c443c 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -1253,4 +1253,4 @@ }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124.dtsi rename to arch/arm/boot/dts/nvidia/tegra124.dtsi diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-acer-a500-picasso.dts rename to arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-asus-tf101.dts rename to arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri-eval-v3.dts rename to arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri-iris.dts rename to arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-cpu-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-harmony.dts rename to arch/arm/boot/dts/nvidia/tegra20-harmony.dts diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-medcom-wide.dts rename to arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-paz00.dts rename to arch/arm/boot/dts/nvidia/tegra20-paz00.dts diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/nvidia/tegra20-plutux.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-plutux.dts rename to arch/arm/boot/dts/nvidia/tegra20-plutux.dts diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-seaboard.dts rename to arch/arm/boot/dts/nvidia/tegra20-seaboard.dts diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-tamonten.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/nvidia/tegra20-tec.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-tec.dts rename to arch/arm/boot/dts/nvidia/tegra20-tec.dts diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-trimslice.dts rename to arch/arm/boot/dts/nvidia/tegra20-trimslice.dts diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-ventana.dts rename to arch/arm/boot/dts/nvidia/tegra20-ventana.dts diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20.dtsi rename to arch/arm/boot/dts/nvidia/tegra20.dtsi diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-eval.dts rename to arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts rename to arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf201.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf300t.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf300tg.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf700t.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-beaver.dts rename to arch/arm/boot/dts/nvidia/tegra30-beaver.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu-a02.dts rename to arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu-a04.dts rename to arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-colibri-eval-v3.dts rename to arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-colibri.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cpu-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-ouya.dts rename to arch/arm/boot/dts/nvidia/tegra30-ouya.dts diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-pegatron-chagall.dts rename to arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30.dtsi rename to arch/arm/boot/dts/nvidia/tegra30.dtsi diff --git a/arch/arm/boot/dts/nxp/Makefile b/arch/arm/boot/dts/nxp/Makefile new file mode 100644 index 000000000000..db44e7a0a198 --- /dev/null +++ b/arch/arm/boot/dts/nxp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += imx +subdir-y += lpc +subdir-y += ls +subdir-y += mxs +subdir-y += vf diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile new file mode 100644 index 000000000000..3629e343d322 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -0,0 +1,388 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_IMX1) += \ + imx1-ads.dtb \ + imx1-apf9328.dtb +dtb-$(CONFIG_SOC_IMX25) += \ + imx25-eukrea-mbimxsd25-baseboard.dtb \ + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ + imx25-karo-tx25.dtb \ + imx25-pdk.dtb +dtb-$(CONFIG_SOC_IMX27) += \ + imx27-apf27.dtb \ + imx27-apf27dev.dtb \ + imx27-eukrea-mbimxsd27-baseboard.dtb \ + imx27-pdk.dtb \ + imx27-phytec-phycore-rdk.dtb \ + imx27-phytec-phycard-s-rdk.dtb +dtb-$(CONFIG_SOC_IMX31) += \ + imx31-bug.dtb \ + imx31-lite.dtb +dtb-$(CONFIG_SOC_IMX35) += \ + imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-pdk.dtb +dtb-$(CONFIG_SOC_IMX50) += \ + imx50-evk.dtb \ + imx50-kobo-aura.dtb +dtb-$(CONFIG_SOC_IMX51) += \ + imx51-apf51.dtb \ + imx51-apf51dev.dtb \ + imx51-babbage.dtb \ + imx51-digi-connectcore-jsk.dtb \ + imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-ts4800.dtb \ + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb +dtb-$(CONFIG_SOC_IMX53) += \ + imx53-ard.dtb \ + imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ + imx53-m53evk.dtb \ + imx53-m53menlo.dtb \ + imx53-mba53.dtb \ + imx53-ppd.dtb \ + imx53-qsb.dtb \ + imx53-qsrb.dtb \ + imx53-sk-imx53.dtb \ + imx53-smd.dtb \ + imx53-tx53-x03x.dtb \ + imx53-tx53-x13x.dtb \ + imx53-usbarmory.dtb \ + imx53-voipac-bsb.dtb +dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ + imx6dl-apf6dev.dtb \ + imx6dl-aristainetos_4.dtb \ + imx6dl-aristainetos_7.dtb \ + imx6dl-aristainetos2_4.dtb \ + imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ + imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ + imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ + imx6dl-dfi-fs700-m60.dtb \ + imx6dl-dhcom-picoitx.dtb \ + imx6dl-eckelmann-ci4x10.dtb \ + imx6dl-emcon-avari.dtb \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-gw551x.dtb \ + imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ + imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ + imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ + imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ + imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ + imx6dl-nit6xlite.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-mira-rdk-nand.dtb \ + imx6dl-phytec-pbab01.dtb \ + imx6dl-pico-dwarf.dtb \ + imx6dl-pico-hobbit.dtb \ + imx6dl-pico-nymph.dtb \ + imx6dl-pico-pi.dtb \ + imx6dl-plybas.dtb \ + imx6dl-plym2m.dtb \ + imx6dl-prtmvt.dtb \ + imx6dl-prtrvt.dtb \ + imx6dl-prtvt7.dtb \ + imx6dl-rex-basic.dtb \ + imx6dl-riotboard.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabrelite.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-savageboard.dtb \ + imx6dl-skov-revc-lt2.dtb \ + imx6dl-skov-revc-lt6.dtb \ + imx6dl-solidsense.dtb \ + imx6dl-ts4900.dtb \ + imx6dl-ts7970.dtb \ + imx6dl-tx6dl-comtft.dtb \ + imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8034-mb7.dtb \ + imx6dl-tx6s-8035.dtb \ + imx6dl-tx6s-8035-mb7.dtb \ + imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-80xx-mb7.dtb \ + imx6dl-tx6u-8033.dtb \ + imx6dl-tx6u-8033-mb7.dtb \ + imx6dl-tx6u-811x.dtb \ + imx6dl-tx6u-81xx-mb7.dtb \ + imx6dl-udoo.dtb \ + imx6dl-victgo.dtb \ + imx6dl-vicut1.dtb \ + imx6dl-wandboard.dtb \ + imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ + imx6dl-yapp4-draco.dtb \ + imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-lynx.dtb \ + imx6dl-yapp4-orion.dtb \ + imx6dl-yapp4-phoenix.dtb \ + imx6dl-yapp4-ursa.dtb \ + imx6q-apalis-eval.dtb \ + imx6q-apalis-ixora.dtb \ + imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ + imx6q-apf6dev.dtb \ + imx6q-arm2.dtb \ + imx6q-b450v3.dtb \ + imx6q-b650v3.dtb \ + imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ + imx6q-cm-fx6.dtb \ + imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ + imx6q-dfi-fs700-m60.dtb \ + imx6q-dhcom-pdk2.dtb \ + imx6q-display5-tianma-tm070-1280x768.dtb \ + imx6q-dmo-edmqmx6.dtb \ + imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ + imx6q-emcon-avari.dtb \ + imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ + imx6q-gk802.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw5400-a.dtb \ + imx6q-gw54xx.dtb \ + imx6q-gw551x.dtb \ + imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ + imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ + imx6q-icore.dtb \ + imx6q-icore-mipi.dtb \ + imx6q-icore-ofcap10.dtb \ + imx6q-icore-ofcap12.dtb \ + imx6q-icore-rqs.dtb \ + imx6q-kp-tpc.dtb \ + imx6q-logicpd.dtb \ + imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ + imx6q-mccmon6.dtb \ + imx6q-nitrogen6x.dtb \ + imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_som2.dtb \ + imx6q-novena.dtb \ + imx6q-phytec-mira-rdk-emmc.dtb \ + imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-phytec-pbab01.dtb \ + imx6q-pico-dwarf.dtb \ + imx6q-pico-hobbit.dtb \ + imx6q-pico-nymph.dtb \ + imx6q-pico-pi.dtb \ + imx6q-pistachio.dtb \ + imx6q-prti6q.dtb \ + imx6q-prtwd2.dtb \ + imx6q-rex-pro.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb \ + imx6q-savageboard.dtb \ + imx6q-sbc6x.dtb \ + imx6q-skov-revc-lt2.dtb \ + imx6q-skov-revc-lt6.dtb \ + imx6q-skov-reve-mi1010ait-1cp1.dtb \ + imx6q-solidsense.dtb \ + imx6q-tbs2910.dtb \ + imx6q-ts4900.dtb \ + imx6q-ts7970.dtb \ + imx6q-tx6q-1010.dtb \ + imx6q-tx6q-1010-comtft.dtb \ + imx6q-tx6q-1020.dtb \ + imx6q-tx6q-1020-comtft.dtb \ + imx6q-tx6q-1036.dtb \ + imx6q-tx6q-1036-mb7.dtb \ + imx6q-tx6q-10x0-mb7.dtb \ + imx6q-tx6q-1110.dtb \ + imx6q-tx6q-11x0-mb7.dtb \ + imx6q-udoo.dtb \ + imx6q-utilite-pro.dtb \ + imx6q-var-dt6customboard.dtb \ + imx6q-vicut1.dtb \ + imx6q-wandboard.dtb \ + imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ + imx6q-yapp4-pegasus.dtb \ + imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ + imx6qp-nitrogen6_max.dtb \ + imx6qp-nitrogen6_som2.dtb \ + imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ + imx6qp-sabreauto.dtb \ + imx6qp-sabresd.dtb \ + imx6qp-tx6qp-8037.dtb \ + imx6qp-tx6qp-8037-mb7.dtb \ + imx6qp-tx6qp-8137.dtb \ + imx6qp-tx6qp-8137-mb7.dtb \ + imx6qp-vicutp.dtb \ + imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ + imx6qp-yapp4-pegasus-plus.dtb \ + imx6qp-zii-rdu2.dtb \ + imx6s-dhcom-drc02.dtb +dtb-$(CONFIG_SOC_IMX6SL) += \ + imx6sl-evk.dtb \ + imx6sl-kobo-aura2.dtb \ + imx6sl-tolino-shine2hd.dtb \ + imx6sl-tolino-shine3.dtb \ + imx6sl-tolino-vision.dtb \ + imx6sl-tolino-vision5.dtb \ + imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb \ + imx6sll-kobo-clarahd.dtb \ + imx6sll-kobo-librah2o.dtb +dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-nitrogen6sx.dtb \ + imx6sx-sabreauto.dtb \ + imx6sx-sdb-reva.dtb \ + imx6sx-sdb-sai.dtb \ + imx6sx-sdb.dtb \ + imx6sx-sdb-mqs.dtb \ + imx6sx-softing-vining-2000.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ + imx6ul-ccimx6ulsbcpro.dtb \ + imx6ul-geam.dtb \ + imx6ul-isiot-emmc.dtb \ + imx6ul-isiot-nand.dtb \ + imx6ul-kontron-bl.dtb \ + imx6ul-kontron-bl-43.dtb \ + imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ + imx6ul-opos6uldev.dtb \ + imx6ul-pico-dwarf.dtb \ + imx6ul-pico-hobbit.dtb \ + imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ + imx6ul-phytec-segin-ff-rdk-nand.dtb \ + imx6ul-prti6g.dtb \ + imx6ul-tx6ul-0010.dtb \ + imx6ul-tx6ul-0011.dtb \ + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ + imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ + imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ + imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-dhcom-drc02.dtb \ + imx6ull-dhcom-pdk2.dtb \ + imx6ull-dhcom-picoitx.dtb \ + imx6ull-dhcor-maveo-box.dtb \ + imx6ull-jozacp.dtb \ + imx6ull-kontron-bl.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-opos6uldev.dtb \ + imx6ull-phytec-segin-ff-rdk-nand.dtb \ + imx6ull-phytec-segin-ff-rdk-emmc.dtb \ + imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tarragon-master.dtb \ + imx6ull-tarragon-micro.dtb \ + imx6ull-tarragon-slave.dtb \ + imx6ull-tarragon-slavext.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb +dtb-$(CONFIG_SOC_IMX7D) += \ + imx7d-cl-som-imx7.dtb \ + imx7d-colibri-aster.dtb \ + imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ + imx7d-colibri-eval-v3.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ + imx7d-mba7.dtb \ + imx7d-meerkat96.dtb \ + imx7d-nitrogen7.dtb \ + imx7d-pico-dwarf.dtb \ + imx7d-pico-hobbit.dtb \ + imx7d-pico-nymph.dtb \ + imx7d-pico-pi.dtb \ + imx7d-remarkable2.dtb \ + imx7d-sbc-imx7.dtb \ + imx7d-sdb.dtb \ + imx7d-sdb-reva.dtb \ + imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ + imx7d-zii-rmu2.dtb \ + imx7d-zii-rpu2.dtb \ + imx7s-colibri-aster.dtb \ + imx7s-colibri-eval-v3.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ + imx7s-mba7.dtb \ + imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-com.dtb \ + imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi similarity index 100% rename from arch/arm/boot/dts/e60k02.dtsi rename to arch/arm/boot/dts/nxp/imx/e60k02.dtsi diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi similarity index 100% rename from arch/arm/boot/dts/e70k02.dtsi rename to arch/arm/boot/dts/nxp/imx/e70k02.dtsi diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts similarity index 100% rename from arch/arm/boot/dts/imx1-ads.dts rename to arch/arm/boot/dts/nxp/imx/imx1-ads.dts diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts similarity index 100% rename from arch/arm/boot/dts/imx1-apf9328.dts rename to arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx1-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx1.dtsi diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts similarity index 100% rename from arch/arm/boot/dts/imx25-karo-tx25.dts rename to arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx25-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx25-pdk.dts diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx25-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi similarity index 100% rename from arch/arm/boot/dts/imx25.dtsi rename to arch/arm/boot/dts/nxp/imx/imx25.dtsi diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts similarity index 100% rename from arch/arm/boot/dts/imx27-apf27.dts rename to arch/arm/boot/dts/nxp/imx/imx27-apf27.dts diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts similarity index 100% rename from arch/arm/boot/dts/imx27-apf27dev.dts rename to arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-pdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx27-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27.dtsi diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts similarity index 100% rename from arch/arm/boot/dts/imx31-bug.dts rename to arch/arm/boot/dts/nxp/imx/imx31-bug.dts diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts similarity index 100% rename from arch/arm/boot/dts/imx31-lite.dts rename to arch/arm/boot/dts/nxp/imx/imx31-lite.dts diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi similarity index 100% rename from arch/arm/boot/dts/imx31.dtsi rename to arch/arm/boot/dts/nxp/imx/imx31.dtsi diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi similarity index 100% rename from arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi rename to arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx35-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx35-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx35-pdk.dts diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx35-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi similarity index 99% rename from arch/arm/boot/dts/imx35.dtsi rename to arch/arm/boot/dts/nxp/imx/imx35.dtsi index d650f54c3fc6..2d20e5541acc 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -298,7 +298,6 @@ compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 74>; - clock-names = ""; interrupts = <55>; }; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx50-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx50-evk.dts diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts similarity index 100% rename from arch/arm/boot/dts/imx50-kobo-aura.dts rename to arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx50-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi similarity index 100% rename from arch/arm/boot/dts/imx50.dtsi rename to arch/arm/boot/dts/nxp/imx/imx50.dtsi diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51.dts similarity index 100% rename from arch/arm/boot/dts/imx51-apf51.dts rename to arch/arm/boot/dts/nxp/imx/imx51-apf51.dts diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts similarity index 100% rename from arch/arm/boot/dts/imx51-apf51dev.dts rename to arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts similarity index 100% rename from arch/arm/boot/dts/imx51-babbage.dts rename to arch/arm/boot/dts/nxp/imx/imx51-babbage.dts diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts similarity index 100% rename from arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts rename to arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx51-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts similarity index 100% rename from arch/arm/boot/dts/imx51-ts4800.dts rename to arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts similarity index 99% rename from arch/arm/boot/dts/imx51-zii-rdu1.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts index e537e06e11d7..5d4b29d76585 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts @@ -145,9 +145,9 @@ pinctrl-0 = <&pinctrl_gpiospi0>; status = "okay"; - gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; @@ -181,7 +181,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rev-mii"; ethernet = <&fec>; fixed-link { diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts similarity index 99% rename from arch/arm/boot/dts/imx51-zii-scu2-mezz.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts index 21dd3f7abd48..625f9ac671ae 100644 --- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts @@ -82,7 +82,7 @@ port@4 { reg = <4>; - label = "cpu"; + phy-mode = "rev-mii"; ethernet = <&fec>; fixed-link { diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts similarity index 99% rename from arch/arm/boot/dts/imx51-zii-scu3-esb.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts index 9f857eb44bf7..19a3b142c964 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts @@ -267,7 +267,6 @@ port@6 { reg = <6>; - label = "cpu"; phy-mode = "mii"; ethernet = <&fec>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51.dtsi diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts similarity index 100% rename from arch/arm/boot/dts/imx53-ard.dts rename to arch/arm/boot/dts/nxp/imx/imx53-ard.dts diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts similarity index 100% rename from arch/arm/boot/dts/imx53-cx9020.dts rename to arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts similarity index 100% rename from arch/arm/boot/dts/imx53-kp-ddc.dts rename to arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts similarity index 100% rename from arch/arm/boot/dts/imx53-kp-hsc.dts rename to arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-kp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-m53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts similarity index 100% rename from arch/arm/boot/dts/imx53-m53evk.dts rename to arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts similarity index 100% rename from arch/arm/boot/dts/imx53-m53menlo.dts rename to arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts similarity index 100% rename from arch/arm/boot/dts/imx53-mba53.dts rename to arch/arm/boot/dts/nxp/imx/imx53-mba53.dts diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx53-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts similarity index 100% rename from arch/arm/boot/dts/imx53-ppd.dts rename to arch/arm/boot/dts/nxp/imx/imx53-ppd.dts diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-qsb-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-qsb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-qsb.dts diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-qsrb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts diff --git a/arch/arm/boot/dts/imx53-sk-imx53.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts similarity index 100% rename from arch/arm/boot/dts/imx53-sk-imx53.dts rename to arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts similarity index 100% rename from arch/arm/boot/dts/imx53-smd.dts rename to arch/arm/boot/dts/nxp/imx/imx53-smd.dts diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi similarity index 99% rename from arch/arm/boot/dts/imx53-tqma53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi index 7e7f9f3b3906..d930739674a1 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi @@ -274,7 +274,7 @@ reg = <0x48>; }; - eeprom: 24c64@50 { + eeprom: eeprom@50 { compatible = "atmel,24c64"; pagesize = <32>; reg = <0x50>; diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts similarity index 100% rename from arch/arm/boot/dts/imx53-tx53-x03x.dts rename to arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts similarity index 100% rename from arch/arm/boot/dts/imx53-tx53-x13x.dts rename to arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-tx53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts similarity index 100% rename from arch/arm/boot/dts/imx53-usbarmory.dts rename to arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-voipac-bsb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53.dtsi diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6-logicpd-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts similarity index 98% rename from arch/arm/boot/dts/imx6dl-alti6p.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts index e6a4e2770640..4989e8d069a1 100644 --- a/arch/arm/boot/dts/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts @@ -361,6 +361,7 @@ pinctrl-0 = <&pinctrl_usbh1>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; @@ -370,9 +371,18 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-apf6dev.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos2_4.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos2_7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos_4.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos_7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b105pv2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b105v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b125pv2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b125v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b155v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-b1x5v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts diff --git a/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-emcon-avari.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw51xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw52xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw53xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw54xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw551x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw552x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw553x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw560x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5903.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5904.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5907.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5910.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5912.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5913.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore-mipi.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore-rqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts diff --git a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts similarity index 99% rename from arch/arm/boot/dts/imx6dl-lanmcu.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts index fa823988312d..7c62db91173b 100644 --- a/arch/arm/boot/dts/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts @@ -257,9 +257,18 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mamoj.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6a.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-nit6xlite.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-nitrogen6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-pbab01.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6dl-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts similarity index 99% rename from arch/arm/boot/dts/imx6dl-plybas.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts index e98046eea7a4..84f34da06267 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts @@ -235,7 +235,7 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts similarity index 96% rename from arch/arm/boot/dts/imx6dl-plym2m.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts index e3c10483f33b..dfa8110b1d97 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts @@ -113,18 +113,42 @@ polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts similarity index 99% rename from arch/arm/boot/dts/imx6dl-prtmvt.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts index 5f4fa796ca18..773a84a5739d 100644 --- a/arch/arm/boot/dts/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts @@ -560,6 +560,7 @@ pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -569,10 +570,18 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts similarity index 98% rename from arch/arm/boot/dts/imx6dl-prtrvt.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts index 56bb1ca56a2d..36b031236e47 100644 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts @@ -124,6 +124,10 @@ status = "disabled"; }; +&usbotg { + disable-over-current; +}; + &vpu { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts similarity index 96% rename from arch/arm/boot/dts/imx6dl-prtvt7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts index a1eb53851794..568e98cb62aa 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts @@ -24,7 +24,7 @@ compatible = "pwm-backlight"; pwms = <&pwm1 0 500000 0>; brightness-levels = <0 20 81 248 1000>; - default-brightness-level = <20>; + default-brightness-level = <65>; num-interpolated-steps = <21>; power-supply = <®_bl_12v0>; }; @@ -246,18 +246,42 @@ polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; @@ -267,8 +291,6 @@ <&adc_ts 5>; io-channel-names = "y", "z1", "z2", "x"; touchscreen-min-pressure = <64687>; - touchscreen-inverted-x; - touchscreen-inverted-y; touchscreen-x-plate-ohms = <300>; touchscreen-y-plate-ohms = <800>; }; diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6dl-qmx6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi index 150d69858255..05fd8ff4da1e 100644 --- a/arch/arm/boot/dts/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -48,7 +48,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -60,7 +60,7 @@ >; }; - audmux_aud6 { + mux-aud6 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-rex-basic.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts similarity index 99% rename from arch/arm/boot/dts/imx6dl-riotboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts index 24c7f535f63b..0366d1037ef4 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts @@ -177,7 +177,7 @@ VDDIO-supply = <®_3p3v>; }; - pmic: pf0100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabrelite.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts diff --git a/arch/arm/boot/dts/imx6dl-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-savageboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts diff --git a/arch/arm/boot/dts/imx6dl-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-solidsense.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-ts4900.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-ts7970.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8034.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8035.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-801x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-8033.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-811x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-udoo.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts similarity index 94% rename from arch/arm/boot/dts/imx6dl-victgo.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts index 23274be08e61..4875afadb630 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts @@ -74,18 +74,42 @@ polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-vicut1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard-revb1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-draco.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-hydra.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-lynx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-orion.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-ursa.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp43-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl.dtsi diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-eval.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apf6dev.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-arm2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b450v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b650v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b850v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-ba16.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-bosch-acc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-bx50v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-cm-fx6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts index 1ad41c944b4b..ffb3b8eeae5d 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts @@ -141,7 +141,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_RCLKDIR | @@ -152,7 +152,7 @@ >; }; - audmux4 { + mux-audmux4 { fsl,audmux-port = <3>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | diff --git a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dhcom-pdk2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6q-display5.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi index fef5d7254536..4ab31f2217cd 100644 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi @@ -147,7 +147,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -159,7 +159,7 @@ >; }; - aud6 { + mux-aud6 { fsl,audmux-port = <5>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_RFSEL(8) | @@ -276,7 +276,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - at24@50 { + eeprom@50 { compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts index 9591848cbd37..3815cb660ff7 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -134,7 +134,7 @@ &pinctrl_pfuze>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio3>; diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dms-ba16.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ds.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ds.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ds.dts diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-emcon-avari.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-evi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-evi.dts diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gk802.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw51xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw52xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw53xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-gw5400-a.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts index 522a51042965..0ba802b891b5 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts @@ -206,7 +206,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw54xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw551x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw552x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts diff --git a/arch/arm/boot/dts/imx6q-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw553x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts diff --git a/arch/arm/boot/dts/imx6q-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw560x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts diff --git a/arch/arm/boot/dts/imx6q-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5903.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts diff --git a/arch/arm/boot/dts/imx6q-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5904.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5907.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5910.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5912.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5913.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-h100.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-h100.dts index 6406ade14f57..3fe4591e21f5 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts @@ -166,7 +166,7 @@ pinctrl-0 = <&pinctrl_h100_i2c1>; status = "okay"; - eeprom: 24c02@51 { + eeprom: eeprom@51 { compatible = "microchip,24c02", "atmel,24c02"; reg = <0x51>; }; diff --git a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-mipi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-ofcap10.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-ofcap12.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-rqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore.dts diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6q-kp-tpc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-kp-tpc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6q-kp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi index 5e0ed5560040..091903f53a56 100644 --- a/arch/arm/boot/dts/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi @@ -135,7 +135,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -147,7 +147,7 @@ >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-logicpd.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-marsboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6a.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mccmon6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6_max.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6_som2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-novena.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index ee8c0bd3ecfd..a7d5a68110fc 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -308,7 +308,7 @@ pinctrl-0 = <&pinctrl_i2c2_novena>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-pbab01.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6q-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts similarity index 99% rename from arch/arm/boot/dts/imx6q-pistachio.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts index bad8d831e64e..109b46a22b5e 100644 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -208,7 +208,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-prti6q.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts similarity index 97% rename from arch/arm/boot/dts/imx6q-prtwd2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts index 54a57a4548e2..792b8903d345 100644 --- a/arch/arm/boot/dts/imx6q-prtwd2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts @@ -156,9 +156,6 @@ MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 /* nINTRP */ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 >; }; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-rex-pro.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabrelite.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts diff --git a/arch/arm/boot/dts/imx6q-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-savageboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sbc6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-revc-lt2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-revc-lt6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts diff --git a/arch/arm/boot/dts/imx6q-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-solidsense.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tbs2910.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ts4900.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ts7970.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1010.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1020.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1036.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1110.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-udoo.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-utilite-pro.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-var-dt6customboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-vicut1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard-revb1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-yapp4-crux.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts diff --git a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-yapp4-pegasus.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-zii-rdu2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apalis.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apf6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apf6dev.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-aristainetos.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-cubox-i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ds.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-emcon.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw51xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw52xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw53xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-gw54xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index 4e20cb97058e..a642be45ffe2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -187,7 +187,7 @@ pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -199,7 +199,7 @@ >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -349,8 +349,6 @@ fan-controller@2c { compatible = "gw,gsc-fan"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x2c>; }; }; @@ -400,7 +398,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-gw551x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 0fa4b8eeddee..29960d1cf6a0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -171,7 +171,7 @@ pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -183,7 +183,7 @@ >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw552x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw553x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw560x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5903.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-gw5904.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 9fc79af2bc9a..9594bc5745ed 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -238,8 +238,13 @@ port@5 { reg = <5>; - label = "cpu"; ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5907.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5910.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-gw5912.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi index 40e235e315cc..de5983cf7810 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi @@ -243,8 +243,6 @@ fan-controller@a { compatible = "gw,gsc-fan"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x0a>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5913.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-hummingboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi index 2ffb21dd89f2..bfade7149080 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi @@ -147,7 +147,7 @@ &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -159,7 +159,7 @@ >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi index eb1ad28946d3..0883ef99cded 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi @@ -179,7 +179,7 @@ &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -191,7 +191,7 @@ >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi index a4217f564a53..d339957cc097 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi @@ -118,7 +118,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -130,7 +130,7 @@ >; }; - audmux_aud4 { + mux-aud4 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -262,7 +262,7 @@ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmcc-supply = <®_sd3_vmmc>; + vmmc-supply = <®_sd3_vmmc>; cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; bus-width = <4>; no-1-8-v; @@ -274,7 +274,7 @@ pinctrl-0 = <&pinctrl_usdhc4>; pinctrl-1 = <&pinctrl_usdhc4_100mhz>; pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - vmcc-supply = <®_sd4_vmmc>; + vmmc-supply = <®_sd4_vmmc>; bus-width = <8>; no-1-8-v; non-removable; diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-icore.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi index 23c318d9636f..efe11524b885 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi @@ -109,7 +109,7 @@ status = "okay"; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -121,7 +121,7 @@ >; }; - audmux_aud4 { + mux-aud4 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi similarity index 91% rename from arch/arm/boot/dts/imx6qdl-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 7b7e6c2ad190..7d032d1f3b47 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -129,7 +129,7 @@ &audmux { status = "okay"; - ssi0 { + mux-ssi0 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -141,7 +141,7 @@ >; }; - aud3 { + mux-aud3 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -192,6 +192,13 @@ }; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -205,6 +212,17 @@ }; }; +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -272,6 +290,22 @@ &usbh1 { disable-over-current; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,2517"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usb424,9e00"; + reg = <1>; + nvmem-cells = <&mba_mac_address>; + nvmem-cell-names = "mac-address"; + }; + }; }; &usbotg { @@ -396,6 +430,15 @@ >; }; + pinctrl_hdmi: hdmigrp { + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 @@ -432,6 +475,20 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi similarity index 83% rename from arch/arm/boot/dts/imx6qdl-mba6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi index df8fa169e9f6..27fec340c380 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi @@ -21,6 +21,12 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; rtc0: rtc@68 { diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi similarity index 89% rename from arch/arm/boot/dts/imx6qdl-mba6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi index 7d1cd7454c7f..0a9f076eeb36 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi @@ -31,6 +31,12 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; rtc0: rtc@68 { diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi index 51d28e275aa6..a41e47c06ef4 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi @@ -75,7 +75,7 @@ &audmux { status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -87,7 +87,7 @@ >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-pi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi similarity index 97% rename from arch/arm/boot/dts/imx6qdl-prti6q.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi index f0db0d4471f4..36f84f4da6b0 100644 --- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi @@ -69,6 +69,7 @@ vbus-supply = <®_usb_h1_vbus>; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -78,10 +79,18 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-rex.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-sabreauto.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index f79caa36f3d2..68e97180d33e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -336,7 +336,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sabrelite.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-sabresd.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index 53b080c97f2d..4fe58764b929 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -338,7 +338,7 @@ }; }; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-savageboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-solidsense.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-solidsense.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ts4900.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ts7970.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-tx6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index a197bac95cba..e2fe337f7d9e 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -216,7 +216,7 @@ &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -228,7 +228,7 @@ >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-udoo.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-var-dart.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi index c41cac502bac..200559d7158d 100644 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi @@ -39,7 +39,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -51,7 +51,7 @@ >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi index f505f2704530..73f381e14467 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi @@ -10,7 +10,7 @@ pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + power-button { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi similarity index 98% rename from arch/arm/boot/dts/imx6qdl-vicut1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi index c4e6cf0527ba..96e4f4b0b248 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi @@ -169,6 +169,14 @@ polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; }; @@ -393,8 +401,6 @@ }; &ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; status = "okay"; }; @@ -426,6 +432,7 @@ pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -439,6 +446,14 @@ status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi index bf86b639fdac..9b8c9c23ab54 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi @@ -27,7 +27,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi index 5bb47c79a4da..9ff183e4e069 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi @@ -757,7 +757,7 @@ port@2 { reg = <2>; - label = "cpu"; + phy-mode = "rev-rmii"; ethernet = <&fec>; fixed-link { @@ -848,7 +848,7 @@ pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -860,7 +860,7 @@ >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -868,7 +868,7 @@ >; }; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -880,7 +880,7 @@ >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6qdl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index b72ec745f6d1..bda182edc589 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -150,7 +150,7 @@ interrupt-parent = <&gpc>; ranges; - dma_apbh: dma-apbh@110000 { + dma_apbh: dma-controller@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-nitrogen6_max.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts similarity index 99% rename from arch/arm/boot/dts/imx6qp-prtwd3.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts index cf6571cc4682..ae00d538a4df 100644 --- a/arch/arm/boot/dts/imx6qp-prtwd3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts @@ -350,7 +350,7 @@ pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qp-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8037.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8137.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-vicutp.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts diff --git a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-zii-rdu2.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qp.dtsi diff --git a/arch/arm/boot/dts/imx6s-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/imx6s-dhcom-drc02.dts rename to arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts similarity index 99% rename from arch/arm/boot/dts/imx6sl-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts index dc5d596c18db..239bc6dfc584 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts @@ -160,7 +160,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-kobo-aura2.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sl-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-shine3.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-vision.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-vision5.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-warp.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sl.dtsi diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts similarity index 85% rename from arch/arm/boot/dts/imx6sll-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts index 269092ac881c..e3e9b0ec4f73 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts @@ -109,6 +109,14 @@ enable-active-high; }; + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + reg_sd3_vmmc: regulator-sd3-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -343,6 +351,17 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; @@ -444,7 +463,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 @@ -455,7 +474,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 @@ -466,6 +485,54 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x13059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130f9 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 @@ -484,7 +551,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { fsl,pins = < MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 @@ -496,7 +563,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { fsl,pins = < MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts similarity index 100% rename from arch/arm/boot/dts/imx6sll-kobo-clarahd.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts similarity index 100% rename from arch/arm/boot/dts/imx6sll-kobo-librah2o.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sll-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sll.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sll.dtsi diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-nitrogen6sx.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sx-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb-mqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts similarity index 99% rename from arch/arm/boot/dts/imx6sx-sdb-reva.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts index 7dda42553f4b..48f19dede467 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts @@ -15,7 +15,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb-sai.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts similarity index 99% rename from arch/arm/boot/dts/imx6sx-sdb.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts index 969cfe920d25..e05a1be5553c 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts @@ -14,7 +14,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts similarity index 99% rename from arch/arm/boot/dts/imx6sx-softing-vining-2000.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts index b9a1401e6c6d..bfcd8f7d86dd 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts @@ -171,7 +171,7 @@ reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; }; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-full.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi similarity index 98% rename from arch/arm/boot/dts/imx6sx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 93ac2380ca1e..3a4308666552 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -209,7 +209,7 @@ power-domains = <&pd_pu>; }; - dma_apbh: dma-apbh@1804000 { + dma_apbh: dma-controller@1804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = , @@ -841,10 +841,40 @@ reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@20e4000 { + gpr: syscon@20e4000 { compatible = "fsl,imx6sx-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x020e4000 0x4000>; + + lvds_bridge: bridge@18 { + compatible = "fsl,imx6sx-ldb"; + reg = <0x18 0x4>; + clocks = <&clks IMX6SX_CLK_LDB_DI0>; + clock-names = "ldb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + }; + }; }; sdma: dma-controller@20ec000 { @@ -1278,6 +1308,14 @@ clock-names = "pix", "axi", "disp_axi"; power-domains = <&pd_disp>; status = "disabled"; + + ports { + port { + lcdif1_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif1>; + }; + }; + }; }; lcdif2: lcdif@2224000 { diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ul-14x14-evk.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 7275a1366413..155515fe13fa 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -89,8 +89,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; + sck-gpios = <&gpio5 11 0>; + mosi-gpios = <&gpio5 10 0>; cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi index b5781c3656d1..7d1a391431bd 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi @@ -158,7 +158,7 @@ regulator-max-microvolt = <3300000>; }; - vcoin_chg: vcoin { + vcoin_chg: coin { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-geam.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl-43.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-liteboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-litesom.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-opos6uldev.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ul-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi index 357ffb2f5ad6..4ffe99ed55ca 100644 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi @@ -131,7 +131,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6ul-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts similarity index 99% rename from arch/arm/boot/dts/imx6ul-prti6g.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts index b7c96fbe7a91..c3c50f51a5a8 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts @@ -177,6 +177,7 @@ &usbotg1 { dr_mode = "host"; + over-current-active-low; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-0010.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-0011.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ul-tx6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 70cef5e817bd..6bd90473050b 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -218,9 +218,9 @@ compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi_gpio>; - gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; cs-gpios = < &gpio1 29 GPIO_ACTIVE_HIGH diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index 3d9d0f823568..0174f3edbd16 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -164,7 +164,7 @@ <0x00a06000 0x2000>; }; - dma_apbh: dma-apbh@1804000 { + dma_apbh: dma-controller@1804000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, @@ -719,6 +719,18 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + clocks = <&clks IMX6UL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; }; iomuxc: pinctrl@20e0000 { diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-aster.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-drc02.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ull-dhcom-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi index 17837663c0b0..830b5a5064f2 100644 --- a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi @@ -7,8 +7,6 @@ / { aliases { - /delete-property/ mmc0; /* Avoid double definitions */ - /delete-property/ mmc1; /delete-property/ spi2; /delete-property/ spi3; i2c0 = &i2c2; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts new file mode 100644 index 000000000000..047f7b2d8526 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 DH electronics GmbH + * Copyright (C) 2023 Marantec electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG + * DHCOR PCB number: 578-200 or newer + * maveo box PCB number: 525-200 or newer + */ + +/dts-v1/; + +#include "imx6ull-dhcor-som.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOR on maveo box"; + compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som", + "fsl,imx6ull"; + + aliases { + mmc2 = &usdhc2; + spi0 = &ecspi4; + spi3 = &ecspi1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg1-vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg2-vbus"; + }; + + /* WiFi pin WL_REG_ON is connected to GPIO 5.9 */ + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; +}; + +/* BT pin BT_REG_ON is connected to GPIO 1.18 */ +&bluetooth { + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; +}; + +/* X10 connector */ +&ecspi4 { + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi4>; + pinctrl-names = "default"; + status = "okay"; + + spidev@0 { + compatible = "dh,dhcom-board"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <54000000>; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "BUTTON-USER", "", "", + "BUTTON-RESET", "", "", "", + "", "", "", "", + "", "", "BT-REG-ON", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "PSOC-GPIO-1", "", "", "X10-12", + "X10-10", "PSOC-GPIO-2", "PSOC-GPIO-3", "", + "X10-11", "X10-9", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "DHCOR-HW0", "DHCOR-HW1", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "MAVEO-BOX-HW0", "LED-G", "MAVEO-BOX-VAR1", + "MAVEO-BOX-VAR0", "MAVEO-BOX-HW1", "MAVEO-BOX-HW2", "LED-B", + "LED-R", "", "", "", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG", + "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE", + "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* Console UART */ +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* BT on LGA */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt_gpio>; +}; + +/* Zigbee UART */ +&uart3 { + pinctrl-0 = <&pinctrl_uart3 &pinctrl_snvs_zigbee_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "otg"; + hnp-disable; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbotg2>; + pinctrl-names = "default"; + tpl-support; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +/* WiFi on LGA */ +&usdhc1 { + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&pinctrl_usdhc1_wifi &pinctrl_snvs_wifi_gpio>; +}; + +/* eMMC */ +&usdhc2 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_hog_maveo_box: hog-maveo-box-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 /* BUTTON_USER */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x120b0 /* BUTTON_RESET */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0 /* LED_G */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0 /* LED_B */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0 /* LED_R */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x400120b0 /* X10_9 */ + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x400120b0 /* X10_10 */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x400120b0 /* X10_11 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x400120b0 /* X10_12 */ + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x400120b0 /* PSOC_GPIO_1 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x400120b0 /* PSOC_GPIO_2 */ + MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x400120b0 /* PSOC_GPIO_3 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x120b0 /* MAVEO_BOX_HW0 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x120b0 /* MAVEO_BOX_HW1 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x120b0 /* MAVEO_BOX_HW2 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x120b0 /* MAVEO_BOX_VAR0 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x120b0 /* MAVEO_BOX_VAR1 */ + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x120b0 /* DHCOR_HW0 */ + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x120b0 /* DHCOR_HW1 */ + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x120b0 + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x120b0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x120b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x120b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x120b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x120b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x120b0 + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x120b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x120b0 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x120b0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x120b0 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x120b0 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x120b0 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x120b0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x120b0 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x120b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x120b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x120b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x120b0 + >; + }; + + pinctrl_bt_gpio: bt-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0 /* BT_REG_ON */ + >; + }; + + pinctrl_ecspi4: ecspi4-grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x120b0 /* USB_OTG1_PWR */ + >; + }; + + pinctrl_usbotg2: usbotg2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x120b0 /* USB_OTG2_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ + >; + }; +}; + +&iomuxc_snvs { + pinctrl-0 = <&pinctrl_snvs_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0 /* PSOC_SWD_IO */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0 /* PSOC_SWD_CLK */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0 /* PSOC_RESET */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x400120b0 /* PSOC_PWR_FAIL_OUT */ + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0 /* NFC_ENABLE */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0 /* NFC_IRQ */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x120b0 /* DHCOR_BOOT_M0 */ + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x120b0 /* DHCOR_BOOT_M1 */ + >; + }; + + pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0 /* WL_REG_ON */ + >; + }; + + pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0 /* ZIGBEE_PROG */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0 /* ZIGBEE_RESET */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi similarity index 98% rename from arch/arm/boot/dts/imx6ull-dhcor-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi index 32a6022625d9..45315adfaa86 100644 --- a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi @@ -12,6 +12,11 @@ #include "imx6ull.dtsi" / { + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + }; + memory@80000000 { /* Appropriate memory size will be filled by U-Boot */ reg = <0x80000000 0>; diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-jozacp.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts diff --git a/arch/arm/boot/dts/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-kontron-bl.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts diff --git a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-kontron-sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi diff --git a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-opos6uldev.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi similarity index 99% rename from arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index 5464a52a1f94..ea627638e40c 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -260,7 +260,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; linux,rs485-enabled-at-boot-time; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h similarity index 100% rename from arch/arm/boot/dts/imx6ull-pinfunc-snvs.h rename to arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6ull-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-master.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-micro.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-slave.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-slavext.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull.dtsi diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ulz-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ulz.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-aster.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-iris.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-mba7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-cl-som-imx7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts similarity index 99% rename from arch/arm/boot/dts/imx7d-flex-concentrator.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts index bd6b5285aa8d..3a723843d562 100644 --- a/arch/arm/boot/dts/imx7d-flex-concentrator.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts @@ -107,7 +107,6 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; status = "okay"; @@ -122,7 +121,6 @@ &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - num-chipselects = <1>; cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-mba7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts diff --git a/arch/arm/boot/dts/imx7d-meerkat96.dts b/arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-meerkat96.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts similarity index 99% rename from arch/arm/boot/dts/imx7d-nitrogen7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts index a31de900139d..9c6476bda4a0 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts @@ -159,7 +159,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi similarity index 99% rename from arch/arm/boot/dts/imx7d-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi index e0bff39e8d3e..73d90845e85c 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi @@ -170,7 +170,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx7d-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-remarkable2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts diff --git a/arch/arm/boot/dts/imx7d-sbc-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sbc-imx7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sdb-reva.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts diff --git a/arch/arm/boot/dts/imx7d-sdb-sht11.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sdb-sht11.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts similarity index 93% rename from arch/arm/boot/dts/imx7d-sdb.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index 234e5fc647b2..75f1cd14bea1 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -43,8 +43,8 @@ compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; @@ -60,6 +60,17 @@ }; }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -264,7 +275,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -473,10 +484,13 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; wakeup-source; keep-power-in-suspend; status = "okay"; @@ -731,6 +745,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -739,9 +762,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts similarity index 97% rename from arch/arm/boot/dts/imx7d-smegw01.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts index c0f00f5db11e..85b97b5f64e7 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts @@ -13,6 +13,8 @@ compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; mmc0 = &usdhc1; mmc1 = &usdhc3; mmc2 = &usdhc2; @@ -67,7 +69,7 @@ reg_wlan_rfkill: regulator-wlan-rfkill { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-2 = <&pinctrl_rfkill>; + pinctrl-0 = <&pinctrl_rfkill>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "wlan_rfkill"; @@ -97,8 +99,6 @@ sram@0 { compatible = "microchip,48l640"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <16000000>; }; }; @@ -329,7 +329,7 @@ >; }; - pinctrl_rfkill: rfkillrp { + pinctrl_rfkill: rfkillgrp { fsl,pins = < MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 >; @@ -355,19 +355,19 @@ >; }; - pinctrl_usbotg1_lpsr: usbotg1 { + pinctrl_usbotg1_lpsr: usbotg1grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 >; }; - pinctrl_usbotg1_pwr: usbotg1-pwr { + pinctrl_usbotg1_pwr: usbotg1-pwrgrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 >; }; - pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio { + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 >; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-zii-rmu2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-zii-rpu2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d.dtsi diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-mba7.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7s-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts similarity index 99% rename from arch/arm/boot/dts/imx7s-warp.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-warp.dts index e8734d218b9d..ba7231b364bb 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts @@ -94,7 +94,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi similarity index 99% rename from arch/arm/boot/dts/imx7s.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s.dtsi index efe2525b62fa..54026c2c93fa 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -1257,7 +1257,7 @@ }; }; - dma_apbh: dma-apbh@33000000 { + dma_apbh: dma-controller@33000000 { compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x33000000 0x2000>; interrupts = , diff --git a/arch/arm/boot/dts/imx7ulp-com.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts similarity index 100% rename from arch/arm/boot/dts/imx7ulp-com.dts rename to arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx7ulp-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx7ulp-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi similarity index 99% rename from arch/arm/boot/dts/imx7ulp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index f91bf719d4e2..b01ddda7bd9e 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -459,6 +459,8 @@ compatible = "fsl,imx7ulp-ocotp", "syscon"; reg = <0x410a6000 0x4000>; clocks = <&scg1 IMX7ULP_CLK_DUMMY>; + #address-cells = <1>; + #size-cells = <1>; }; }; }; diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts similarity index 100% rename from arch/arm/boot/dts/imxrt1050-evk.dts rename to arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts diff --git a/arch/arm/boot/dts/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imxrt1050-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi similarity index 99% rename from arch/arm/boot/dts/imxrt1050.dtsi rename to arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi index 852861558b47..dd714d235d5f 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi @@ -4,7 +4,7 @@ * Author(s): Giulio Benetti */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include #include #include diff --git a/arch/arm/boot/dts/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imxrt1170-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi similarity index 98% rename from arch/arm/boot/dts/mba6ulx.dtsi rename to arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index 5bf831b072d6..e3b2d23068f7 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -57,7 +57,7 @@ label = "POWER"; linux,code = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; + wakeup-source; }; }; @@ -235,6 +235,7 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; }; expander_in0: gpio-expander@21 { @@ -248,6 +249,7 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; enet1_int-hog { gpio-hog; @@ -267,6 +269,7 @@ reg = <0x22>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; }; analog_touch: touchscreen@41 { @@ -300,6 +303,7 @@ compatible = "nxp,se97b", "atmel,24c02"; reg = <0x51>; pagesize = <16>; + vcc-supply = <®_mba6ul_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile new file mode 100644 index 000000000000..56b9a0ebb917 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ + lpc4350-hitex-eval.dtb \ + lpc4357-ea4357-devkit.dtb \ + lpc4357-myd-lpc4357.dtb +dtb-$(CONFIG_ARCH_LPC32XX) += \ + lpc3250-ea3250.dtb \ + lpc3250-phy3250.dtb diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi similarity index 99% rename from arch/arm/boot/dts/lpc18xx.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 1bb686a7b3ec..9cf09c183b85 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -11,7 +11,7 @@ * */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include "dt-bindings/clock/lpc18xx-cgu.h" #include "dt-bindings/clock/lpc18xx-ccu.h" diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts similarity index 100% rename from arch/arm/boot/dts/lpc3250-ea3250.dts rename to arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts similarity index 100% rename from arch/arm/boot/dts/lpc3250-phy3250.dts rename to arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc32xx.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts similarity index 100% rename from arch/arm/boot/dts/lpc4337-ciaa.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts similarity index 100% rename from arch/arm/boot/dts/lpc4350-hitex-eval.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts diff --git a/arch/arm/boot/dts/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc4350.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts similarity index 100% rename from arch/arm/boot/dts/lpc4357-ea4357-devkit.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts similarity index 100% rename from arch/arm/boot/dts/lpc4357-myd-lpc4357.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts diff --git a/arch/arm/boot/dts/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc4357.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi diff --git a/arch/arm/boot/dts/nxp/ls/Makefile b/arch/arm/boot/dts/nxp/ls/Makefile new file mode 100644 index 000000000000..3cb1d516f6fb --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ + ls1021a-moxa-uc-8410a.dtb \ + ls1021a-qds.dtb \ + ls1021a-tsn.dtb \ + ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-iot.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-qds.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-tsn.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-twr.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi similarity index 100% rename from arch/arm/boot/dts/ls1021a.dtsi rename to arch/arm/boot/dts/nxp/ls/ls1021a.dtsi diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile new file mode 100644 index 000000000000..a430d04f9c69 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MXS) += \ + imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-sansa.dtb \ + imx23-stmp378x_devb.dtb \ + imx23-xfi3.dtb \ + imx28-apf28.dtb \ + imx28-apf28dev.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-cfa10037.dtb \ + imx28-cfa10049.dtb \ + imx28-cfa10055.dtb \ + imx28-cfa10056.dtb \ + imx28-cfa10057.dtb \ + imx28-cfa10058.dtb \ + imx28-duckbill-2-485.dtb \ + imx28-duckbill-2.dtb \ + imx28-duckbill-2-enocean.dtb \ + imx28-duckbill-2-spi.dtb \ + imx28-duckbill.dtb \ + imx28-eukrea-mbmx283lc.dtb \ + imx28-eukrea-mbmx287lc.dtb \ + imx28-evk.dtb \ + imx28-m28cu3.dtb \ + imx28-m28evk.dtb \ + imx28-sps1.dtb \ + imx28-ts4600.dtb \ + imx28-tx28.dtb \ + imx28-xea.dtb diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx23-evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-evk.dts diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/imx23-olinuxino.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx23-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts similarity index 100% rename from arch/arm/boot/dts/imx23-sansa.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts similarity index 100% rename from arch/arm/boot/dts/imx23-stmp378x_devb.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts similarity index 100% rename from arch/arm/boot/dts/imx23-xfi3.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi similarity index 99% rename from arch/arm/boot/dts/imx23.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx23.dtsi index d19508c8f9ed..a3668a0827fc 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi @@ -59,7 +59,7 @@ reg = <0x80000000 0x2000>; }; - dma_apbh: dma-apbh@80004000 { + dma_apbh: dma-controller@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; interrupts = <0 14 20 0 diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apf28.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apf28dev.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apx4devkit.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10036.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10037.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts similarity index 98% rename from arch/arm/boot/dts/imx28-cfa10049.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts index 94d6614c1983..c5a7f56d83db 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts @@ -100,9 +100,9 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10049>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; @@ -124,8 +124,8 @@ pinctrl-names = "default"; pinctrl-0 = <&spi3_pins_cfa10049>; status = "okay"; - gpio-sck = <&gpio0 24 0>; - gpio-mosi = <&gpio0 28 0>; + sck-gpios = <&gpio0 24 0>; + mosi-gpios = <&gpio0 28 0>; cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; num-chipselects = <3>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts similarity index 97% rename from arch/arm/boot/dts/imx28-cfa10055.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts index 42ba7da48beb..70e225a99fbe 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts @@ -19,9 +19,9 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10055>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts similarity index 96% rename from arch/arm/boot/dts/imx28-cfa10056.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts index 0e15bdfd7281..bc2d6fcad12f 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts @@ -18,9 +18,9 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10056>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10057.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10058.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-485.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-enocean.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-spi.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx28-evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-evk.dts diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-lwe.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-m28.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts similarity index 100% rename from arch/arm/boot/dts/imx28-m28cu3.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts similarity index 100% rename from arch/arm/boot/dts/imx28-m28evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx28-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts similarity index 100% rename from arch/arm/boot/dts/imx28-sps1.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts similarity index 100% rename from arch/arm/boot/dts/imx28-ts4600.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts similarity index 99% rename from arch/arm/boot/dts/imx28-tx28.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts index ffe58c7093e1..23ad7cd0a1de 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -192,9 +192,9 @@ pinctrl-names = "default"; pinctrl-0 = <&tx28_spi_gpio_pins>; - gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; num-chipselects = <3>; cs-gpios = < &gpio2 27 GPIO_ACTIVE_LOW diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts similarity index 100% rename from arch/arm/boot/dts/imx28-xea.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-xea.dts diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi similarity index 99% rename from arch/arm/boot/dts/imx28.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28.dtsi index a8d3c3113e0f..29e37b1fae66 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi @@ -78,7 +78,7 @@ status = "disabled"; }; - dma_apbh: dma-apbh@80004000 { + dma_apbh: dma-controller@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; interrupts = <82 83 84 85 diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/mxs-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile new file mode 100644 index 000000000000..0a4a7f9dd43e --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_VF610) += \ + vf500-colibri-eval-v3.dtb \ + vf610-bk4.dtb \ + vf610-colibri-eval-v3.dtb \ + vf610m4-colibri.dtb \ + vf610-cosmic.dtb \ + vf610m4-cosmic.dtb \ + vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ + vf610-zii-dev-rev-b.dtb \ + vf610-zii-dev-rev-c.dtb \ + vf610-zii-scu4-aib.dtb \ + vf610-zii-spb4.dtb \ + vf610-zii-ssmb-dtu.dtb \ + vf610-zii-ssmb-spu3.dtb diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/vf-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/vf500-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf500-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/nxp/vf/vf500.dtsi similarity index 100% rename from arch/arm/boot/dts/vf500.dtsi rename to arch/arm/boot/dts/nxp/vf/vf500.dtsi diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts similarity index 100% rename from arch/arm/boot/dts/vf610-bk4.dts rename to arch/arm/boot/dts/nxp/vf/vf610-bk4.dts diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/vf610-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts similarity index 100% rename from arch/arm/boot/dts/vf610-cosmic.dts rename to arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/vf610-pinfunc.h rename to arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts similarity index 100% rename from arch/arm/boot/dts/vf610-twr.dts rename to arch/arm/boot/dts/nxp/vf/vf610-twr.dts diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts similarity index 99% rename from arch/arm/boot/dts/vf610-zii-cfu1.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts index 96495d965163..1a19aec8957b 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts @@ -202,7 +202,7 @@ port@6 { reg = <6>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts similarity index 98% rename from arch/arm/boot/dts/vf610-zii-dev-rev-b.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts index 6280c5e86a12..16b4e06c4efa 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts @@ -75,7 +75,7 @@ port@6 { reg = <6>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { @@ -294,9 +294,9 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts similarity index 98% rename from arch/arm/boot/dts/vf610-zii-dev-rev-c.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts index c00d39562a10..6f9878f124c4 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts @@ -44,7 +44,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { @@ -82,6 +82,11 @@ label = "dsa"; phy-mode = "xaui"; link = <&switch1port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; @@ -174,6 +179,11 @@ label = "dsa"; phy-mode = "xaui"; link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; mdio { diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610-zii-dev.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts similarity index 97% rename from arch/arm/boot/dts/vf610-zii-scu4-aib.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts index 7b3276cd470f..df1335492a19 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts @@ -59,7 +59,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { @@ -115,6 +115,11 @@ link = <&switch1port10 &switch3port10 &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; @@ -156,6 +161,11 @@ phy-mode = "xgmii"; link = <&switch3port10 &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; switch1port10: port@10 { @@ -163,6 +173,11 @@ label = "dsa"; phy-mode = "xgmii"; link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; @@ -246,6 +261,11 @@ link = <&switch3port9 &switch1port9 &switch0port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; }; }; @@ -295,6 +315,11 @@ label = "dsa"; phy-mode = "2500base-x"; link = <&switch2port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; switch3port10: port@10 { @@ -303,6 +328,11 @@ phy-mode = "xgmii"; link = <&switch1port9 &switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts similarity index 99% rename from arch/arm/boot/dts/vf610-zii-spb4.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts index 180acb0795b9..1461804ecaea 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts @@ -140,7 +140,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts similarity index 99% rename from arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts index 73fdace4cb42..463c2452b9b7 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts @@ -129,7 +129,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts similarity index 99% rename from arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts index 20beaa8433b6..f5ae0d5de315 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts @@ -154,7 +154,7 @@ port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/nxp/vf/vf610.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610.dtsi diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts similarity index 100% rename from arch/arm/boot/dts/vf610m4-colibri.dts rename to arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts diff --git a/arch/arm/boot/dts/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts similarity index 100% rename from arch/arm/boot/dts/vf610m4-cosmic.dts rename to arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi similarity index 98% rename from arch/arm/boot/dts/vf610m4.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610m4.dtsi index 76bbfd5e32b6..2bb331a87721 100644 --- a/arch/arm/boot/dts/vf610m4.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi @@ -42,7 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include "vfxxx.dtsi" / { diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi similarity index 99% rename from arch/arm/boot/dts/vfxxx.dtsi rename to arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index ff4479994b60..3f7dc787938e 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -294,7 +294,6 @@ reg = <0x4003e000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_WDT>; - clock-names = "wdog"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile new file mode 100644 index 000000000000..3dfb1c8cefb8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/Makefile @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ + qcom-apq8026-asus-sparrow.dtb \ + qcom-apq8026-huawei-sturgeon.dtb \ + qcom-apq8026-lg-lenok.dtb \ + qcom-apq8026-samsung-matisse-wifi.dtb \ + qcom-apq8060-dragonboard.dtb \ + qcom-apq8064-cm-qs600.dtb \ + qcom-apq8064-ifc6410.dtb \ + qcom-apq8064-sony-xperia-lagan-yuga.dtb \ + qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-ap120c-ac-bit.dtb \ + qcom-ipq4018-jalapeno.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c3.dtb \ + qcom-ipq4019-ap.dk07.1-c1.dtb \ + qcom-ipq4019-ap.dk07.1-c2.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-e5.dtb \ + qcom-msm8916-samsung-e7.dtb \ + qcom-msm8916-samsung-grandmax.dtb \ + qcom-msm8916-samsung-serranove.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8960-samsung-expressatt.dtb \ + qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-sony-xperia-rhine-amami.dtb \ + qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-oneplus-bacon.dtb \ + qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb \ + qcom-sdx55-mtp.dtb \ + qcom-sdx55-t55.dtb \ + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8016-sbc.dts rename to arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts similarity index 92% rename from arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts index 5593a3a60d6c..de19640efe55 100644 --- a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts @@ -7,6 +7,7 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +#include /delete-node/ &adsp_region; @@ -68,6 +69,26 @@ status = "okay"; }; +&blsp1_i2c2 { + clock-frequency = <384000>; + + status = "okay"; + + vibrator@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + mode = ; + library-sel = ; + vib-rated-mv = <2765>; + vib-overdrive-mv = <3525>; + + pinctrl-0 = <&vibrator_default_state>; + pinctrl-names = "default"; + }; +}; + &blsp1_i2c5 { clock-frequency = <384000>; @@ -347,6 +368,13 @@ }; }; + vibrator_default_state: vibrator-default-state { + pins = "gpio59", "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + wlan_hostwake_default_state: wlan-hostwake-default-state { pins = "gpio66"; function = "gpio"; diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts similarity index 99% rename from arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts index 91b860e24681..884d99297d4c 100644 --- a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -99,7 +99,6 @@ dev-ctrl = /bits/ 8 <0x80>; init-brt = /bits/ 8 <0x3f>; - pwm-period = <100000>; pwms = <&backlight_pwm 0 100000>; pwm-names = "lp8556"; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts similarity index 94% rename from arch/arm/boot/dts/qcom-apq8060-dragonboard.dts rename to arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts index 8e4b61e4d4b1..db4c791b2e2f 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts @@ -18,50 +18,46 @@ stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; + /* Main power of the board: 3.7V */ + vph: regulator-fixed { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-always-on; + regulator-boot-on; + }; - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; - /* GPIO controlled ethernet power regulator */ - dragon_veth: xc622a331mrg { - compatible = "regulator-fixed"; - regulator-name = "XC6222A331MR-G"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vph>; - gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_veth_gpios>; - regulator-always-on; - }; + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; - /* VDDvario fixed regulator */ - dragon_vario: nds332p { - compatible = "regulator-fixed"; - regulator-name = "NDS332P"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&pm8058_s3>; - }; - - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; + /* This is a levelshifter for SDCC5 */ + dragon_vio_txb: txb0104rgyr { + compatible = "regulator-fixed"; + regulator-name = "Dragon SDCC levelshifter"; + vin-supply = <&pm8058_l14>; + regulator-always-on; }; /* @@ -451,7 +447,7 @@ * PM8901 supplies "preliminary regulators" whatever * that means */ - pm8901-regulators { + regulators-0 { vdd_l0-supply = <&pm8901_s4>; vdd_l1-supply = <&vph>; vdd_l2-supply = <&vph>; @@ -537,7 +533,7 @@ }; - pm8058-regulators { + regulators-1 { vdd_l0_l1_lvs-supply = <&pm8058_s3>; vdd_l2_l11_l12-supply = <&vph>; vdd_l3_l4_l5-supply = <&vph>; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-ifc6410.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-pins.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts similarity index 71% rename from arch/arm/boot/dts/qcom-apq8074-dragonboard.dts rename to arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 1345df7cbd00..e0679436000b 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -1,9 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include +#include +#include #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" +/delete-node/ &mpss_region; + / { model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; @@ -17,12 +22,43 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-0 = <&msm_keys_default>; + pinctrl-names = "default"; + + button-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + }; + + button-general { + label = "General"; + linux,code = ; + gpios = <&pm8941_gpios 23 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + mpss_region: mpss@ac00000 { + reg = <0x0ac00000 0x2500000>; + no-map; + }; + }; }; &blsp1_uart2 { status = "okay"; }; +&blsp2_dma { + qcom,controlled-remotely; +}; + &blsp2_i2c5 { status = "okay"; clock-frequency = <200000>; @@ -35,6 +71,119 @@ }; }; +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + + status = "okay"; + + panel: panel@0 { + compatible = "sharp,ls043t1le01-qhd"; + reg = <0>; + + avdd-supply = <&pm8941_l22>; + backlight = <&pm8941_wled>; + reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8941_gpios { + msm_keys_default: pm8941-gpio-keys-state { + pins = "gpio5", "gpio23"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; +}; + +&pm8941_lpg { + qcom,power-source = <1>; + status = "okay"; + + led@5 { + reg = <5>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@6 { + reg = <6>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@7 { + reg = <7>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; +}; + +&pm8941_wled { + qcom,cs-out; + qcom,switching-freq = <3200>; + qcom,ovp = <32>; + qcom,num-strings = <1>; + + status = "okay"; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + + firmware-name = "qcom/apq8074/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + firmware-name = "qcom/apq8074/mba.mbn", "qcom/apq8074/modem.mbn"; + + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8084-ifc6540.dts rename to arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8084-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi similarity index 99% rename from arch/arm/boot/dts/qcom-apq8084.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 83839e1ec4d1..8f178bc87e1d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -507,7 +507,7 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts similarity index 87% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts index 79b0c6318e52..0993f840d1fc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts @@ -11,9 +11,9 @@ dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - status = "okay"; - }; }; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi similarity index 96% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi index a63b3778636d..468ebc40d2ad 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -102,10 +102,10 @@ status = "okay"; perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi similarity index 92% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index 0107f552f520..7ef635997efa 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -65,11 +65,11 @@ dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8062.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-ap148.dts rename to arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts similarity index 99% rename from arch/arm/boot/dts/qcom-ipq8064-rb3011.dts rename to arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts index 4d509876294b..104eb729c2d6 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -323,7 +323,7 @@ pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "rb3011:green:user"; color = ; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi similarity index 97% rename from arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi index 411c8d63c38e..c5abe7151f14 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi @@ -92,34 +92,34 @@ pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "led_usb1"; gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@8 { + led-1 { label = "led_usb3"; gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@9 { + led-2 { label = "status_led_fail"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@26 { + led-3 { label = "sata_led"; gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@53 { + led-4 { label = "status_led_pass"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi similarity index 99% rename from arch/arm/boot/dts/qcom-ipq8064.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 7581845737a8..6198f42f6a9c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -521,7 +521,7 @@ #reset-cells = <1>; #power-domain-cells = <1>; - tsens: thermal-sensor@900000 { + tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; @@ -607,12 +607,12 @@ regulator; }; - nss_common: syscon@03000000 { + nss_common: syscon@3000000 { compatible = "syscon"; reg = <0x03000000 0x0000FFFF>; }; - usb3_0: usb3@100f8800 { + usb3_0: usb@100f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -627,7 +627,7 @@ status = "disabled"; - dwc3_0: dwc3@10000000 { + dwc3_0: usb@10000000 { compatible = "snps,dwc3"; reg = <0x10000000 0xcd00>; interrupts = ; @@ -658,7 +658,7 @@ status = "disabled"; }; - usb3_1: usb3@110f8800 { + usb3_1: usb@110f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -673,7 +673,7 @@ status = "disabled"; - dwc3_1: dwc3@11000000 { + dwc3_1: usb@11000000 { compatible = "snps,dwc3"; reg = <0x11000000 0xcd00>; interrupts = ; diff --git a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8065.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts rename to arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi rename to arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615.dtsi rename to arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts rename to arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi similarity index 78% rename from arch/arm/boot/dts/qcom-msm8226.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 42acb9ddb8cc..313a726f4704 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -47,6 +47,12 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -176,7 +182,7 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc1_default_state>; @@ -192,7 +198,7 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_default_state>; @@ -208,7 +214,7 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC3_AHB_CLK>, <&gcc GCC_SDCC3_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc3_default_state>; @@ -362,7 +368,8 @@ compatible = "qcom,usb-hs-phy-msm8226", "qcom,usb-hs-phy"; #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; clock-names = "ref", "sleep"; resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; reset-names = "phy", "por"; @@ -391,6 +398,21 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte"; }; tlmm: pinctrl@fd510000 { @@ -506,11 +528,131 @@ }; }; + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2"; + #qcom,sensors = <6>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; }; + qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@1c1 { + reg = <0x1c1 0x2>; + bits = <5 8>; + }; + + tsens_s0_p1: s0-p1@1c2 { + reg = <0x1c2 0x2>; + bits = <5 6>; + }; + + tsens_s1_p1: s1-p1@1c4 { + reg = <0x1c4 0x1>; + bits = <0 6>; + }; + + tsens_s2_p1: s2-p1@1c4 { + reg = <0x1c4 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1c5 { + reg = <0x1c5 0x2>; + bits = <4 6>; + }; + + tsens_s4_p1: s4-p1@1c6 { + reg = <0x1c6 0x1>; + bits = <2 6>; + }; + + tsens_s5_p1: s5-p1@1c7 { + reg = <0x1c7 0x1>; + bits = <0 6>; + }; + + tsens_s6_p1: s6-p1@1ca { + reg = <0x1ca 0x2>; + bits = <4 6>; + }; + + tsens_base2: base2@1cc { + reg = <0x1cc 0x1>; + bits = <0 8>; + }; + + tsens_s0_p2: s0-p2@1cd { + reg = <0x1cd 0x1>; + bits = <0 6>; + }; + + tsens_s1_p2: s1-p2@1cd { + reg = <0x1cd 0x2>; + bits = <6 6>; + }; + + tsens_s2_p2: s2-p2@1ce { + reg = <0x1ce 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1cf { + reg = <0x1cf 0x1>; + bits = <2 6>; + }; + + tsens_s4_p2: s4-p2@446 { + reg = <0x446 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@447 { + reg = <0x447 0x1>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@44e { + reg = <0x44e 0x1>; + bits = <1 6>; + }; + + tsens_mode: mode@44f { + reg = <0x44f 0x1>; + bits = <5 3>; + }; + }; + spmi_bus: spmi@fc4cf000 { compatible = "qcom,spmi-pmic-arb"; reg-names = "core", "intr", "cnfg"; @@ -592,6 +734,11 @@ }; }; + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + rpm_msg_ram: sram@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; @@ -617,7 +764,7 @@ power-domains = <&rpmpd MSM8226_VDDCX>; power-domain-names = "cx"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; memory-region = <&adsp_region>; @@ -636,6 +783,64 @@ label = "lpass"; }; }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; timer { diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8660-surf.dts rename to arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8660.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8660.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-smp.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts similarity index 96% rename from arch/arm/boot/dts/qcom-msm8960-cdp.dts rename to arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts index 8fa2befa629a..6c1bc3818883 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts @@ -15,16 +15,12 @@ stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; - - ext_l2: gpio-regulator { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; + ext_l2: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ext_l2"; + gpio = <&msmgpio 91 0>; + startup-delay-us = <10000>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts new file mode 100644 index 000000000000..13e85c287498 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include "qcom-msm8960.dtsi" +#include + +/ { + model = "Samsung Galaxy Express SGH-I437"; + compatible = "samsung,expressatt", "qcom,msm8960"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi5_serial; + mmc0 = &sdcc1; /* SDCC1 eMMC slot */ + mmc1 = &sdcc3; /* SDCC3 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + status = "okay"; +}; + +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + vqmmc-supply = <&pm8921_l7>; + status = "okay"; +}; + +&gsbi1 { + qcom,mode = ; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1-default-state { + mosi-pins { + pins = "gpio6"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + miso-pins { + pins = "gpio7"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk-pins { + pins = "gpio9"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi similarity index 90% rename from arch/arm/boot/dts/qcom-msm8960.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 616fef2ea682..fa2013388d99 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -72,7 +73,7 @@ clock-output-names = "pxo_board"; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -371,5 +372,36 @@ status = "disabled"; }; }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + status = "disabled"; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-msm8960", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts similarity index 94% rename from arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 861695cecf84..60bdfddeae69 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -41,6 +41,25 @@ }; }; + clk_pwm: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP1_CLK>; + + pinctrl-0 = <&vibrator_pin>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <&pm8941_l19>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + }; + vreg_wlan: wlan-regulator { compatible = "regulator-fixed"; @@ -211,7 +230,11 @@ }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&pm8941_l2>; @@ -227,27 +250,23 @@ port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vddio-supply = <&pm8941_l12>; }; -&mdss { - status = "okay"; -}; - &pm8941_gpios { gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3"; @@ -635,6 +654,22 @@ function = "gpio"; }; }; + + vibrator_pin: vibrator-state { + core-pins { + pins = "gpio27"; + function = "gp1_clk"; + drive-strength = <6>; + bias-disable; + }; + + enable-pins { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &usb { diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi similarity index 98% rename from arch/arm/boot/dts/qcom-msm8974.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 7ed0d925a4e9..aeca504918a0 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -301,7 +301,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests: rpm_requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; @@ -676,7 +676,7 @@ #reset-cells = <1>; ulpi { - usb_hs1_phy: phy@a { + usb_hs1_phy: phy-0 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; @@ -687,7 +687,7 @@ status = "disabled"; }; - usb_hs2_phy: phy@b { + usb_hs2_phy: phy-1 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; @@ -707,7 +707,7 @@ clock-names = "core"; }; - pronto: remoteproc@fb21b000 { + pronto: remoteproc@fb204000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -746,7 +746,7 @@ qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; @@ -1837,10 +1837,10 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>; @@ -1905,20 +1905,20 @@ port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@fd922800 { + mdss_dsi0: dsi@fd922800 { compatible = "qcom,msm8974-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; @@ -1928,7 +1928,7 @@ interrupts = <4>; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -1945,7 +1945,7 @@ "core", "core_mmss"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1958,20 +1958,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@fd922a00 { + mdss_dsi0_phy: phy@fd922a00 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd922a00 0xd4>, <0xfd922b00 0x280>, @@ -1989,7 +1989,7 @@ status = "disabled"; }; - dsi1: dsi@fd922e00 { + mdss_dsi1: dsi@fd922e00 { compatible = "qcom,msm8974-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0xfd922e00 0x1f8>; @@ -1999,7 +1999,7 @@ interrupts = <4>; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2016,7 +2016,7 @@ "core", "core_mmss"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -2029,20 +2029,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@fd923000 { + mdss_dsi1_phy: phy@fd923000 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd923000 0xd4>, <0xfd923100 0x280>, diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts similarity index 99% rename from arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts index eb505d6d7f31..3e2c86591ee2 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts @@ -329,7 +329,15 @@ }; }; -&dsi0 { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&pma8084_l2>; @@ -351,31 +359,23 @@ port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vddio-supply = <&pma8084_l12>; }; -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &pma8084_gpios { gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio5"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts similarity index 98% rename from arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 0f650ed31005..154639d56f35 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -150,47 +150,48 @@ bl-name = "backlight"; dev-ctrl = /bits/ 8 <0x05>; init-brt = /bits/ 8 <0x3f>; - rom_a0h { + + rom-a0h { rom-addr = /bits/ 8 <0xa0>; rom-val = /bits/ 8 <0xff>; }; - rom_a1h { + rom-a1h { rom-addr = /bits/ 8 <0xa1>; rom-val = /bits/ 8 <0x3f>; }; - rom_a2h { + rom-a2h { rom-addr = /bits/ 8 <0xa2>; rom-val = /bits/ 8 <0x20>; }; - rom_a3h { + rom-a3h { rom-addr = /bits/ 8 <0xa3>; rom-val = /bits/ 8 <0x5e>; }; - rom_a4h { + rom-a4h { rom-addr = /bits/ 8 <0xa4>; rom-val = /bits/ 8 <0x02>; }; - rom_a5h { + rom-a5h { rom-addr = /bits/ 8 <0xa5>; rom-val = /bits/ 8 <0x04>; }; - rom_a6h { + rom-a6h { rom-addr = /bits/ 8 <0xa6>; rom-val = /bits/ 8 <0x80>; }; - rom_a7h { + rom-a7h { rom-addr = /bits/ 8 <0xa7>; rom-val = /bits/ 8 <0xf7>; }; - rom_a9h { + rom-a9h { rom-addr = /bits/ 8 <0xa9>; rom-val = /bits/ 8 <0x80>; }; - rom_aah { + rom-aah { rom-addr = /bits/ 8 <0xaa>; rom-val = /bits/ 8 <0x0f>; }; - rom_aeh { + rom-aeh { rom-addr = /bits/ 8 <0xae>; rom-val = /bits/ 8 <0x0f>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi similarity index 81% rename from arch/arm/boot/dts/qcom-pm8226.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8226.dtsi index 46ba84f86c9f..3b8ad28cecb0 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi @@ -4,6 +4,36 @@ #include #include +/ { + thermal-zones { + pm8226-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8226_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8226_0: pm8226@0 { compatible = "qcom,pm8226", "qcom,spmi-pmic"; @@ -55,6 +85,15 @@ chg_otg: otg-vbus { }; }; + pm8226_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8226_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + pm8226_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi similarity index 62% rename from arch/arm/boot/dts/qcom-pm8841.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8841.dtsi index b5cdde034d18..3bf2ce5c86a6 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi @@ -2,6 +2,37 @@ #include #include + +/ { + thermal-zones { + pm8841-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8841_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <140000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8841_0: pm8841@4 { @@ -20,7 +51,7 @@ #interrupt-cells = <2>; }; - temp-alarm@2400 { + pm8841_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi similarity index 91% rename from arch/arm/boot/dts/qcom-pm8941.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8941.dtsi index a821f0368a28..b3e246bacd78 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi @@ -3,6 +3,37 @@ #include #include + +/ { + thermal-zones { + pm8941-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8941_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8941_0: pm8941@0 { diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pma8084.dtsi rename to arch/arm/boot/dts/qcom/qcom-pma8084.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pmx55.dtsi rename to arch/arm/boot/dts/qcom/qcom-pmx55.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pmx65.dtsi rename to arch/arm/boot/dts/qcom/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-t55.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi similarity index 99% rename from arch/arm/boot/dts/qcom-sdx55.dtsi rename to arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 342c3d14001e..df3cd9c4ffb9 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -421,6 +421,10 @@ ; interrupt-names = "global", "doorbell"; + + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "pcie-mem"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; @@ -515,7 +519,7 @@ #hwlock-cells = <1>; }; - tcsr: syscon@1fcb000 { + tcsr: syscon@1fc0000 { compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; @@ -792,7 +796,7 @@ }; }; - apps_rsc: rsc@17840000 { + apps_rsc: rsc@17830000 { compatible = "qcom,rpmh-rsc"; reg = <0x17830000 0x10000>, <0x17840000 0x10000>; reg-names = "drv-0", "drv-1"; diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts similarity index 89% rename from arch/arm/boot/dts/qcom-sdx65-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts index 57bc3b03d3aa..02d8d6e241ae 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -250,6 +250,25 @@ status = "okay"; }; +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; @@ -274,6 +293,29 @@ status = "okay"; }; +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi similarity index 89% rename from arch/arm/boot/dts/qcom-sdx65.dtsi rename to arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 525dd8a1f664..1a3583029a64 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -295,12 +296,98 @@ status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + ipa: ipa@3f40000 { compatible = "qcom,sdx65-ipa"; diff --git a/arch/arm/boot/dts/realtek/Makefile b/arch/arm/boot/dts/realtek/Makefile new file mode 100644 index 000000000000..c83671b5560f --- /dev/null +++ b/arch/arm/boot/dts/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-horseradish.dtb \ + rtd1195-mele-x1000.dtb diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/realtek/rtd1195-horseradish.dts similarity index 100% rename from arch/arm/boot/dts/rtd1195-horseradish.dts rename to arch/arm/boot/dts/realtek/rtd1195-horseradish.dts diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts similarity index 100% rename from arch/arm/boot/dts/rtd1195-mele-x1000.dts rename to arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/realtek/rtd1195.dtsi similarity index 100% rename from arch/arm/boot/dts/rtd1195.dtsi rename to arch/arm/boot/dts/realtek/rtd1195.dtsi diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..833a02447ecf --- /dev/null +++ b/arch/arm/boot/dts/renesas/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RENESAS) += \ + emev2-kzm9d.dtb \ + r7s72100-genmai.dtb \ + r7s72100-gr-peach.dtb \ + r7s72100-rskrza1.dtb \ + r7s9210-rza2mevb.dtb \ + r8a73a4-ape6evm.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ + r8a7742-iwg21d-q7-dbcm-ca.dtb \ + r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ + r8a7743-sk-rzg1m.dtb \ + r8a7744-iwg20d-q7.dtb \ + r8a7744-iwg20d-q7-dbcm-ca.dtb \ + r8a7745-iwg22d-sodimm.dtb \ + r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ + r8a7745-sk-rzg1e.dtb \ + r8a77470-iwg23s-sbc.dtb \ + r8a7778-bockw.dtb \ + r8a7779-marzen.dtb \ + r8a7790-lager.dtb \ + r8a7790-stout.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ + r8a7792-wheat.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb \ + r9a06g032-rzn1d400-db.dtb \ + sh73a0-kzm9g.dtb diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/renesas/emev2-kzm9d.dts similarity index 100% rename from arch/arm/boot/dts/emev2-kzm9d.dts rename to arch/arm/boot/dts/renesas/emev2-kzm9d.dts diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/renesas/emev2.dtsi similarity index 100% rename from arch/arm/boot/dts/emev2.dtsi rename to arch/arm/boot/dts/renesas/emev2.dtsi diff --git a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi similarity index 100% rename from arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi rename to arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi similarity index 99% rename from arch/arm/boot/dts/iwg20d-q7-common.dtsi rename to arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi index 03caea6fc6ff..4351c5a02fa5 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi @@ -49,7 +49,7 @@ lcd_backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; + pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi similarity index 100% rename from arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi rename to arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-genmai.dts rename to arch/arm/boot/dts/renesas/r7s72100-genmai.dts diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-gr-peach.dts rename to arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-rskrza1.dts rename to arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi similarity index 100% rename from arch/arm/boot/dts/r7s72100.dtsi rename to arch/arm/boot/dts/renesas/r7s72100.dtsi diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts similarity index 100% rename from arch/arm/boot/dts/r7s9210-rza2mevb.dts rename to arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/renesas/r7s9210.dtsi similarity index 100% rename from arch/arm/boot/dts/r7s9210.dtsi rename to arch/arm/boot/dts/renesas/r7s9210.dtsi diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts similarity index 100% rename from arch/arm/boot/dts/r8a73a4-ape6evm.dts rename to arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a73a4.dtsi rename to arch/arm/boot/dts/renesas/r8a73a4.dtsi diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts similarity index 100% rename from arch/arm/boot/dts/r8a7740-armadillo800eva.dts rename to arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7740.dtsi rename to arch/arm/boot/dts/renesas/r8a7740.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21m.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742.dtsi rename to arch/arm/boot/dts/renesas/r8a7742.dtsi diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20m.dtsi rename to arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-sk-rzg1m.dts rename to arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7743.dtsi rename to arch/arm/boot/dts/renesas/r8a7743.dtsi diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20m.dtsi rename to arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7744.dtsi rename to arch/arm/boot/dts/renesas/r8a7744.dtsi diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts rename to arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts rename to arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22m.dtsi rename to arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-sk-rzg1e.dts rename to arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7745.dtsi rename to arch/arm/boot/dts/renesas/r8a7745.dtsi diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts similarity index 100% rename from arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts rename to arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a77470.dtsi rename to arch/arm/boot/dts/renesas/r8a77470.dtsi diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts similarity index 100% rename from arch/arm/boot/dts/r8a7778-bockw.dts rename to arch/arm/boot/dts/renesas/r8a7778-bockw.dts diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7778.dtsi rename to arch/arm/boot/dts/renesas/r8a7778.dtsi diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts similarity index 100% rename from arch/arm/boot/dts/r8a7779-marzen.dts rename to arch/arm/boot/dts/renesas/r8a7779-marzen.dts diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7779.dtsi rename to arch/arm/boot/dts/renesas/r8a7779.dtsi diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts similarity index 100% rename from arch/arm/boot/dts/r8a7790-lager.dts rename to arch/arm/boot/dts/renesas/r8a7790-lager.dts diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts similarity index 100% rename from arch/arm/boot/dts/r8a7790-stout.dts rename to arch/arm/boot/dts/renesas/r8a7790-stout.dts diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7790.dtsi rename to arch/arm/boot/dts/renesas/r8a7790.dtsi diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts similarity index 100% rename from arch/arm/boot/dts/r8a7791-koelsch.dts rename to arch/arm/boot/dts/renesas/r8a7791-koelsch.dts diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts similarity index 100% rename from arch/arm/boot/dts/r8a7791-porter.dts rename to arch/arm/boot/dts/renesas/r8a7791-porter.dts diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7791.dtsi rename to arch/arm/boot/dts/renesas/r8a7791.dtsi diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts similarity index 100% rename from arch/arm/boot/dts/r8a7792-blanche.dts rename to arch/arm/boot/dts/renesas/r8a7792-blanche.dts diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts similarity index 100% rename from arch/arm/boot/dts/r8a7792-wheat.dts rename to arch/arm/boot/dts/renesas/r8a7792-wheat.dts diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7792.dtsi rename to arch/arm/boot/dts/renesas/r8a7792.dtsi diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts similarity index 100% rename from arch/arm/boot/dts/r8a7793-gose.dts rename to arch/arm/boot/dts/renesas/r8a7793-gose.dts diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7793.dtsi rename to arch/arm/boot/dts/renesas/r8a7793.dtsi diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts similarity index 100% rename from arch/arm/boot/dts/r8a7794-alt.dts rename to arch/arm/boot/dts/renesas/r8a7794-alt.dts diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts similarity index 100% rename from arch/arm/boot/dts/r8a7794-silk.dts rename to arch/arm/boot/dts/renesas/r8a7794-silk.dts diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7794.dtsi rename to arch/arm/boot/dts/renesas/r8a7794.dtsi diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi rename to arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts similarity index 100% rename from arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts rename to arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi similarity index 100% rename from arch/arm/boot/dts/r9a06g032.dtsi rename to arch/arm/boot/dts/renesas/r9a06g032.dtsi diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts similarity index 100% rename from arch/arm/boot/dts/sh73a0-kzm9g.dts rename to arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/renesas/sh73a0.dtsi similarity index 100% rename from arch/arm/boot/dts/sh73a0.dtsi rename to arch/arm/boot/dts/renesas/sh73a0.dtsi diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile new file mode 100644 index 000000000000..0f46e18fe275 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1108-elgin-r1.dtb \ + rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ + rk3036-evb.dtb \ + rk3036-kylin.dtb \ + rk3066a-bqcurie2.dtb \ + rk3066a-marsboard.dtb \ + rk3066a-mk808.dtb \ + rk3066a-rayeager.dtb \ + rk3128-evb.dtb \ + rk3188-bqedison2qc.dtb \ + rk3188-px3-evb.dtb \ + rk3188-radxarock.dtb \ + rk3228-evb.dtb \ + rk3229-evb.dtb \ + rk3229-xms6.dtb \ + rk3288-evb-act8846.dtb \ + rk3288-evb-rk808.dtb \ + rk3288-firefly-beta.dtb \ + rk3288-firefly.dtb \ + rk3288-firefly-reload.dtb \ + rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ + rk3288-popmetal.dtb \ + rk3288-r89.dtb \ + rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ + rk3288-tinker.dtb \ + rk3288-tinker-s.dtb \ + rk3288-veyron-brain.dtb \ + rk3288-veyron-fievel.dtb \ + rk3288-veyron-jaq.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-mighty.dtb \ + rk3288-veyron-minnie.dtb \ + rk3288-veyron-pinky.dtb \ + rk3288-veyron-speedy.dtb \ + rk3288-veyron-tiger.dtb \ + rk3288-vyasa.dtb diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3036-evb.dts rename to arch/arm/boot/dts/rockchip/rk3036-evb.dts diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts similarity index 100% rename from arch/arm/boot/dts/rk3036-kylin.dts rename to arch/arm/boot/dts/rockchip/rk3036-kylin.dts diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3036.dtsi rename to arch/arm/boot/dts/rockchip/rk3036.dtsi diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-bqcurie2.dts rename to arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts index 962b4d1291db..f924d4d64c3d 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts @@ -159,7 +159,7 @@ }; /* must be included after &tps gets defined */ -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &mmc0 { /* sdmmc */ status = "okay"; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-marsboard.dts rename to arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index 8beecd628282..f6e8d49a02ef 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -147,7 +147,7 @@ }; /* must be included after &tps gets defined */ -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &emac { phy = <&phy0>; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts similarity index 100% rename from arch/arm/boot/dts/rk3066a-mk808.dts rename to arch/arm/boot/dts/rockchip/rk3066a-mk808.dts diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-rayeager.dts rename to arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts index 3eee42137b6d..29d8e5bf88f5 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts @@ -296,7 +296,7 @@ }; }; -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &i2c2 { status = "okay"; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3066a.dtsi rename to arch/arm/boot/dts/rockchip/rk3066a.dtsi diff --git a/arch/arm/boot/dts/rk3128-evb.dts b/arch/arm/boot/dts/rockchip/rk3128-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3128-evb.dts rename to arch/arm/boot/dts/rockchip/rk3128-evb.dts diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3128.dtsi rename to arch/arm/boot/dts/rockchip/rk3128.dtsi diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-bqedison2qc.dts rename to arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-px3-evb.dts rename to arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-radxarock.dts rename to arch/arm/boot/dts/rockchip/rk3188-radxarock.dts diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3188.dtsi rename to arch/arm/boot/dts/rockchip/rk3188.dtsi diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rockchip/rk3228-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3228-evb.dts rename to arch/arm/boot/dts/rockchip/rk3228-evb.dts diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rockchip/rk3229-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3229-evb.dts rename to arch/arm/boot/dts/rockchip/rk3229-evb.dts diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rockchip/rk3229-xms6.dts similarity index 100% rename from arch/arm/boot/dts/rk3229-xms6.dts rename to arch/arm/boot/dts/rockchip/rk3229-xms6.dts diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rockchip/rk3229.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3229.dtsi rename to arch/arm/boot/dts/rockchip/rk3229.dtsi diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi similarity index 100% rename from arch/arm/boot/dts/rk322x.dtsi rename to arch/arm/boot/dts/rockchip/rk322x.dtsi diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-evb-act8846.dts rename to arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-evb-rk808.dts rename to arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-evb.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-evb.dtsi diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-beta.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-reload.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly.dts diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-miqi.dts rename to arch/arm/boot/dts/rockchip/rk3288-miqi.dts diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-phycore-rdk.dts rename to arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-phycore-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rockchip/rk3288-popmetal.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-popmetal.dts rename to arch/arm/boot/dts/rockchip/rk3288-popmetal.dts diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rockchip/rk3288-r89.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-r89.dts rename to arch/arm/boot/dts/rockchip/rk3288-r89.dts diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts similarity index 86% rename from arch/arm/boot/dts/rk3288-rock-pi-n8.dts rename to arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts index b19593021713..673466d264be 100644 --- a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288.dtsi" -#include +#include #include "rk3288-vmarc-som.dtsi" / { diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-rock2-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-rock2-square.dts rename to arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker-s.dts rename to arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker.dts rename to arch/arm/boot/dts/rockchip/rk3288-tinker.dts diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-brain.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 700bb548d6b2..092316be67f7 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -181,4 +181,4 @@ }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-edp.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-fievel.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-jaq.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts index 4a148cf1defc..0d4c50e05558 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Jaq"; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-jerry.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts index 2c916c50dda5..6894763979f0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Jerry"; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-mickey.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-mighty.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-minnie.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts similarity index 98% rename from arch/arm/boot/dts/rk3288-veyron-pinky.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts index e2a4e6232eb5..6337238891eb 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Pinky"; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-speedy.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts index 4a3ea934d03e..336cd2be5265 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" #include "rk3288-veyron-broadcom-bluetooth.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Speedy"; diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-tiger.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-vmarc-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rockchip/rk3288-vyasa.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-vyasa.dts rename to arch/arm/boot/dts/rockchip/rk3288-vyasa.dts diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288.dtsi rename to arch/arm/boot/dts/rockchip/rk3288.dtsi diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3xxx.dtsi rename to arch/arm/boot/dts/rockchip/rk3xxx.dtsi diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi similarity index 100% rename from arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi rename to arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts similarity index 100% rename from arch/arm/boot/dts/rv1108-elgin-r1.dts rename to arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rockchip/rv1108-evb.dts similarity index 100% rename from arch/arm/boot/dts/rv1108-evb.dts rename to arch/arm/boot/dts/rockchip/rv1108-evb.dts diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1108.dtsi rename to arch/arm/boot/dts/rockchip/rv1108.dtsi diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts similarity index 100% rename from arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts rename to arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi rename to arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126-pinctrl.dtsi rename to arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126.dtsi rename to arch/arm/boot/dts/rockchip/rv1126.dtsi diff --git a/arch/arm/boot/dts/samsung/Makefile b/arch/arm/boot/dts/samsung/Makefile new file mode 100644 index 000000000000..c8d067abdd59 --- /dev/null +++ b/arch/arm/boot/dts/samsung/Makefile @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_EXYNOS3) += \ + exynos3250-artik5-eval.dtb \ + exynos3250-monk.dtb \ + exynos3250-rinato.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += \ + exynos4210-i9100.dtb \ + exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos4210-trats.dtb \ + exynos4210-universal_c210.dtb \ + exynos4412-i9300.dtb \ + exynos4412-i9305.dtb \ + exynos4412-itop-elite.dtb \ + exynos4412-n710x.dtb \ + exynos4412-odroidu3.dtb \ + exynos4412-odroidx.dtb \ + exynos4412-odroidx2.dtb \ + exynos4412-origen.dtb \ + exynos4412-p4note-n8010.dtb \ + exynos4412-smdk4412.dtb \ + exynos4412-tiny4412.dtb \ + exynos4412-trats2.dtb +dtb-$(CONFIG_ARCH_EXYNOS5) += \ + exynos5250-arndale.dtb \ + exynos5250-smdk5250.dtb \ + exynos5250-snow.dtb \ + exynos5250-snow-rev5.dtb \ + exynos5250-spring.dtb \ + exynos5260-xyref5260.dtb \ + exynos5410-odroidxu.dtb \ + exynos5410-smdk5410.dtb \ + exynos5420-arndale-octa.dtb \ + exynos5420-peach-pit.dtb \ + exynos5420-smdk5420.dtb \ + exynos5420-chagall-wifi.dtb \ + exynos5420-klimt-wifi.dtb \ + exynos5422-odroidhc1.dtb \ + exynos5422-odroidxu3.dtb \ + exynos5422-odroidxu3-lite.dtb \ + exynos5422-odroidxu4.dtb \ + exynos5422-samsung-k3g.dtb \ + exynos5800-peach-pi.dtb +dtb-$(CONFIG_ARCH_S3C64XX) += \ + s3c6410-mini6410.dtb \ + s3c6410-smdk6410.dtb +dtb-$(CONFIG_ARCH_S5PV210) += \ + s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ + s5pv210-galaxys.dtb \ + s5pv210-goni.dtb \ + s5pv210-smdkc110.dtb \ + s5pv210-smdkv210.dtb \ + s5pv210-torbreck.dtb diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi rename to arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/samsung/exynos-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/exynos-pinctrl.h rename to arch/arm/boot/dts/samsung/exynos-pinctrl.h diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos-syscon-restart.dtsi rename to arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-artik5-eval.dts rename to arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos3250-artik5.dtsi rename to arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/samsung/exynos3250-monk.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-monk.dts rename to arch/arm/boot/dts/samsung/exynos3250-monk.dts diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos3250-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi index 011ba2eff29e..07828551d4b3 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2014 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-rinato.dts rename to arch/arm/boot/dts/samsung/exynos3250-rinato.dts diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/samsung/exynos3250.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos3250.dtsi rename to arch/arm/boot/dts/samsung/exynos3250.dtsi index bd37f1b587f0..3f1015edab43 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos3250.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4-cpu-thermal.dtsi rename to arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4.dtsi rename to arch/arm/boot/dts/samsung/exynos4.dtsi index 8dd6976ab0a7..f775b9377a38 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4.dtsi @@ -9,7 +9,7 @@ * * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular * SoCs from Exynos4 series can include this file and provide values for SoCs - * specfic bindings. + * specific bindings. * * Note: This file does not include device nodes for all the controllers in * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional @@ -201,8 +201,8 @@ #size-cells = <0>; }; - camera: camera { - compatible = "samsung,fimc", "simple-bus"; + camera: camera@11800000 { + compatible = "samsung,fimc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-i9100.dts rename to arch/arm/boot/dts/samsung/exynos4210-i9100.dts diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/samsung/exynos4210-origen.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-origen.dts rename to arch/arm/boot/dts/samsung/exynos4210-origen.dts diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4210-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi index 76f44ae0de46..70d268f9fcb1 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi @@ -7,8 +7,8 @@ * Copyright (c) 2011-2012 Linaro Ltd. * www.linaro.org * - * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-smdkv310.dts rename to arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/samsung/exynos4210-trats.dts similarity index 99% rename from arch/arm/boot/dts/exynos4210-trats.dts rename to arch/arm/boot/dts/samsung/exynos4210-trats.dts index ff6ee4b2c31b..bfb04b31e11b 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-trats.dts @@ -150,8 +150,6 @@ }; &camera { - pinctrl-names = "default"; - pinctrl-0 = <>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts similarity index 99% rename from arch/arm/boot/dts/exynos4210-universal_c210.dts rename to arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts index 8fe0d5d2be2d..c84af3d27c1c 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts @@ -197,9 +197,6 @@ &camera { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <>; }; &cpu0 { diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/samsung/exynos4210.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4210.dtsi rename to arch/arm/boot/dts/samsung/exynos4210.dtsi diff --git a/arch/arm/boot/dts/samsung/exynos4212.dtsi b/arch/arm/boot/dts/samsung/exynos4212.dtsi new file mode 100644 index 000000000000..aa984601ee06 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4212", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4212-clock"; +}; + +&combiner { + samsung,combiner-nr = <18>; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon"; +}; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/samsung/exynos4412-i9300.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-i9300.dts rename to arch/arm/boot/dts/samsung/exynos4412-i9300.dts diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/samsung/exynos4412-i9305.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-i9305.dts rename to arch/arm/boot/dts/samsung/exynos4412-i9305.dts diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-itop-elite.dts rename to arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-midas.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-midas.dtsi diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-n710x.dts rename to arch/arm/boot/dts/samsung/exynos4412-n710x.dts diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4412-odroid-common.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi index 45ef7b7ba7e0..93ddbd4b0a18 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi @@ -122,8 +122,6 @@ &camera { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; }; &clock { diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidu3.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidx.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidx.dts diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidx2.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/samsung/exynos4412-origen.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-origen.dts rename to arch/arm/boot/dts/samsung/exynos4412-origen.dts diff --git a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-p4note-n8010.dts rename to arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-p4note.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-ppmu-common.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/samsung/exynos4412-prime.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-prime.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-prime.dtsi diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-smdk4412.dts rename to arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-tiny4412.dts rename to arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/samsung/exynos4412-trats2.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-trats2.dts rename to arch/arm/boot/dts/samsung/exynos4412-trats2.dts diff --git a/arch/arm/boot/dts/samsung/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi new file mode 100644 index 000000000000..dcbe0ce6180f --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4412.dtsi @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu2: cpu@a02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa02>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu3: cpu@a03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa03>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4412-clock"; +}; + +&combiner { + samsung,combiner-nr = <20>; +}; + +&gic { + cpu-offset = <0x4000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; +}; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4412-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi index 8ab31c3daa48..04935fbe2f2a 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4x12.dtsi similarity index 81% rename from arch/arm/boot/dts/exynos4412.dtsi rename to arch/arm/boot/dts/samsung/exynos4x12.dtsi index 82a36fb5ee8b..84c1db221c98 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4x12.dtsi @@ -5,12 +5,12 @@ * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 - * based board files can include this file and provide values for board specfic - * bindings. + * Samsung's Exynos4x12 SoC series device nodes are listed in this file. + * Particular SoCs from Exynos4x12 series can include this file and provide + * values for SoCs specific bindings. * * Note: This file does not include device nodes for all the controllers in - * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional * nodes can be added to this file. */ @@ -19,8 +19,6 @@ #include "exynos4-cpu-thermal.dtsi" / { - compatible = "samsung,exynos4412", "samsung,exynos4"; - aliases { pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; @@ -158,146 +156,6 @@ status = "disabled"; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - opp-suspend; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - cpu0_opp_1500: opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; - bus_dmc_opp_table: opp-table-1 { compatible = "operating-points-v2"; @@ -421,7 +279,6 @@ }; clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x18000>; #clock-cells = <1>; }; @@ -571,7 +428,6 @@ }; &combiner { - samsung,combiner-nr = <20>; interrupts = , , , @@ -719,10 +575,6 @@ samsung,lcd-wb; }; -&gic { - cpu-offset = <0x4000>; -}; - &gpu { interrupts = , , @@ -790,14 +642,7 @@ interconnects = <&bus_display &bus_dmc>; }; -&pmu { - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - &pmu_system_controller { - compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, @@ -816,4 +661,4 @@ status = "disabled"; }; -#include "exynos4412-pinctrl.dtsi" +#include "exynos4x12-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/samsung/exynos5.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5.dtsi rename to arch/arm/boot/dts/samsung/exynos5.dtsi index 48e43b6b3213..4a17a19586bb 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5.dtsi @@ -7,7 +7,7 @@ * * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular * SoCs from Exynos5 series can include this file and provide values for SoCs - * specfic bindings. + * specific bindings. */ #include diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/samsung/exynos5250-arndale.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-arndale.dts rename to arch/arm/boot/dts/samsung/exynos5250-arndale.dts diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5250-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi index 48732edadff1..d956540a2d88 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-smdk5250.dts rename to arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5250-snow-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi index 59b2cc35c37b..c82e2762e07c 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -715,4 +715,4 @@ vbus-supply = <&usb3_vbus_reg>; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-snow-rev5.dts rename to arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/samsung/exynos5250-snow.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-snow.dts rename to arch/arm/boot/dts/samsung/exynos5250-snow.dts diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/samsung/exynos5250-spring.dts similarity index 99% rename from arch/arm/boot/dts/exynos5250-spring.dts rename to arch/arm/boot/dts/samsung/exynos5250-spring.dts index c12bb17631b7..d126fccdcaf3 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-spring.dts @@ -564,4 +564,4 @@ vdd33-supply = <&ldo12_reg>; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5250.dtsi rename to arch/arm/boot/dts/samsung/exynos5250.dtsi index 1a4c6c028d03..99c84bebf25a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5250 SoC device nodes are listed in this file. * Exynos5250 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. * * Note: This file does not include device nodes for all the controllers in * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5260-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi index 43e4a541f479..d15494b4bda9 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts similarity index 100% rename from arch/arm/boot/dts/exynos5260-xyref5260.dts rename to arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/samsung/exynos5260.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5260.dtsi rename to arch/arm/boot/dts/samsung/exynos5260.dtsi diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts similarity index 100% rename from arch/arm/boot/dts/exynos5410-odroidxu.dts rename to arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5410-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts similarity index 100% rename from arch/arm/boot/dts/exynos5410-smdk5410.dts rename to arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/samsung/exynos5410.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5410.dtsi rename to arch/arm/boot/dts/samsung/exynos5410.dtsi index 350b8afa0a3a..546035e78f40 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5410.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5410 SoC device nodes are listed in this file. * Exynos5410 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos54xx.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-arndale-octa.dts rename to arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts diff --git a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-chagall-wifi.dts rename to arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-cpus.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi diff --git a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-klimt-wifi.dts rename to arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts similarity index 99% rename from arch/arm/boot/dts/exynos5420-peach-pit.dts rename to arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts index 7a48f2b32819..4e757b6e28e1 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -1122,5 +1122,5 @@ timeout-sec = <32>; }; -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5420-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi index 14cf9c4ca0ed..93b9873fa84f 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-smdk5420.dts rename to arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-trip-points.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/samsung/exynos5420.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5420.dtsi rename to arch/arm/boot/dts/samsung/exynos5420.dtsi index dd291f1199f2..25ed90374679 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5420.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5420 SoC device nodes are listed in this file. * Exynos5420 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos54xx.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-cpus.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroid-core.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidhc1.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu4.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-samsung-k3g.dts rename to arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi rename to arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/samsung/exynos54xx.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos54xx.dtsi rename to arch/arm/boot/dts/samsung/exynos54xx.dtsi diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts similarity index 99% rename from arch/arm/boot/dts/exynos5800-peach-pi.dts rename to arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts index 1f544f12da6c..f91bc4ae008e 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -1104,5 +1104,5 @@ timeout-sec = <32>; }; -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/samsung/exynos5800.dtsi similarity index 98% rename from arch/arm/boot/dts/exynos5800.dtsi rename to arch/arm/boot/dts/samsung/exynos5800.dtsi index 8328ddb3b02f..72d3a3535a7a 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5800.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5800 SoC device nodes are listed in this file. * Exynos5800 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos5420.dtsi" diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/samsung/s3c6400.dtsi similarity index 98% rename from arch/arm/boot/dts/s3c6400.dtsi rename to arch/arm/boot/dts/samsung/s3c6400.dtsi index 8c28e8a0c824..7cc785a63866 100644 --- a/arch/arm/boot/dts/s3c6400.dtsi +++ b/arch/arm/boot/dts/samsung/s3c6400.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Tomasz Figa * * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts similarity index 100% rename from arch/arm/boot/dts/s3c6410-mini6410.dts rename to arch/arm/boot/dts/samsung/s3c6410-mini6410.dts diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts similarity index 100% rename from arch/arm/boot/dts/s3c6410-smdk6410.dts rename to arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/samsung/s3c6410.dtsi similarity index 98% rename from arch/arm/boot/dts/s3c6410.dtsi rename to arch/arm/boot/dts/samsung/s3c6410.dtsi index a766d6de696c..13e9cc69b8a8 100644 --- a/arch/arm/boot/dts/s3c6410.dtsi +++ b/arch/arm/boot/dts/samsung/s3c6410.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Tomasz Figa * * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/s3c64xx-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/s3c64xx-pinctrl.h rename to arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/samsung/s3c64xx.dtsi similarity index 99% rename from arch/arm/boot/dts/s3c64xx.dtsi rename to arch/arm/boot/dts/samsung/s3c64xx.dtsi index c03df6355500..0b59135ffe88 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/samsung/s3c64xx.dtsi @@ -6,7 +6,7 @@ * * Samsung's S3C64xx SoC series device nodes are listed in this file. * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. + * values for SoCs specific bindings. * * Note: This file does not include device nodes for all the controllers in * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/samsung/s5pv210-aquila.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-aquila.dts rename to arch/arm/boot/dts/samsung/s5pv210-aquila.dts diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi similarity index 100% rename from arch/arm/boot/dts/s5pv210-aries.dtsi rename to arch/arm/boot/dts/samsung/s5pv210-aries.dtsi diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-fascinate4g.dts rename to arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-galaxys.dts rename to arch/arm/boot/dts/samsung/s5pv210-galaxys.dts diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/samsung/s5pv210-goni.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-goni.dts rename to arch/arm/boot/dts/samsung/s5pv210-goni.dts diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi similarity index 98% rename from arch/arm/boot/dts/s5pv210-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi index 6d6daef9fb7a..af740abd9e0f 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi @@ -1,25 +1,21 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Samsung's S5PV210 SoC device tree source + * Samsung's S5PV210 SoC device tree source - pin control-related + * definitions * * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. * * Mateusz Krawczuk * Tomasz Figa * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. + * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are + * listed as device tree nodes in this file. */ #include "s5pv210-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = ; \ samsung,pin-pud-pdn = ; \ diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/s5pv210-pinctrl.h rename to arch/arm/boot/dts/samsung/s5pv210-pinctrl.h diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-smdkc110.dts rename to arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts similarity index 95% rename from arch/arm/boot/dts/s5pv210-smdkv210.dts rename to arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts index fbae768d65e2..6e26c67e0a26 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts @@ -55,6 +55,14 @@ default-brightness-level = <6>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_out>; + power-supply = <&dc5v_reg>; + }; + + dc5v_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "DC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/samsung/s5pv210-torbreck.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-torbreck.dts rename to arch/arm/boot/dts/samsung/s5pv210-torbreck.dts diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi similarity index 98% rename from arch/arm/boot/dts/s5pv210.dtsi rename to arch/arm/boot/dts/samsung/s5pv210.dtsi index 1a9e4a96b2ff..f7de5b5f2f38 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -8,7 +8,7 @@ * Tomasz Figa * * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in @@ -401,7 +401,7 @@ status = "disabled"; }; - hsotg: hsotg@ec000000 { + hsotg: usb@ec000000 { compatible = "samsung,s3c6400-hsotg"; reg = <0xec000000 0x20000>; interrupt-parent = <&vic1>; @@ -452,8 +452,8 @@ reg = <0xf1700000 0x10000>; interrupt-parent = <&vic2>; interrupts = <14>; - clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>; - clock-names = "sclk_mfc", "mfc"; + clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>; + clock-names = "mfc", "sclk_mfc"; }; vic0: interrupt-controller@f2000000 { @@ -547,10 +547,8 @@ status = "disabled"; }; - camera: camera { - compatible = "samsung,fimc", "simple-bus"; - pinctrl-names = "default"; - pinctrl-0 = <>; + camera: camera@fa600000 { + compatible = "samsung,fimc"; clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; clock-names = "sclk_cam0", "sclk_cam1"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sigmastar/Makefile b/arch/arm/boot/dts/sigmastar/Makefile new file mode 100644 index 000000000000..b07eaf5d8add --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MSTARV7) += \ + mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ + mstar-infinity2m-ssd202d-miyoo-mini.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ + mstar-infinity2m-ssd202d-unitv2.dtb \ + mstar-infinity3-msc313e-breadbee.dtb \ + mstar-mercury5-ssc8336n-midrived08.dtb diff --git a/arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-msc313.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts rename to arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-v7.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-v7.dtsi diff --git a/arch/arm/boot/dts/socionext/Makefile b/arch/arm/boot/dts/socionext/Makefile new file mode 100644 index 000000000000..dab4275f6bd6 --- /dev/null +++ b/arch/arm/boot/dts/socionext/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pro5-epcore.dtb \ + uniphier-pro5-proex.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld8-ref.dtb diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts similarity index 100% rename from arch/arm/boot/dts/milbeaut-m10v-evb.dts rename to arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi similarity index 100% rename from arch/arm/boot/dts/milbeaut-m10v.dtsi rename to arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-ld4-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld4.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ld4.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ld4.dtsi diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-ld6b-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ld6b.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pinctrl.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-ace.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-sanji.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro4.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pro4.dtsi diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5-epcore.dts rename to arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts diff --git a/arch/arm/boot/dts/uniphier-pro5-proex.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5-proex.dts rename to arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pro5.dtsi diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2-gentil.dts rename to arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2-vodka.dts rename to arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ref-daughter.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-sld8-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/socionext/uniphier-sld8.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-sld8.dtsi rename to arch/arm/boot/dts/socionext/uniphier-sld8.dtsi diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/socionext/uniphier-support-card.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-support-card.dtsi rename to arch/arm/boot/dts/socionext/uniphier-support-card.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile new file mode 100644 index 000000000000..b3e9d29390e3 --- /dev/null +++ b/arch/arm/boot/dts/st/Makefile @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NOMADIK) += \ + ste-nomadik-s8815.dtb \ + ste-nomadik-nhk15.dtb +dtb-$(CONFIG_ARCH_SPEAR13XX) += \ + spear1310-evb.dtb \ + spear1340-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR3XX) += \ + spear300-evb.dtb \ + spear310-evb.dtb \ + spear320-evb.dtb \ + spear320-hmi.dtb +dtb-$(CONFIG_ARCH_SPEAR6XX) += \ + spear600-evb.dtb +dtb-$(CONFIG_ARCH_STI) += \ + stih407-b2120.dtb \ + stih410-b2120.dtb \ + stih410-b2260.dtb \ + stih418-b2199.dtb \ + stih418-b2264.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32f429-disco.dtb \ + stm32f469-disco.dtb \ + stm32f746-disco.dtb \ + stm32f769-disco.dtb \ + stm32429i-eval.dtb \ + stm32746g-eval.dtb \ + stm32h743i-eval.dtb \ + stm32h743i-disco.dtb \ + stm32h750i-art-pi.dtb \ + stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ + stm32mp151a-dhcor-testbench.dtb \ + stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp157a-avenger96.dtb \ + stm32mp157a-dhcor-avenger96.dtb \ + stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ + stm32mp157a-iot-box.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ + stm32mp157a-stinger96.dtb \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp157c-dhcom-picoitx.dtb \ + stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ + stm32mp157c-emsbc-argon.dtb \ + stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp157c-phycore-stm32mp1-3.dtb +dtb-$(CONFIG_ARCH_U8500) += \ + ste-snowball.dtb \ + ste-hrefprev60-stuib.dtb \ + ste-hrefprev60-tvk.dtb \ + ste-hrefv60plus-stuib.dtb \ + ste-hrefv60plus-tvk.dtb \ + ste-href520-tvk.dtb \ + ste-ux500-samsung-golden.dtb \ + ste-ux500-samsung-janice.dtb \ + ste-ux500-samsung-gavini.dtb \ + ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ + ste-ux500-samsung-skomer.dtb \ + ste-ux500-samsung-kyle.dtb diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear1310-evb.dts rename to arch/arm/boot/dts/st/spear1310-evb.dts diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/st/spear1310.dtsi similarity index 100% rename from arch/arm/boot/dts/spear1310.dtsi rename to arch/arm/boot/dts/st/spear1310.dtsi diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear1340-evb.dts rename to arch/arm/boot/dts/st/spear1340-evb.dts diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/st/spear1340.dtsi similarity index 100% rename from arch/arm/boot/dts/spear1340.dtsi rename to arch/arm/boot/dts/st/spear1340.dtsi diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi similarity index 100% rename from arch/arm/boot/dts/spear13xx.dtsi rename to arch/arm/boot/dts/st/spear13xx.dtsi diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/st/spear300-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear300-evb.dts rename to arch/arm/boot/dts/st/spear300-evb.dts diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/st/spear300.dtsi similarity index 100% rename from arch/arm/boot/dts/spear300.dtsi rename to arch/arm/boot/dts/st/spear300.dtsi diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/st/spear310-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear310-evb.dts rename to arch/arm/boot/dts/st/spear310-evb.dts diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/st/spear310.dtsi similarity index 100% rename from arch/arm/boot/dts/spear310.dtsi rename to arch/arm/boot/dts/st/spear310.dtsi diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/st/spear320-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear320-evb.dts rename to arch/arm/boot/dts/st/spear320-evb.dts diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/st/spear320-hmi.dts similarity index 100% rename from arch/arm/boot/dts/spear320-hmi.dts rename to arch/arm/boot/dts/st/spear320-hmi.dts diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/st/spear320.dtsi similarity index 100% rename from arch/arm/boot/dts/spear320.dtsi rename to arch/arm/boot/dts/st/spear320.dtsi diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/st/spear320s.dtsi similarity index 100% rename from arch/arm/boot/dts/spear320s.dtsi rename to arch/arm/boot/dts/st/spear320s.dtsi diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/st/spear3xx.dtsi similarity index 100% rename from arch/arm/boot/dts/spear3xx.dtsi rename to arch/arm/boot/dts/st/spear3xx.dtsi diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/st/spear600-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear600-evb.dts rename to arch/arm/boot/dts/st/spear600-evb.dts diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/st/spear600.dtsi similarity index 100% rename from arch/arm/boot/dts/spear600.dtsi rename to arch/arm/boot/dts/st/spear600.dtsi diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st/st-pincfg.h similarity index 100% rename from arch/arm/boot/dts/st-pincfg.h rename to arch/arm/boot/dts/st/st-pincfg.h diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/st/ste-ab8500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-ab8500.dtsi rename to arch/arm/boot/dts/st/ste-ab8500.dtsi diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/st/ste-ab8505.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-ab8505.dtsi rename to arch/arm/boot/dts/st/ste-ab8505.dtsi diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/st/ste-db8500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db8500.dtsi rename to arch/arm/boot/dts/st/ste-db8500.dtsi diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/st/ste-db8520.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db8520.dtsi rename to arch/arm/boot/dts/st/ste-db8520.dtsi diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/st/ste-db9500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db9500.dtsi rename to arch/arm/boot/dts/st/ste-db9500.dtsi diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi similarity index 93% rename from arch/arm/boot/dts/ste-dbx5x0.dtsi rename to arch/arm/boot/dts/st/ste-dbx5x0.dtsi index fead7afd5517..d5d88771ef97 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi @@ -110,6 +110,74 @@ interrupt-parent = <&intc>; ranges; + /* + * 640KB ESRAM (embedded static random access memory), divided + * into 5 banks of 128 KB each. This is a fast memory usually + * used by different accelerators. We group these according to + * their power domains: ESRAM0 (always on) ESRAM 1+2 and + * ESRAM 3+4. + */ + sram@40000000 { + /* The first (always on) ESRAM 0, 128 KB */ + compatible = "mmio-sram"; + reg = <0x40000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x20000>; + + sram@0 { + compatible = "stericsson,u8500-esram"; + reg = <0x0 0x10000>; + pool; + }; + lcpa: sram@10000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Paramers (LCP), the address + * where these parameters are stored is called "LCPA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCPA"; + reg = <0x10000 0x800>; + }; + sram@10800 { + compatible = "stericsson,u8500-esram"; + reg = <0x10800 0xf800>; + pool; + }; + }; + sram@40020000 { + /* ESRAM 1+2, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x40000>; + }; + sram@40060000 { + /* ESRAM 3+4, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40060000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40060000 0x40000>; + + lcla: sram@20000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Logical Addresses (LCLA), the address + * where these parameters are stored is called "LCLA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCLA"; + reg = <0x20000 0x2000>; + }; + }; + ptm@801ae000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x801ae000 0x1000>; @@ -536,9 +604,10 @@ dma: dma-controller@801C0000 { compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - reg-names = "base", "lcpa"; + reg = <0x801C0000 0x1000>; + reg-names = "base"; interrupts = ; + sram = <&lcpa>, <&lcla>; #dma-cells = <3>; memcpy-channels = <56 57 58 59 60>; @@ -852,7 +921,7 @@ status = "disabled"; }; - serial0: uart@80120000 { + serial0: serial@80120000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80120000 0x1000>; interrupts = ; @@ -868,7 +937,7 @@ status = "disabled"; }; - serial1: uart@80121000 { + serial1: serial@80121000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80121000 0x1000>; interrupts = ; @@ -884,7 +953,7 @@ status = "disabled"; }; - serial2: uart@80007000 { + serial2: serial@80007000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80007000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi similarity index 95% rename from arch/arm/boot/dts/ste-href-ab8500.dtsi rename to arch/arm/boot/dts/st/ste-href-ab8500.dtsi index 9fa024900d53..e1de9d389a01 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi @@ -418,6 +418,24 @@ }; }; }; + /* + * Charging is not working on the HREF unless an actual battery is + * mounted, most HREFs have a DC cable in to the "battery power" + * which means this will only be cofusing. So do not enable charging + * of the HREFs. + */ + ab8500_fg { + status = "disabled"; + }; + ab8500_btemp { + status = "disabled"; + }; + ab8500_charger { + status = "disabled"; + }; + ab8500_chargalg { + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-family-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/st/ste-href-stuib.dtsi similarity index 98% rename from arch/arm/boot/dts/ste-href-stuib.dtsi rename to arch/arm/boot/dts/st/ste-href-stuib.dtsi index e32d0c36feb8..79c2be36acae 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/st/ste-href-stuib.dtsi @@ -30,12 +30,11 @@ soc { i2c@80004000 { - stmpe1601: stmpe1601@40 { + stmpe1601: port-expander@40 { compatible = "st,stmpe1601"; reg = <0x40>; interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpio6>; - interrupt-controller; vcc-supply = <&db8500_vsmps2_reg>; vio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; @@ -44,7 +43,7 @@ wakeup-source; st,autosleep-timeout = <1024>; - stmpe_keypad { + keyboard-controller { compatible = "st,stmpe-keypad"; debounce-interval = <64>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi rename to arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi rename to arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/st/ste-href.dtsi similarity index 99% rename from arch/arm/boot/dts/ste-href.dtsi rename to arch/arm/boot/dts/st/ste-href.dtsi index e716121a78ce..13b11dbeba1c 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/st/ste-href.dtsi @@ -45,7 +45,7 @@ }; soc { - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -53,13 +53,13 @@ }; /* This UART is unused and thus left disabled */ - uart@80121000 { + serial@80121000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; }; - uart@80007000 { + serial@80007000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; pinctrl-1 = <&u2rxtx_c_1_sleep>; diff --git a/arch/arm/boot/dts/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-href520-tvk.dts rename to arch/arm/boot/dts/st/ste-href520-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefprev60-stuib.dts rename to arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefprev60-tvk.dts rename to arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/st/ste-hrefprev60.dtsi similarity index 99% rename from arch/arm/boot/dts/ste-hrefprev60.dtsi rename to arch/arm/boot/dts/st/ste-hrefprev60.dtsi index 29b67abfc461..9859ee91a15e 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/st/ste-hrefprev60.dtsi @@ -17,7 +17,7 @@ soc { /* Enable UART1 on this board */ - uart@80121000 { + serial@80121000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus-stuib.dts rename to arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus-tvk.dts rename to arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus.dtsi rename to arch/arm/boot/dts/st/ste-hrefv60plus.dtsi diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts similarity index 95% rename from arch/arm/boot/dts/ste-nomadik-nhk15.dts rename to arch/arm/boot/dts/st/ste-nomadik-nhk15.dts index 4d741adc16cd..cdff33063d6f 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts @@ -99,17 +99,16 @@ pinctrl-names = "default"; reg = <0x1d>; }; - stmpe0: stmpe2401@43 { + stmpe0: port-expander@43 { compatible = "st,stmpe2401"; reg = <0x43>; reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 interrupt-parent = <&gpio2>; - interrupt-controller; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&stmpe2401_1_nhk_mode>; - stmpe_gpio43: stmpe_gpio { + stmpe_gpio43: gpio { compatible = "st,stmpe-gpio"; gpio-controller; #gpio-cells = <2>; @@ -118,7 +117,7 @@ /* Some pins in alternate functions */ st,norequest-mask = <0xf0f002>; }; - stmpe_keypad { + keyboard-controller { compatible = "st,stmpe-keypad"; debounce-interval = <64>; st,scan-count = <8>; @@ -140,22 +139,21 @@ 0x03020067 // Up 0x0303006c>; // Down }; - stmpe0_pwm: stmpe_pwm { + stmpe0_pwm: pwm { compatible = "st,stmpe-pwm"; #pwm-cells = <2>; }; }; - stmpe1: stmpe2401@44 { + stmpe1: port-expander@44 { compatible = "st,stmpe2401"; reg = <0x44>; reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 interrupt-parent = <&gpio2>; - interrupt-controller; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&stmpe2401_2_nhk_mode>; - stmpe_gpio44: stmpe_gpio { + stmpe_gpio44: gpio { compatible = "st,stmpe-gpio"; gpio-controller; #gpio-cells = <2>; @@ -165,7 +163,7 @@ * This will turn off SATA so that MMC/SD * can thrive */ - mmcsd-gpio { + mmcsd-hog { gpio-hog; gpios = <2 0x0>; output-low; @@ -190,7 +188,7 @@ }; /* Activate RX/TX and CTS/RTS on UART 0 */ - uart0: uart@101fd000 { + uart0: serial@101fd000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_nhk_mode>; status = "okay"; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts similarity index 99% rename from arch/arm/boot/dts/ste-nomadik-s8815.dts rename to arch/arm/boot/dts/st/ste-nomadik-s8815.dts index f16314ffbf4b..c905c2643a12 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts @@ -133,7 +133,7 @@ amba { /* Activate RXTX on UART 0 */ - uart0: uart@101fd000 { + uart0: serial@101fd000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_s8815_mode>; status = "okay"; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi similarity index 99% rename from arch/arm/boot/dts/ste-nomadik-stn8815.dtsi rename to arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi index 1815361fe73c..6816eef39d45 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi @@ -769,7 +769,7 @@ reg = <0x10140020 0x20>; }; - uart0: uart@101fd000 { + uart0: serial@101fd000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101fd000 0x1000>; interrupt-parent = <&vica>; @@ -782,7 +782,7 @@ dma-names = "rx", "tx"; }; - uart1: uart@101fb000 { + uart1: serial@101fb000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101fb000 0x1000>; interrupt-parent = <&vica>; @@ -796,7 +796,7 @@ dma-names = "rx", "tx"; }; - uart2: uart@101f2000 { + uart2: serial@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupt-parent = <&vica>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/st/ste-snowball.dts similarity index 99% rename from arch/arm/boot/dts/ste-snowball.dts rename to arch/arm/boot/dts/st/ste-snowball.dts index e2f0cdacba7d..9a3d6546399d 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/st/ste-snowball.dts @@ -308,7 +308,7 @@ status = "okay"; }; - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -316,13 +316,13 @@ }; /* This UART is unused and thus left disabled */ - uart@80121000 { + serial@80121000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; }; - uart@80007000 { + serial@80007000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; pinctrl-1 = <&u2rxtx_c_1_sleep>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts index e036393d5415..463942ae755e 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts @@ -369,7 +369,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -393,7 +393,7 @@ }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -403,7 +403,7 @@ }; /* Debugging console UART connected to AB8505 */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-codina.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts index 1a6d24a7ccb8..c1ae0e23fe45 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts @@ -462,7 +462,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -485,7 +485,7 @@ }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -505,7 +505,7 @@ }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-gavini.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts index 5b445fa4c8c0..b21e40da3dfd 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts @@ -417,7 +417,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -439,7 +439,7 @@ }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -449,7 +449,7 @@ }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-golden.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts index 9604695edf53..f736888474e7 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts @@ -186,7 +186,7 @@ }; /* BT UART */ - uart@80120000 { + serial@80120000 { status = "okay"; pinctrl-names = "default", "sleep"; @@ -209,7 +209,7 @@ }; /* GPF UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; @@ -218,7 +218,7 @@ }; /* Debugging console UART */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-janice.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts index e901cb76b899..6e586e875565 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts @@ -467,7 +467,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -491,7 +491,7 @@ }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -520,7 +520,7 @@ }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-kyle.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts index 45fab5283a9d..ba4421080b2a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts @@ -292,7 +292,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -310,7 +310,7 @@ }; /* GPF UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -333,7 +333,7 @@ }; /* Debugging console UART connected to AB8505 USB */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts similarity index 99% rename from arch/arm/boot/dts/ste-ux500-samsung-skomer.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts index 93e5f5ed888d..064d6fee8821 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts @@ -271,7 +271,7 @@ }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -290,7 +290,7 @@ }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -313,7 +313,7 @@ }; /* Debugging console UART connected to AB8505 USB */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/st/stih407-b2120.dts similarity index 100% rename from arch/arm/boot/dts/stih407-b2120.dts rename to arch/arm/boot/dts/st/stih407-b2120.dts diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/st/stih407-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-clock.dtsi rename to arch/arm/boot/dts/st/stih407-clock.dtsi diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-family.dtsi rename to arch/arm/boot/dts/st/stih407-family.dtsi diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-pinctrl.dtsi rename to arch/arm/boot/dts/st/stih407-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/st/stih407.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407.dtsi rename to arch/arm/boot/dts/st/stih407.dtsi diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/st/stih410-b2120.dts similarity index 100% rename from arch/arm/boot/dts/stih410-b2120.dts rename to arch/arm/boot/dts/st/stih410-b2120.dts diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/st/stih410-b2260.dts similarity index 100% rename from arch/arm/boot/dts/stih410-b2260.dts rename to arch/arm/boot/dts/st/stih410-b2260.dts diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/st/stih410-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410-clock.dtsi rename to arch/arm/boot/dts/st/stih410-clock.dtsi diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/st/stih410-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410-pinctrl.dtsi rename to arch/arm/boot/dts/st/stih410-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410.dtsi rename to arch/arm/boot/dts/st/stih410.dtsi diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/st/stih418-b2199.dts similarity index 100% rename from arch/arm/boot/dts/stih418-b2199.dts rename to arch/arm/boot/dts/st/stih418-b2199.dts diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/st/stih418-b2264.dts similarity index 100% rename from arch/arm/boot/dts/stih418-b2264.dts rename to arch/arm/boot/dts/st/stih418-b2264.dts diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/st/stih418-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih418-clock.dtsi rename to arch/arm/boot/dts/st/stih418-clock.dtsi diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi similarity index 100% rename from arch/arm/boot/dts/stih418.dtsi rename to arch/arm/boot/dts/st/stih418.dtsi diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/st/stihxxx-b2120.dtsi similarity index 100% rename from arch/arm/boot/dts/stihxxx-b2120.dtsi rename to arch/arm/boot/dts/st/stihxxx-b2120.dtsi diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32429i-eval.dts rename to arch/arm/boot/dts/st/stm32429i-eval.dts diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32746g-eval.dts rename to arch/arm/boot/dts/st/stm32746g-eval.dts diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f4-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f429-disco.dts rename to arch/arm/boot/dts/st/stm32f429-disco.dts diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f429-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32f429.dtsi rename to arch/arm/boot/dts/st/stm32f429.dtsi index 00bf53f99c29..8efcda9ef8ae 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -45,7 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts similarity index 99% rename from arch/arm/boot/dts/stm32f469-disco.dts rename to arch/arm/boot/dts/st/stm32f469-disco.dts index 5a0daf8e8b11..cbbd521bf010 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -160,7 +160,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; @@ -179,7 +179,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f469-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f469.dtsi b/arch/arm/boot/dts/st/stm32f469.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f469.dtsi rename to arch/arm/boot/dts/st/stm32f469.dtsi diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f7-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f746-disco.dts rename to arch/arm/boot/dts/st/stm32f746-disco.dts diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f746-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32f746.dtsi rename to arch/arm/boot/dts/st/stm32f746.dtsi index dc868e6da40e..d1802efd067c 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include @@ -515,7 +515,7 @@ crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f769-disco.dts rename to arch/arm/boot/dts/st/stm32f769-disco.dts diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f769-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32h7-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32h743.dtsi rename to arch/arm/boot/dts/st/stm32h743.dtsi index f30796f7adf3..b8d4c44c8a82 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include #include diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32h743i-disco.dts rename to arch/arm/boot/dts/st/stm32h743i-disco.dts diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32h743i-eval.dts rename to arch/arm/boot/dts/st/stm32h743i-eval.dts diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/st/stm32h750.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32h750.dtsi rename to arch/arm/boot/dts/st/stm32h750.dtsi diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts similarity index 99% rename from arch/arm/boot/dts/stm32h750i-art-pi.dts rename to arch/arm/boot/dts/st/stm32h750i-art-pi.dts index f3e70d3b65ac..44c307f8b09c 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -208,7 +208,7 @@ dmas = <&dmamux1 45 0x400 0x05>, <&dmamux1 46 0x400 0x05>; dma-names = "rx", "tx"; - st,hw-flow-ctrl; + uart-has-rtscts; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp131.dtsi rename to arch/arm/boot/dts/st/stm32mp131.dtsi diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp133.dtsi rename to arch/arm/boot/dts/st/stm32mp133.dtsi diff --git a/arch/arm/boot/dts/stm32mp135.dtsi b/arch/arm/boot/dts/st/stm32mp135.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp135.dtsi rename to arch/arm/boot/dts/st/stm32mp135.dtsi diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp135f-dk.dts rename to arch/arm/boot/dts/st/stm32mp135f-dk.dts diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13xc.dtsi rename to arch/arm/boot/dts/st/stm32mp13xc.dtsi diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13xf.dtsi rename to arch/arm/boot/dts/st/stm32mp13xf.dtsi diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi similarity index 91% rename from arch/arm/boot/dts/stm32mp15-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index e86d989dd351..06e969aa5fdb 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -341,6 +341,56 @@ }; }; + ethernet0_rgmii_pins_d: rgmii-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ @@ -1441,6 +1491,30 @@ }; }; + sai2b_pins_d: sai2b-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_d: sai2b-sleep-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + , /* SAI2_MCLK_B */ + ; /* SAI2_SD_B */ + }; + }; + sai4a_pins_a: sai4a-0 { pins { pinmux = ; /* SAI4_SD_A */ @@ -1522,6 +1596,60 @@ }; }; + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = , /* SDMMC1_D0DIR */ @@ -1759,6 +1887,27 @@ }; }; + sdmmc2_d47_pins_e: sdmmc2-d47-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ @@ -2124,6 +2273,33 @@ }; }; + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_CTS_NSS */ + bias-disable; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -2226,6 +2402,23 @@ }; }; + usart3_idle_pins_a: usart3-idle-0 { + pins1 { + pinmux = ; /* USART3_TX */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_a: usart3-sleep-0 { + pins { + pinmux = , /* USART3_TX */ + ; /* USART3_RX */ + }; + }; + usart3_pins_b: usart3-1 { pins1 { pinmux = , /* USART3_TX */ @@ -2463,4 +2656,42 @@ bias-disable; }; }; + + spi1_sleep_pins_a: spi1-sleep-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + }; + }; + + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; }; diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15-scmi.dtsi rename to arch/arm/boot/dts/st/stm32mp15-scmi.dtsi diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32mp151.dtsi rename to arch/arm/boot/dts/st/stm32mp151.dtsi index 63f4c78fcc1d..61508917521c 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -1093,6 +1093,8 @@ adc1: adc@0 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0>; interrupt-parent = <&adc>; interrupts = <0>; @@ -1104,12 +1106,24 @@ adc2: adc@100 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x100>; interrupt-parent = <&adc>; interrupts = <1>; dmas = <&dmamux1 10 0x400 0x01>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; }; }; @@ -1529,11 +1543,6 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - }; }; iwdg2: watchdog@5a002000 { @@ -1620,6 +1629,12 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + part_number_otp: part-number-otp@4 { + reg = <0x4 0x1>; + }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; @@ -1820,8 +1835,8 @@ <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts rename to arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1a.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1c.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi rename to arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1s.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp153.dtsi rename to arch/arm/boot/dts/st/stm32mp153.dtsi diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts rename to arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts rename to arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi similarity index 86% rename from arch/arm/boot/dts/stm32mp157.dtsi rename to arch/arm/boot/dts/st/stm32mp157.dtsi index 54e73ccea446..5e733cd16ff9 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157.dtsi @@ -24,14 +24,7 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-avenger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-avenger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-avenger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts similarity index 89% rename from arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index e539cc80bef8..afcd6285890c 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -55,8 +55,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-dk1.dts rename to arch/arm/boot/dts/st/stm32mp157a-dk1.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts similarity index 97% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 9a2a4bc7d079..4279b26547df 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -49,6 +49,9 @@ phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -104,8 +107,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts similarity index 97% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index 390ee8c05754..efba54289820 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -49,6 +49,9 @@ phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in_ltdc: endpoint { @@ -104,8 +107,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { - reg = <0>; + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in_ltdc>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-iot-box.dts rename to arch/arm/boot/dts/st/stm32mp157a-iot-box.dts diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts similarity index 98% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 0d7560ba2950..5116a7785201 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -81,8 +81,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-stinger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-stinger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32mp157a-stinger96.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi index 3a36f7fe0a2c..5f85598cc7c6 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi @@ -287,7 +287,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; @@ -297,7 +297,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts rename to arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts rename to arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts similarity index 90% rename from arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 97e4f94b0a24..39358d902000 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -61,8 +61,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts similarity index 92% rename from arch/arm/boot/dts/stm32mp157c-dk2.dts rename to arch/arm/boot/dts/st/stm32mp157c-dk2.dts index ab13e340f4ef..4bef2300ed7c 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -31,10 +31,15 @@ }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -82,6 +87,9 @@ status = "okay"; port { + #address-cells = <1>; + #size-cells = <0>; + ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts similarity index 90% rename from arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 9cf0a44d2f47..07ea765a4553 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -60,8 +60,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts similarity index 97% rename from arch/arm/boot/dts/stm32mp157c-ed1.dts rename to arch/arm/boot/dts/st/stm32mp157c-ed1.dts index 8beb901be506..66ed5f9921ba 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -103,10 +103,20 @@ vref-supply = <&vdda>; status = "disabled"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-nsecs = <400>; status = "okay"; + channel@0 { + reg = <0>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <400>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <400>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <400>; + }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts rename to arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi rename to arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi index b01470a9a3d5..94e38141af67 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -97,9 +97,11 @@ adc1: adc@0 { pinctrl-names = "default"; pinctrl-0 = <&adc1_in6_pins_a>; - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <6>; status = "disabled"; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts similarity index 90% rename from arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 3b9dd6f4ccc9..813086ec2489 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -66,8 +66,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts similarity index 97% rename from arch/arm/boot/dts/stm32mp157c-ev1.dts rename to arch/arm/boot/dts/st/stm32mp157c-ev1.dts index ba8e9d9a42fa..af3800501875 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -101,9 +101,14 @@ &dsi { phy-dsi-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -119,7 +124,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "raydium,rm68200"; reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; @@ -185,7 +190,9 @@ reg = <0x3c>; clocks = <&clk_ext_camera>; clock-names = "xclk"; + AVDD-supply = <&v2v8>; DOVDD-supply = <&v2v8>; + DVDD-supply = <&v2v8>; powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; rotation = <180>; @@ -239,8 +246,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts similarity index 99% rename from arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts rename to arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts index 407ed3952f75..eada9cf257be 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts @@ -161,8 +161,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_input>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi rename to arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-odyssey.dts rename to arch/arm/boot/dts/st/stm32mp157c-odyssey.dts diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts new file mode 100644 index 000000000000..28d7203264ce --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +/dts-v1/; + +#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157c-phycore-stm32mp15-som.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + compatible = "phytec,phycore-stm32mp1-3", + "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&fmc { + status = "disabled"; +}; + +&gpu { + status = "okay"; +}; + +&i2c4_eeprom { + status = "okay"; +}; + +&i2c4_rtc { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&sdmmc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi new file mode 100644 index 000000000000..4e8b2d2b30c7 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -0,0 +1,577 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp15-pinctrl.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP15 SOM"; + compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + rtc0 = &i2c4_rtc; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; + + regulator_vin: regulator { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rgmii_pins_d>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <®ulator_vin>; + buck2-supply = <®ulator_vin>; + buck3-supply = <®ulator_vin>; + buck4-supply = <®ulator_vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <®ulator_vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + boost-supply = <®ulator_vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + vdd_eth_2v5: ldo2 { + regulator-name = "dd_eth_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + vdd_eth_1v0: ldo6 { + regulator-name = "vdd_eth_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , + ; + interrupt-names = "onkey-falling", + "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + }; + + i2c4_eeprom: eeprom@50 { + compatible = "microchip,24c32", + "atmel,24c32"; + reg = <0x50>; + }; + + i2c4_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + status = "okay"; + + flash0: flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + st,sync = <&sai2b 2>; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + pinctrl-3 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xc.dtsi rename to arch/arm/boot/dts/st/stm32mp15xc.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi similarity index 96% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 4709677151aa..46b87a27d8b3 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -137,10 +137,13 @@ sound { compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; + widgets = "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Microphone", "Microphone Jack"; + routing = "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; dais = <&sai2a_port &sai2b_port>; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi similarity index 98% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index c06edd2eacb0..e61df23d361a 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -80,17 +80,19 @@ vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <0>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; +}; - adc2: adc@100 { - st,adc-channels = <1>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc2 { + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi similarity index 94% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index 50af4a27d6be..0069ad75d55e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -87,7 +87,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-AV96-HDMI"; + label = "STM32-AV96-HDMI"; dais = <&sai2a_port>; status = "okay"; }; @@ -111,17 +111,39 @@ vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; +}; + +&adc2 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; }; }; @@ -321,6 +343,12 @@ }; }; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; <dc { @@ -330,11 +358,7 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&adv7513_in>; }; }; @@ -452,7 +476,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi similarity index 92% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi index c32c160f97f2..92d906bfd5d7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi @@ -57,15 +57,35 @@ status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; @@ -192,6 +212,12 @@ reg = <0x50>; pagesize = <16>; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &sdmmc1 { /* MicroSD */ diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi similarity index 98% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi index bb40fb46da81..bba19f21e527 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -213,12 +213,6 @@ status = "disabled"; }; }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; }; &ipcc { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi similarity index 86% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi index 5fdb74b652ac..ab7f0ba49639 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi @@ -41,15 +41,35 @@ status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; @@ -90,6 +110,14 @@ }; }; +&i2c4 { + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi similarity index 96% rename from arch/arm/boot/dts/stm32mp15xx-dkx.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index cefeeb00fc22..511113f2e399 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -93,28 +93,39 @@ &adc { pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; + pinctrl-0 = <&adc12_usb_cc_pins_a>; vdd-supply = <&vdd>; vdda-supply = <&vdd>; vref-supply = <&vrefbuf>; - status = "disabled"; + status = "okay"; adc1: adc@0 { + status = "okay"; /* * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: * 5 * (56 + 47kOhms) * 5pF => 2.5us. * Use arbitrary margin here (e.g. 5us). */ - st,min-sample-time-nsecs = <5000>; - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 6 13 18 19>; - status = "okay"; + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 2 6 18 19>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + /* USB Type-C CC1 & CC2 */ + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; }; @@ -379,21 +390,21 @@ regulator-always-on; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = ; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; regulator-active-discharge = <1>; - }; + }; }; onkey { @@ -435,7 +446,7 @@ i2s2_port: port { i2s2_endpoint: endpoint { remote-endpoint = <&sii9022_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; }; }; @@ -457,8 +468,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&sii9022_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-osd32.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile new file mode 100644 index 000000000000..868f2ea0c127 --- /dev/null +++ b/arch/arm/boot/dts/sunplus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021-achip.dtsi rename to arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts rename to arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021.dtsi rename to arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi diff --git a/arch/arm/boot/dts/synaptics/Makefile b/arch/arm/boot/dts/synaptics/Makefile new file mode 100644 index 000000000000..0ecccd156d18 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BERLIN) += \ + berlin2-sony-nsz-gs7.dtb \ + berlin2cd-google-chromecast.dtb \ + berlin2cd-valve-steamlink.dtb \ + berlin2q-marvell-dmp.dtb diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts similarity index 100% rename from arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts rename to arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/synaptics/berlin2.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2.dtsi rename to arch/arm/boot/dts/synaptics/berlin2.dtsi diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts similarity index 100% rename from arch/arm/boot/dts/berlin2cd-google-chromecast.dts rename to arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts similarity index 100% rename from arch/arm/boot/dts/berlin2cd-valve-steamlink.dts rename to arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/synaptics/berlin2cd.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2cd.dtsi rename to arch/arm/boot/dts/synaptics/berlin2cd.dtsi diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts similarity index 100% rename from arch/arm/boot/dts/berlin2q-marvell-dmp.dts rename to arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/synaptics/berlin2q.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2q.dtsi rename to arch/arm/boot/dts/synaptics/berlin2q.dtsi diff --git a/arch/arm/boot/dts/ti/Makefile b/arch/arm/boot/dts/ti/Makefile new file mode 100644 index 000000000000..871079a7bc3b --- /dev/null +++ b/arch/arm/boot/dts/ti/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += davinci +subdir-y += keystone +subdir-y += omap diff --git a/arch/arm/boot/dts/ti/davinci/Makefile b/arch/arm/boot/dts/ti/davinci/Makefile new file mode 100644 index 000000000000..c0e388eb3dd1 --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DAVINCI) += \ + da850-lcdk.dtb \ + da850-enbw-cmc.dtb \ + da850-evm.dtb \ + da850-lego-ev3.dtb diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts similarity index 100% rename from arch/arm/boot/dts/da850-enbw-cmc.dts rename to arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts similarity index 99% rename from arch/arm/boot/dts/da850-evm.dts rename to arch/arm/boot/dts/ti/davinci/da850-evm.dts index 0ca849885d1f..111708d992ca 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -333,7 +333,7 @@ status = "okay"; }; -/include/ "tps6507x.dtsi" +/include/ "../../tps6507x.dtsi" &tps { vdcdc1_2-supply = <&vbat>; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts similarity index 100% rename from arch/arm/boot/dts/da850-lcdk.dts rename to arch/arm/boot/dts/ti/davinci/da850-lcdk.dts diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts similarity index 100% rename from arch/arm/boot/dts/da850-lego-ev3.dts rename to arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/ti/davinci/da850.dtsi similarity index 100% rename from arch/arm/boot/dts/da850.dtsi rename to arch/arm/boot/dts/ti/davinci/da850.dtsi diff --git a/arch/arm/boot/dts/ti/keystone/Makefile b/arch/arm/boot/dts/ti/keystone/Makefile new file mode 100644 index 000000000000..4b18d08fa57c --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_KEYSTONE) += \ + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb \ + keystone-k2g-ice.dtb diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2e-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts similarity index 98% rename from arch/arm/boot/dts/keystone-k2e-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts index abd5aef8b87d..6978d6a362f3 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts @@ -78,7 +78,7 @@ }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; @@ -130,7 +130,7 @@ partition@180000 { label = "ubifs"; - reg = <0x180000 0x1FE80000>; + reg = <0x180000 0x1fe80000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi similarity index 99% rename from arch/arm/boot/dts/keystone-k2e-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi index 42cf74db673c..bff73a0ed10b 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi @@ -167,7 +167,7 @@ netcp: netcp@24000000 { <&tsipclka>, <&tsrefclk>, <&tsipclkb>; ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x4>, <0x8>, <0xC>; + <0x3>, <0x4>, <0x8>, <0xc>; assigned-clocks = <&cpts_refclk_mux>; assigned-clock-parents = <&chipclk12>; }; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2e.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts similarity index 95% rename from arch/arm/boot/dts/keystone-k2g-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts index 3a87b7943c70..7bfc80f1af26 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts @@ -120,14 +120,14 @@ }; &k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; - mmc0_pins: pinmux_mmc0_pins { + mmc0_pins: mmc0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ @@ -139,7 +139,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ @@ -154,27 +154,27 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - ecap0_pins: ecap0_pins { + ecap0_pins: ecap0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ @@ -183,7 +183,7 @@ >; }; - qspi_pins: pinmux_qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ @@ -195,52 +195,52 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ >; }; - emac_pins: pinmux_emac_pins { + emac_pins: emac-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ >; }; - mdio_pins: pinmux_mdio_pins { + mdio_pins: mdio-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; - vout_pins: pinmux_vout_pins { + vout_pins: vout-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ @@ -274,7 +274,7 @@ >; }; - mcasp2_pins: pinmux_mcasp2_pins { + mcasp2_pins: mcasp2-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ @@ -424,11 +424,11 @@ }; partition@4 { label = "QSPI.kernel"; - reg = <0x001C0000 0x0800000>; + reg = <0x001c0000 0x0800000>; }; partition@5 { label = "QSPI.file-system"; - reg = <0x009C0000 0x3640000>; + reg = <0x009c0000 0x3640000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts similarity index 94% rename from arch/arm/boot/dts/keystone-k2g-ice.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts index bd84d7f0f2fe..6ceb0d5c6388 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts @@ -218,14 +218,14 @@ }; &k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; - qspi_pins: pinmux_qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ @@ -237,35 +237,35 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ - K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ + K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - user_leds: pinmux_user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ @@ -283,26 +283,26 @@ >; }; - emac_pins: pinmux_emac_pins { + emac_pins: emac-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ >; }; - mdio_pins: pinmux_mdio_pins { + mdio_pins: mdio-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2g-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi similarity index 99% rename from arch/arm/boot/dts/keystone-k2g.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi index 380dd9d637ee..102d59694d90 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi @@ -177,7 +177,7 @@ dcan0: can@260b200 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B200 0x200>; + reg = <0x0260b200 0x200>; interrupts = ; status = "disabled"; power-domains = <&k2g_pds 0x0008>; @@ -186,7 +186,7 @@ dcan1: can@260b400 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B400 0x200>; + reg = <0x0260b400 0x200>; interrupts = ; status = "disabled"; power-domains = <&k2g_pds 0x0009>; @@ -593,7 +593,7 @@ spi2: spi@21805c00 { compatible = "ti,keystone-spi"; - reg = <0x21805C00 0x200>; + reg = <0x21805c00 0x200>; num-cs = <4>; ti,davinci-spi-intr-line = <0>; interrupts = ; diff --git a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts similarity index 99% rename from arch/arm/boot/dts/keystone-k2hk-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts index 1f762af6f502..206df8a8d9dd 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts @@ -154,7 +154,7 @@ }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2l-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts similarity index 98% rename from arch/arm/boot/dts/keystone-k2l-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts index 3a69f65de81e..be619e39a16f 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts @@ -51,7 +51,7 @@ }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; @@ -103,7 +103,7 @@ partition@180000 { label = "ubifs"; - reg = <0x180000 0x7FE80000>; + reg = <0x180000 0x7fe80000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2l-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi similarity index 95% rename from arch/arm/boot/dts/keystone-k2l.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi index 421a02bbc9d3..8949578e62e8 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi @@ -116,42 +116,42 @@ pinctrl-single,function-mask = <0x1>; status = "disabled"; - uart3_emifa_pins: pinmux_uart3_emifa_pins { + uart3_emifa_pins: uart3-emifa-pins { pinctrl-single,bits = < /* UART3_EMIFA_SEL */ 0x0 0x0 0xc0 >; }; - uart2_emifa_pins: pinmux_uart2_emifa_pins { + uart2_emifa_pins: uart2-emifa-pins { pinctrl-single,bits = < /* UART2_EMIFA_SEL */ 0x0 0x0 0x30 >; }; - uart01_spi2_pins: pinmux_uart01_spi2_pins { + uart01_spi2_pins: uart01-spi2-pins { pinctrl-single,bits = < /* UART01_SPI2_SEL */ 0x0 0x0 0x4 >; }; - dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ + dfesync_rp1_pins: dfesync-rp1-pins{ pinctrl-single,bits = < /* DFESYNC_RP1_SEL */ 0x0 0x0 0x2 >; }; - avsif_pins: pinmux_avsif_pins { + avsif_pins: avsif-pins { pinctrl-single,bits = < /* AVSIF_SEL */ 0x0 0x0 0x1 >; }; - gpio_emu_pins: pinmux_gpio_emu_pins { + gpio_emu_pins: gpio-emu-pins { pinctrl-single,bits = < /* * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 @@ -170,11 +170,11 @@ * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 */ - 0x4 0x0000 0xFFFE0000 + 0x4 0x0000 0xfffe0000 >; }; - gpio_timio_pins: pinmux_gpio_timio_pins { + gpio_timio_pins: gpio-timio-pins { pinctrl-single,bits = < /* * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 @@ -190,11 +190,11 @@ * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 */ - 0x4 0x0 0xFFF0 + 0x4 0x0 0xfff0 >; }; - gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { + gpio_spi2cs_pins: gpio-spi2cs-pins { pinctrl-single,bits = < /* * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 @@ -202,11 +202,11 @@ * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 */ - 0x4 0x0 0xF + 0x4 0x0 0xf >; }; - gpio_dfeio_pins: pinmux_gpio_dfeio_pins { + gpio_dfeio_pins: gpio-dfeio-pins { pinctrl-single,bits = < /* * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 @@ -226,11 +226,11 @@ * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 */ - 0x8 0x0 0xFFFF0000 + 0x8 0x0 0xffff0000 >; }; - gpio_emifa_pins: pinmux_gpio_emifa_pins { + gpio_emifa_pins: gpio-emifa-pins { pinctrl-single,bits = < /* * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 @@ -250,7 +250,7 @@ * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 */ - 0x8 0x0 0xFFFF + 0x8 0x0 0xffff >; }; }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/ti/keystone/keystone.dtsi similarity index 98% rename from arch/arm/boot/dts/keystone.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone.dtsi index 50789f9e2215..1fd04bb37a15 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone.dtsi @@ -69,9 +69,9 @@ }; soc0: soc@0 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; interrupt-parent = <&gic>; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; @@ -282,7 +282,7 @@ ti,davinci-gpio-unbanked = <32>; }; - aemif: aemif@21000A00 { + aemif: aemif@21000a00 { compatible = "ti,keystone-aemif", "ti,davinci-aemif"; #address-cells = <2>; #size-cells = <1>; @@ -290,9 +290,9 @@ clock-names = "aemif"; clock-ranges; - reg = <0x21000A00 0x00000100>; + reg = <0x21000a00 0x00000100>; ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000A00 0x00000100>; + 1 0 0x21000a00 0x00000100>; }; pcie0: pcie@21800000 { diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile new file mode 100644 index 000000000000..d2b590004fed --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_OMAP2) += \ + omap2420-h4.dtb \ + omap2420-n800.dtb \ + omap2420-n810.dtb \ + omap2420-n810-wimax.dtb \ + omap2430-sdp.dtb +dtb-$(CONFIG_ARCH_OMAP3) += \ + am3517-craneboard.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit-28.dtb \ + logicpd-som-lv-35xx-devkit.dtb \ + logicpd-som-lv-37xx-devkit.dtb \ + omap3430-sdp.dtb \ + omap3-beagle.dtb \ + omap3-beagle-ab4.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle-xm-ab.dtb \ + omap3-cm-t3517.dtb \ + omap3-cm-t3530.dtb \ + omap3-cm-t3730.dtb \ + omap3-devkit8000.dtb \ + omap3-devkit8000-lcd43.dtb \ + omap3-devkit8000-lcd70.dtb \ + omap3-echo.dtb \ + omap3-evm.dtb \ + omap3-evm-37xx.dtb \ + omap3-gta04a3.dtb \ + omap3-gta04a4.dtb \ + omap3-gta04a5.dtb \ + omap3-gta04a5one.dtb \ + omap3-ha.dtb \ + omap3-ha-lcd.dtb \ + omap3-igep0020.dtb \ + omap3-igep0020-rev-f.dtb \ + omap3-igep0030.dtb \ + omap3-igep0030-rev-g.dtb \ + omap3-ldp.dtb \ + omap3-lilly-dbb056.dtb \ + omap3-n900.dtb \ + omap3-n9.dtb \ + omap3-n950.dtb \ + omap3-overo-alto35.dtb \ + omap3-overo-chestnut43.dtb \ + omap3-overo-gallop43.dtb \ + omap3-overo-palo35.dtb \ + omap3-overo-palo43.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-storm-gallop43.dtb \ + omap3-overo-storm-palo35.dtb \ + omap3-overo-storm-palo43.dtb \ + omap3-overo-storm-summit.dtb \ + omap3-overo-storm-tobi.dtb \ + omap3-overo-storm-tobiduo.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-tobi.dtb \ + omap3-overo-tobiduo.dtb \ + omap3-pandora-600mhz.dtb \ + omap3-pandora-1ghz.dtb \ + omap3-sbc-t3517.dtb \ + omap3-sbc-t3530.dtb \ + omap3-sbc-t3730.dtb \ + omap3-sniper.dtb \ + omap3-thunder.dtb \ + omap3-zoom3.dtb +dtb-$(CONFIG_ARCH_OMAP4) += \ + omap4-droid-bionic-xt875.dtb \ + omap4-droid4-xt894.dtb \ + omap4-duovero-parlor.dtb \ + omap4-epson-embt2ws.dtb \ + omap4-kc1.dtb \ + omap4-panda.dtb \ + omap4-panda-a4.dtb \ + omap4-panda-es.dtb \ + omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb \ + omap4-var-dvk-om44.dtb \ + omap4-var-stk-om44.dtb +dtb-$(CONFIG_SOC_AM33XX) += \ + am335x-baltos-ir2110.dtb \ + am335x-baltos-ir3220.dtb \ + am335x-baltos-ir5221.dtb \ + am335x-base0033.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ + am335x-bonegreen.dtb \ + am335x-bonegreen-wireless.dtb \ + am335x-chiliboard.dtb \ + am335x-cm-t335.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-guardian.dtb \ + am335x-icev2.dtb \ + am335x-lxm.dtb \ + am335x-moxa-uc-2101.dtb \ + am335x-moxa-uc-8100-me-t.dtb \ + am335x-myirtech-myd.dtb \ + am335x-nano.dtb \ + am335x-netcan-plus-1xx.dtb \ + am335x-netcom-plus-2xx.dtb \ + am335x-netcom-plus-8xx.dtb \ + am335x-pdu001.dtb \ + am335x-pepper.dtb \ + am335x-phycore-rdk.dtb \ + am335x-pocketbeagle.dtb \ + am335x-regor-rdk.dtb \ + am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ + am335x-shc.dtb \ + am335x-sbc-t335.dtb \ + am335x-sl50.dtb \ + am335x-wega-rdk.dtb \ + am335x-osd3358-sm-red.dtb +dtb-$(CONFIG_SOC_AM43XX) += \ + am43x-epos-evm.dtb \ + am437x-cm-t43.dtb \ + am437x-gp-evm.dtb \ + am437x-idk-evm.dtb \ + am437x-sbc-t43.dtb \ + am437x-sk-evm.dtb + +am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo +am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo + +dtb-$(CONFIG_SOC_DRA7XX) += \ + am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ + am57xx-beagle-x15-revc.dtb \ + am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ + am5729-beagleboneai.dtb \ + am57xx-cl-som-am57x.dtb \ + am57xx-sbc-am57x.dtb \ + am572x-idk.dtb \ + am572x-idk-touchscreen.dtbo \ + am571x-idk.dtb \ + am571x-idk-touchscreen.dtbo \ + am574x-idk.dtb \ + am57xx-idk-lcd-osd101t2045.dtbo \ + am57xx-idk-lcd-osd101t2587.dtbo \ + dra7-evm.dtb \ + dra72-evm.dtb \ + dra72-evm-revc.dtb \ + dra71-evm.dtb \ + dra76-evm.dtb +dtb-$(CONFIG_SOC_OMAP5) += \ + omap5-cm-t54.dtb \ + omap5-igep0050.dtb \ + omap5-sbc-t54.dtb \ + omap5-uevm.dtb +dtb-$(CONFIG_SOC_TI81XX) += \ + am3874-iceboard.dtb \ + dm8148-evm.dtb \ + dm8148-t410.dtb \ + dm8168-evm.dtb \ + dra62x-j5eco-evm.dtb diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts similarity index 98% rename from arch/arm/boot/dts/am335x-baltos-ir2110.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts index 75992eec830f..ea5882ed7010 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts @@ -18,7 +18,7 @@ }; &am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -31,7 +31,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts similarity index 97% rename from arch/arm/boot/dts/am335x-baltos-ir3220.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts index 087e084506d2..ea4f8dde6424 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts @@ -18,13 +18,13 @@ }; &am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -37,7 +37,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ @@ -52,7 +52,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts similarity index 97% rename from arch/arm/boot/dts/am335x-baltos-ir5221.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts index faeb39aab60a..ec914f27d11d 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts @@ -18,21 +18,21 @@ }; &am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -45,7 +45,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ @@ -60,7 +60,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi similarity index 97% rename from arch/arm/boot/dts/am335x-baltos-leds.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi index 025014657d12..6a52e42b9e81 100644 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -37,7 +37,7 @@ }; &am33xx_pinmux { - user_leds: pinmux_user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi similarity index 96% rename from arch/arm/boot/dts/am335x-baltos.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi index 6161c8929a78..c14d5b70c72f 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -48,7 +48,7 @@ }; &am33xx_pinmux { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ @@ -60,33 +60,33 @@ >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ >; }; - tps65910_pins: pinmux_tps65910_pins { + tps65910_pins: tps65910-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -114,7 +114,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -141,7 +141,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ @@ -149,7 +149,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -157,7 +157,7 @@ >; }; - nandflash_pins_s0: nandflash_pins_s0 { + nandflash_pins_s0: nandflash-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ @@ -258,7 +258,7 @@ }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts similarity index 95% rename from arch/arm/boot/dts/am335x-base0033.dts rename to arch/arm/boot/dts/ti/omap/am335x-base0033.dts index 89c00ce42c26..eba843e22ea1 100644 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts @@ -41,7 +41,7 @@ }; &am33xx_pinmux { - nxp_hdmi_pins: pinmux_nxp_hdmi_pins { + nxp_hdmi_pins: nxp-hdmi-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) @@ -66,13 +66,13 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { + nxp_hdmi_off_pins: nxp-hdmi-off-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ >; }; - leds_base_pins: pinmux_leds_base_pins { + leds_base_pins: leds-base-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi similarity index 96% rename from arch/arm/boot/dts/am335x-bone-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index 02e04a12a270..b958607c71dc 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -75,34 +75,34 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) @@ -121,7 +121,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -140,7 +140,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -148,7 +148,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -156,7 +156,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -168,7 +168,7 @@ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -273,7 +273,7 @@ }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { /* diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/ti/omap/am335x-bone.dts similarity index 100% rename from arch/arm/boot/dts/am335x-bone.dts rename to arch/arm/boot/dts/ti/omap/am335x-bone.dts diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi similarity index 97% rename from arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi index 486f24deb875..109f08fd174d 100644 --- a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi @@ -7,7 +7,7 @@ #include &am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) @@ -33,13 +33,13 @@ >; }; - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; - mcasp0_pins: mcasp0_pins { + mcasp0_pins: mcasp0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts similarity index 96% rename from arch/arm/boot/dts/am335x-boneblack-wireless.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts index 207d2b63e0eb..b4b4b80df08c 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts @@ -28,13 +28,13 @@ }; &am33xx_pinmux { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ @@ -45,7 +45,7 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ @@ -54,7 +54,7 @@ >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblack.dts diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts similarity index 96% rename from arch/arm/boot/dts/am335x-boneblue.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblue.dts index 34579e98636e..801399702547 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts @@ -115,7 +115,7 @@ }; &am33xx_pinmux { - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ @@ -132,7 +132,7 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ @@ -140,7 +140,7 @@ }; /* UT0 */ - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -148,7 +148,7 @@ }; /* UT1 */ - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -156,7 +156,7 @@ }; /* GPS */ - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ @@ -164,27 +164,27 @@ }; /* DSM2 */ - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ >; }; /* UT5 */ - uart5_pins: pinmux_uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ @@ -199,7 +199,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ @@ -210,13 +210,13 @@ >; }; - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ @@ -225,7 +225,7 @@ >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ @@ -234,7 +234,7 @@ }; /* DCAN */ - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ @@ -243,7 +243,7 @@ }; /* E1 */ - eqep0_pins: pinmux_eqep0_pins { + eqep0_pins: eqep0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ @@ -251,7 +251,7 @@ }; /* E2 */ - eqep1_pins: pinmux_eqep1_pins { + eqep1_pins: eqep1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ @@ -259,7 +259,7 @@ }; /* E3 */ - eqep2_pins: pinmux_eqep2_pins { + eqep2_pins: eqep2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ @@ -353,7 +353,7 @@ }; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { /delete-property/ ti,pmic-shutdown-controller; diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi similarity index 96% rename from arch/arm/boot/dts/am335x-bonegreen-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi index 9f7fb63744d0..383beeddf595 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi @@ -22,7 +22,7 @@ }; &am33xx_pinmux { - uart2_pins: uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts similarity index 96% rename from arch/arm/boot/dts/am335x-bonegreen-wireless.dts rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts index d388cffa1a4d..a4f5b5262645 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts @@ -27,13 +27,13 @@ }; &am33xx_pinmux { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ @@ -44,7 +44,7 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ @@ -53,7 +53,7 @@ >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ diff --git a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts similarity index 100% rename from arch/arm/boot/dts/am335x-bonegreen.dts rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts similarity index 94% rename from arch/arm/boot/dts/am335x-chiliboard.dts rename to arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts index a223cdd3e30e..648e97fe1dfd 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts @@ -36,14 +36,14 @@ }; &am33xx_pinmux { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -57,7 +57,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -72,7 +72,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* mdio_data.mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -81,7 +81,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -89,13 +89,13 @@ >; }; - usb1_drvvbus: usb1_drvvbus { + usb1_drvvbus: usb1-drvvbus-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - sd_pins: pinmux_sd_card { + sd_pins: sd-card-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) @@ -107,7 +107,7 @@ >; }; - led_gpio_pins: led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi similarity index 97% rename from arch/arm/boot/dts/am335x-chilisom.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi index 43b61e43ed1e..bd43da6356b6 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi @@ -25,14 +25,14 @@ &am33xx_pinmux { pinctrl-names = "default"; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - nandflash_pins: nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -66,7 +66,7 @@ }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { regulators { diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts similarity index 95% rename from arch/arm/boot/dts/am335x-cm-t335.dts rename to arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts index 993b13420699..72990e7ffe10 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts @@ -88,14 +88,14 @@ pinctrl-names = "default"; pinctrl-0 = <&bluetooth_pins>; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) @@ -104,14 +104,14 @@ >; }; - gpio_led_pins: pinmux_gpio_led_pins { + gpio_led_pins: gpio-led-pins { pinctrl-single,pins = < /* gpmc_csn3.gpio2_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -132,14 +132,14 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -148,7 +148,7 @@ >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < /* uart1_ctsn.dcan0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) @@ -157,7 +157,7 @@ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < /* uart1_rxd.dcan1_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) @@ -166,13 +166,13 @@ >; }; - ecap0_pins: pinmux_ecap0_pins { + ecap0_pins: ecap0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ /* mii1_tx_en.rgmii1_tctl */ @@ -202,7 +202,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -220,14 +220,14 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -235,7 +235,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -246,7 +246,7 @@ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) @@ -257,7 +257,7 @@ }; /* wl1271 bluetooth */ - bluetooth_pins: pinmux_bluetooth_pins { + bluetooth_pins: bluetooth-pins { pinctrl-single,pins = < /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) @@ -265,7 +265,7 @@ }; /* TLV320AIC23B codec */ - mcasp1_pins: pinmux_mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < /* MII1_CRS.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) @@ -279,7 +279,7 @@ }; /* wl1271 WiFi */ - wifi_pins: pinmux_wifi_pins { + wifi_pins: wifi-pins { pinctrl-single,pins = < /* EMU1.gpio3_8 - WiFi IRQ */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/ti/omap/am335x-evm.dts similarity index 96% rename from arch/arm/boot/dts/am335x-evm.dts rename to arch/arm/boot/dts/ti/omap/am335x-evm.dts index 5beabaa5ff6a..61bf8bcd4c4e 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts @@ -163,7 +163,7 @@ pinctrl-names = "default"; pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - matrix_keypad_s0: matrix_keypad_s0 { + matrix_keypad_s0: matrix-keypad-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -173,35 +173,35 @@ >; }; - volume_keys_s0: volume_keys_s0 { + volume_keys_s0: volume-keys-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -210,13 +210,13 @@ >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - nandflash_pins_s0: nandflash_pins_s0 { + nandflash_pins_s0: nandflash-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -236,13 +236,13 @@ >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -260,7 +260,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -278,7 +278,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -286,7 +286,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -294,7 +294,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -307,7 +307,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ @@ -318,7 +318,7 @@ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ @@ -326,7 +326,7 @@ >; }; - lcd_pins_s0: lcd_pins_s0 { + lcd_pins_s0: lcd-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ @@ -359,7 +359,7 @@ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -368,7 +368,7 @@ >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -377,7 +377,7 @@ >; }; - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -585,7 +585,7 @@ }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &mcasp1 { #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts similarity index 97% rename from arch/arm/boot/dts/am335x-evmsk.dts rename to arch/arm/boot/dts/ti/omap/am335x-evmsk.dts index 5b3278c0c46a..57f78846c42d 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts @@ -202,7 +202,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ @@ -235,7 +235,7 @@ >; }; - lcd_pins_sleep: lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ @@ -269,7 +269,7 @@ }; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ @@ -278,7 +278,7 @@ >; }; - gpio_keys_s0: gpio_keys_s0 { + gpio_keys_s0: gpio-keys-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ @@ -287,33 +287,33 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - ecap2_pins: backlight_pins { + ecap2_pins: backlight-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -345,7 +345,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -377,7 +377,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -385,7 +385,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -393,7 +393,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -406,7 +406,7 @@ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -415,7 +415,7 @@ >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -424,7 +424,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ @@ -436,7 +436,7 @@ >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; @@ -517,7 +517,7 @@ }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts similarity index 96% rename from arch/arm/boot/dts/am335x-guardian.dts rename to arch/arm/boot/dts/ti/omap/am335x-guardian.dts index b357364e93f9..205fe0ed7352 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -292,7 +292,7 @@ status = "okay"; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { /* @@ -481,14 +481,14 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; - guardian_interface_pins: pinmux_interface_pins { + guardian_interface_pins: interface-pins { pinctrl-single,pins = < /* ADC_BATSENSE_EN */ /* (A14) MCASP0_AHCLKx.gpio3[21] */ @@ -518,13 +518,13 @@ >; }; - guardian_beeper_pins: pinmux_dmtimer7_pins { + guardian_beeper_pins: dmtimer7-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ >; }; - guardian_button_pins: pinmux_guardian_button_pins { + guardian_button_pins: guardian-button-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ @@ -532,28 +532,28 @@ }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - led_bl_pins: gpio_led_bl_pins { + led_bl_pins: gpio-led-bl-pins { pinctrl-single,pins = < /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) >; }; - lcd_disen_pins: pinmux_lcd_disen_pins { + lcd_disen_pins: lcd-disen-pins { pinctrl-single,pins = < /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; - lcd_pins_default: pinmux_lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < /* (U10) gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) @@ -614,7 +614,7 @@ >; }; - lcd_pins_sleep: pinmux_lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) @@ -659,13 +659,13 @@ >; }; - guardian_led_pins: pinmux_guardian_led_pins { + guardian_led_pins: guardian-led-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ @@ -677,7 +677,7 @@ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < /* SPI0_CLK - spi0_clk.spi */ AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) @@ -690,7 +690,7 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) @@ -699,7 +699,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < /* K18 uart2_rxd.mirx_txd */ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) @@ -708,7 +708,7 @@ >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts similarity index 96% rename from arch/arm/boot/dts/am335x-icev2.dts rename to arch/arm/boot/dts/ti/omap/am335x-icev2.dts index 5835c0cdda50..3c4228927f56 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts @@ -152,7 +152,7 @@ }; &am33xx_pinmux { - user_leds: user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ @@ -163,7 +163,7 @@ >; }; - mmc0_pins_default: mmc0_pins_default { + mmc0_pins_default: mmc0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -174,14 +174,14 @@ >; }; - i2c0_pins_default: i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - spi0_pins_default: spi0_pins_default { + spi0_pins_default: spi0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -192,14 +192,14 @@ >; }; - uart3_pins_default: uart3_pins_default { + uart3_pins_default: uart3-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1, RMII mode */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -222,7 +222,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -246,7 +246,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -254,7 +254,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -360,7 +360,7 @@ }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi similarity index 97% rename from arch/arm/boot/dts/am335x-igep0033.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi index 3fddf80dcf71..e85c33fd42f0 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi @@ -52,14 +52,14 @@ }; &am33xx_pinmux { - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -79,14 +79,14 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ >; @@ -221,7 +221,7 @@ dr_mode = "host"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts similarity index 97% rename from arch/arm/boot/dts/am335x-lxm.dts rename to arch/arm/boot/dts/ti/omap/am335x-lxm.dts index 1282dae144dd..be27b5a21b2c 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts @@ -41,7 +41,7 @@ }; &am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -52,14 +52,14 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ @@ -85,7 +85,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ @@ -111,7 +111,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -119,7 +119,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -127,7 +127,7 @@ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -142,7 +142,7 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -177,7 +177,7 @@ }; }; -/include/ "tps65910.dtsi" +/include/ "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi similarity index 95% rename from arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi index 49e280b42442..b8730aa52ce6 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi @@ -31,27 +31,27 @@ &am33xx_pinmux { pinctrl-names = "default"; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - push_button_pins: pinmux_push_button { + push_button_pins: push-button-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -59,7 +59,7 @@ >; }; - mmc1_pins_default: pinmux_mmc1_pins { + mmc1_pins_default: mmc1-pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ @@ -75,7 +75,7 @@ >; }; - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts similarity index 97% rename from arch/arm/boot/dts/am335x-moxa-uc-2101.dts rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts index 1cc513ed92cc..e986945ac1b5 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts @@ -28,7 +28,7 @@ &am33xx_pinmux { pinctrl-names = "default"; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -42,7 +42,7 @@ >; }; - spi1_pins: pinmux_spi1 { + spi1_pins: spi1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi similarity index 95% rename from arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi index 7d00e8b20f18..daaa5eee0f0d 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi @@ -38,7 +38,7 @@ pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins>; - minipcie_pins: pinmux_minipcie { + minipcie_pins: minipcie-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ @@ -46,13 +46,13 @@ >; }; - push_button_pins: pinmux_push_button { + push_button_pins: push-button-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) @@ -60,21 +60,21 @@ }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -83,7 +83,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ @@ -92,7 +92,7 @@ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -117,7 +117,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -125,7 +125,7 @@ >; }; - mmc0_pins_default: pinmux_mmc0_pins { + mmc0_pins_default: mmc0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -138,7 +138,7 @@ >; }; - mmc2_pins_default: pinmux_mmc2_pins { + mmc2_pins_default: mmc2-pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ @@ -154,7 +154,7 @@ >; }; - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -233,7 +233,7 @@ }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts similarity index 100% rename from arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi similarity index 95% rename from arch/arm/boot/dts/am335x-myirtech-myc.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi index 6eea18b29355..584599269217 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi @@ -127,6 +127,7 @@ gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; + gpmc,wait-pin = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; @@ -159,21 +160,21 @@ }; &am33xx_pinmux { - mdio_pins_default: pinmux_mdio_pins_default { + mdio_pins_default: mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ >; }; - mdio_pins_sleep: pinmux_mdio_pins_sleep { + mdio_pins_sleep: mdio-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - eth_slave1_pins_default: pinmux_eth_slave1_pins_default { + eth_slave1_pins_default: eth-slave1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ @@ -190,7 +191,7 @@ >; }; - eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep { + eth_slave1_pins_sleep: eth-slave1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -207,34 +208,34 @@ >; }; - i2c0_pins_default: pinmux_i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ >; }; - i2c0_pins_gpio: pinmux_i2c0_pins_gpio { + i2c0_pins_gpio: i2c0-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ >; }; - i2c0_pins_sleep: pinmux_i2c0_pins_sleep { + i2c0_pins_sleep: i2c0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - led_mod_pins: pinmux_led_mod_pins { + led_mod_pins: led-mod-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ >; }; - nand_pins_default: pinmux_nand_pins_default { + nand_pins_default: nand-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ @@ -254,7 +255,7 @@ >; }; - nand_pins_sleep: pinmux_nand_pins_sleep { + nand_pins_sleep: nand-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts similarity index 93% rename from arch/arm/boot/dts/am335x-myirtech-myd.dts rename to arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts index 425ad9b81a68..d3bba79b9358 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts @@ -304,47 +304,47 @@ }; &am33xx_pinmux { - dcan0_pins_default: pinmux_dcan0_pins_default { + dcan0_pins_default: dcan0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ >; }; - dcan0_pins_sleep: pinmux_dcan0_pins_sleep { + dcan0_pins_sleep: dcan0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - dcan1_pins_default: pinmux_dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ >; }; - dcan1_pins_sleep: pinmux_dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default { + ehrpwm0_pins_default: ehrpwm0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ >; }; - ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep { + ehrpwm0_pins_sleep: ehrpwm0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - eth_slave2_pins_default: pinmux_eth_slave2_pins_default { + eth_slave2_pins_default: eth-slave2-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ @@ -361,7 +361,7 @@ >; }; - eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep { + eth_slave2_pins_sleep: eth-slave2-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -378,35 +378,35 @@ >; }; - gpio_buttons_pins: pinmux_gpio_buttons_pins { + gpio_buttons_pins: gpio-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ >; }; - i2c1_pins_default: pinmux_i2c1_pins_default { + i2c1_pins_default: i2c1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ >; }; - i2c1_pins_gpio: pinmux_i2c1_pins_gpio { + i2c1_pins_gpio: i2c1-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ >; }; - i2c1_pins_sleep: pinmux_i2c1_pins_sleep { + i2c1_pins_sleep: i2c1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - lcdc_pins_default: pinmux_lcdc_pins_default { + lcdc_pins_default: lcdc-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ @@ -431,7 +431,7 @@ >; }; - lcdc_pins_sleep: pinmux_lcdc_pins_sleep { + lcdc_pins_sleep: lcdc-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) @@ -456,14 +456,14 @@ >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ >; }; - mcasp0_pins_default: pinmux_mcasp0_pins_default { + mcasp0_pins_default: mcasp0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ @@ -472,7 +472,7 @@ >; }; - mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep { + mcasp0_pins_sleep: mcasp0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -481,7 +481,7 @@ >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ @@ -493,7 +493,7 @@ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -505,42 +505,42 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ >; }; - uart1_pins_default: pinmux_uart1_pins_default { + uart1_pins_default: uart1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ >; }; - uart1_pins_sleep: pinmux_uart1_pins_sleep { + uart1_pins_sleep: uart1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - uart2_pins_default: pinmux_uart2_pins_default { + uart2_pins_default: uart2-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ >; }; - uart2_pins_sleep: pinmux_uart2_pins_sleep { + uart2_pins_sleep: uart2-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - usb_pins: pinmux_usb_pins { + usb_pins: usb-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/ti/omap/am335x-nano.dts similarity index 97% rename from arch/arm/boot/dts/am335x-nano.dts rename to arch/arm/boot/dts/ti/omap/am335x-nano.dts index c447aebd8d86..a475c0d91306 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-nano.dts @@ -36,13 +36,13 @@ pinctrl-names = "default"; pinctrl-0 = <&misc_pins>; - misc_pins: misc_pins { + misc_pins: misc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ >; }; - gpmc_pins: gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -86,21 +86,21 @@ >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - uart0_pins: uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart1_pins: uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) @@ -109,7 +109,7 @@ >; }; - uart2_pins: uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ @@ -118,7 +118,7 @@ >; }; - uart3_pins: uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ @@ -127,7 +127,7 @@ >; }; - uart4_pins: uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ @@ -136,14 +136,14 @@ >; }; - uart5_pins: uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ >; }; - mmc1_pins: mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -427,7 +427,7 @@ dr_mode = "host"; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { regulators { diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts similarity index 98% rename from arch/arm/boot/dts/am335x-netcan-plus-1xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts index 2e049489ac06..f7fad48e36ed 100644 --- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts @@ -37,14 +37,14 @@ }; &am33xx_pinmux { - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts similarity index 98% rename from arch/arm/boot/dts/am335x-netcom-plus-2xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts index 6ed886c3306b..76751a324ad7 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts @@ -18,7 +18,7 @@ }; &am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ @@ -31,7 +31,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts similarity index 97% rename from arch/arm/boot/dts/am335x-netcom-plus-8xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts index ad3adc7679f9..5a9fcec040fa 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts @@ -20,7 +20,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dip_switches>; - dip_switches: pinmux_dip_switches { + dip_switches: dip-switches-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -29,13 +29,13 @@ >; }; - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts similarity index 97% rename from arch/arm/boot/dts/am335x-osd3358-sm-red.dts rename to arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts index b2846cd220f0..d28d39728847 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts @@ -239,25 +239,25 @@ >; }; - flash_enable: flash-enable { + flash_enable: flash-enable-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ >; }; - imu_interrupt: imu-interrupt { + imu_interrupt: imu-interrupt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ >; }; - ethernet_interrupt: ethernet-interrupt{ + ethernet_interrupt: ethernet-interrupt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; - user_leds_s0: user-leds-s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -280,13 +280,13 @@ >; }; - clkout2_pin: pinmux-clkout2-pin { + clkout2_pin: pinmux-clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw-default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -304,7 +304,7 @@ >; }; - cpsw_sleep: cpsw-sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -322,7 +322,7 @@ >; }; - davinci_mdio_default: davinci-mdio-default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -330,7 +330,7 @@ >; }; - davinci_mdio_sleep: davinci-mdio-sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi similarity index 98% rename from arch/arm/boot/dts/am335x-osd335x-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi index 2888b15999ee..9863bf499a39 100644 --- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi @@ -54,7 +54,7 @@ }; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { interrupts = <7>; /* NMI */ diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi similarity index 95% rename from arch/arm/boot/dts/am335x-pcm-953.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi index 67c7fcc52ce6..75efe1cf1dd2 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi @@ -68,14 +68,14 @@ }; &am33xx_pinmux { - user_buttons_pins: pinmux-user-buttons { + user_buttons_pins: pinmux-user-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ >; }; - user_leds_pins: pinmux-user-leds { + user_leds_pins: pinmux-user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ @@ -85,7 +85,7 @@ /* CAN */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ @@ -101,7 +101,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { + ethernet1_pins: ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ @@ -142,7 +142,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cb_gpio_pins>; - cb_gpio_pins: pinmux-cb-gpio { + cb_gpio_pins: pinmux-cb-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ @@ -176,14 +176,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux-uart1 { + uart1_pins: pinmux-uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -192,14 +192,14 @@ >; }; - uart2_pins: pinmux-uart2 { + uart2_pins: pinmux-uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; - uart3_pins: pinmux-uart3 { + uart3_pins: pinmux-uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts similarity index 96% rename from arch/arm/boot/dts/am335x-pdu001.dts rename to arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index ce6cc2b96654..3c9444e98c14 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -90,28 +90,28 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -120,7 +120,7 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) @@ -128,27 +128,27 @@ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Port 1 (emac0) */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) @@ -186,14 +186,14 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { /* eMMC */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) @@ -205,7 +205,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { /* SD cardcage */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ @@ -219,7 +219,7 @@ >; }; - lcd_pins_s0: lcd_pins_s0 { + lcd_pins_s0: lcd-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -244,7 +244,7 @@ >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ @@ -400,7 +400,7 @@ status = "okay"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts similarity index 97% rename from arch/arm/boot/dts/am335x-pepper.dts rename to arch/arm/boot/dts/ti/omap/am335x-pepper.dts index a4509e9e1056..d5a4a21889d1 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -26,7 +26,7 @@ compatible = "gpio-keys"; }; - leds: user_leds { + leds: user-leds-pins { compatible = "gpio-leds"; }; @@ -88,13 +88,13 @@ }; &am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1 { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ @@ -125,7 +125,7 @@ }; &am33xx_pinmux { - accel_pins: pinmux_accel { + accel_pins: accel-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; @@ -172,7 +172,7 @@ }; &am33xx_pinmux { - audio_pins: pinmux_audio { + audio_pins: audio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -223,7 +223,7 @@ }; &am33xx_pinmux { - lcd_pins: pinmux_lcd { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -292,7 +292,7 @@ }; &am33xx_pinmux { - ethernet_pins: pinmux_ethernet { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ @@ -313,7 +313,7 @@ >; }; - mdio_pins: pinmux_mdio { + mdio_pins: mdio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) @@ -357,7 +357,7 @@ &am33xx_pinmux { - sd_pins: pinmux_sd_card { + sd_pins: sd-card-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -368,7 +368,7 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - emmc_pins: pinmux_emmc { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -384,7 +384,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ >; }; - wireless_pins: pinmux_wireless { + wireless_pins: wireless-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ @@ -423,7 +423,7 @@ vin-supply = <&vbat>; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { backlight { @@ -491,7 +491,7 @@ }; &am33xx_pinmux { - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -532,13 +532,13 @@ }; &am33xx_pinmux { - uart0_pins: pinmux_uart0 { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1 { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -563,7 +563,7 @@ }; &am33xx_pinmux { - usb_pins: pinmux_usb { + usb_pins: usb-pins { pinctrl-single,pins = < /* USB0 Over-Current (active low) */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ @@ -620,14 +620,14 @@ }; &am33xx_pinmux { - user_leds_pins: pinmux_user_leds { + user_leds_pins: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ >; }; - user_buttons_pins: pinmux_user_buttons { + user_buttons_pins: user-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ diff --git a/arch/arm/boot/dts/am335x-phycore-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-phycore-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi similarity index 97% rename from arch/arm/boot/dts/am335x-phycore-som.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi index 034dc5181679..84c15a44df6a 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi @@ -76,7 +76,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet0_pins: pinmux_ethernet0 { + ethernet0_pins: ethernet0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -89,7 +89,7 @@ >; }; - mdio_pins: pinmux_mdio { + mdio_pins: mdio-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -125,7 +125,7 @@ /* I2C Busses */ &am33xx_pinmux { - i2c0_pins: pinmux-i2c0 { + i2c0_pins: pinmux-i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) @@ -165,7 +165,7 @@ /* NAND memory */ &am33xx_pinmux { - nandflash_pins: pinmux-nandflash { + nandflash_pins: pinmux-nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -233,7 +233,7 @@ }; /* Power */ -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vcc5v>; @@ -316,7 +316,7 @@ /* SPI Busses */ &am33xx_pinmux { - spi0_pins: pinmux-spi0 { + spi0_pins: pinmux-spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts similarity index 96% rename from arch/arm/boot/dts/am335x-pocketbeagle.dts rename to arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts index 0ba4883cd4ef..5dfe4d4bab93 100644 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts @@ -214,7 +214,7 @@ &P2_17_gpio >; /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ - P2_03_gpio: pinmux_P2_03_gpio { + P2_03_gpio: P2-03-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -223,7 +223,7 @@ }; /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ - P1_34_gpio: pinmux_P1_34_gpio { + P1_34_gpio: P1-34-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -232,7 +232,7 @@ }; /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ - P2_19_gpio: pinmux_P2_19_gpio { + P2_19_gpio: P2-19-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -241,7 +241,7 @@ }; /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ - P2_24_gpio: pinmux_P2_24_gpio { + P2_24_gpio: P2-24-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -250,7 +250,7 @@ }; /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ - P2_33_gpio: pinmux_P2_33_gpio { + P2_33_gpio: P2-33-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -259,7 +259,7 @@ }; /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ - P2_22_gpio: pinmux_P2_22_gpio { + P2_22_gpio: P2-22-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -268,7 +268,7 @@ }; /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ - P2_18_gpio: pinmux_P2_18_gpio { + P2_18_gpio: P2-18-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -277,7 +277,7 @@ }; /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ - P2_10_gpio: pinmux_P2_10_gpio { + P2_10_gpio: P2-10-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -286,7 +286,7 @@ }; /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ - P2_06_gpio: pinmux_P2_06_gpio { + P2_06_gpio: P2-06-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -295,7 +295,7 @@ }; /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ - P2_04_gpio: pinmux_P2_04_gpio { + P2_04_gpio: P2-04-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -304,7 +304,7 @@ }; /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ - P2_02_gpio: pinmux_P2_02_gpio { + P2_02_gpio: P2-02-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -313,7 +313,7 @@ }; /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ - P2_08_gpio: pinmux_P2_08_gpio { + P2_08_gpio: P2-08-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) >; @@ -322,7 +322,7 @@ }; /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ - P2_17_gpio: pinmux_P2_17_gpio { + P2_17_gpio: P2-17-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) >; diff --git a/arch/arm/boot/dts/am335x-regor-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-regor-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi similarity index 95% rename from arch/arm/boot/dts/am335x-regor.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-regor.dtsi index 3894f14a914c..625db3bcd365 100644 --- a/arch/arm/boot/dts/am335x-regor.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi @@ -39,7 +39,7 @@ /* User Leds */ &am33xx_pinmux { - user_leds_pins: pinmux-user-leds { + user_leds_pins: pinmux-user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ @@ -49,7 +49,7 @@ /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -65,7 +65,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1 { + ethernet1_pins: pinmux-ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -108,7 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&user_gpios_pins>; - user_gpios_pins: pinmux-user-gpios { + user_gpios_pins: pinmux-user-gpios-pins { pinctrl-single,pins = < /* DIGIN 1-4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ @@ -126,7 +126,7 @@ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux-mmc1 { + mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -155,14 +155,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart2_pins: pinmux-uart2 { + uart2_pins: pinmux-uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi similarity index 96% rename from arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi index f9b7e774ac48..a138eb356874 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi @@ -4,7 +4,7 @@ */ &am33xx_pinmux { - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -22,7 +22,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -40,7 +40,7 @@ >; }; - usb_hub_ctrl: usb_hub_ctrl { + usb_hub_ctrl: usb-hub-ctrl-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ >; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts similarity index 96% rename from arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index a2676d10c24a..5522759def26 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -28,7 +28,7 @@ }; &am33xx_pinmux { - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < /* gpmc_a9.gpio1_25: RADIO_EN */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) @@ -53,14 +53,14 @@ >; }; - bluetooth_pins: pinmux_bluetooth_pins { + bluetooth_pins: bluetooth-pins { pinctrl-single,pins = < /* event_intr0.gpio0_19 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < /* uart1_rxd */ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts similarity index 96% rename from arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts index d6ef19311a91..b1b400226d83 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts @@ -19,7 +19,7 @@ }; &am33xx_pinmux { - bb_spi0_pins: pinmux_bb_spi0_pins { + bb_spi0_pins: bb-spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts similarity index 94% rename from arch/arm/boot/dts/am335x-sancloud-bbe.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts index efbe93135dbe..32669346cefe 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts @@ -17,13 +17,13 @@ }; &am33xx_pinmux { - mpu6050_pins: pinmux_mpu6050_pins { + mpu6050_pins: mpu6050-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ >; }; - lps3331ap_pins: pinmux_lps3331ap_pins { + lps3331ap_pins: lps3331ap-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts similarity index 98% rename from arch/arm/boot/dts/am335x-sbc-t335.dts rename to arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts index 81e4453687ba..596774c84744 100644 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts @@ -64,7 +64,7 @@ &am33xx_pinmux { /* Display */ - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) @@ -105,7 +105,7 @@ >; }; - lcd_pins_sleep: lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/ti/omap/am335x-shc.dts similarity index 96% rename from arch/arm/boot/dts/am335x-shc.dts rename to arch/arm/boot/dts/ti/omap/am335x-shc.dts index c497200f9cb0..9297cb1efcd4 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-shc.dts @@ -366,14 +366,14 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -392,7 +392,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -411,14 +411,14 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -426,13 +426,13 @@ >; }; - ehrpwm1_pins: pinmux_ehrpwm1 { + ehrpwm1_pins: ehrpwm1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) @@ -447,20 +447,20 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) @@ -471,7 +471,7 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) @@ -480,7 +480,7 @@ >; }; - uart1_pins: pinmux_uart1 { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) @@ -489,21 +489,21 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) >; }; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts similarity index 95% rename from arch/arm/boot/dts/am335x-sl50.dts rename to arch/arm/boot/dts/ti/omap/am335x-sl50.dts index 73b5d1a024bd..1115c812f6c8 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -213,7 +213,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; - audio_pins: pinmux_audio_pins { + audio_pins: audio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -223,31 +223,31 @@ >; }; - audio_pa_pins: pinmux_audio_pa_pins { + audio_pa_pins: audio-pa-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ >; }; - audio_mclk_pins: pinmux_audio_mclk_pins { + audio_mclk_pins: audio-mclk-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; - backlight0_pins: pinmux_backlight0_pins { + backlight0_pins: backlight0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; - backlight1_pins: pinmux_backlight1_pins { + backlight1_pins: backlight1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -272,7 +272,7 @@ >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -281,42 +281,42 @@ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) @@ -335,7 +335,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -354,7 +354,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -364,7 +364,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -372,19 +372,19 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; - emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { + emmc_pwrseq_pins: emmc-pwrseq-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -399,20 +399,20 @@ >; }; - ehrpwm1_pins: pinmux_ehrpwm1a_pins { + ehrpwm1_pins: ehrpwm1a-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ >; }; - rtc0_irq_pins: pinmux_rtc0_irq_pins { + rtc0_irq_pins: rtc0-irq-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ @@ -422,7 +422,7 @@ >; }; - lwb_pins: pinmux_lwb_pins { + lwb_pins: lwb-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ @@ -597,7 +597,7 @@ }; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { ti,pmic-shutdown-controller; diff --git a/arch/arm/boot/dts/am335x-wega-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-wega-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi similarity index 96% rename from arch/arm/boot/dts/am335x-wega.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-wega.dtsi index 6a103f17585b..cb27ff464dbe 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi @@ -49,7 +49,7 @@ /* Audio */ &am33xx_pinmux { - mcasp0_pins: pinmux-mcasp0 { + mcasp0_pins: pinmux-mcasp0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -90,7 +90,7 @@ /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -106,7 +106,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1 { + ethernet1_pins: pinmux-ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -146,7 +146,7 @@ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux-mmc1 { + mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -176,14 +176,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux-uart1 { + uart1_pins: pinmux-uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx-l4.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx.dtsi diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts similarity index 98% rename from arch/arm/boot/dts/am3517-craneboard.dts rename to arch/arm/boot/dts/ti/omap/am3517-craneboard.dts index 3642cfc80194..d035c888731f 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts @@ -69,10 +69,10 @@ status = "disabled"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &omap3_pmx_core { - tps_pins: pinmux_tps_pins { + tps_pins: tps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ >; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi similarity index 98% rename from arch/arm/boot/dts/am3517-evm-ui.dtsi rename to arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi index 75ad42179aee..16b8968d5be8 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi @@ -197,7 +197,7 @@ }; &omap3_pmx_core { - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ @@ -206,7 +206,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts similarity index 96% rename from arch/arm/boot/dts/am3517-evm.dts rename to arch/arm/boot/dts/ti/omap/am3517-evm.dts index 11618aa501fc..af9df15274be 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts @@ -242,7 +242,7 @@ &omap3_pmx_core { - ethernet_pins: pinmux_ethernet_pins { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ @@ -257,28 +257,28 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -291,19 +291,19 @@ >; }; - pwm_pins: pinmux_pwm_pins { + pwm_pins: pwm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ @@ -329,7 +329,7 @@ >; }; - hsusb1_rst_pins: pinmux_hsusb1_rst_pins { + hsusb1_rst_pins: hsusb1-rst-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; @@ -338,7 +338,7 @@ &omap3_pmx_core2 { - hsusb1_pins: pinmux_hsusb1_pins { + hsusb1_pins: hsusb1-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/ti/omap/am3517-som.dtsi similarity index 96% rename from arch/arm/boot/dts/am3517-som.dtsi rename to arch/arm/boot/dts/ti/omap/am3517-som.dtsi index f7b680f6c48a..bd0a6c95afa1 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517-som.dtsi @@ -181,20 +181,20 @@ &omap3_pmx_core { - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { + wl12xx_buffer_pins: wl12xx-buffer-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ @@ -210,19 +210,19 @@ >; }; - rtc_pins: pinmux_rtc_pins { + rtc_pins: rtc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ @@ -235,7 +235,7 @@ &omap3_pmx_wkup { - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + wl12xx_wkup_pins: wl12xx-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ >; diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi similarity index 100% rename from arch/arm/boot/dts/am3517.dtsi rename to arch/arm/boot/dts/ti/omap/am3517.dtsi diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts similarity index 100% rename from arch/arm/boot/dts/am3517_mt_ventoux.dts rename to arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am35xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am3703.dtsi b/arch/arm/boot/dts/ti/omap/am3703.dtsi similarity index 100% rename from arch/arm/boot/dts/am3703.dtsi rename to arch/arm/boot/dts/ti/omap/am3703.dtsi diff --git a/arch/arm/boot/dts/am3715.dtsi b/arch/arm/boot/dts/ti/omap/am3715.dtsi similarity index 100% rename from arch/arm/boot/dts/am3715.dtsi rename to arch/arm/boot/dts/ti/omap/am3715.dtsi diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts similarity index 98% rename from arch/arm/boot/dts/am3874-iceboard.dts rename to arch/arm/boot/dts/ti/omap/am3874-iceboard.dts index 791478e81c5a..ac082e83a9a2 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts @@ -285,7 +285,7 @@ }; &pincntl { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -299,19 +299,19 @@ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; }; - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ @@ -336,7 +336,7 @@ >; }; - gpio2_pins: pinmux_gpio2_pins { + gpio2_pins: gpio2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ @@ -349,7 +349,7 @@ >; }; - gpio4_pins: pinmux_gpio4_pins { + gpio4_pins: gpio4-pins { pinctrl-single,pins = < /* The PLL doesn't react well to the SPI controller reset, so * we force the CS lines to pull up as GPIOs until we're ready. @@ -364,14 +364,14 @@ >; }; - spi2_pins: pinmux_spi2_pins { + spi2_pins: spi2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ >; }; - spi4_pins: pinmux_spi4_pins { + spi4_pins: spi4-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0a7c, 0x20) DM814X_IOPAD(0x0b74, 0x20) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi similarity index 100% rename from arch/arm/boot/dts/am4372.dtsi rename to arch/arm/boot/dts/ti/omap/am4372.dtsi diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts similarity index 97% rename from arch/arm/boot/dts/am437x-cm-t43.dts rename to arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts index 0861e868b75a..9ec75d03eaff 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts @@ -38,20 +38,20 @@ pinctrl-names = "default"; pinctrl-0 = <&cm_t43_led_pins>; - cm_t43_led_pins: cm_t43_led_pins { + cm_t43_led_pins: cm-t43-led-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa78, MUX_MODE7) >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - emmc_pins: emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ @@ -66,7 +66,7 @@ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -75,7 +75,7 @@ >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8: nand-flash-x8-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) @@ -95,7 +95,7 @@ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ @@ -128,7 +128,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts similarity index 95% rename from arch/arm/boot/dts/am437x-gp-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts index 46d5361fe876..f7aad0323d19 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts @@ -153,45 +153,45 @@ pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; pinctrl-1 = <&wlan_pins_sleep>; - ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + ddr3_vtt_toggle_default: ddr-vtt-toggle-default-pins { pinctrl-single,pins = < 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; - pixcir_ts_pins: pixcir_ts_pins { + pixcir_ts_pins: pixcir-ts-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ @@ -209,7 +209,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -227,7 +227,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -235,7 +235,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -243,7 +243,7 @@ >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8: nand-flash-x8-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ @@ -263,7 +263,7 @@ >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) @@ -297,42 +297,42 @@ >; }; - display_mux_pins: display_mux_pins { + display_mux_pins: display-mux-pins { pinctrl-single,pins = < /* GPIO 5_8 to select LCD / HDMI */ AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - dcan0_default: dcan0_default_pins { + dcan0_default: dcan0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; - dcan0_sleep: dcan0_sleep_pins { + dcan0_sleep: dcan0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ >; }; - dcan1_default: dcan1_default_pins { + dcan1_default: dcan1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ >; }; - dcan1_sleep: dcan1_sleep_pins { + dcan1_sleep: dcan1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ >; }; - vpfe0_pins_default: vpfe0_pins_default { + vpfe0_pins_default: vpfe0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ @@ -350,7 +350,7 @@ >; }; - vpfe0_pins_sleep: vpfe0_pins_sleep { + vpfe0_pins_sleep: vpfe0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ @@ -368,7 +368,7 @@ >; }; - vpfe1_pins_default: vpfe1_pins_default { + vpfe1_pins_default: vpfe1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ @@ -386,7 +386,7 @@ >; }; - vpfe1_pins_sleep: vpfe1_pins_sleep { + vpfe1_pins_sleep: vpfe1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ @@ -404,7 +404,7 @@ >; }; - mmc3_pins_default: pinmux_mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ @@ -415,7 +415,7 @@ >; }; - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + mmc3_pins_sleep: mmc3-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ @@ -426,7 +426,7 @@ >; }; - wlan_pins_default: pinmux_wlan_pins_default { + wlan_pins_default: wlan-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ @@ -434,7 +434,7 @@ >; }; - wlan_pins_sleep: pinmux_wlan_pins_sleep { + wlan_pins_sleep: wlan-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ @@ -442,7 +442,7 @@ >; }; - uart3_pins: uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ @@ -451,7 +451,7 @@ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ @@ -460,7 +460,7 @@ >; }; - mcasp1_sleep_pins: mcasp1_sleep_pins { + mcasp1_sleep_pins: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -469,13 +469,13 @@ >; }; - gpio0_pins: gpio0_pins { + gpio0_pins: gpio0-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ >; }; - emmc_pins_default: emmc_pins_default { + emmc_pins_default: emmc-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ @@ -490,7 +490,7 @@ >; }; - emmc_pins_sleep: emmc_pins_sleep { + emmc_pins_sleep: emmc-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ @@ -505,19 +505,19 @@ >; }; - beeper_pins_default: beeper_pins_default { + beeper_pins_default: beeper-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; - beeper_pins_sleep: beeper_pins_sleep { + beeper_pins_sleep: beeper-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; - unused_pins: unused_pins { + unused_pins: unused-pins { pinctrl-single,pins = < AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -566,7 +566,7 @@ >; }; - debugss_pins: pinmux_debugss_pins { + debugss_pins: debugss-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) @@ -578,7 +578,7 @@ >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ @@ -587,7 +587,7 @@ >; }; - uart0_pins_sleep: uart0_pins_sleep { + uart0_pins_sleep: uart0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ @@ -596,7 +596,7 @@ >; }; - matrix_keypad_default: matrix_keypad_default { + matrix_keypad_default: matrix-keypad-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) @@ -605,7 +605,7 @@ >; }; - matrix_keypad_sleep: matrix_keypad_sleep { + matrix_keypad_sleep: matrix-keypad-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts similarity index 95% rename from arch/arm/boot/dts/am437x-idk-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts index e46cf2a9d075..863552393c07 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts @@ -171,41 +171,41 @@ }; &am43xx_pinmux { - gpio_keys_pins_default: gpio_keys_pins_default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ >; }; - i2c0_pins_default: i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c0_pins_sleep: i2c0_pins_sleep { + i2c0_pins_sleep: i2c0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - i2c2_pins_default: i2c2_pins_default { + i2c2_pins_default: i2c2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ >; }; - i2c2_pins_sleep: i2c2_pins_sleep { + i2c2_pins_sleep: i2c2-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ @@ -217,7 +217,7 @@ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -229,7 +229,7 @@ >; }; - spi1_pins_default: spi1_pins_default { + spi1_pins_default: spi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ @@ -238,7 +238,7 @@ >; }; - spi1_pins_sleep: spi1_pins_sleep { + spi1_pins_sleep: spi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -247,13 +247,13 @@ >; }; - ecap0_pins_default: backlight_pins_default { + ecap0_pins_default: backlight-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -270,7 +270,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -287,7 +287,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -295,7 +295,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -303,7 +303,7 @@ >; }; - qspi_pins_default: qspi_pins_default { + qspi_pins_default: qspi-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ @@ -314,7 +314,7 @@ >; }; - qspi_pins_sleep: qspi_pins_sleep{ + qspi_pins_sleep: qspi-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/am437x-l4.dtsi rename to arch/arm/boot/dts/ti/omap/am437x-l4.dtsi diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts similarity index 95% rename from arch/arm/boot/dts/am437x-sbc-t43.dts rename to arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts index 8ea3780f939d..34a5407bee15 100644 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts @@ -16,7 +16,7 @@ }; &am43xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ @@ -29,7 +29,7 @@ >; }; - dss_pinctrl_default: dss_pinctrl_default { + dss_pinctrl_default: dss-pinctrl-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) @@ -64,7 +64,7 @@ >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) @@ -73,27 +73,27 @@ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ >; }; - i2c2_pins: i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - usb2_phy1_default: usb2_phy1_default { + usb2_phy1_default: usb2-phy1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy2_default: usb2_phy2_default { + usb2_phy2_default: usb2-phy2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) >; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts similarity index 96% rename from arch/arm/boot/dts/am437x-sk-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts index 511a02e13e2c..9c97006ffd5b 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts @@ -159,7 +159,7 @@ }; &am43xx_pinmux { - matrix_keypad_pins: matrix_keypad_pins { + matrix_keypad_pins: matrix-keypad-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ @@ -168,7 +168,7 @@ >; }; - leds_pins: leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ @@ -177,21 +177,21 @@ >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ @@ -203,20 +203,20 @@ >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ >; }; - edt_ft5306_ts_pins: edt_ft5306_ts_pins { + edt_ft5306_ts_pins: edt-ft5306-ts-pins { pinctrl-single,pins = < AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ >; }; - vpfe0_pins_default: vpfe0_pins_default { + vpfe0_pins_default: vpfe0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ @@ -236,7 +236,7 @@ >; }; - vpfe0_pins_sleep: vpfe0_pins_sleep { + vpfe0_pins_sleep: vpfe0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -256,13 +256,13 @@ >; }; - clkout1_pin: pinmux_clkout1_pin { + clkout1_pin: clkout1-pins { pinctrl-single,pins = < 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ @@ -294,7 +294,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -326,7 +326,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -334,7 +334,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -342,7 +342,7 @@ >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) @@ -376,7 +376,7 @@ >; }; - qspi_pins: qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ @@ -387,7 +387,7 @@ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -396,7 +396,7 @@ >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -405,25 +405,25 @@ >; }; - lcd_pins: lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ >; }; - usb1_pins: usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; - usb2_pins: usb2_pins { + usb2_pins: usb2-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; - mmc3_pins_default: pinmux_mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ @@ -434,7 +434,7 @@ >; }; - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + mmc3_pins_sleep: mmc3-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ @@ -445,21 +445,21 @@ >; }; - wlan_pins_default: pinmux_wlan_pins_default { + wlan_pins_default: wlan-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; - wlan_pins_sleep: pinmux_wlan_pins_sleep { + wlan_pins_sleep: wlan-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; - uart1_bt_pins_default: pinmux_uart1_bt_pins_default { + uart1_bt_pins_default: uart1-bt-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ @@ -469,7 +469,7 @@ >; }; - uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { + uart1_bt_pins_sleep: uart1-bt-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts similarity index 95% rename from arch/arm/boot/dts/am43x-epos-evm.dts rename to arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts index 9fc915a2582e..9193a4cfba78 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts @@ -141,7 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&unused_pins>; - unused_pins: unused_pins { + unused_pins: unused-pins { pinctrl-single,pins = < AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -175,7 +175,7 @@ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ @@ -190,7 +190,7 @@ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -205,7 +205,7 @@ >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -213,7 +213,7 @@ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -221,14 +221,14 @@ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - nand_flash_x8_default: nand_flash_x8_default { + nand_flash_x8_default: nand-flash-x8-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ @@ -249,7 +249,7 @@ >; }; - nand_flash_x8_sleep: nand_flash_x8_sleep { + nand_flash_x8_sleep: nand-flash-x8-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) @@ -270,26 +270,26 @@ >; }; - ecap0_pins_default: backlight_pins_default { + ecap0_pins_default: backlight-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; - ecap0_pins_sleep: backlight_pins_sleep { + ecap0_pins_sleep: backlight-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ >; }; - spi0_pins_default: pinmux_spi0_pins_default { + spi0_pins_default: spi0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -298,7 +298,7 @@ >; }; - spi0_pins_sleep: pinmux_spi0_pins_sleep { + spi0_pins_sleep: spi0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -307,7 +307,7 @@ >; }; - spi1_pins_default: pinmux_spi1_pins_default { + spi1_pins_default: spi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -316,7 +316,7 @@ >; }; - spi1_pins_sleep: pinmux_spi1_pins_sleep { + spi1_pins_sleep: spi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) @@ -325,19 +325,19 @@ >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) >; }; - matrix_keypad_default: matrix_keypad_default { + matrix_keypad_default: matrix-keypad-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ @@ -350,7 +350,7 @@ >; }; - matrix_keypad_sleep: matrix_keypad_sleep { + matrix_keypad_sleep: matrix-keypad-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) @@ -363,7 +363,7 @@ >; }; - qspi1_pins_default: qspi1_pins_default { + qspi1_pins_default: qspi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) @@ -374,7 +374,7 @@ >; }; - qspi1_pins_sleep: qspi1_pins_sleep { + qspi1_pins_sleep: qspi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -385,25 +385,25 @@ >; }; - pixcir_ts_pins_default: pixcir_ts_pins_default { + pixcir_ts_pins_default: pixcir-ts-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; - pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { + pixcir_ts_pins_sleep: pixcir-ts-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; - hdq_pins: pinmux_hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) @@ -436,14 +436,14 @@ >; }; - display_mux_pins: display_mux_pins { + display_mux_pins: display-mux-pins { pinctrl-single,pins = < /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - vpfe1_pins_default: vpfe1_pins_default { + vpfe1_pins_default: vpfe1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ @@ -461,7 +461,7 @@ >; }; - vpfe1_pins_sleep: vpfe1_pins_sleep { + vpfe1_pins_sleep: vpfe1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -479,7 +479,7 @@ >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ @@ -488,7 +488,7 @@ >; }; - uart0_pins_sleep: uart0_pins_sleep { + uart0_pins_sleep: uart0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -497,31 +497,31 @@ >; }; - usb2_phy1_default: usb2_phy1_default { + usb2_phy1_default: usb2-phy1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy1_sleep: usb2_phy1_sleep { + usb2_phy1_sleep: usb2-phy1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - usb2_phy2_default: usb2_phy2_default { + usb2_phy2_default: usb2-phy2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy2_sleep: usb2_phy2_sleep { + usb2_phy2_sleep: usb2-phy2-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ @@ -530,7 +530,7 @@ >; }; - mcasp1_sleep_pins: mcasp1_sleep_pins { + mcasp1_sleep_pins: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am43xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi similarity index 100% rename from arch/arm/boot/dts/am57-pruss.dtsi rename to arch/arm/boot/dts/ti/omap/am57-pruss.dtsi diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/ti/omap/am5718.dtsi similarity index 100% rename from arch/arm/boot/dts/am5718.dtsi rename to arch/arm/boot/dts/ti/omap/am5718.dtsi diff --git a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso similarity index 100% rename from arch/arm/boot/dts/am571x-idk-touchscreen.dtso rename to arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/ti/omap/am571x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am571x-idk.dts rename to arch/arm/boot/dts/ti/omap/am571x-idk.dts diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/ti/omap/am5728.dtsi similarity index 100% rename from arch/arm/boot/dts/am5728.dtsi rename to arch/arm/boot/dts/ti/omap/am5728.dtsi diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts similarity index 100% rename from arch/arm/boot/dts/am5729-beagleboneai.dts rename to arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am572x-idk-common.dtsi rename to arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi diff --git a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso similarity index 100% rename from arch/arm/boot/dts/am572x-idk-touchscreen.dtso rename to arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/ti/omap/am572x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am572x-idk.dts rename to arch/arm/boot/dts/ti/omap/am572x-idk.dts diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/ti/omap/am5748.dtsi similarity index 100% rename from arch/arm/boot/dts/am5748.dtsi rename to arch/arm/boot/dts/ti/omap/am5748.dtsi diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/ti/omap/am574x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am574x-idk.dts rename to arch/arm/boot/dts/ti/omap/am574x-idk.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-revc.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts similarity index 96% rename from arch/arm/boot/dts/am57xx-cl-som-am57x.dts rename to arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts index 625b9b311b49..4fd831ff206f 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts @@ -77,40 +77,40 @@ }; &dra7_pmx_core { - leds_pins_default: leds_pins_default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ >; }; - i2c1_pins_default: i2c1_pins_default { + i2c1_pins_default: i2c1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ >; }; - i2c3_pins_default: i2c3_pins_default { + i2c3_pins_default: i2c3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ >; }; - i2c4_pins_default: i2c4_pins_default { + i2c4_pins_default: i2c4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ >; }; - tps659038_pins_default: tps659038_pins_default { + tps659038_pins_default: tps659038-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -125,7 +125,7 @@ >; }; - qspi1_pins: pinmux_qspi1_pins { + qspi1_pins: qspi1-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ @@ -136,7 +136,7 @@ >; }; - cpsw_pins_default: cpsw_pins_default { + cpsw_pins_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave at addr 0x0 */ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ @@ -168,7 +168,7 @@ >; }; - cpsw_pins_sleep: cpsw_pins_sleep { + cpsw_pins_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 */ DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) @@ -200,7 +200,7 @@ >; }; - davinci_mdio_pins_default: davinci_mdio_pins_default { + davinci_mdio_pins_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ @@ -208,20 +208,20 @@ >; }; - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { + davinci_mdio_pins_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ >; }; - mcasp3_pins_default: mcasp3_pins_default { + mcasp3_pins_default: mcasp3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ @@ -230,7 +230,7 @@ >; }; - mcasp3_pins_sleep: mcasp3_pins_sleep { + mcasp3_pins_sleep: mcasp3-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) diff --git a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-commercial-grade.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi diff --git a/arch/arm/boot/dts/am57xx-evm.dtso b/arch/arm/boot/dts/ti/omap/am57xx-evm.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-evm.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-evm.dtso diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi similarity index 99% rename from arch/arm/boot/dts/am57xx-idk-common.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi index 7f092a8811e8..43e3623f079c 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi @@ -158,14 +158,14 @@ }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso diff --git a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-industrial-grade.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts similarity index 93% rename from arch/arm/boot/dts/am57xx-sbc-am57x.dts rename to arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts index beef63e8a005..363115afb0a4 100644 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts @@ -20,14 +20,14 @@ }; &dra7_pmx_core { - uart3_pins_default: uart3_pins_default { + uart3_pins_default: uart3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -40,33 +40,33 @@ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ >; }; - i2c5_pins_default: i2c5_pins_default { + i2c5_pins_default: i2c5-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ >; }; - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ >; }; - hdmi_pins: pinmux_hdmi_pins { + hdmi_pins: hdmi-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ >; }; - hdmi_conn_pins: pinmux_hdmi_conn_pins { + hdmi_conn_pins: hdmi-conn-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ >; diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi similarity index 100% rename from arch/arm/boot/dts/compulab-sb-som.dtsi rename to arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi diff --git a/arch/arm/boot/dts/dm3725.dtsi b/arch/arm/boot/dts/ti/omap/dm3725.dtsi similarity index 100% rename from arch/arm/boot/dts/dm3725.dtsi rename to arch/arm/boot/dts/ti/omap/dm3725.dtsi diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts similarity index 97% rename from arch/arm/boot/dts/dm8148-evm.dts rename to arch/arm/boot/dts/ti/omap/dm8148-evm.dts index fe3f9a970b18..ae8d9fa09d16 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts @@ -116,7 +116,7 @@ }; &pincntl { - sd1_pins: pinmux_sd1_pins { + sd1_pins: sd1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -129,13 +129,13 @@ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/ti/omap/dm8148-t410.dts similarity index 96% rename from arch/arm/boot/dts/dm8148-t410.dts rename to arch/arm/boot/dts/ti/omap/dm8148-t410.dts index 79ccdd4470f4..f3e2ecf6d723 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/ti/omap/dm8148-t410.dts @@ -71,7 +71,7 @@ }; &pincntl { - sd2_pins: pinmux_sd2_pins { + sd2_pins: sd2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ @@ -87,13 +87,13 @@ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dm814x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/ti/omap/dm814x.dtsi similarity index 100% rename from arch/arm/boot/dts/dm814x.dtsi rename to arch/arm/boot/dts/ti/omap/dm814x.dtsi diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts similarity index 97% rename from arch/arm/boot/dts/dm8168-evm.dts rename to arch/arm/boot/dts/ti/omap/dm8168-evm.dts index 244a957f9ba3..1d80288f6ba5 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts @@ -30,7 +30,7 @@ }; &dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ @@ -39,7 +39,7 @@ >; }; - mmc_pins: pinmux_mmc_pins { + mmc_pins: mmc-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ @@ -53,19 +53,19 @@ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; - nandflash_pins: nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dm816x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi similarity index 100% rename from arch/arm/boot/dts/dm816x.dtsi rename to arch/arm/boot/dts/ti/omap/dm816x.dtsi diff --git a/arch/arm/boot/dts/dra62x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dra62x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts similarity index 98% rename from arch/arm/boot/dts/dra62x-j5eco-evm.dts rename to arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts index 577114c4c20a..2f6ac267fc15 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts @@ -108,7 +108,7 @@ }; &pincntl { - sd1_pins: pinmux_sd1_pins { + sd1_pins: sd1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -121,7 +121,7 @@ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/ti/omap/dra62x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra62x.dtsi rename to arch/arm/boot/dts/ti/omap/dra62x.dtsi diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-dspeve-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/ti/omap/dra7-evm.dts similarity index 99% rename from arch/arm/boot/dts/dra7-evm.dts rename to arch/arm/boot/dts/ti/omap/dra7-evm.dts index 8cbcf55a5a33..46efbaa67a8e 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dra7-evm.dts @@ -152,14 +152,14 @@ }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-iva-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-l4.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-l4.dtsi diff --git a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi similarity index 92% rename from arch/arm/boot/dts/dra7-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi index aa0947266526..cb1a682c26cd 100644 --- a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi @@ -6,7 +6,7 @@ */ &dra7_pmx_core { - mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { + mmc1_pins_default_no_clk_pu: mmc1-default-no-clk-pu-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7.dtsi rename to arch/arm/boot/dts/ti/omap/dra7.dtsi diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/ti/omap/dra71-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra71-evm.dts rename to arch/arm/boot/dts/ti/omap/dra71-evm.dts diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/ti/omap/dra71x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra71x.dtsi rename to arch/arm/boot/dts/ti/omap/dra71x.dtsi diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi similarity index 99% rename from arch/arm/boot/dts/dra72-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi index c79ba671ec2b..31ab0c60ca75 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi @@ -197,14 +197,14 @@ }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts similarity index 100% rename from arch/arm/boot/dts/dra72-evm-revc.dts rename to arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72-evm-tps65917.dtsi rename to arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/ti/omap/dra72-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra72-evm.dts rename to arch/arm/boot/dts/ti/omap/dra72-evm.dts diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi similarity index 97% rename from arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi index 34eea3c048bd..d006f1dfdeb5 100644 --- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi @@ -32,7 +32,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -43,7 +43,7 @@ >; }; - mmc1_pins_sdr12: mmc1_pins_sdr12 { + mmc1_pins_sdr12: mmc1-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -54,7 +54,7 @@ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -65,7 +65,7 @@ >; }; - mmc1_pins_sdr25: mmc1_pins_sdr25 { + mmc1_pins_sdr25: mmc1-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -76,7 +76,7 @@ >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -87,7 +87,7 @@ >; }; - mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { + mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ @@ -98,7 +98,7 @@ >; }; - mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { + mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -109,7 +109,7 @@ >; }; - mmc1_pins_sdr104: mmc1_pins_sdr104 { + mmc1_pins_sdr104: mmc1-sdr104-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -120,7 +120,7 @@ >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -135,7 +135,7 @@ >; }; - mmc2_pins_hs: mmc2_pins_hs { + mmc2_pins_hs: mmc2-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -150,7 +150,7 @@ >; }; - mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { + mmc2_pins_ddr_rev10: mmc2-ddr-rev10-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ @@ -165,7 +165,7 @@ >; }; - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -180,7 +180,7 @@ >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -195,7 +195,7 @@ >; }; - mmc4_pins_default: mmc4_pins_default { + mmc4_pins_default: mmc4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/ti/omap/dra72x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72x.dtsi rename to arch/arm/boot/dts/ti/omap/dra72x.dtsi diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi similarity index 97% rename from arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi index b9d040135c5f..e2fdb0702f5c 100644 --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi @@ -30,7 +30,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -41,7 +41,7 @@ >; }; - mmc1_pins_sdr12: mmc1_pins_sdr12 { + mmc1_pins_sdr12: mmc1-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -52,7 +52,7 @@ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -63,7 +63,7 @@ >; }; - mmc1_pins_sdr25: mmc1_pins_sdr25 { + mmc1_pins_sdr25: mmc1-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -74,7 +74,7 @@ >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -85,7 +85,7 @@ >; }; - mmc1_pins_ddr50: mmc1_pins_ddr50 { + mmc1_pins_ddr50: mmc1-ddr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -96,7 +96,7 @@ >; }; - mmc1_pins_sdr104: mmc1_pins_sdr104 { + mmc1_pins_sdr104: mmc1-sdr104-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -107,7 +107,7 @@ >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -122,7 +122,7 @@ >; }; - mmc2_pins_hs: mmc2_pins_hs { + mmc2_pins_hs: mmc2-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -137,7 +137,7 @@ >; }; - mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { + mmc2_pins_ddr_3_3v_rev11: mmc2-ddr-3-3v-rev11-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -152,7 +152,7 @@ >; }; - mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { + mmc2_pins_ddr_1_8v_rev11: mmc2-ddr-1-8v-rev11-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -167,7 +167,7 @@ >; }; - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -182,7 +182,7 @@ >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -197,7 +197,7 @@ >; }; - mmc4_pins_default: mmc4_pins_default { + mmc4_pins_default: mmc4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -208,7 +208,7 @@ >; }; - mmc4_pins_hs: mmc4_pins_hs { + mmc4_pins_hs: mmc4-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -219,7 +219,7 @@ >; }; - mmc3_pins_default: mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -230,7 +230,7 @@ >; }; - mmc3_pins_hs: mmc3_pins_hs { + mmc3_pins_hs: mmc3-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -241,7 +241,7 @@ >; }; - mmc3_pins_sdr12: mmc3_pins_sdr12 { + mmc3_pins_sdr12: mmc3-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -252,7 +252,7 @@ >; }; - mmc3_pins_sdr25: mmc3_pins_sdr25 { + mmc3_pins_sdr25: mmc3-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -263,7 +263,7 @@ >; }; - mmc3_pins_sdr50: mmc3_pins_sdr50 { + mmc3_pins_sdr50: mmc3-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -274,7 +274,7 @@ >; }; - mmc4_pins_sdr12: mmc4_pins_sdr12 { + mmc4_pins_sdr12: mmc4-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -285,7 +285,7 @@ >; }; - mmc4_pins_sdr25: mmc4_pins_sdr25 { + mmc4_pins_sdr25: mmc4-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ diff --git a/arch/arm/boot/dts/dra74x-p.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74x-p.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x-p.dtsi diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/ti/omap/dra74x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74x.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x.dtsi diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/ti/omap/dra76-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra76-evm.dts rename to arch/arm/boot/dts/ti/omap/dra76-evm.dts diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi similarity index 98% rename from arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi index fdca48186916..4690554dfa6e 100644 --- a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi @@ -27,7 +27,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -38,7 +38,7 @@ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -49,7 +49,7 @@ >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -60,7 +60,7 @@ >; }; - mmc1_pins_ddr50: mmc1_pins_ddr50 { + mmc1_pins_ddr50: mmc1-ddr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -71,7 +71,7 @@ >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -86,7 +86,7 @@ >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -101,7 +101,7 @@ >; }; - mmc3_pins_default: mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -112,7 +112,7 @@ >; }; - mmc4_pins_hs: mmc4_pins_hs { + mmc4_pins_hs: mmc4-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra76x.dtsi rename to arch/arm/boot/dts/ti/omap/dra76x.dtsi diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi similarity index 100% rename from arch/arm/boot/dts/elpida_ecb240abacn.dtsi rename to arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts similarity index 96% rename from arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts index 3240c67e0c39..c1705f6f3d10 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts @@ -15,7 +15,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts similarity index 96% rename from arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts index c757f0d7781c..9dbbcc7ced7c 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts @@ -15,7 +15,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi similarity index 95% rename from arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi index 7d0468a23781..690f2ad50c65 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi @@ -141,25 +141,25 @@ }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ >; }; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -172,13 +172,13 @@ >; }; - lcd_enable_pin: pinmux_lcd_enable_pin { + lcd_enable_pin: lcd-enable-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins1 { + dss_dpi_pins1: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -206,13 +206,13 @@ }; &omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { + led_pins_wkup: led-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ >; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi similarity index 95% rename from arch/arm/boot/dts/logicpd-som-lv.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi index 9ba0ea4eb48a..c0e6b73fa472 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi @@ -157,7 +157,7 @@ &omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { + mmc3_pins: mm3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ @@ -167,7 +167,7 @@ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ @@ -175,7 +175,7 @@ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -184,7 +184,7 @@ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -193,7 +193,7 @@ >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -204,7 +204,7 @@ >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -221,7 +221,7 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ @@ -229,21 +229,21 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ >; @@ -252,12 +252,12 @@ &omap3_pmx_wkup { - hsusb2_reset_pin: pinmux_hsusb1_reset_pin { + hsusb2_reset_pin: hsusb1-reset-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; - wl127x_gpio: pinmux_wl127x_gpio_pin { + wl127x_gpio: wl127x-gpio-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts similarity index 92% rename from arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts index cb08aa62d967..eaa583fdc3d6 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts @@ -13,7 +13,7 @@ }; &omap3_pmx_core { - isp1763_pins: pinmux_isp1763_pins { + isp1763_pins: isp1763-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts similarity index 96% rename from arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts index 07ea822fe405..533ce7ce387a 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts @@ -65,7 +65,7 @@ }; &omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { + mmc3_pins: mm3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ @@ -78,7 +78,7 @@ }; &omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { + mmc3_core2_pins: mmc3-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -88,7 +88,7 @@ /* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ &omap3_pmx_wkup { - isp1763_pins: pinmux_isp1763_pins { + isp1763_pins: isp1763-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi similarity index 96% rename from arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi index e0cbac500e17..e0caed539810 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi @@ -209,33 +209,33 @@ }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ >; }; - hdq_pins: hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ >; }; - pwm_pins: pinmux_pwm_pins { + pwm_pins: pwm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -246,19 +246,19 @@ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ >; }; - isp_pins: pinmux_isp_pins { + isp_pins: isp-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ @@ -276,13 +276,13 @@ >; }; - panel_pwr_pins: pinmux_panel_pwr_pins { + panel_pwr_pins: panel-pwr-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins1 { + dss_dpi_pins1: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -313,20 +313,20 @@ }; &omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { + gpio_key_pins_wkup: gpio-key-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ >; }; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ >; }; - mmc1_cd: pinmux_mmc1_cd { + mmc1_cd: mmc1-cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi similarity index 95% rename from arch/arm/boot/dts/logicpd-torpedo-som.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi index 72b5af475d09..227699890890 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi @@ -111,7 +111,7 @@ }; &omap3_pmx_core { - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ @@ -119,7 +119,7 @@ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -128,7 +128,7 @@ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -136,7 +136,7 @@ OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -153,19 +153,19 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi similarity index 100% rename from arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi rename to arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi similarity index 95% rename from arch/arm/boot/dts/motorola-mapphone-common.dtsi rename to arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi index f7cc8fc678fa..091ba310053e 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi @@ -352,13 +352,13 @@ &omap4_pmx_core { /* hdmi_hpd.gpio_63 */ - hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { + hdmi_hpd_gpio: hdmi-hpd-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) >; }; - hdq_pins: pinmux_hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < /* 0x4a100120 hdq_sio.hdq_sio aa27 */ OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) @@ -366,7 +366,7 @@ }; /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) @@ -380,7 +380,7 @@ * devices. Off mode value should be tested if we have off mode working * later on. */ - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) @@ -406,40 +406,40 @@ }; /* gpmc_ncs0.gpio_50 */ - poweroff_gpio: pinmux_poweroff_pins { + poweroff_gpio: poweroff-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) >; }; /* kpd_row0.gpio_178 */ - tmp105_irq: pinmux_tmp105_irq { + tmp105_irq: tmp105-irq-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { + usb_gpio_mux_sel1: usb-gpio-mux-sel1-pins { /* gpio_60 */ pinctrl-single,pins = < OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) >; }; - touchscreen_pins: pinmux_touchscreen_pins { + touchscreen_pins: touchscreen-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - als_proximity_pins: pinmux_als_proximity_pins { + als_proximity_pins: als-proximity-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - usb_mdm6600_pins: pinmux_usb_mdm6600_pins { + usb_mdm6600_pins: usb-mdm6600-pins { pinctrl-single,pins = < /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) @@ -476,7 +476,7 @@ >; }; - usb_ulpi_pins: pinmux_usb_ulpi_pins { + usb_ulpi_pins: usb-ulpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) OMAP4_IOPAD(0x198, MUX_MODE7) @@ -496,7 +496,7 @@ }; /* usb0_otg_dp and usb0_otg_dm */ - usb_utmi_pins: pinmux_usb_utmi_pins { + usb_utmi_pins: usb-utmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) @@ -521,7 +521,7 @@ * when not used. If needed, we can add rts pin remux later based * on power measurements. */ - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) @@ -538,7 +538,7 @@ }; /* uart3_tx_irtx and uart3_rx_irrx */ - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) OMAP4_IOPAD(0x198, MUX_MODE7) @@ -557,7 +557,7 @@ >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ @@ -566,7 +566,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ @@ -575,7 +575,7 @@ >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ @@ -584,13 +584,13 @@ >; }; - vibrator_direction_pin: pinmux_vibrator_direction_pin { + vibrator_direction_pin: vibrator-direction-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ >; }; - vibrator_enable_pin: pinmux_vibrator_enable_pin { + vibrator_enable_pin: vibrator-enable-pins { pinctrl-single,pins = < OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ >; @@ -598,7 +598,7 @@ }; &omap4_pmx_wkup { - usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + usb_gpio_mux_sel2: usb-gpio-mux-sel2-pins { /* gpio_wk0 */ pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi rename to arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi rename to arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-zoom-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2.dtsi rename to arch/arm/boot/dts/ti/omap/omap2.dtsi diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-h4.dts rename to arch/arm/boot/dts/ti/omap/omap2420-h4.dts diff --git a/arch/arm/boot/dts/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-n800.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n800.dts diff --git a/arch/arm/boot/dts/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-n810-wimax.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts similarity index 97% rename from arch/arm/boot/dts/omap2420-n810.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n810.dts index 09c1dbc0bb69..3bf8175d85a8 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts @@ -23,7 +23,7 @@ }; &omap2420_pmx { - mcbsp2_pins: mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ @@ -32,7 +32,7 @@ >; }; - aic33_pins: aic33_pins { + aic33_pins: aic33-pins { pinctrl-single,pins = < OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420-n8x0-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420.dtsi diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2430-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts similarity index 100% rename from arch/arm/boot/dts/omap2430-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap2430-sdp.dts diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2430.dtsi rename to arch/arm/boot/dts/ti/omap/omap2430.dtsi diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap24xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap3-beagle-ab4.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle-ab4.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts diff --git a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle-xm-ab.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts similarity index 97% rename from arch/arm/boot/dts/omap3-beagle-xm.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts index 1a085bc01317..08ee0f8ea68f 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts @@ -90,7 +90,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; @@ -183,13 +183,13 @@ }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; - dss_dpi_pins2: pinmux_dss_dpi_pins1 { + dss_dpi_pins2: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ @@ -207,14 +207,14 @@ &hsusb2_pins >; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -225,7 +225,7 @@ >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins2 { + dss_dpi_pins1: dss-dpi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -261,7 +261,7 @@ &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle.dts similarity index 97% rename from arch/arm/boot/dts/omap3-beagle.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle.dts index 47ff1ffddfc5..4d9a8eab6abf 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle.dts @@ -57,7 +57,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; @@ -170,7 +170,7 @@ }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ >; @@ -183,7 +183,7 @@ &hsusb2_pins >; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -194,20 +194,20 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -247,7 +247,7 @@ &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts similarity index 92% rename from arch/arm/boot/dts/omap3-cm-t3517.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts index f25c0a84a190..f776e0527049 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts @@ -43,7 +43,7 @@ &omap3_pmx_wkup { - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + wl12xx_wkup_pins: wl12xx-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ @@ -53,25 +53,25 @@ &omap3_pmx_core { - phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { + phy1_reset_pins: hsusb1-phy-reset-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ >; }; - phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { + phy2_reset_pins: hsusb2-phy-reset-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ >; }; - otg_drv_vbus: pinmux_otg_drv_vbus { + otg_drv_vbus: otg-drv-vbus-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -82,14 +82,14 @@ >; }; - wl12xx_core_pins: pinmux_wl12xx_core_pins { + wl12xx_core_pins: wl12xx-core-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - usb_hub_pins: pinmux_usb_hub_pins { + usb_hub_pins: usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts similarity index 98% rename from arch/arm/boot/dts/omap3-cm-t3530.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts index bc545ee23e71..0c6f14963e5e 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts @@ -23,7 +23,7 @@ }; &omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts similarity index 95% rename from arch/arm/boot/dts/omap3-cm-t3730.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts index e1b1a047f77a..f1a8f0fd7a83 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts @@ -33,7 +33,7 @@ }; &omap3_pmx_wkup { - dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { + dss_dpi_pins_cm_t3730: dss-dpi-cm-t3730-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ @@ -47,7 +47,7 @@ &omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -58,7 +58,7 @@ >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-cm-t3x.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi index 51baedf1603b..950a29f9b4a0 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi @@ -47,7 +47,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb2_power>; #phy-cells = <0>; @@ -74,14 +74,14 @@ &omap3_pmx_core { - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -92,13 +92,13 @@ >; }; - green_led_pins: pinmux_green_led_pins { + green_led_pins: green-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ >; }; - dss_dpi_pins_common: pinmux_dss_dpi_pins_common { + dss_dpi_pins_common: dss-dpi-common-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -126,7 +126,7 @@ >; }; - dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { + dss_dpi_pins_cm_t35x: dss-dpi-cm-t35x-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ @@ -137,13 +137,13 @@ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ @@ -152,14 +152,14 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi similarity index 97% rename from arch/arm/boot/dts/omap3-cm-t3x30.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi index 5e8943539fcc..0e942513560d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi @@ -22,14 +22,14 @@ &omap3_pmx_core { - smsc1_pins: pinmux_smsc1_pins { + smsc1_pins: smsc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ >; }; - hsusb0_pins: pinmux_hsusb0_pins { + hsusb0_pins: hsusb0-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-cpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi similarity index 99% rename from arch/arm/boot/dts/omap3-devkit8000-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi index 38aa1febc33f..3b9838f1bb6b 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi @@ -312,7 +312,7 @@ }; &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd43.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd70.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/ti/omap/omap3-echo.dts similarity index 98% rename from arch/arm/boot/dts/omap3-echo.dts rename to arch/arm/boot/dts/ti/omap/omap3-echo.dts index 06d2377d28ad..96011c976f5b 100644 --- a/arch/arm/boot/dts/omap3-echo.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-echo.dts @@ -521,16 +521,16 @@ }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &omap3_pmx_core { - tps_pins: pinmux_tps_pins { + tps_pins: tps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ @@ -540,7 +540,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -551,7 +551,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -566,7 +566,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ @@ -577,7 +577,7 @@ }; &omap3_pmx_core2 { - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts similarity index 96% rename from arch/arm/boot/dts/omap3-evm-37xx.dts rename to arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts index abd403c228c7..e0346bf842fc 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts @@ -17,7 +17,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - ehci_phy_pins: pinmux_ehci_phy_pins { + ehci_phy_pins: ehci-phy-pins { pinctrl-single,pins = < /* EHCI PHY reset GPIO etk_d7.gpio_21 */ @@ -29,7 +29,7 @@ }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < /* etk_d10.hsusb2_clk */ diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi similarity index 99% rename from arch/arm/boot/dts/omap3-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi index 17c89df6ce6b..1b6023c4cdf3 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi @@ -25,7 +25,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ vcc-supply = <&hsusb2_power>; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-evm-processor-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi index e6ba30a21166..e27837093e43 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi @@ -33,7 +33,7 @@ pinctrl-names = "default"; pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - dss_dpi_pins1: pinmux_dss_dpi_pins2 { + dss_dpi_pins1: dss-dpi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -62,7 +62,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -78,7 +78,7 @@ }; /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -93,7 +93,7 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ @@ -101,14 +101,14 @@ }; /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { + on_board_gpio_61: ehci-port-select-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) >; }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < /* mcspi1_cs3.hsusb2_data2 */ @@ -135,14 +135,14 @@ * Note that gpio_150 pulled high with internal pull to prevent wlcore * reset on return from off mode in idle. */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ >; }; - smsc911x_pins: pinmux_smsc911x_pins { + smsc911x_pins: smsc911x-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; @@ -150,7 +150,7 @@ }; &omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { + dss_dpi_pins2: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/ti/omap/omap3-evm.dts similarity index 96% rename from arch/arm/boot/dts/omap3-evm.dts rename to arch/arm/boot/dts/ti/omap/omap3-evm.dts index f95eea63b355..a2a1613c45c3 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-evm.dts @@ -17,7 +17,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - ehci_phy_pins: pinmux_ehci_phy_pins { + ehci_phy_pins: ehci-phy-pins { pinctrl-single,pins = < /* EHCI PHY reset GPIO etk_d7.gpio_21 */ @@ -29,7 +29,7 @@ }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < /* etk_d10.hsusb2_clk */ diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-gta04.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi index 4183fde46059..b6b27e93857f 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi @@ -153,7 +153,7 @@ ti,clock-source = <0x01>; }; - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; #phy-cells = <0>; @@ -200,7 +200,7 @@ }; /* devconf0 setup for mcbsp1 clock pins */ - pinmux_mcbsp1@48002274 { + pinmux@48002274 { compatible = "pinctrl-single"; reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ #address-cells = <1>; @@ -211,14 +211,14 @@ #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_devconf0_pins>; - mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { + mcbsp1_devconf0_pins: mcbsp1-devconf0-pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ }; }; /* devconf1 setup for tvout pins */ - pinmux_tv_out@480022d8 { + pinmux@480022d8 { compatible = "pinctrl-single"; reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ #address-cells = <1>; @@ -229,7 +229,7 @@ #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&tv_acbias_devconf1_pins>; - tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { + tv_acbias_devconf1_pins: tv-acbias-devconf1-pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ }; @@ -237,7 +237,7 @@ }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ @@ -251,7 +251,7 @@ &hsusb2_pins >; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -262,28 +262,28 @@ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -294,13 +294,13 @@ >; }; - backlight_pins: backlight_pins_pinmux { + backlight_pins: backlight-pinmux-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -333,50 +333,50 @@ >; }; - gps_pins: pinmux_gps_pins { + gps_pins: gps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ >; }; - hdq_pins: hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ >; }; - bmp085_pins: pinmux_bmp085_pins { + bmp085_pins: bmp085-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ >; }; - bma180_pins: pinmux_bma180_pins { + bma180_pins: bma180-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ >; }; - itg3200_pins: pinmux_itg3200_pins { + itg3200_pins: itg3200-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ >; }; - hmc5843_pins: pinmux_hmc5843_pins { + hmc5843_pins: hmc5843-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ >; }; - penirq_pins: pinmux_penirq_pins { + penirq_pins: penirq-pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ >; }; - camera_pins: pinmux_camera_pins { + camera_pins: camera-pins { pinctrl-single,pins = < /* set up parallel camera interface */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ @@ -402,7 +402,7 @@ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ @@ -415,7 +415,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ @@ -424,7 +424,7 @@ >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ @@ -433,7 +433,7 @@ >; }; - mcbsp4_pins: pinmux_mcbsp4_pins { + mcbsp4_pins: mcbsp4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ @@ -448,7 +448,7 @@ &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -459,7 +459,7 @@ >; }; - spi_gpio_pins: spi_gpio_pinmux { + spi_gpio_pins: spi-gpio-pinmux-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a3.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a4.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts similarity index 95% rename from arch/arm/boot/dts/omap3-gta04a5.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts index 425081201fd4..8bd6b4b1f30b 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts @@ -45,31 +45,31 @@ }; &omap3_pmx_core { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ >; }; - wlan_irq_pin: pinmux_wlan_irq_pin { + wlan_irq_pin: wlan-irq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ >; }; - irda_pins: pinmux_irda { + irda_pins: irda-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ >; }; - pps_pins: pinmux_pps_pins { + pps_pins: pps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ >; diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts similarity index 99% rename from arch/arm/boot/dts/omap3-gta04a5one.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts index 9db9fe67cd63..1e5703d1b02e 100644 --- a/arch/arm/boot/dts/omap3-gta04a5one.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts @@ -5,10 +5,12 @@ #include "omap3-gta04a5.dts" -&omap3_pmx_core { +/ { model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; +}; - gpmc_pins: pinmux_gpmc_pins { +&omap3_pmx_core { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* address lines */ diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi similarity index 86% rename from arch/arm/boot/dts/omap3-ha-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi index a010585d0302..3a258a692757 100644 --- a/arch/arm/boot/dts/omap3-ha-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi @@ -17,43 +17,43 @@ }; &omap3_pmx_core { - sound2_pins: pinmux_sound2_pins { + sound2_pins: sound2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ >; }; - led_blue_pins: pinmux_led_blue_pins { + led_blue_pins: led-blue-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ >; }; - led_green_pins: pinmux_led_green_pins { + led_green_pins: led-green-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ >; }; - led_red_pins: pinmux_led_red_pins { + led_red_pins: led-red-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ >; }; - poweroff_pins: pinmux_poweroff_pins { + poweroff_pins: poweroff-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ >; }; - powerdown_input_pins: pinmux_powerdown_input_pins { + powerdown_input_pins: powerdown-input-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ >; }; - fpga_boot0_pins: fpga_boot0_pins { + fpga_boot0_pins: fpga-boot0-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ @@ -62,7 +62,7 @@ >; }; - fpga_boot1_pins: fpga_boot1_pins { + fpga_boot1_pins: fpga-boot1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts similarity index 95% rename from arch/arm/boot/dts/omap3-ha-lcd.dts rename to arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts index 643283f0c3db..94f6b7931e33 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts @@ -24,19 +24,19 @@ &touchscreen_wake_pins >; - touchscreen_irq_pins: pinmux_touchscreen_irq_pins { + touchscreen_irq_pins: touchscreen-irq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ >; }; - touchscreen_wake_pins: pinmux_touchscreen_wake_pins { + touchscreen_wake_pins: touchscreen-wake-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -69,13 +69,13 @@ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/ti/omap/omap3-ha.dts similarity index 100% rename from arch/arm/boot/dts/omap3-ha.dts rename to arch/arm/boot/dts/ti/omap/omap3-ha.dts diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-igep.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep.dtsi index 219202610463..e068ecf86b8f 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi @@ -34,28 +34,28 @@ }; &omap3_pmx_core { - gpmc_pins: pinmux_gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* OneNAND seems to require PIN_INPUT on clock. */ OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ @@ -64,7 +64,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -75,7 +75,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -86,14 +86,14 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-igep0020-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi index 73d8f471b9ec..13f434625407 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi @@ -107,13 +107,13 @@ &dss_dpi_pins >; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -146,7 +146,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -155,7 +155,7 @@ >; }; - smsc9221_pins: pinmux_smsc9221_pins { + smsc9221_pins: smsc9221-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; @@ -168,7 +168,7 @@ &hsusbb1_pins >; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ @@ -185,7 +185,7 @@ >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ @@ -193,7 +193,7 @@ >; }; - mmc1_wp_pins: pinmux_mmc1_cd_pins { + mmc1_wp_pins: mmc1-cd-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts similarity index 97% rename from arch/arm/boot/dts/omap3-igep0020-rev-f.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts index eadb5b857f48..316e8e6b39cd 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts @@ -24,7 +24,7 @@ }; &omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + lbep5clwmc_pins: lbep5clwmc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts similarity index 96% rename from arch/arm/boot/dts/omap3-igep0020.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0020.dts index 3f0197ceae09..232cf9187822 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts @@ -27,7 +27,7 @@ }; &omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { + lbee1usjyc_pins: lbee1usjyc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi similarity index 93% rename from arch/arm/boot/dts/omap3-igep0030-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi index 742e3e147063..d434f75aadac 100644 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi @@ -31,7 +31,7 @@ }; }; - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ #phy-cells = <0>; @@ -42,7 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hsusb2_pins>; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -53,7 +53,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ @@ -67,7 +67,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hsusb2_core2_pins>; - hsusb2_core2_pins: pinmux_hsusb2_core2_pins { + hsusb2_core2_pins: hsusb2-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -78,7 +78,7 @@ >; }; - leds_core2_pins: pinmux_leds_core2_pins { + leds_core2_pins: leds-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts similarity index 96% rename from arch/arm/boot/dts/omap3-igep0030-rev-g.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts index bc95a8df2e6a..fddd7c86fec4 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts @@ -24,7 +24,7 @@ }; &omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + lbep5clwmc_pins: lbep5clwmc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ @@ -32,7 +32,7 @@ >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts similarity index 97% rename from arch/arm/boot/dts/omap3-igep0030.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0030.dts index d36ceecb7328..e3f99dbef2a1 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts @@ -27,7 +27,7 @@ }; &omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { + lbee1usjyc_pins: lbee1usjyc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/ti/omap/omap3-ldp.dts similarity index 98% rename from arch/arm/boot/dts/omap3-ldp.dts rename to arch/arm/boot/dts/ti/omap/omap3-ldp.dts index 85f33bbb566f..bb6fab9fa47d 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-ldp.dts @@ -223,7 +223,7 @@ }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ @@ -237,7 +237,7 @@ >; }; - musb_pins: pinmux_musb_pins { + musb_pins: musb-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ @@ -254,7 +254,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-lilly-a83x.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi index d310b5c7bac3..565a6c0e7b37 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi @@ -54,19 +54,19 @@ &omap3_pmx_wkup { pinctrl-names = "default"; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ >; }; - tsc2048_pins: pinmux_tsc2048_pins { + tsc2048_pins: tsc2048-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ >; }; - mmc1cd_pins: pinmux_mmc1cd_pins { + mmc1cd_pins: mmc1cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ >; @@ -76,7 +76,7 @@ &omap3_pmx_core { pinctrl-names = "default"; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ @@ -85,42 +85,42 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - hsusb1_pins: pinmux_hsusb1_pins { + hsusb1_pins: hsusb1-pins { pinctrl-single,pins = < /* GPIO 182 controls USB-Hub reset. But USB-Phy its @@ -132,7 +132,7 @@ >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -149,7 +149,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -160,7 +160,7 @@ >; }; - spi2_pins: pinmux_spi2_pins { + spi2_pins: spi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ @@ -173,7 +173,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; - hsusb1_2_pins: pinmux_hsusb1_2_pins { + hsusb1_2_pins: hsusb1-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ @@ -190,7 +190,7 @@ >; }; - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ >; diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts similarity index 96% rename from arch/arm/boot/dts/omap3-lilly-dbb056.dts rename to arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts index f6bbea2be54c..0891c6682a67 100644 --- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts @@ -24,25 +24,25 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; - lan9117_pins: pinmux_lan9117_pins { + lan9117_pins: lan9117-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ >; }; - gpio4_pins: pinmux_gpio4_pins { + gpio4_pins: gpio4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ >; }; - gpio5_pins: pinmux_gpio5_pins { + gpio5_pins: gpio5-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -69,7 +69,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -86,7 +86,7 @@ >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/ti/omap/omap3-n9.dts similarity index 100% rename from arch/arm/boot/dts/omap3-n9.dts rename to arch/arm/boot/dts/ti/omap/omap3-n9.dts diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts similarity index 98% rename from arch/arm/boot/dts/omap3-n900.dts rename to arch/arm/boot/dts/ti/omap/omap3-n900.dts index f9f9eca0c56c..d33485341251 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts @@ -209,7 +209,7 @@ &omap3_pmx_core { pinctrl-names = "default"; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ @@ -218,14 +218,14 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ >; }; - ethernet_pins: pinmux_ethernet_pins { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ @@ -233,7 +233,7 @@ >; }; - gpmc_pins: pinmux_gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* address lines */ @@ -260,34 +260,34 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - debug_leds: pinmux_debug_led_pins { + debug_leds: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ >; }; - mcspi4_pins: pinmux_mcspi4_pins { + mcspi4_pins: mcspi4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ @@ -296,7 +296,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ @@ -307,7 +307,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ @@ -322,13 +322,13 @@ >; }; - acx565akm_pins: pinmux_acx565akm_pins { + acx565akm_pins: acx565akm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ >; }; - dss_sdi_pins: pinmux_dss_sdi_pins { + dss_sdi_pins: dss-sdi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ @@ -340,14 +340,14 @@ >; }; - wl1251_pins: pinmux_wl1251 { + wl1251_pins: wl1251-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ >; }; - ssi_pins: pinmux_ssi { + ssi_pins: ssi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ @@ -360,7 +360,7 @@ >; }; - modem_pins: pinmux_modem { + modem_pins: modem-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ @@ -371,7 +371,7 @@ >; }; - camera_pins: pinmux_camera { + camera_pins: camera-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi similarity index 97% rename from arch/arm/boot/dts/omap3-n950-n9.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi index f68da828b050..aa4fcdbedd8f 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi @@ -57,20 +57,20 @@ }; &omap3_pmx_core { - accelerator_pins: pinmux_accelerator_pins { + accelerator_pins: accelerator-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ >; }; - debug_leds: pinmux_debug_led_pins { + debug_leds: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ @@ -81,14 +81,14 @@ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ >; }; - ssi_pins: pinmux_ssi_pins { + ssi_pins: ssi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ @@ -101,7 +101,7 @@ >; }; - ssi_pins_idle: pinmux_ssi_pins_idle { + ssi_pins_idle: ssi-idle-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ @@ -114,7 +114,7 @@ >; }; - modem_pins1: pinmux_modem_core1_pins { + modem_pins1: modem-core1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ @@ -122,7 +122,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ @@ -133,7 +133,7 @@ }; &omap3_pmx_core2 { - modem_pins2: pinmux_modem_core2_pins { + modem_pins2: modem-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ >; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/ti/omap/omap3-n950.dts similarity index 97% rename from arch/arm/boot/dts/omap3-n950.dts rename to arch/arm/boot/dts/ti/omap/omap3-n950.dts index cbaf79c4e842..b99f97880204 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-n950.dts @@ -30,7 +30,7 @@ }; &omap3_pmx_core { - keypad_slide_pins: pinmux_debug_led_pins { + keypad_slide_pins: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ >; @@ -38,7 +38,7 @@ }; &omap3_pmx_core { - spi4_pins: pinmux_spi4_pins { + spi4_pins: spi4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ @@ -49,7 +49,7 @@ }; &omap3_pmx_core { - dsi_pins: pinmux_dsi_pins { + dsi_pins: dsi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ @@ -60,7 +60,7 @@ >; }; - display_pins: pinmux_display_pins { + display_pins: display-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-overo-alto35-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi index a6dbbba799b2..7f1671bf3dfa 100644 --- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi @@ -51,7 +51,7 @@ }; &omap3_pmx_core { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ @@ -62,7 +62,7 @@ }; &omap3_pmx_wkup { - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-alto35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-overo-base.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi index adc714c39825..cc57626ea607 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi @@ -44,7 +44,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ vcc-supply = <&hsusb2_power>; @@ -80,7 +80,7 @@ &hsusb2_pins >; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ @@ -89,14 +89,14 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -107,7 +107,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -119,14 +119,14 @@ }; /* WiFi/BT combo */ - w3cbw003c_pins: pinmux_w3cbw003c_pins { + w3cbw003c_pins: w3cbw003c-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-chestnut43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts index d147d704b89f..bb53c76fff6c 100644 --- a/arch/arm/boot/dts/omap3-overo-chestnut43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi similarity index 98% rename from arch/arm/boot/dts/omap3-overo-common-dvi.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi index 339a51fa4119..b1a800f2e940 100644 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi index c3570acc35fa..0da561a23f36 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -41,19 +41,19 @@ >; }; - lb035_pins: pinmux_lb035_pins { + lb035_pins: lb035-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -63,7 +63,7 @@ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi index d95a0e130058..981f02f088f8 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -41,19 +41,19 @@ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -62,7 +62,7 @@ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi index 8a4a02472c9a..00369f699e20 100644 --- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi @@ -24,14 +24,14 @@ }; &omap3_pmx_core { - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-gallop43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts index 24b40bdf7ea1..d882a58028c1 100644 --- a/arch/arm/boot/dts/omap3-overo-gallop43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo35-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-palo35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts index 55e08d56b18b..39c8e9ce5776 100644 --- a/arch/arm/boot/dts/omap3-overo-palo35.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-palo43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts index 092c8325a133..2c0f755ec8cc 100644 --- a/arch/arm/boot/dts/omap3-overo-palo43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-alto35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts index 3af8d10d7224..25e82efe4f3b 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-storm-gallop43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts index 813e3c9fe3b6..0c93ea3f9774 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-storm-palo35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts index 8405bd9262de..9468ef9f9742 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts similarity index 92% rename from arch/arm/boot/dts/omap3-overo-storm-palo43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts index b9558d736e79..9feead584479 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts @@ -18,14 +18,14 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts similarity index 95% rename from arch/arm/boot/dts/omap3-overo-storm-summit.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts index fcfc449f2abe..92f56b9d009d 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts @@ -18,7 +18,7 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-tobi.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi similarity index 91% rename from arch/arm/boot/dts/omap3-overo-storm.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi index 2af15d5f61f9..da583b47ed8d 100644 --- a/arch/arm/boot/dts/omap3-overo-storm.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi @@ -12,7 +12,7 @@ &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -23,7 +23,7 @@ >; }; - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { + w3cbw003c_2_pins: w3cbw003c-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-summit-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts similarity index 94% rename from arch/arm/boot/dts/omap3-overo-summit.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts index a6c9799fe491..da5ca80430ae 100644 --- a/arch/arm/boot/dts/omap3-overo-summit.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts @@ -18,7 +18,7 @@ }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobi-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobi.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobiduo.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi similarity index 91% rename from arch/arm/boot/dts/omap3-overo.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo.dtsi index cc9263e99254..7dc044e87226 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi @@ -12,7 +12,7 @@ &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -23,7 +23,7 @@ >; }; - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { + w3cbw003c_2_pins: w3cbw003c-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts similarity index 95% rename from arch/arm/boot/dts/omap3-pandora-1ghz.dts rename to arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts index c0252f8a798a..8d8c9085e6ff 100644 --- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts @@ -27,7 +27,7 @@ &control_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -38,7 +38,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -49,7 +49,7 @@ >; }; - control_pins: pinmux_control_pins { + control_pins: control-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts similarity index 95% rename from arch/arm/boot/dts/omap3-pandora-600mhz.dts rename to arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts index 6bd9041942f2..2d5eac3ffc6c 100644 --- a/arch/arm/boot/dts/omap3-pandora-600mhz.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts @@ -27,7 +27,7 @@ &control_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -38,7 +38,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -49,7 +49,7 @@ >; }; - control_pins: pinmux_control_pins { + control_pins: control-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi similarity index 98% rename from arch/arm/boot/dts/omap3-pandora-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi index 4c3b6bab179c..06c5b2358999 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi @@ -205,7 +205,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ vcc-supply = <&vaux2>; @@ -251,7 +251,7 @@ &omap3_pmx_core { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -262,7 +262,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -277,7 +277,7 @@ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -311,14 +311,14 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - led_pins: pinmux_leds_pins { + led_pins: leds-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ @@ -327,7 +327,7 @@ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ @@ -349,7 +349,7 @@ >; }; - penirq_pins: pinmux_penirq_pins { + penirq_pins: penirq-pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi similarity index 95% rename from arch/arm/boot/dts/omap3-sb-t35.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi index 5ec0893415e0..6730c749d5ea 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi @@ -56,27 +56,27 @@ }; &omap3_pmx_core { - smsc2_pins: pinmux_smsc2_pins { + smsc2_pins: smsc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - sb_t35_audio_amp: pinmux_sb_t35_audio_amp { + sb_t35_audio_amp: sb-t35-audio-amp-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts similarity index 94% rename from arch/arm/boot/dts/omap3-sbc-t3517.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts index a69d32860421..07bec48dc441 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts @@ -36,14 +36,14 @@ &usb_hub_pins >; - mmc1_aux_pins: pinmux_mmc1_aux_pins { + mmc1_aux_pins: mmc1-aux-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts similarity index 94% rename from arch/arm/boot/dts/omap3-sbc-t3530.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts index 24bf3fd86641..1beefc319422 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts @@ -20,7 +20,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts similarity index 94% rename from arch/arm/boot/dts/omap3-sbc-t3730.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts index 4c36bde62491..aefc1187ebc9 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts @@ -20,7 +20,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/ti/omap/omap3-sniper.dts similarity index 94% rename from arch/arm/boot/dts/omap3-sniper.dts rename to arch/arm/boot/dts/ti/omap/omap3-sniper.dts index 0591af494184..79e004057482 100644 --- a/arch/arm/boot/dts/omap3-sniper.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-sniper.dts @@ -26,48 +26,48 @@ &omap3_pmx_core { pinctrl-names = "default"; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ >; }; - dp3t_sel_pins: pinmux_dp3t_sel_pins { + dp3t_sel_pins: dp3t-sel-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - lp8720_en_pin: pinmux_lp8720_en_pin { + lp8720_en_pin: lp8720-en-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ @@ -78,7 +78,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ @@ -93,7 +93,7 @@ >; }; - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { + usb_otg_hs_pins: usb-otg-hs-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ @@ -114,7 +114,7 @@ &omap3_pmx_wkup { pinctrl-names = "default"; - mmc1_cd_pin: pinmux_mmc1_cd_pin { + mmc1_cd_pin: mmc1-cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ >; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi similarity index 96% rename from arch/arm/boot/dts/omap3-tao3530.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi index 7f440d11f7e7..92a5846048bd 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi @@ -43,7 +43,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ vcc-supply = <&hsusb2_power>; @@ -70,7 +70,7 @@ }; &omap3_pmx_core { - hsusbb2_pins: pinmux_hsusbb2_pins { + hsusbb2_pins: hsusbb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -87,7 +87,7 @@ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -102,7 +102,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -114,27 +114,27 @@ }; /* wlan GPIO output for WLAN_EN */ - wlan_gpio: pinmux_wlan_gpio { + wlan_gpio: wlan-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -143,7 +143,7 @@ >; }; - mcspi3_pins: pinmux_mcspi3_pins { + mcspi3_pins: mcspi3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ @@ -152,7 +152,7 @@ >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/ti/omap/omap3-thunder.dts similarity index 97% rename from arch/arm/boot/dts/omap3-thunder.dts rename to arch/arm/boot/dts/ti/omap/omap3-thunder.dts index d82cab8e213a..c87956c59b08 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-thunder.dts @@ -12,7 +12,7 @@ }; &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -45,13 +45,13 @@ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts similarity index 95% rename from arch/arm/boot/dts/omap3-zoom3.dts rename to arch/arm/boot/dts/ti/omap/omap3-zoom3.dts index ab52e8d68f76..9f1e125fd77b 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts @@ -49,7 +49,7 @@ &omap3_pmx_core { /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -60,7 +60,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -75,14 +75,14 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ @@ -91,7 +91,7 @@ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -100,7 +100,7 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -110,7 +110,7 @@ }; /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ >; @@ -118,7 +118,7 @@ }; &omap3_pmx_core2 { - mmc3_2_pins: pinmux_mmc3_2_pins { + mmc3_2_pins: mmc3-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ @@ -130,7 +130,7 @@ }; &omap3_pmx_wkup { - wlan_host_wkup: pinmux_wlan_host_wkup_pins { + wlan_host_wkup: wlan-host-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ >; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3.dtsi rename to arch/arm/boot/dts/ti/omap/omap3.dtsi diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap3430-sdp.dts similarity index 100% rename from arch/arm/boot/dts/omap3430-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap3430-sdp.dts diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3430es1-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi similarity index 100% rename from arch/arm/boot/dts/omap34xx.dtsi rename to arch/arm/boot/dts/ti/omap/omap34xx.dtsi diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx.dtsi diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3xxx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-cpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts similarity index 100% rename from arch/arm/boot/dts/omap4-droid-bionic-xt875.dts rename to arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts similarity index 100% rename from arch/arm/boot/dts/omap4-droid4-xt894.dts rename to arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts similarity index 95% rename from arch/arm/boot/dts/omap4-duovero-parlor.dts rename to arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts index b294c22177cb..6d1beb453234 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts @@ -62,33 +62,33 @@ &smsc_pins >; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - smsc_pins: pinmux_smsc_pins { + smsc_pins: smsc-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ @@ -96,7 +96,7 @@ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi similarity index 95% rename from arch/arm/boot/dts/omap4-duovero.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi index 805dfd40030d..b8af455b411a 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi @@ -73,14 +73,14 @@ &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -89,7 +89,7 @@ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -106,34 +106,34 @@ >; }; - hsusb1phy_pins: pinmux_hsusb1phy_pins { + hsusb1phy_pins: hsusb1phy-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ >; }; - w2cbw0015_pins: pinmux_w2cbw0015_pins { + w2cbw0015_pins: w2cbw0015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ @@ -144,7 +144,7 @@ >; }; - mmc5_pins: pinmux_mmc5_pins { + mmc5_pins: mmc5-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts new file mode 100644 index 000000000000..e119e2cccc4e --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Andreas Kemnade + */ +/dts-v1/; + +#include +#include "omap4460.dtsi" + +/ { + model = "Epson Moverio BT-200"; + compatible = "epson,embt2ws", "ti,omap4460", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1024M */ + }; + + backlight-left { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 1 7812500>; + power-supply = <&unknown_supply>; + }; + + backlight-right { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 0 7812500>; + power-supply = <&unknown_supply>; + }; + + chosen { + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-lock { + label = "Lock"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; /* SW_TOUCHPAD_LOCK */ + linux,input-type = ; + }; + }; + + unknown_supply: unknown-supply { + compatible = "regulator-fixed"; + regulator-name = "unknown"; + }; + + /* regulator for wl12xx on sdio2 */ + wl12xx_vmmc: wl12xx-vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: pmic@48 { + compatible = "ti,twl6032"; + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + ldo2: regulator-ldo2 { + compatible = "ti,twl6032-ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo4: regulator-ldo4 { + compatible = "ti,twl6032-ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + }; + + ldo3: regulator-ldo3 { + compatible = "ti,twl6032-ldo3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo5: regulator-ldo5 { + compatible = "ti,twl6032-ldo5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + ti,retain-on-reset; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,twl6032-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + }; + + ldo7: regulator-ldo7 { + compatible = "ti,twl6032-ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2900000>; + }; + + ldoln: regulator-ldoln { + compatible = "ti,twl6032-ldoln"; + regulator-always-on; + }; + + ldo6: regulator-ldo6 { + compatible = "ti,twl6032-ldo6"; + regulator-always-on; + }; + + ldousb: regulator-ldousb { + compatible = "ti,twl6032-ldousb"; + regulator-always-on; + }; + + vio: regulator-vio { + compatible = "ti,twl6032-vio"; + regulator-always-on; + }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; + + twl_pwm: pwm { + /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + /* provides one PWM (id 0 for Charging indicator LED) */ + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; + + gpadc { + compatible = "ti,twl6032-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; + + }; +}; + +#include "twl6030_omap4.dtsi" + +&twl_usb_comparator { + usb-supply = <&ldousb>; +}; + + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <200000>; + + /* at head/glasses */ + mpu9150h: imu@68 { + compatible = "invensense,mpu9150"; + reg = <0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu9150h_pins>; + interrupt-parent = <&gpio2>; + interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* TODO: BD2606MVV at 0x66 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <360000>; + + /* TODO: KXTI9 at 0xf */ + + tlv320aic3x: codec@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&tlv320aic3x_pins>; + #sound-dai-cells = <0>; + + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + /* TODO: mpu9150 at control unit, seems to require quirks */ +}; + +&keypad { + pinctrl-names = "default"; + pinctrl-0 = <&keypad_pins>; + keypad,num-rows = <2>; + keypad,num-columns = <3>; + linux,keymap = ; + linux,input-no-autorepeat; +}; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + + +&mmc1 { + /* sdcard */ + vmmc-supply = <&ldo5>; + broken-cd; + bus-width = <4>; +}; + +&mmc2 { + /* emmc */ + vmmc-supply = <&ldo2>; + bus-width = <8>; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_pins>; + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x12e>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupts-extended = <&gpio1 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq"; + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&omap4_pmx_core { + bt_pins: pinmux-bt-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE3) /* gpio25 */ + >; + }; + + gpio_keys_pins: pinmux-gpio-key-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x56, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio35 */ + >; + }; + + i2c1_pins: pinmux-i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux-i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: pinmux-i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ + >; + }; + + keypad_pins: pinmux-keypad-pins { + pinctrl-single,pins = < + /* kpd_row0 */ + OMAP4_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row1 */ + OMAP4_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row2 */ + OMAP4_IOPAD(0x0054, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_col0 */ + OMAP4_IOPAD(0x0058, PIN_OUTPUT | MUX_MODE1) + /* kpd_col1 */ + OMAP4_IOPAD(0x005a, PIN_OUTPUT | MUX_MODE1) + /* kpd_col2 */ + OMAP4_IOPAD(0x005c, PIN_OUTPUT | MUX_MODE1) + >; + }; + + mcbsp2_pins: pinmux-mcbsp2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mpu9150h_pins: pinmux-mpu9150h-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x76, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + tlv320aic3x_pins: pinmux-tlv320aic3x-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x7e, PIN_OUTPUT | MUX_MODE3) + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux-uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + usb_otg_hs_pins: pinmux-usb-otg-hs-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ + >; + }; + + wl12xx_pins: pinmux-wl12xx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c6, PIN_INPUT | MUX_MODE3) /* gpio_23 / IRQ */ + OMAP4_IOPAD(0x16c, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat2 */ + OMAP4_IOPAD(0x16e, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat1 */ + OMAP4_IOPAD(0x170, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat0 */ + OMAP4_IOPAD(0x172, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat3 */ + OMAP4_IOPAD(0x174, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_cmd */ + OMAP4_IOPAD(0x176, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_clk */ + >; + }; + + wl12xx_gpio: pinmux-wl12xx-gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE3) /* gpio_24 / WLAN_EN */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; + + /* + * BT + GPS in WL1283 in WG7500 requiring CLK32KAUDIO of pmic + * which does not have a driver + */ +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/ti/omap/omap4-kc1.dts similarity index 94% rename from arch/arm/boot/dts/omap4-kc1.dts rename to arch/arm/boot/dts/ti/omap/omap4-kc1.dts index e59d17b25a1d..c6b79ba8bbc9 100644 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-kc1.dts @@ -35,42 +35,42 @@ &omap4_pmx_core { pinctrl-names = "default"; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ @@ -85,7 +85,7 @@ >; }; - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { + usb_otg_hs_pins: usb-otg-hs-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-l4-abe.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-l4.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-l4.dtsi diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi similarity index 97% rename from arch/arm/boot/dts/omap4-mcpdm.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi index 915a9b31a33b..03ade47431fb 100644 --- a/arch/arm/boot/dts/omap4-mcpdm.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi @@ -7,7 +7,7 @@ */ &omap4_pmx_core { - mcpdm_pins: pinmux_mcpdm_pins { + mcpdm_pins: mcpdm-pins { pinctrl-single,pins = < /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts similarity index 100% rename from arch/arm/boot/dts/omap4-panda-a4.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi similarity index 96% rename from arch/arm/boot/dts/omap4-panda-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi index 0269424350aa..f528511c2537 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi @@ -237,14 +237,14 @@ &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -253,7 +253,7 @@ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ @@ -288,13 +288,13 @@ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -302,7 +302,7 @@ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ @@ -310,7 +310,7 @@ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -327,28 +327,28 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ @@ -359,7 +359,7 @@ * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP * REVISIT: Are the pull-ups needed for GPIO 48 and 49? */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ @@ -369,7 +369,7 @@ }; /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { + wl12xx_pins: wl12xx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ @@ -382,7 +382,7 @@ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ >; @@ -390,7 +390,7 @@ }; &omap4_pmx_wkup { - led_wkgpio_pins: pinmux_leds_wkpins { + led_wkgpio_pins: leds-wkpins-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts similarity index 95% rename from arch/arm/boot/dts/omap4-panda-es.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda-es.dts index 7631029e4d7a..fe7b156d10ed 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts @@ -38,26 +38,26 @@ }; &omap4_pmx_core { - led_gpio_pins: gpio_led_pmx { + led_gpio_pins: gpio-led-pmx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/ti/omap/omap4-panda.dts similarity index 100% rename from arch/arm/boot/dts/omap4-panda.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda.dts diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts similarity index 100% rename from arch/arm/boot/dts/omap4-sdp-es23plus.dts rename to arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts similarity index 96% rename from arch/arm/boot/dts/omap4-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap4-sdp.dts index 9e976140f34a..b2cb93edbc3a 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts @@ -214,7 +214,7 @@ &tpd12s015_pins >; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -223,7 +223,7 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -232,21 +232,21 @@ >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ >; }; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - dmic_pins: pinmux_dmic_pins { + dmic_pins: dmic-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ @@ -255,7 +255,7 @@ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -264,7 +264,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ @@ -273,7 +273,7 @@ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ @@ -282,7 +282,7 @@ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -290,7 +290,7 @@ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ @@ -298,28 +298,28 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ @@ -327,14 +327,14 @@ }; /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ >; }; /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { + wl12xx_pins: wl12xx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ @@ -347,13 +347,13 @@ }; /* gpio_48 for ENET_ENABLE */ - enet_enable_gpio: pinmux_enet_enable_gpio { + enet_enable_gpio: enet-enable-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ >; }; - ks8851_pins: pinmux_ks8851_pins { + ks8851_pins: ks8851-pins { pinctrl-single,pins = < /* ENET_INT */ OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts similarity index 100% rename from arch/arm/boot/dts/omap4-var-dvk-om44.dts rename to arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi similarity index 93% rename from arch/arm/boot/dts/omap4-var-om44customboard.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi index 458cb53dd3d1..cadc7e02592b 100644 --- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi @@ -60,7 +60,7 @@ }; &omap4_pmx_core { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ @@ -69,7 +69,7 @@ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ @@ -78,13 +78,13 @@ >; }; - mcasp_pins: pinmux_mcsasp_pins { + mcasp_pins: mcsasp-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ @@ -117,7 +117,7 @@ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -125,14 +125,14 @@ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc5_pins: pinmux_mmc5_pins { + mmc5_pins: mmc5-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ @@ -144,32 +144,32 @@ >; }; - gpio_led_pins: pinmux_gpio_led_pins { + gpio_led_pins: gpio-led-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ >; }; - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ >; }; - ks8851_irq_pins: pinmux_ks8851_irq_pins { + ks8851_irq_pins: ks8851-irq-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ >; }; - hdmi_hpd_pins: pinmux_hdmi_hpd_pins { + hdmi_hpd_pins: hdmi-hpd-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ >; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi similarity index 95% rename from arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi index d0032213101e..de779d2d7c3e 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi @@ -19,7 +19,7 @@ }; &omap4_pmx_core { - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -28,7 +28,7 @@ >; }; - wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { + wl12xx_ctrl_pins: wl12xx-ctrl-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ @@ -36,7 +36,7 @@ >; }; - mmc4_pins: pinmux_mmc4_pins { + mmc4_pins: mmc4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi similarity index 94% rename from arch/arm/boot/dts/omap4-var-som-om44.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi index 334cbbaa5b8b..37d56b3010cf 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi @@ -65,21 +65,21 @@ &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -88,7 +88,7 @@ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -105,27 +105,27 @@ >; }; - hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { + hsusbb1_phy_rst_pins: hsusbb1-phy-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -144,19 +144,19 @@ &lan7500_rst_pins >; - hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { + hsusbb1_phy_clk_pins: hsusbb1-phy-clk-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ >; }; - hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { + hsusbb1_hub_rst_pins: hsusbb1-hub-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ >; }; - lan7500_rst_pins: pinmux_lan7500_rst_pins { + lan7500_rst_pins: lan7500-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ >; diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts similarity index 100% rename from arch/arm/boot/dts/omap4-var-stk-om44.dts rename to arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4.dtsi rename to arch/arm/boot/dts/ti/omap/omap4.dtsi diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap443x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/ti/omap/omap443x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap443x.dtsi rename to arch/arm/boot/dts/ti/omap/omap443x.dtsi diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/ti/omap/omap4460.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4460.dtsi rename to arch/arm/boot/dts/ti/omap/omap4460.dtsi diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap446x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap44xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi similarity index 95% rename from arch/arm/boot/dts/omap5-board-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi index 373984c130e0..6f46f1ecf1e5 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi @@ -56,7 +56,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ clocks = <&auxclk1_ck>; @@ -156,13 +156,13 @@ &led_gpio_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ >; }; - mcpdm_pins: pinmux_mcpdm_pins { + mcpdm_pins: mcpdm-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ @@ -172,7 +172,7 @@ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ @@ -181,7 +181,7 @@ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ @@ -190,14 +190,14 @@ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - mcspi2_pins: pinmux_mcspi2_pins { + mcspi2_pins: mcspi2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ @@ -206,7 +206,7 @@ >; }; - mcspi3_pins: pinmux_mcspi3_pins { + mcspi3_pins: mcspi3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ @@ -215,7 +215,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ @@ -226,20 +226,20 @@ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ >; }; /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { + palmas_msecure_pins: palmas-msecure-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ >; }; - usbhost_pins: pinmux_usbhost_pins { + usbhost_pins: usbhost-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ @@ -252,13 +252,13 @@ >; }; - led_gpio_pins: pinmux_led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ @@ -267,14 +267,14 @@ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ >; }; - uart5_pins: pinmux_uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ @@ -283,7 +283,7 @@ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ @@ -291,7 +291,7 @@ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ >; @@ -304,20 +304,20 @@ &usbhost_wkup_pins >; - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { + palmas_sys_nirq_pins: palmas-sys-nirq-pins { pinctrl-single,pins = < /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) >; }; - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { + usbhost_wkup_pins: usbhost-wkup-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ >; }; - wlcore_irq_pin: pinmux_wlcore_irq_pin { + wlcore_irq_pin: wlcore-irq-pin-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ >; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts similarity index 96% rename from arch/arm/boot/dts/omap5-cm-t54.dts rename to arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts index af288d63a26a..6767382996ab 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts @@ -60,7 +60,7 @@ }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ #phy-cells = <0>; @@ -176,13 +176,13 @@ &omap5_pmx_wkup { - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ >; }; - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { + palmas_sys_nirq_pins: palmas-sys-nirq-pins { pinctrl-single,pins = < /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) @@ -197,27 +197,27 @@ &usbhost_pins >; - led_gpio_pins: pinmux_led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ @@ -228,7 +228,7 @@ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ @@ -243,7 +243,7 @@ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ @@ -254,14 +254,14 @@ >; }; - wlan_gpios_pins: pinmux_wlan_gpios_pins { + wlan_gpios_pins: wlan-gpios-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ >; }; - usbhost_pins: pinmux_usbhost_pins { + usbhost_pins: usbhost-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ @@ -274,7 +274,7 @@ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ @@ -282,19 +282,19 @@ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ >; }; - hdmi_conn_pins: pinmux_hdmi_conn_pins { + hdmi_conn_pins: hdmi-conn-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ @@ -327,7 +327,7 @@ >; }; - mcspi2_pins: pinmux_mcspi1_pins { + mcspi2_pins: mcspi1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-core-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-gpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts similarity index 97% rename from arch/arm/boot/dts/omap5-igep0050.dts rename to arch/arm/boot/dts/ti/omap/omap5-igep0050.dts index 3851120857d7..d4ca2e3a14dd 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts @@ -85,14 +85,14 @@ }; &omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ >; }; - power_button_pin: pinctrl_power_button_pin { + power_button_pin: power-button-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ >; diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-l4-abe.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-l4.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-l4.dtsi diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts similarity index 93% rename from arch/arm/boot/dts/omap5-sbc-t54.dts rename to arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts index 657df46251c2..02716fb796bd 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts @@ -11,14 +11,14 @@ }; &omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc1_aux_pins: pinmux_mmc1_aux_pins { + mmc1_aux_pins: mmc1-aux-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/ti/omap/omap5-uevm.dts similarity index 97% rename from arch/arm/boot/dts/omap5-uevm.dts rename to arch/arm/boot/dts/ti/omap/omap5-uevm.dts index 453da9f18a99..933de05d3ca1 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/ti/omap/omap5-uevm.dts @@ -162,20 +162,20 @@ }; &omap5_pmx_core { - evm_keys_pins: pinmux_evm_keys_gpio_pins { + evm_keys_pins: evm-keys-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ >; }; - i2c5_pins: pinmux_i2c5_pins { + i2c5_pins: i2c5-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ >; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5.dtsi rename to arch/arm/boot/dts/ti/omap/omap5.dtsi diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap54xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/ti/omap/twl4030.dtsi similarity index 100% rename from arch/arm/boot/dts/twl4030.dtsi rename to arch/arm/boot/dts/ti/omap/twl4030.dtsi diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi similarity index 93% rename from arch/arm/boot/dts/twl4030_omap3.dtsi rename to arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi index 683419d5c0e5..89433f251df0 100644 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ b/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi @@ -14,7 +14,7 @@ * to the SYS_NIRQ line on OMAP. Therefore, configure the * defaults for the SYS_NIRQ pin here. */ - twl4030_pins: pinmux_twl4030_pins { + twl4030_pins: twl4030-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ >; @@ -28,7 +28,7 @@ * sys_nvmode2 signaling. */ &omap3_pmx_wkup { - twl4030_vpins: pinmux_twl4030_vpins { + twl4030_vpins: twl4030-vpins-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/ti/omap/twl6030.dtsi similarity index 100% rename from arch/arm/boot/dts/twl6030.dtsi rename to arch/arm/boot/dts/ti/omap/twl6030.dtsi diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi similarity index 90% rename from arch/arm/boot/dts/twl6030_omap4.dtsi rename to arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi index 5730e46b0067..64e38c7c8be7 100644 --- a/arch/arm/boot/dts/twl6030_omap4.dtsi +++ b/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi @@ -19,7 +19,7 @@ }; &omap4_pmx_wkup { - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + twl6030_wkup_pins: twl6030-wkup-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ >; @@ -27,7 +27,7 @@ }; &omap4_pmx_core { - twl6030_pins: pinmux_twl6030_pins { + twl6030_pins: twl6030-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ >; diff --git a/arch/arm/boot/dts/unisoc/Makefile b/arch/arm/boot/dts/unisoc/Makefile new file mode 100644 index 000000000000..dba5cd874ee7 --- /dev/null +++ b/arch/arm/boot/dts/unisoc/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RDA) += \ + rda8810pl-orangepi-2g-iot.dtb \ + rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts similarity index 100% rename from arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts rename to arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts similarity index 100% rename from arch/arm/boot/dts/rda8810pl-orangepi-i96.dts rename to arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi similarity index 100% rename from arch/arm/boot/dts/rda8810pl.dtsi rename to arch/arm/boot/dts/unisoc/rda8810pl.dtsi diff --git a/arch/arm/boot/dts/vt8500/Makefile b/arch/arm/boot/dts/vt8500/Makefile new file mode 100644 index 000000000000..255f4403af91 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VT8500) += \ + vt8500-bv07.dtb \ + wm8505-ref.dtb \ + wm8650-mid.dtb \ + wm8750-apc8750.dtb \ + wm8850-w70v2.dtb diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts similarity index 100% rename from arch/arm/boot/dts/vt8500-bv07.dts rename to arch/arm/boot/dts/vt8500/vt8500-bv07.dts diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi similarity index 100% rename from arch/arm/boot/dts/vt8500.dtsi rename to arch/arm/boot/dts/vt8500/vt8500.dtsi diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts similarity index 100% rename from arch/arm/boot/dts/wm8505-ref.dts rename to arch/arm/boot/dts/vt8500/wm8505-ref.dts diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8505.dtsi rename to arch/arm/boot/dts/vt8500/wm8505.dtsi diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts similarity index 100% rename from arch/arm/boot/dts/wm8650-mid.dts rename to arch/arm/boot/dts/vt8500/wm8650-mid.dts diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8650.dtsi rename to arch/arm/boot/dts/vt8500/wm8650.dtsi diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts similarity index 100% rename from arch/arm/boot/dts/wm8750-apc8750.dts rename to arch/arm/boot/dts/vt8500/wm8750-apc8750.dts diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8750.dtsi rename to arch/arm/boot/dts/vt8500/wm8750.dtsi diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts similarity index 100% rename from arch/arm/boot/dts/wm8850-w70v2.dts rename to arch/arm/boot/dts/vt8500/wm8850-w70v2.dts diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8850.dtsi rename to arch/arm/boot/dts/vt8500/wm8850.dtsi diff --git a/arch/arm/boot/dts/xen/Makefile b/arch/arm/boot/dts/xen/Makefile new file mode 100644 index 000000000000..26c50f138952 --- /dev/null +++ b/arch/arm/boot/dts/xen/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VIRT) += \ + xenvm-4.2.dtb diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xen/xenvm-4.2.dts similarity index 100% rename from arch/arm/boot/dts/xenvm-4.2.dts rename to arch/arm/boot/dts/xen/xenvm-4.2.dts diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile new file mode 100644 index 000000000000..9233e539b192 --- /dev/null +++ b/arch/arm/boot/dts/xilinx/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ + zynq-microzed.dtb \ + zynq-parallella.dtb \ + zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ + zynq-zed.dtb \ + zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ + zynq-zybo.dtb \ + zynq-zybo-z7.dtb diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi similarity index 99% rename from arch/arm/boot/dts/zynq-7000.dtsi rename to arch/arm/boot/dts/xilinx/zynq-7000.dtsi index cd9931f6bcbd..a7db3f3009f2 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -149,6 +149,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -160,6 +161,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts similarity index 100% rename from arch/arm/boot/dts/zynq-cc108.dts rename to arch/arm/boot/dts/xilinx/zynq-cc108.dts diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts similarity index 100% rename from arch/arm/boot/dts/zynq-ebaz4205.dts rename to arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/xilinx/zynq-microzed.dts similarity index 100% rename from arch/arm/boot/dts/zynq-microzed.dts rename to arch/arm/boot/dts/xilinx/zynq-microzed.dts diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/xilinx/zynq-parallella.dts similarity index 100% rename from arch/arm/boot/dts/zynq-parallella.dts rename to arch/arm/boot/dts/xilinx/zynq-parallella.dts diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts similarity index 93% rename from arch/arm/boot/dts/zynq-zc702.dts rename to arch/arm/boot/dts/xilinx/zynq-zc702.dts index d23201ba8cd7..6efdbca9d3ef 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" +#include / { model = "Xilinx ZC702 board"; @@ -106,8 +107,11 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; @@ -298,6 +302,19 @@ }; }; + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_50_grp", "gpio0_51_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_50_grp", "gpio0_51_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + }; + pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc706.dts rename to arch/arm/boot/dts/xilinx/zynq-zc706.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm010.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm011.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm012.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm013.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/xilinx/zynq-zed.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zed.dts rename to arch/arm/boot/dts/xilinx/zynq-zed.dts diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi similarity index 100% rename from arch/arm/boot/dts/zynq-zturn-common.dtsi rename to arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zturn-v5.dts rename to arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/xilinx/zynq-zturn.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zturn.dts rename to arch/arm/boot/dts/xilinx/zynq-zturn.dts diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zybo-z7.dts rename to arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/xilinx/zynq-zybo.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zybo.dts rename to arch/arm/boot/dts/xilinx/zynq-zybo.dts diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index aad6ba236f0f..77c83ba81715 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -695,7 +695,7 @@ static u32 sa1111_dma_mask[] = { /* * Configure the SA1111 shared memory controller. */ -void +static void sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, unsigned int cas_latency) { diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index 3f633eaf9770..a25834e4c901 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -15,7 +15,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y # CONFIG_SWAP is not set -CONFIG_SLAB=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_NET=y CONFIG_PACKET=m diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 82bcf4dc7f54..8cc602853cc5 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -27,7 +27,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_SWAP is not set -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index c8d559f38f48..46859e6fee5b 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -17,7 +17,6 @@ CONFIG_VFP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 3154125321c5..44e89a980d29 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -24,7 +24,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index c9a602aee715..ec45e6225225 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -26,7 +26,6 @@ CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_SWAP is not set -CONFIG_SLAB=y # CONFIG_COMPAT_BRK is not set CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 4de293da4789..05706696a5fb 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -1,4 +1,3 @@ -CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y @@ -80,8 +79,6 @@ CONFIG_PCI_IMX6_HOST=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_MTD=y diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index fabb66a53350..d7df0486850f 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -23,7 +23,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig index 7984640e994e..3d1d6f3b592a 100644 --- a/arch/arm/configs/mmp2_defconfig +++ b/arch/arm/configs/mmp2_defconfig @@ -12,7 +12,6 @@ CONFIG_VFP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 871fffe92187..f0800f806b5f 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -596,7 +596,7 @@ CONFIG_MFD_CPCAP=y CONFIG_MFD_PM8XXX=y CONFIG_MFD_QCOM_RPM=y CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y +CONFIG_MFD_RK8XX_I2C=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_STMPE=y diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index 68a18264f31b..2d2a4dc8f379 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -23,7 +23,6 @@ CONFIG_VFP=y CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 4171dafddc0a..ea28ed8991b4 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -16,7 +16,6 @@ CONFIG_AEABI=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_SWAP is not set -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c4216c552100..9bd36dd39bd0 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -62,7 +62,6 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_PARTITION_ADVANCED=y CONFIG_BINFMT_MISC=y -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_ZSMALLOC=m CONFIG_NET=y diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig index 8422ddc9bab2..ec3a43f9c85e 100644 --- a/arch/arm/configs/pxa168_defconfig +++ b/arch/arm/configs/pxa168_defconfig @@ -12,7 +12,6 @@ CONFIG_FPE_NWFPE=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index d1e83b52e03a..7f95fa273a7d 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -12,7 +12,6 @@ CONFIG_AEABI=y CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M debug" CONFIG_FPE_NWFPE=y CONFIG_MODULES=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig index 48e41ca582af..958d958377dc 100644 --- a/arch/arm/configs/pxa910_defconfig +++ b/arch/arm/configs/pxa910_defconfig @@ -13,7 +13,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_AEABI=y CONFIG_FPE_NWFPE=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 92f803c2805c..a221a99f6472 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -20,7 +20,6 @@ CONFIG_VFP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_SWAP is not set -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig index 210974364d61..65a3fded55be 100644 --- a/arch/arm/configs/rpc_defconfig +++ b/arch/arm/configs/rpc_defconfig @@ -11,7 +11,6 @@ CONFIG_CPU_SA110=y CONFIG_FPE_NWFPE=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index c6aff6fb084d..56ee511210de 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -26,7 +26,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_SWAP is not set -CONFIG_SLAB=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 954112041403..a89767c89d17 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -41,7 +41,6 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_EFI_PARTITION is not set # CONFIG_COREDUMP is not set # CONFIG_SWAP is not set -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_CMA=y # CONFIG_VM_EVENT_COUNTERS is not set diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 0b21c0a47582..22205ef0f376 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -24,7 +24,6 @@ CONFIG_CPUFREQ_DT=y CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y @@ -36,8 +35,8 @@ CONFIG_NET_DSA=y CONFIG_CAN=y CONFIG_PCI=y CONFIG_PCI_MSI=y -CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCI_RCAR_GEN2=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y @@ -76,7 +75,6 @@ CONFIG_SERIAL_8250=y # CONFIG_SERIAL_8250_16550A_VARIANTS is not set CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set -# CONFIG_SERIAL_8250_PCI1XXXX is not set CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y # CONFIG_SERIAL_8250_PERICOM is not set diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_defconfig index c6448ac860b6..ec723401b440 100644 --- a/arch/arm/configs/sp7021_defconfig +++ b/arch/arm/configs/sp7021_defconfig @@ -24,7 +24,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_SLAB=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index f32047e24b63..3c6af935e932 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -32,7 +32,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 67e3f9138306..849118cbbb44 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -14,7 +14,6 @@ CONFIG_VFP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3dd9e718661b..a8c022b4c053 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -97,7 +97,6 @@ config SOC_AT91SAM9 depends on ARCH_MULTI_V5 select ATMEL_AIC_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select CPU_ARM926T select HAVE_AT91_SMD select HAVE_AT91_USB_CLK @@ -131,7 +130,6 @@ config SOC_SAM9X60 depends on ARCH_MULTI_V5 select ATMEL_AIC5_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select CPU_ARM926T select HAVE_AT91_USB_CLK select HAVE_AT91_GENERATED_CLK @@ -213,7 +211,6 @@ config SOC_SAMA5 bool select ATMEL_AIC5_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select MEMORY select SOC_SAM_V7 select SRAM if PM @@ -234,7 +231,6 @@ config SOC_SAMA7 bool select ARM_GIC select ATMEL_PM if PM - select ATMEL_SDRAMC select MEMORY select SOC_SAM_V7 select SRAM if PM diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index c1ce6b2a8d48..7bc7018688de 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h index b4fd0e9acf6c..8aa6d4fc3f6f 100644 --- a/arch/arm/mach-davinci/common.h +++ b/arch/arm/mach-davinci/common.h @@ -55,12 +55,6 @@ extern void davinci_common_init(const struct davinci_soc_info *soc_info); extern void davinci_init_ide(void); void davinci_init_late(void); -#ifdef CONFIG_CPU_FREQ -int davinci_cpufreq_init(void); -#else -static inline int davinci_cpufreq_init(void) { return 0; } -#endif - #ifdef CONFIG_SUSPEND int davinci_pm_init(void); #else diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index dd4b164d1831..a9efa7bc2fa1 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -9,6 +9,7 @@ #include #include #include "soc.h" +#include "platform.h" /************************************************************************* * Timer handling for EP93xx @@ -60,7 +61,7 @@ static u64 notrace ep93xx_read_sched_clock(void) return ret; } -u64 ep93xx_clocksource_read(struct clocksource *c) +static u64 ep93xx_clocksource_read(struct clocksource *c) { u64 ret; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4d3b40e4049a..b3d5df5225fe 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -78,6 +78,11 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 +config SOC_EXYNOS4212 + bool "Samsung Exynos4212" + default y + depends on ARCH_EXYNOS4 + config SOC_EXYNOS4412 bool "Samsung Exynos4412" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index b5287ff1c542..f4c0d33a29e2 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -15,6 +15,7 @@ #define EXYNOS3_SOC_MASK 0xFFFFF000 #define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4412_CPU_ID 0xE4412200 #define EXYNOS4_CPU_MASK 0xFFFE0000 @@ -34,6 +35,7 @@ static inline int is_samsung_##name(void) \ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) @@ -52,6 +54,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos4210() 0 #endif +#if defined(CONFIG_SOC_EXYNOS4212) +# define soc_is_exynos4212() is_samsung_exynos4212() +#else +# define soc_is_exynos4212() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS4412) # define soc_is_exynos4412() is_samsung_exynos4412() #else diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 966a0995e047..2e8099479ffa 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -180,6 +180,7 @@ static void __init exynos_dt_machine_init(void) exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data; #endif if (of_machine_is_compatible("samsung,exynos4210") || + of_machine_is_compatible("samsung,exynos4212") || (of_machine_is_compatible("samsung,exynos4412") && (of_machine_is_compatible("samsung,trats2") || of_machine_is_compatible("samsung,midas") || @@ -194,6 +195,7 @@ static char const *const exynos_dt_compat[] __initconst = { "samsung,exynos3250", "samsung,exynos4", "samsung,exynos4210", + "samsung,exynos4212", "samsung,exynos4412", "samsung,exynos5", "samsung,exynos5250", diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 2da5b60b59e2..a5e22678e27b 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -63,12 +63,18 @@ static int exynos_cpu_boot(int cpu) * * On Exynos5 devices the call is ignored by trustzone firmware. */ - if (!soc_is_exynos4210() && !soc_is_exynos4412()) + if (!soc_is_exynos4210() && !soc_is_exynos4212() && + !soc_is_exynos4412()) return 0; /* * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. + * But, Exynos4212 has only one secondary CPU so second parameter + * isn't used for informing secure firmware about CPU id. */ + if (soc_is_exynos4212()) + cpu = 0; + exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); return 0; } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 30f4e55bf39e..0019d21bff90 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -161,7 +161,7 @@ void exynos_enter_aftr(void) exynos_pm_central_suspend(); - if (soc_is_exynos4412()) { + if (soc_is_exynos4212() || soc_is_exynos4412()) { /* Setting SEQ_OPTION register */ pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, S5P_CENTRAL_SEQ_OPTION); diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 6d5d7696aaf7..cac4e82f6c82 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -231,6 +231,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node, EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); +EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); @@ -640,6 +641,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { }, { .compatible = "samsung,exynos4210-pmu", .data = &exynos4_pm_data, + }, { + .compatible = "samsung,exynos4212-pmu", + .data = &exynos4_pm_data, }, { .compatible = "samsung,exynos4412-pmu", .data = &exynos4_pm_data, diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 561941baeda9..3fdbdb83113b 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c @@ -12,6 +12,8 @@ #include +#include "core.h" + #define HIGHBANK_SUSPEND_PARAM \ ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ diff --git a/arch/arm/mach-imx/pm-imx25.c b/arch/arm/mach-imx/pm-imx25.c index f253e5019465..0c574e8607fd 100644 --- a/arch/arm/mach-imx/pm-imx25.c +++ b/arch/arm/mach-imx/pm-imx25.c @@ -6,6 +6,7 @@ #include #include #include +#include "common.h" static int imx25_suspend_enter(suspend_state_t state) { diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index 3e765c4bf986..3b1203db81b2 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "lpc32xx.h" #include "common.h" diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 9761d8404949..6a5815aa05e6 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -632,7 +632,7 @@ static int __init omap_pm_init(void) error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); if (error) - printk(KERN_ERR "sysfs_create_file failed: %d\n", error); + pr_err("sysfs_create_file failed: %d\n", error); if (cpu_is_omap16xx()) { /* configure LOW_PWR pin */ diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 3adceb97138f..ffa4a9bece1e 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -20,6 +20,7 @@ #include +#include "common.h" #include "serial.h" #include "mux.h" #include "pm.h" diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c index 26427d6be896..736a72a2b184 100644 --- a/arch/arm/mach-omap1/sram-init.c +++ b/arch/arm/mach-omap1/sram-init.c @@ -23,7 +23,7 @@ #define OMAP1_SRAM_PA 0x20000000 #define SRAM_BOOTLOADER_SZ 0x80 -#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) +#define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1))) static void __iomem *omap_sram_base; static unsigned long omap_sram_start; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 1610c567a6a3..10d2f078e4a8 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 564bf80a2621..8e3b5068d4ab 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -158,7 +158,7 @@ static struct gpiod_lookup_table nokia810_mmc_gpio_table = { "vsd", 1, GPIO_ACTIVE_HIGH), /* Slot index 1, VIO power, GPIO 9 */ GPIO_LOOKUP_IDX("gpio-0-15", 9, - "vsd", 1, GPIO_ACTIVE_HIGH), + "vio", 1, GPIO_ACTIVE_HIGH), { } }, }; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 8d21e3a3c05f..6f0d6120c174 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -374,6 +374,7 @@ static void irq_restore_context(void) static void irq_save_secure_context(void) { u32 ret; + ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX, FLAG_START_CRITICAL, 0, 0, 0, 0, 0); diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cb33f0382a90..5cbdf58ad59f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1851,7 +1851,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { .fw = { .omap2 = { .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, .flags = OMAP_FIREWALL_L4, }, }, @@ -2172,7 +2172,7 @@ static struct omap_hwmod am35xx_emac_hwmod = { /* * According to Mark Greer, the MPU will not return from WFI * when the EMAC signals an interrupt. - * http://www.spinics.net/lists/arm-kernel/msg174734.html + * https://lore.kernel.org/all/1336770778-23044-3-git-send-email-mgreer@animalcreek.com/ */ .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), }; @@ -2346,13 +2346,12 @@ static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { NULL }; - /* * Apparently the SHA/MD5 and AES accelerator IP blocks are * only present on some AM35xx chips, and no one knows which - * ones. See - * http://www.spinics.net/lists/arm-kernel/msg215466.html So - * if you need these IP blocks on an AM35xx, try uncommenting + * ones. + * See https://lore.kernel.org/all/20130108203853.GB1876@animalcreek.com/ + * So if you need these IP blocks on an AM35xx, try uncommenting * the following lines. */ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 21c6e7929d37..a1d001170a68 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * This file configures the internal USB PHY in OMAP4430. Used - * with TWL6030 transceiver and MUSB on OMAP4430. - * - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com - * Author: Hema HK - */ + * This file configures the internal USB PHY in OMAP4430. Used + * with TWL6030 transceiver and MUSB on OMAP4430. + * + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com + * Author: Hema HK + */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 529d46cfdea2..5a275b4fd404 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/mach-omap2/sdrc2xxx.c - * * SDRAM timing related functions for OMAP2xxx * * Copyright (C) 2005, 2008 Texas Instruments Inc. diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c index 815d390109d2..898b011ae8d9 100644 --- a/arch/arm/mach-omap2/sram.c +++ b/arch/arm/mach-omap2/sram.c @@ -45,7 +45,7 @@ #define GP_DEVICE 0x300 -#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) +#define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1))) static unsigned long omap_sram_start; static unsigned long omap_sram_size; @@ -118,7 +118,7 @@ static void omap_sram_reset(void) */ static int is_sram_locked(void) { - if (OMAP2_DEVICE_TYPE_GP == omap_type()) { + if (omap_type() == OMAP2_DEVICE_TYPE_GP) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ diff --git a/arch/arm/mach-omap2/ti81xx-restart.c b/arch/arm/mach-omap2/ti81xx-restart.c index d6dc518b1dde..5b5fb37caa50 100644 --- a/arch/arm/mach-omap2/ti81xx-restart.c +++ b/arch/arm/mach-omap2/ti81xx-restart.c @@ -26,5 +26,6 @@ void ti81xx_restart(enum reboot_mode mode, const char *cmd) { omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, 0, TI81XX_PRM_DEVICE_RSTCTRL); - while (1); + while (1) + ; } diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index e3736ffc8347..be47492c6640 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -60,6 +60,9 @@ static void __init orion5x_dt_init(void) if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); + if (of_machine_is_compatible("lacie,d2-network")) + d2net_init(); + of_platform_default_populate(NULL, orion5x_auxdata_lookup, NULL); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index f2e0577bf50f..8df70e23aa82 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -73,6 +73,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_D2NET_DT +void d2net_init(void); +#else +static inline void d2net_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 7bb1499de4c5..c9c2c46ecead 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -27,7 +27,6 @@ extern void __init pxa25x_map_io(void); extern void __init pxa26x_init_irq(void); #define pxa27x_handle_irq ichp_handle_irq -extern unsigned pxa27x_get_clk_frequency_khz(int); extern void __init pxa27x_init_irq(void); extern void __init pxa27x_map_io(void); @@ -52,18 +51,4 @@ extern void pxa2xx_clear_reset_status(unsigned int); static inline void pxa2xx_clear_reset_status(unsigned int mask) {} #endif -/* - * Once fully converted to the clock framework, all these functions should be - * removed, and replaced with a clk_get(NULL, "core"). - */ -#ifdef CONFIG_PXA25x -extern unsigned pxa25x_get_clk_frequency_khz(int); -#else -#define pxa25x_get_clk_frequency_khz(x) (0) -#endif - -#ifdef CONFIG_PXA27x -#else -#define pxa27x_get_clk_frequency_khz(x) (0) -#endif diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index b556452dfcf9..f5a3d890f682 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -20,6 +20,7 @@ #include "pxa2xx-regs.h" #include "mfp-pxa2xx.h" +#include "mfp-pxa27x.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 032dc897fe94..02712d24be82 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index c9b56424b653..d71491e2e1d6 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -31,7 +32,9 @@ #include "irqs.h" #include "pxa27x.h" #include "reset.h" +#include #include +#include #include "pm.h" #include "addr-map.h" #include "smemc.h" diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index f0be90573ad3..27293549f8ad 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -10,6 +10,7 @@ #include "regs-ost.h" #include "reset.h" #include "smemc.h" +#include "generic.h" static void do_hw_reset(void); diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 6689b67f9ce5..1c021cef965f 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -166,7 +166,7 @@ static bool spitz_charger_wakeup(void) gpio_get_value(SPITZ_GPIO_SYNC); } -unsigned long spitzpm_read_devdata(int type) +static unsigned long spitzpm_read_devdata(int type) { switch (type) { case SHARPSL_STATUS_ACIN: diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx index 01a7a8eec6e8..8f40af063ad6 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c64xx +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -69,11 +69,6 @@ config S3C64XX_SETUP_I2C1 help Common setup code for i2c bus 1. -config S3C64XX_SETUP_IDE - bool - help - Common setup code for S3C64XX IDE. - config S3C64XX_SETUP_FB_24BPP bool help @@ -110,7 +105,6 @@ config MACH_WLF_CRAGG_6410 select S3C64XX_DEV_SPI0 select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_I2C1 - select S3C64XX_SETUP_IDE select S3C64XX_SETUP_KEYPAD select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_SPI diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 4edde13b89b5..8fce1e815ee8 100644 --- a/arch/arm/mach-s3c/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -418,7 +418,7 @@ static struct i2c_driver wlf_gf_module_driver = { .driver = { .name = "wlf-gf-module" }, - .probe_new = wlf_gf_module_probe, + .probe = wlf_gf_module_probe, .id_table = wlf_gf_module_id, }; diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index d000c678b439..2b833aa0212b 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -710,7 +710,7 @@ static void __init assabet_map_io(void) sa1100_register_uart(2, 3); } -void __init assabet_init_irq(void) +static void __init assabet_init_irq(void) { u32 def_val; diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c index 9a7079f565bd..0c21ef45db68 100644 --- a/arch/arm/mach-sa1100/pm.c +++ b/arch/arm/mach-sa1100/pm.c @@ -33,6 +33,8 @@ #include #include +#include "generic.h" + extern int sa1100_finish_suspend(unsigned long); #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x diff --git a/arch/arm/mach-spear/pl080.c b/arch/arm/mach-spear/pl080.c index d6b8627d2544..47243a8153d0 100644 --- a/arch/arm/mach-spear/pl080.c +++ b/arch/arm/mach-spear/pl080.c @@ -16,6 +16,7 @@ #include #include "spear.h" #include "misc_regs.h" +#include "pl080.h" static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); diff --git a/arch/arm/mach-versatile/versatile.c b/arch/arm/mach-versatile/versatile.c index 02ba68abe533..7ef03d0c224d 100644 --- a/arch/arm/mach-versatile/versatile.c +++ b/arch/arm/mach-versatile/versatile.c @@ -53,7 +53,7 @@ static void __iomem *versatile_sys_base; -unsigned int mmc_status(struct device *dev) +static unsigned int mmc_status(struct device *dev) { struct amba_device *adev = container_of(dev, struct amba_device, dev); u32 mask; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..6069120199bb 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -225,6 +225,14 @@ config ARCH_S32 endif +config ARCH_MA35 + bool "Nuvoton MA35 Architecture" + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + help + This enables support for the ARMv8 based Nuvoton MA35 series SoCs. + config ARCH_NPCM bool "Nuvoton NPCM Architecture" select PINCTRL @@ -277,6 +285,20 @@ config ARCH_INTEL_SOCFPGA Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, Agilex and eASIC N5X. +config ARCH_STM32 + bool "STMicroelectronics STM32 SoC Family" + select GPIOLIB + select PINCTRL + select PINCTRL_STM32MP257 + select ARM_SMC_MBOX + select ARM_SCMI_PROTOCOL + select COMMON_CLK_SCMI + help + This enables support for ARMv8 based STMicroelectronics + STM32 family, including: + - STM32MP25: + - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. + config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" select IRQ_FASTEOI_HIERARCHY_HANDLERS diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 7b107fa7414b..30dd6347a929 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += renesas subdir-y += rockchip subdir-y += socionext subdir-y += sprd +subdir-y += st subdir-y += synaptics subdir-y += tesla subdir-y += ti diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 62f45f71ec65..57ac18738c99 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -93,6 +93,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -407,7 +408,7 @@ interrupts = ; clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts index 8857a3791593..6406a29c85f2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts @@ -4,7 +4,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus v1.2 H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts index 77661006dfba..cfb943e9ae85 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi index fc570011495f..2f4b46746f47 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts index d811df332824..b79018c65cae 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts @@ -5,7 +5,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-CC H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts index e59d68b525fc..dc657de2a1a4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-IT H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index a56fae761a1f..d3caf27b6a55 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2016 ARM Ltd. -#include +#include #include diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 73a352ea8fd5..39481d7fd7d4 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -250,6 +250,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster1_l2: cache@100 { @@ -258,6 +259,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster2_l2: cache@200 { @@ -266,6 +268,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster3_l2: cache@300 { @@ -274,6 +277,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index cd1c5b04890a..6f61798a109f 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts new file mode 100644 index 000000000000..edce8850b338 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model = "Amlogic C302 aw409 Development Board"; + compatible = "amlogic,aw409", "amlogic,c3"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x10000000>; + }; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 000000000000..60ad4f3eef9d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index eed96f262844..c8f344596285 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -37,6 +37,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b984950591e2..768d0ed78dbe 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -106,6 +106,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index f58fd2a6fe61..543e70669df5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -51,6 +51,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 431572b384db..86e6ceb31d5e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -106,6 +106,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 11f89bfecb56..2673f0dbafe7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -133,6 +133,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 617d322af0df..643f94d9d08e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -89,6 +89,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 70a10bcafcff..377660d705d1 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -97,15 +97,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index d73e809fe41a..efa79209f4b2 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,15 +81,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 7bdeb965f0a9..8db4243a4947 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -13,7 +13,7 @@ /dts-v1/; #include -#include "vexpress-v2m-rs1.dtsi" +#include "arm/arm/vexpress-v2m-rs1.dtsi" / { model = "V2F-1XV7 Cortex-A53x2 SMM"; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 05d8c5ecf3b0..8b4591ddd27c 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 + +# Enables support for device-tree overlays +DTC_FLAGS := -@ + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts index d24c53682e44..c7280bdefa8d 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" +#include "arm/broadcom/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts index b9000f58beb5..d9d2852b794f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-400.dts" +#include "arm/broadcom/bcm2711-rpi-400.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index e36d395e3951..8810322aa66a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-cm4-io.dts" +#include "arm/broadcom/bcm2711-rpi-cm4-io.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts index f0ec56a1c4d7..17d778a7e0c9 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-a-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-a-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts index 46ad2023cccf..0cf6240b6bf0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 89b78d6c19bf..f429468fd86e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b.dts" +#include "arm/broadcom/bcm2837-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts index b1c4ab212c64..3fa21bd16b49 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-cm3-io3.dts" +#include "arm/broadcom/bcm2837-rpi-cm3-io3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts index 307ae693e4a0..363381a0cfb5 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-zero-2-w.dts" +#include "arm/broadcom/bcm2837-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index 457805efb385..f549bda8c48c 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -64,6 +64,7 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index 46aa8c0b7971..d658c81f7285 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 7020f2e995e2..4f474d47022e 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index 6a0242cbea57..909f254dc47d 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index 1a12905266ef..685ae32951c9 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -52,6 +52,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index f41ebc30666f..820553ce541b 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -36,6 +36,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index fa2688f41f06..0eb93c298297 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index e1b80e569cdf..9dcd25ec2c04 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -80,6 +80,7 @@ CLUSTER0_L2: l2-cache@0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 56789ccf9454..46a827521921 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -44,7 +44,7 @@ compatible = "pinctrl-single"; reg = <0x0014029c 0x26c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; pinctrl-single,gpio-range = < @@ -56,14 +56,14 @@ }; /* pinctrl functions */ - tsio_pins: pinmux_gpio_14 { + tsio_pins: gpio-14-pins { pinctrl-single,pins = < 0x038 MODE_NITRO /* tsio_0 */ 0x03c MODE_NITRO /* tsio_1 */ >; }; - nor_pins: pinmux_pnor_adv_n { + nor_pins: pnor-adv-n-pins { pinctrl-single,pins = < 0x0ac MODE_PNOR /* nand_ce1_n */ 0x0b0 MODE_PNOR /* nand_ce0_n */ @@ -119,7 +119,7 @@ >; }; - nand_pins: pinmux_nand_ce1_n { + nand_pins: nand-ce1-n-pins { pinctrl-single,pins = < 0x0ac MODE_NAND /* nand_ce1_n */ 0x0b0 MODE_NAND /* nand_ce0_n */ @@ -148,59 +148,59 @@ >; }; - pwm0_pins: pinmux_pwm_0 { + pwm0_pins: pwm-0-pins { pinctrl-single,pins = < 0x10c MODE_NITRO >; }; - pwm1_pins: pinmux_pwm_1 { + pwm1_pins: pwm-1-pins { pinctrl-single,pins = < 0x110 MODE_NITRO >; }; - pwm2_pins: pinmux_pwm_2 { + pwm2_pins: pwm-2-pins { pinctrl-single,pins = < 0x114 MODE_NITRO >; }; - pwm3_pins: pinmux_pwm_3 { + pwm3_pins: pwm-3-pins { pinctrl-single,pins = < 0x118 MODE_NITRO >; }; - dbu_rxd_pins: pinmux_uart1_sin_nitro { + dbu_rxd_pins: uart1-sin-nitro-pins { pinctrl-single,pins = < 0x11c MODE_NITRO /* dbu_rxd */ 0x120 MODE_NITRO /* dbu_txd */ >; }; - uart1_pins: pinmux_uart1_sin_nand { + uart1_pins: uart1-sin-nand-pins { pinctrl-single,pins = < 0x11c MODE_NAND /* uart1_sin */ 0x120 MODE_NAND /* uart1_out */ >; }; - uart2_pins: pinmux_uart2_sin { + uart2_pins: uart2-sin-pins { pinctrl-single,pins = < 0x124 MODE_NITRO /* uart2_sin */ 0x128 MODE_NITRO /* uart2_out */ >; }; - uart3_pins: pinmux_uart3_sin { + uart3_pins: uart3-sin-pins { pinctrl-single,pins = < 0x12c MODE_NITRO /* uart3_sin */ 0x130 MODE_NITRO /* uart3_out */ >; }; - i2s_pins: pinmux_i2s_bitclk { + i2s_pins: i2s-bitclk-pins { pinctrl-single,pins = < 0x134 MODE_NITRO /* i2s_bitclk */ 0x138 MODE_NITRO /* i2s_sdout */ @@ -211,7 +211,7 @@ >; }; - qspi_pins: pinumx_qspi_hold_n { + qspi_pins: qspi-hold-n-pins { pinctrl-single,pins = < 0x14c MODE_NAND /* qspi_hold_n */ 0x150 MODE_NAND /* qspi_wp_n */ @@ -222,28 +222,28 @@ >; }; - mdio_pins: pinumx_ext_mdio { + mdio_pins: ext-mdio-pins { pinctrl-single,pins = < 0x164 MODE_NITRO /* ext_mdio */ 0x168 MODE_NITRO /* ext_mdc */ >; }; - i2c0_pins: pinmux_i2c0_sda { + i2c0_pins: i2c0-sda-pins { pinctrl-single,pins = < 0x16c MODE_NITRO /* i2c0_sda */ 0x170 MODE_NITRO /* i2c0_scl */ >; }; - i2c1_pins: pinmux_i2c1_sda { + i2c1_pins: i2c1-sda-pins { pinctrl-single,pins = < 0x174 MODE_NITRO /* i2c1_sda */ 0x178 MODE_NITRO /* i2c1_scl */ >; }; - sdio0_pins: pinmux_sdio0_cd_l { + sdio0_pins: sdio0-cd-l-pins { pinctrl-single,pins = < 0x17c MODE_NITRO /* sdio0_cd_l */ 0x180 MODE_NITRO /* sdio0_clk_sdcard */ @@ -262,7 +262,7 @@ >; }; - sdio1_pins: pinmux_sdio1_cd_l { + sdio1_pins: sdio1-cd-l-pins { pinctrl-single,pins = < 0x1b4 MODE_NITRO /* sdio1_cd_l */ 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ @@ -281,7 +281,7 @@ >; }; - spi0_pins: pinmux_spi0_sck_nand { + spi0_pins: spi0-sck-nand-pins { pinctrl-single,pins = < 0x1ec MODE_NITRO /* spi0_sck */ 0x1f0 MODE_NITRO /* spi0_rxd */ @@ -290,7 +290,7 @@ >; }; - spi1_pins: pinmux_spi1_sck_nand { + spi1_pins: spi1-sck-nand-pins { pinctrl-single,pins = < 0x1fc MODE_NITRO /* spi1_sck */ 0x200 MODE_NITRO /* spi1_rxd */ @@ -299,14 +299,14 @@ >; }; - nuart_pins: pinmux_uart0_sin_nitro { + nuart_pins: uart0-sin-nitro-pins { pinctrl-single,pins = < 0x20c MODE_NITRO /* nuart_rxd */ 0x210 MODE_NITRO /* nuart_txd */ >; }; - uart0_pins: pinumux_uart0_sin_nand { + uart0_pins: uart0-sin-nand-pins { pinctrl-single,pins = < 0x20c MODE_NAND /* uart0_sin */ 0x210 MODE_NAND /* uart0_out */ @@ -319,7 +319,7 @@ >; }; - drdu2_pins: pinmux_drdu2_overcurrent { + drdu2_pins: drdu2-overcurrent-pins { pinctrl-single,pins = < 0x22c MODE_NITRO /* drdu2_overcurrent */ 0x230 MODE_NITRO /* drdu2_vbus_ppc */ @@ -328,7 +328,7 @@ >; }; - drdu3_pins: pinmux_drdu3_overcurrent { + drdu3_pins: drdu3-overcurrent-pins { pinctrl-single,pins = < 0x23c MODE_NITRO /* drdu3_overcurrent */ 0x240 MODE_NITRO /* drdu3_vbus_ppc */ @@ -337,7 +337,7 @@ >; }; - usb3h_pins: pinmux_usb3h_overcurrent { + usb3h_pins: usb3h-overcurrent-pins { pinctrl-single,pins = < 0x24c MODE_NITRO /* usb3h_overcurrent */ 0x250 MODE_NITRO /* usb3h_vbus_ppc */ diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 388424b3e1d3..7aece79bf882 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -109,21 +109,25 @@ CLUSTER0_L2: l2-cache@0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache@100 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER2_L2: l2-cache@200 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER3_L2: l2-cache@300 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index b1fa68835b09..5ea8bda2bfa6 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -734,4 +734,4 @@ }; #include "exynos7-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0a2c..d69fc2392bd0 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -452,4 +452,4 @@ }; #include "exynos7885-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d67e98120313..aa077008b3be 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -200,7 +200,6 @@ pmu_system_controller: system-controller@11860000 { compatible = "samsung,exynos850-pmu", "syscon"; reg = <0x11860000 0x10000>; - clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; reboot: syscon-reboot { compatible = "syscon-reboot"; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ef7d17aef58f..a750be13ace8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -54,7 +54,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb @@ -99,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 678bb0358751..9cbb31191cf9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -47,6 +47,7 @@ l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index b9fd24cdc919..f8acbefc805b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -85,6 +85,7 @@ l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index a01e3cfec77f..50f68ca5a9af 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -80,6 +80,7 @@ l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1e5d76c4d83d..1aa38ed09aa4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -96,21 +96,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index c12c86915ec8..8581ea55d254 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -96,21 +96,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 70fadd79851a..792b7224ca5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -60,6 +60,7 @@ A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts new file mode 100644 index 000000000000..1c4e4d175989 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Emtop Embedded Solutions + */ + +/dts-v1/; + +#include "imx8mm-emtop-som.dtsi" + +/ { + model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1"; + compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som", + "fsl,imx8mm"; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi new file mode 100644 index 000000000000..67d22d3768aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Emtop Embedded Solutions + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM"; + compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3600000>; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_led: emtop-gpio-led-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + + pinctrl_i2c1: emtop-i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: emtop-pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: emtop-uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc3: emtop-usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: emtop-wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 3f9dfd4d3884..df8e808ac473 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -19,6 +19,18 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -303,6 +315,41 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -348,6 +395,26 @@ }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + &pcie_phy { fsl,refclk-pad-mode = ; fsl,tx-deemph-gen1 = <0x2d>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts b/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts new file mode 100644 index 000000000000..164df627a213 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dtsi" + +/ { + model = "FSL i.MX8MM EVKB"; + compatible = "fsl,imx8mm-evkb", "fsl,imx8mm"; +}; + +&i2c1 { + /delete-node/ pmic@4b; + + pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* VDD_SOC with PCIe */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-standby-voltage = <850000>; + }; + + /* VDD_GPU, VDD_VPU, VDD_DRAM */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_3V3 */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1V8, NVCC_1V8, NVCC_ENET */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_DRAM for LPDDR4 */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_SNVS_1P8 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_SNVS_0P8 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_*_1V8 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_PHY_0V9 */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_SD2 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts index e9447738b104..606a4f4d5f15 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts @@ -80,6 +80,35 @@ startup-delay-us = <100>; off-on-delay-us = <12000>; }; + + panel { + compatible = "panel-lvds"; + width-mm = <170>; + height-mm = <28>; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <49500000>; + hactive = <800>; + hback-porch = <48>; + hfront-porch = <312>; + hsync-len = <40>; + vactive = <600>; + vback-porch = <19>; + vfront-porch = <61>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; }; &ecspi1 { @@ -113,8 +142,60 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bridge>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + data-lanes = <1 2>; + lane-polarities = <1 0 0 0 0>; + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -166,6 +247,12 @@ >; }; + pinctrl_dsi_bridge: dsibridgeggrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x19 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 12260290c109..b4466a26d838 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -219,12 +219,14 @@ read-only; reg = <0x53>; pagesize = <16>; + vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + vcc-supply = <®_vcc3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 9e7d38872157..de7f67a4ff2a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -149,7 +149,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; @@ -234,8 +234,6 @@ }; fan-controller@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "gw,gsc-fan"; reg = <0x0a>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index df3b2c93d2d5..0ec2ce3dd721 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -354,7 +354,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index c33ec6826d32..03cd29063312 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -327,7 +327,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 363020a08c9b..6f26914602c8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -293,7 +293,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 5a1f7c30afe5..16761975f56e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -43,6 +43,17 @@ enable-active-high; }; + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "vsd_3v3"; @@ -63,18 +74,30 @@ enable-active-high; }; - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + frame-master; + bitclock-master; + }; }; }; @@ -96,6 +119,36 @@ }; }; +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; &i2c4 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -142,14 +195,32 @@ 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; + #sound-dai-cells = <0>; }; }; +&isi { + status = "okay"; +}; + &easrc { fsl,asrc-rate = <48000>; status = "okay"; }; +&mipi_csi { + status = "okay"; + + ports { + port@0 { + mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -226,6 +297,14 @@ >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 3ed7021a487c..406a711486da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -152,46 +152,6 @@ extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; }; -&pinctrl_fec1 { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - -&pinctrl_fec1_sleep { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 - MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 - MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 - MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 - MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 - MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 - MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 - MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 - MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 - MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 - MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index cbd9d124c80d..d3a67109d55b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -27,6 +27,7 @@ regulator-name = "eth_phy_pwr"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -228,6 +229,12 @@ }; }; }; + + eeprom_som: eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + pagesize = <16>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 7c12518dbc96..2ddba4213001 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -325,7 +325,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 8be8f090e8b8..9869fe7652fc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1104,6 +1104,30 @@ }; }; + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1147,6 +1171,42 @@ #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index cdae45a48c2c..06e91297fb16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -118,6 +118,15 @@ clock-frequency = <100000000>; }; + reg_audio: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -137,6 +146,32 @@ gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + frame-master; + bitclock-master; + }; + }; }; &ecspi2 { @@ -239,6 +274,34 @@ clock-frequency = <384000>; status = "okay"; + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22576000>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + #sound-dai-cells = <0>; + }; + pca6416: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; @@ -315,6 +378,16 @@ status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -477,6 +550,16 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ @@ -547,4 +630,10 @@ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; }; + + pinctrl_wm8962: wm8962grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 92df6c1277c3..e9fb5f7f39b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -23,6 +23,12 @@ stdout-path = &uart1; }; + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -102,6 +108,43 @@ pinctrl-names = "default"; }; }; + + reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3P3VDD"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&i2c5 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3vdd>; + VDDIO-supply = <®_vdd_3p3v_awo>; + }; }; &fec { /* Second ethernet */ @@ -155,6 +198,17 @@ status = "okay"; }; +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usb3_1 { fsl,over-current-active-low; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index b5e76b992a10..31d85d5871c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -23,10 +23,16 @@ stdout-path = &uart1; }; - clk_pcie: clock-pcie { + clk_ext_audio_codec: clock-codec { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <24000000>; + }; + + clk_xtal25: clock-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; }; connector { @@ -140,12 +146,30 @@ }; }; - reg_avdd: regulator-avdd { /* AUDIO_VDD */ + reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */ compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "AUDIO_VDD"; + regulator-name = "3P3VDD"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; }; }; @@ -161,6 +185,15 @@ #size-cells = <0>; reg = <0>; + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3vdd>; + VDDIO-supply = <®_vdd_3p3v_awo>; + }; + typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; @@ -203,6 +236,13 @@ pagesize = <16>; reg = <0x54>; }; + + pcieclk: clock@6b { + compatible = "skyworks,si52144"; + reg = <0x6b>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; i2cmuxed1: i2c@1 { /* HDMI DDC I2C */ @@ -244,7 +284,7 @@ }; &pcie_phy { - clocks = <&clk_pcie>; + clocks = <&pcieclk 1>; clock-names = "ref"; fsl,refclk-pad-mode = ; status = "okay"; @@ -256,6 +296,16 @@ status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usb_dwc3_0 { usb-role-switch; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 7e804f650784..cb1953d14aa9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -49,6 +49,14 @@ startup-delay-us = <100>; vin-supply = <&buck4>; }; + + reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VDD_3P3V_AWO"; + }; }; &A53_0 { @@ -232,6 +240,36 @@ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + tc_bridge: bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + reg = <0xf>; + clock-names = "ref"; + clocks = <&clk IMX8MP_CLK_CLKOUT2>; + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, + <&clk IMX8MP_CLK_CLKOUT2>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <13000000>, <13000000>, <156000000>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tc_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + pmic: pmic@25 { compatible = "nxp,pca9450c"; reg = <0x25>; @@ -398,6 +436,22 @@ status = "okay"; }; +&mipi_dsi { + samsung,burst-clock-frequency = <160000000>; + samsung,esc-clock-frequency = <10000000>; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&tc_bridge_in>; + }; + }; + }; +}; + &pwm1 { pinctrl-0 = <&pinctrl_pwm1>; pinctrl-names = "default"; @@ -863,6 +917,24 @@ >; }; + pinctrl_tc9595: dhcom-tc9595-grp { + fsl,pins = < + /* RESET_DSIBRIDGE */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 + /* DSI-CONV_INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 + >; + }; + + pinctrl_sai3: dhcom-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + >; + }; + pinctrl_touch: dhcom-touch-grp { fsl,pins = < /* #TOUCH_INT */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7816853162b3..fa37ce89f8d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -40,6 +40,17 @@ clock-frequency = <100000000>; }; + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pwr_reg>; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; regulator-name = "can1-stby"; @@ -83,6 +94,37 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8960-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "External Speaker", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "External Speaker", "SPK_LP", + "External Speaker", "SPK_LN", + "External Speaker", "SPK_RP", + "External Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8960>; + }; + + }; }; &flexspi { @@ -344,6 +386,18 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + wm8960: codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + SPKVDD1-supply = <®_audio_pwr>; + }; + pca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; @@ -422,6 +476,16 @@ status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -499,6 +563,12 @@ }; &iomuxc { + pinctrl_audio_pwr_reg: audiopwrreggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -668,6 +738,16 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts index 470ff8e31e32..64d522c71a44 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -14,6 +14,67 @@ compatible = "avnet,sm2s-imx8mp-14N0600E-ep1", "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp", "fsl,imx8mp"; + + reg_vcc_3v3_audio: 3v3-audio-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_AUD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_1v8_audio: 1v8-audio-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_AUD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sgtl5000-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,bitclock-master = <&codec_dai>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + clocks = <&clk IMX8MP_CLK_CLKOUT1>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + VDDA-supply = <®_vcc_3v3_audio>; + VDDD-supply = <®_vcc_1v8_audio>; + VDDIO-supply = <®_vcc_1v8_audio>; + }; +}; + +/* I2S-0 = sai2 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + + fsl,sai-mclk-direction-output; + status = "okay"; }; &flexcan1 { @@ -32,6 +93,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_smarc_gpio>; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + >; + }; + pinctrl_smarc_gpio: smarcgpiosgrp { fsl,pins = , /* GPIO0 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index d8fb29e7e148..4240e20d38ac 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -202,6 +202,13 @@ }; }; + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tq-tlv320aic32x"; + audio-cpu = <&sai3>; + audio-codec = <&tlv320aic3x04>; + }; + thermal-zones { soc-thermal { trips { @@ -449,6 +456,18 @@ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320aic3x04>; + reg = <0x18>; + clock-names = "mclk"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; + se97_1c: temperature-sensor@1c { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1c>; @@ -528,6 +547,16 @@ status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -843,6 +872,23 @@ fsl,pins = ; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 + >; + }; + + pinctrl_tlv320aic3x04: tlv320aic3x04grp { + fsl,pins = < + /* CODEC RST# */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 + >; + }; + /* X61 */ pinctrl_uart1: uart1grp { fsl,pins = , diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi new file mode 100644 index 000000000000..560c68e4da6d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + aliases { + ethernet0 = &eqos; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck3_reg>; +}; + +&A53_1 { + cpu-supply = <&buck3_reg>; +}; + +&A53_2 { + cpu-supply = <&buck3_reg>; +}; + +&A53_3 { + cpu-supply = <&buck3_reg>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0x0>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_1p0"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_1p8"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_2p5"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_soc"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_arm"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + + fan-controller@0 { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + + pmic@69 { + compatible = "mps,mp5416"; + reg = <0x69>; + + regulators { + /* vdd_soc */ + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_dram */ + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_arm */ + buck3_reg: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_1p8 */ + buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT2: nvcc_snvs_1p8 */ + ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT3: vdd_1p0 */ + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT4: vdd_2p5 */ + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT5: vdd_3p3 */ + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +/* off-board header */ +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* off-board */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index eb51d648359b..92514b71b5f4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -281,7 +281,7 @@ }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts new file mode 100644 index 000000000000..4a1bbbbe19e6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&eqos { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi new file mode 100644 index 000000000000..0d40cb0f05f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "gpiod", "", "", + "gpiob", "gpioc", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "pci_usb_sel", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 428c60462e3d..cc406bb338fe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -304,6 +304,210 @@ nvmem-cells = <&imx8mp_uid>; nvmem-cell-names = "soc_unique_id"; + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28440000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28540000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28640000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28740000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x28c03000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c04000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c06000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -534,26 +738,16 @@ <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, <&clk IMX8MP_CLK_NOC_IO>, - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_CLK_GIC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL2_500M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <0>, <0>, <1000000000>, <800000000>, - <500000000>, - <400000000>, - <800000000>, - <393216000>, - <361267200>; + <500000000>; }; src: reset-controller@30390000 { @@ -595,6 +789,13 @@ reg = ; }; + pgc_audio: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI>; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = ; @@ -1147,6 +1348,157 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c10000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c20000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c30000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c50000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c60000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c80000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e00000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e10000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + audio_blk_ctrl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + }; + noc: interconnect@32700000 { compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; reg = <0x32700000 0x100000>; @@ -1174,6 +1526,118 @@ #size-cells = <1>; ranges; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; + }; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; + }; + }; + }; + mipi_dsi: dsi@32e60000 { compatible = "fsl,imx8mp-mipi-dsim"; reg = <0x32e60000 0x400>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 200268660518..3ae3824be027 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -26,7 +26,7 @@ }; panel { - compatible = "innolux,n125hce-gn1", "simple-panel"; + compatible = "innolux,n125hce-gn1"; power-supply = <®_main_3v3>; backlight = <&backlight>; no-hpd; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index c5244b608524..afb3ceb06751 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -108,8 +108,6 @@ <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; - epdev_on-supply = <®_vcc_3v3>; - hard-wired = <1>; status = "okay"; }; @@ -122,8 +120,6 @@ <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; - epdev_on-supply = <®_vcc_3v3>; - hard-wired = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 3a52679ecd68..cb777b47baf9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -177,7 +177,7 @@ port@2 { reg = <2>; - label = "cpu"; + phy-mode = "rev-rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0492556a10db..1a2d2c04db32 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -547,11 +547,13 @@ }; lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; reg = <0x30320000 0x10000>; interrupts = ; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>, @@ -1054,9 +1056,11 @@ }; }; - mipi_dsi: mipi-dsi@30a00000 { + mipi_dsi: dsi@30a00000 { compatible = "fsl,imx8mq-nwl-dsi"; reg = <0x30a00000 0x300>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, @@ -1577,6 +1581,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 32193a43ff49..57627bdaa851 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -52,6 +52,7 @@ A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index fefb93487291..c50f46f06f62 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -116,6 +116,10 @@ no-mmc; }; +&wdog3 { + status = "okay"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index e8d49660ac85..8643612ace8c 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -46,12 +46,27 @@ #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A55_1: cpu@100 { @@ -60,6 +75,7 @@ reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; }; @@ -153,6 +169,24 @@ nxp,no-divider; }; + wdog1: watchdog@442d0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG1_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog2: watchdog@442e0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG2_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + tpm1: pwm@44310000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44310000 0x1000>; @@ -287,14 +321,6 @@ #size-cells = <1>; ranges; - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; reg = <0x44461800 0x400>, <0x44464800 0x400>; @@ -302,6 +328,14 @@ clocks = <&clk IMX93_CLK_ML_APB>, <&clk IMX93_CLK_ML>; }; + + mediamix: power-domain@44462400 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; }; anatop: anatop@44480000 { @@ -344,6 +378,33 @@ status = "disabled"; }; + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG4_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog5: watchdog@424b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG5_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + tpm3: pwm@424e0000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x424e0000 0x1000>; @@ -640,28 +701,6 @@ status = "disabled"; }; - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <0>; - status = "disabled"; - }; - fec: ethernet@42890000 { compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x42890000 0x10000>; @@ -685,6 +724,29 @@ assigned-clock-rates = <100000000>, <250000000>, <50000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + snps,clk-csr = <0>; status = "disabled"; }; @@ -760,6 +822,13 @@ gpio-ranges = <&iomuxc 0 92 16>; }; + ocotp: efuse@47510000 { + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + s4muap: mailbox@47520000 { compatible = "fsl,imx93-mu-s4"; reg = <0x47520000 0x10000>; @@ -788,5 +857,11 @@ #power-domain-cells = <1>; status = "disabled"; }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = ; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index d8c82da88ca0..5ac1cc9ff50e 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -53,11 +53,13 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 3e306218d533..42409ec56792 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -62,11 +62,13 @@ cluster0_l2_cache: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a57f35eb5ef6..7e137a884ae5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -204,11 +204,13 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; A73_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f6d3202b0d1a..b7e2cbf466b3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -187,11 +187,13 @@ CLUSTER0_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -407,7 +409,7 @@ compatible = "pinctrl-single"; reg = <0x0 0xf7010000 0x0 0x27c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; #gpio-range-cells = <3>; pinctrl-single,register-width = <32>; @@ -446,7 +448,7 @@ compatible = "pinconf-single"; reg = <0x0 0xf7010800 0x0 0x28c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; @@ -455,7 +457,7 @@ compatible = "pinconf-single"; reg = <0x0 0xf8001800 0x0 0x78>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi index e7d22619a4c0..3e27624c31de 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -17,13 +17,13 @@ &bl_pwm_pmx_func >; - boot_sel_pmx_func: boot_sel_pmx_func { + boot_sel_pmx_func: boot-sel-pins { pinctrl-single,pins = < 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ >; }; - emmc_pmx_func: emmc_pmx_func { + emmc_pmx_func: emmc-pins { pinctrl-single,pins = < 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ @@ -38,7 +38,7 @@ >; }; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0xc MUX_M0 /* SD_CLK (IOMG003) */ 0x10 MUX_M0 /* SD_CMD (IOMG004) */ @@ -48,7 +48,7 @@ 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ >; }; - sd_pmx_idle: sd_pmx_idle { + sd_pmx_idle: sd-idle-pins { pinctrl-single,pins = < 0xc MUX_M1 /* SD_CLK (IOMG003) */ 0x10 MUX_M1 /* SD_CMD (IOMG004) */ @@ -59,7 +59,7 @@ >; }; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ @@ -69,7 +69,7 @@ 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ >; }; - sdio_pmx_idle: sdio_pmx_idle { + sdio_pmx_idle: sdio-idle-pins { pinctrl-single,pins = < 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ @@ -80,7 +80,7 @@ >; }; - isp_pmx_func: isp_pmx_func { + isp_pmx_func: isp-pins { pinctrl-single,pins = < 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ @@ -101,19 +101,19 @@ >; }; - hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { + hkadc_ssi_pmx_func: hkadc-ssi-pins { pinctrl-single,pins = < 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ >; }; - codec_clk_pmx_func: codec_clk_pmx_func { + codec_clk_pmx_func: codec-clk-pins { pinctrl-single,pins = < 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ >; }; - codec_pmx_func: codec_pmx_func { + codec_pmx_func: codec-pins { pinctrl-single,pins = < 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ @@ -122,7 +122,7 @@ >; }; - fm_pmx_func: fm_pmx_func { + fm_pmx_func: fm-pins { pinctrl-single,pins = < 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ 0x84 MUX_M1 /* FM_XFS (IOMG033) */ @@ -131,7 +131,7 @@ >; }; - bt_pmx_func: bt_pmx_func { + bt_pmx_func: bt-pins { pinctrl-single,pins = < 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ 0x94 MUX_M0 /* BT_XFS (IOMG037) */ @@ -140,26 +140,26 @@ >; }; - pwm_in_pmx_func: pwm_in_pmx_func { + pwm_in_pmx_func: pwm-in-pins { pinctrl-single,pins = < 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ >; }; - bl_pwm_pmx_func: bl_pwm_pmx_func { + bl_pwm_pmx_func: bl-pwm-pins { pinctrl-single,pins = < 0xbc MUX_M1 /* BL_PWM (IOMG047) */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ @@ -168,7 +168,7 @@ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ @@ -177,7 +177,7 @@ >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ @@ -186,7 +186,7 @@ >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ @@ -195,35 +195,35 @@ >; }; - uart5_pmx_func: uart5_pmx_func { + uart5_pmx_func: uart5-pins { pinctrl-single,pins = < 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ @@ -244,7 +244,7 @@ &bl_pwm_cfg_func >; - boot_sel_cfg_func: boot_sel_cfg_func { + boot_sel_cfg_func: boot-sel-cfg-pins { pinctrl-single,pins = < 0x0 0x0 /* BOOT_SEL (IOCFG000) */ >; @@ -253,7 +253,7 @@ pinctrl-single,drive-strength = ; }; - hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { + hkadc_ssi_cfg_func: hkadc-ssi-cfg-pins { pinctrl-single,pins = < 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ >; @@ -262,7 +262,7 @@ pinctrl-single,drive-strength = ; }; - emmc_clk_cfg_func: emmc_clk_cfg_func { + emmc_clk_cfg_func: emmc-clk-cfg-pins { pinctrl-single,pins = < 0x104 0x0 /* EMMC_CLK (IOCFG065) */ >; @@ -271,7 +271,7 @@ pinctrl-single,drive-strength = ; }; - emmc_cfg_func: emmc_cfg_func { + emmc_cfg_func: emmc-cfg-pins { pinctrl-single,pins = < 0x108 0x0 /* EMMC_CMD (IOCFG066) */ 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ @@ -288,7 +288,7 @@ pinctrl-single,drive-strength = ; }; - emmc_rst_cfg_func: emmc_rst_cfg_func { + emmc_rst_cfg_func: emmc-rst-cfg-pins { pinctrl-single,pins = < 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ >; @@ -297,7 +297,7 @@ pinctrl-single,drive-strength = ; }; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0xc 0x0 /* SD_CLK (IOCFG003) */ >; @@ -305,7 +305,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sd_clk_cfg_idle: sd_clk_cfg_idle { + sd_clk_cfg_idle: sd-clk-cfg-idle-pins { pinctrl-single,pins = < 0xc 0x0 /* SD_CLK (IOCFG003) */ >; @@ -314,7 +314,7 @@ pinctrl-single,drive-strength = ; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x10 0x0 /* SD_CMD (IOCFG004) */ 0x14 0x0 /* SD_DATA0 (IOCFG005) */ @@ -326,7 +326,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sd_cfg_idle: sd_cfg_idle { + sd_cfg_idle: sd-cfg-idle-pins { pinctrl-single,pins = < 0x10 0x0 /* SD_CMD (IOCFG004) */ 0x14 0x0 /* SD_DATA0 (IOCFG005) */ @@ -339,7 +339,7 @@ pinctrl-single,drive-strength = ; }; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x134 0x0 /* SDIO_CLK (IOCFG077) */ >; @@ -347,7 +347,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sdio_clk_cfg_idle: sdio_clk_cfg_idle { + sdio_clk_cfg_idle: sdio-clk-cfg-idle-pins { pinctrl-single,pins = < 0x134 0x0 /* SDIO_CLK (IOCFG077) */ >; @@ -356,7 +356,7 @@ pinctrl-single,drive-strength = ; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ @@ -368,7 +368,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sdio_cfg_idle: sdio_cfg_idle { + sdio_cfg_idle: sdio-cfg-idle-pins { pinctrl-single,pins = < 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ @@ -381,7 +381,7 @@ pinctrl-single,drive-strength = ; }; - isp_cfg_func1: isp_cfg_func1 { + isp_cfg_func1: isp-cfg-func1-pins { pinctrl-single,pins = < 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ @@ -403,7 +403,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - isp_cfg_idle1: isp_cfg_idle1 { + isp_cfg_idle1: isp-cfg-idle1-pins { pinctrl-single,pins = < 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ @@ -413,7 +413,7 @@ pinctrl-single,drive-strength = ; }; - isp_cfg_func2: isp_cfg_func2 { + isp_cfg_func2: isp-cfg-func2-pins { pinctrl-single,pins = < 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ >; @@ -422,7 +422,7 @@ pinctrl-single,drive-strength = ; }; - codec_clk_cfg_func: codec_clk_cfg_func { + codec_clk_cfg_func: codec-clk-cfg-pins { pinctrl-single,pins = < 0x70 0x0 /* CODEC_CLK (IOCFG028) */ >; @@ -430,7 +430,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - codec_clk_cfg_idle: codec_clk_cfg_idle { + codec_clk_cfg_idle: codec-clk-cfg-idle-pins { pinctrl-single,pins = < 0x70 0x0 /* CODEC_CLK (IOCFG028) */ >; @@ -439,7 +439,7 @@ pinctrl-single,drive-strength = ; }; - codec_cfg_func1: codec_cfg_func1 { + codec_cfg_func1: codec-cfg-func1-pins { pinctrl-single,pins = < 0x74 0x0 /* DMIC_CLK (IOCFG029) */ >; @@ -448,7 +448,7 @@ pinctrl-single,drive-strength = ; }; - codec_cfg_func2: codec_cfg_func2 { + codec_cfg_func2: codec-cfg-func2-pins { pinctrl-single,pins = < 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 0x7c 0x0 /* CODEC_DI (IOCFG031) */ @@ -458,7 +458,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - codec_cfg_idle2: codec_cfg_idle2 { + codec_cfg_idle2: codec-cfg-idle2-pins { pinctrl-single,pins = < 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 0x7c 0x0 /* CODEC_DI (IOCFG031) */ @@ -469,7 +469,7 @@ pinctrl-single,drive-strength = ; }; - fm_cfg_func: fm_cfg_func { + fm_cfg_func: fm-cfg-pins { pinctrl-single,pins = < 0x84 0x0 /* FM_XCLK (IOCFG033) */ 0x88 0x0 /* FM_XFS (IOCFG034) */ @@ -481,7 +481,7 @@ pinctrl-single,drive-strength = ; }; - bt_cfg_func: bt_cfg_func { + bt_cfg_func: bt-cfg-pins { pinctrl-single,pins = < 0x94 0x0 /* BT_XCLK (IOCFG037) */ 0x98 0x0 /* BT_XFS (IOCFG038) */ @@ -492,7 +492,7 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - bt_cfg_idle: bt_cfg_idle { + bt_cfg_idle: bt-cfg-idle-pins { pinctrl-single,pins = < 0x94 0x0 /* BT_XCLK (IOCFG037) */ 0x98 0x0 /* BT_XFS (IOCFG038) */ @@ -504,7 +504,7 @@ pinctrl-single,drive-strength = ; }; - pwm_in_cfg_func: pwm_in_cfg_func { + pwm_in_cfg_func: pwm-in-cfg-pins { pinctrl-single,pins = < 0xbc 0x0 /* PWM_IN (IOCFG047) */ >; @@ -513,7 +513,7 @@ pinctrl-single,drive-strength = ; }; - bl_pwm_cfg_func: bl_pwm_cfg_func { + bl_pwm_cfg_func: bl-pwm-cfg-pins { pinctrl-single,pins = < 0xc0 0x0 /* BL_PWM (IOCFG048) */ >; @@ -522,7 +522,7 @@ pinctrl-single,drive-strength = ; }; - uart0_cfg_func1: uart0_cfg_func1 { + uart0_cfg_func1: uart0-cfg-func1-pins { pinctrl-single,pins = < 0xc4 0x0 /* UART0_RXD (IOCFG049) */ >; @@ -531,7 +531,7 @@ pinctrl-single,drive-strength = ; }; - uart0_cfg_func2: uart0_cfg_func2 { + uart0_cfg_func2: uart0-cfg-func2-pins { pinctrl-single,pins = < 0xc8 0x0 /* UART0_TXD (IOCFG050) */ >; @@ -540,7 +540,7 @@ pinctrl-single,drive-strength = ; }; - uart1_cfg_func1: uart1_cfg_func1 { + uart1_cfg_func1: uart1-cfg-func1-pins { pinctrl-single,pins = < 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ 0xd4 0x0 /* UART1_RXD (IOCFG053) */ @@ -550,7 +550,7 @@ pinctrl-single,drive-strength = ; }; - uart1_cfg_func2: uart1_cfg_func2 { + uart1_cfg_func2: uart1-cfg-func2-pins { pinctrl-single,pins = < 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ 0xd8 0x0 /* UART1_TXD (IOCFG054) */ @@ -560,7 +560,7 @@ pinctrl-single,drive-strength = ; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ @@ -572,7 +572,7 @@ pinctrl-single,drive-strength = ; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ @@ -584,7 +584,7 @@ pinctrl-single,drive-strength = ; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ @@ -596,7 +596,7 @@ pinctrl-single,drive-strength = ; }; - uart5_cfg_func: uart5_cfg_func { + uart5_cfg_func: uart5-cfg-pins { pinctrl-single,pins = < 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ @@ -606,7 +606,7 @@ pinctrl-single,drive-strength = ; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0xec 0x0 /* I2C0_SCL (IOCFG059) */ 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ @@ -616,7 +616,7 @@ pinctrl-single,drive-strength = ; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ @@ -626,7 +626,7 @@ pinctrl-single,drive-strength = ; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ 0x100 0x0 /* I2C2_SDA (IOCFG064) */ @@ -636,7 +636,7 @@ pinctrl-single,drive-strength = ; }; - spi0_cfg_func: spi0_cfg_func { + spi0_cfg_func: spi0-cfg-pins { pinctrl-single,pins = < 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ @@ -656,7 +656,7 @@ &rstout_n_cfg_func >; - rstout_n_cfg_func: rstout_n_cfg_func { + rstout_n_cfg_func: rstout-n-cfg-pins { pinctrl-single,pins = < 0x0 0x0 /* RSTOUT_N (IOCFG000) */ >; @@ -665,7 +665,7 @@ pinctrl-single,drive-strength = ; }; - pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { + pmu_peri_en_cfg_func: pmu-peri-en-cfg-pins { pinctrl-single,pins = < 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ >; @@ -674,7 +674,7 @@ pinctrl-single,drive-strength = ; }; - sysclk0_en_cfg_func: sysclk0_en_cfg_func { + sysclk0_en_cfg_func: sysclk0-en-cfg-pins { pinctrl-single,pins = < 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ >; @@ -683,7 +683,7 @@ pinctrl-single,drive-strength = ; }; - jtag_tdo_cfg_func: jtag_tdo_cfg_func { + jtag_tdo_cfg_func: jtag-tdo-cfg-pins { pinctrl-single,pins = < 0xc 0x0 /* JTAG_TDO (IOCFG003) */ >; @@ -692,7 +692,7 @@ pinctrl-single,drive-strength = ; }; - rf_reset_cfg_func: rf_reset_cfg_func { + rf_reset_cfg_func: rf-reset-cfg-pins { pinctrl-single,pins = < 0x70 0x0 /* RF_RESET0 (IOCFG028) */ 0x74 0x0 /* RF_RESET1 (IOCFG029) */ diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 920a3111c66d..b801a48041f9 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -25,7 +25,7 @@ &range 0 7 0 &range 8 116 0>; - pmu_pmx_func: pmu_pmx_func { + pmu_pmx_func: pmu-pins { pinctrl-single,pins = < 0x008 MUX_M1 /* PMU1_SSI */ 0x00c MUX_M1 /* PMU2_SSI */ @@ -34,19 +34,19 @@ >; }; - csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + csi0_pwd_n_pmx_func: csi0-pwd-n-pins { pinctrl-single,pins = < 0x044 MUX_M0 /* CSI0_PWD_N */ >; }; - csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + csi1_pwd_n_pmx_func: csi1-pwd-n-pins { pinctrl-single,pins = < 0x04c MUX_M0 /* CSI1_PWD_N */ >; }; - isp0_pmx_func: isp0_pmx_func { + isp0_pmx_func: isp0-pins { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ 0x064 MUX_M1 /* ISP_SCL0 */ @@ -54,7 +54,7 @@ >; }; - isp1_pmx_func: isp1_pmx_func { + isp1_pmx_func: isp1-pins { pinctrl-single,pins = < 0x05c MUX_M1 /* ISP_CLK1 */ 0x06c MUX_M1 /* ISP_SCL1 */ @@ -62,47 +62,47 @@ >; }; - pwr_key_pmx_func: pwr_key_pmx_func { + pwr_key_pmx_func: pwr-key-pins { pinctrl-single,pins = < 0x080 MUX_M0 /* GPIO_034 */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ 0x030 MUX_M1 /* I2C3_SDA */ >; }; - i2c4_pmx_func: i2c4_pmx_func { + i2c4_pmx_func: i2c4-pins { pinctrl-single,pins = < 0x090 MUX_M1 /* I2C4_SCL */ 0x094 MUX_M1 /* I2C4_SDA */ >; }; - pcie_perstn_pmx_func: pcie_perstn_pmx_func { + pcie_perstn_pmx_func: pcie-perstn-pins { pinctrl-single,pins = < 0x15c MUX_M1 /* PCIE_PERST_N */ >; }; - usbhub5734_pmx_func: usbhub5734_pmx_func { + usbhub5734_pmx_func: usbhub5734-pins { pinctrl-single,pins = < 0x11c MUX_M0 /* GPIO_073 */ 0x120 MUX_M0 /* GPIO_074 */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0x0b0 MUX_M2 /* UART1_CTS_N */ 0x0b4 MUX_M2 /* UART1_RTS_N */ @@ -111,7 +111,7 @@ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x0bc MUX_M2 /* UART2_CTS_N */ 0x0c0 MUX_M2 /* UART2_RTS_N */ @@ -120,7 +120,7 @@ >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x0dc MUX_M1 /* UART3_CTS_N */ 0x0e0 MUX_M1 /* UART3_RTS_N */ @@ -129,7 +129,7 @@ >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x0ec MUX_M1 /* UART4_CTS_N */ 0x0f0 MUX_M1 /* UART4_RTS_N */ @@ -138,7 +138,7 @@ >; }; - uart5_pmx_func: uart5_pmx_func { + uart5_pmx_func: uart5-pins { pinctrl-single,pins = < 0x0c4 MUX_M3 /* UART5_CTS_N */ 0x0c8 MUX_M3 /* UART5_RTS_N */ @@ -147,7 +147,7 @@ >; }; - uart6_pmx_func: uart6_pmx_func { + uart6_pmx_func: uart6-pins { pinctrl-single,pins = < 0x0cc MUX_M1 /* UART6_CTS_N */ 0x0d0 MUX_M1 /* UART6_RTS_N */ @@ -156,13 +156,13 @@ >; }; - cam0_rst_pmx_func: cam0_rst_pmx_func { + cam0_rst_pmx_func: cam0-rst-pins { pinctrl-single,pins = < 0x0c8 MUX_M0 /* CAM0_RST */ >; }; - cam1_rst_pmx_func: cam1_rst_pmx_func { + cam1_rst_pmx_func: cam1-rst-pins { pinctrl-single,pins = < 0x124 MUX_M0 /* CAM1_RST */ >; @@ -180,7 +180,7 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 6 0>; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SD_CLK */ 0x004 MUX_M1 /* SD_CMD */ @@ -203,14 +203,14 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; - ufs_pmx_func: ufs_pmx_func { + ufs_pmx_func: ufs-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* UFS_REF_CLK */ 0x004 MUX_M1 /* UFS_RST_N */ >; }; - spi3_pmx_func: spi3_pmx_func { + spi3_pmx_func: spi3-pins { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ 0x00c MUX_M1 /* SPI3_DI */ @@ -231,7 +231,7 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 6 0>; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SDIO_CLK */ 0x004 MUX_M1 /* SDIO_CMD */ @@ -254,7 +254,7 @@ /* pin base in node, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 42 0>; - i2s2_pmx_func: i2s2_pmx_func { + i2s2_pmx_func: i2s2-pins { pinctrl-single,pins = < 0x044 MUX_M1 /* I2S2_DI */ 0x048 MUX_M1 /* I2S2_DO */ @@ -263,42 +263,42 @@ >; }; - slimbus_pmx_func: slimbus_pmx_func { + slimbus_pmx_func: slimbus-pins { pinctrl-single,pins = < 0x02c MUX_M1 /* SLIMBUS_CLK */ 0x030 MUX_M1 /* SLIMBUS_DATA */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x014 MUX_M1 /* I2C0_SCL */ 0x018 MUX_M1 /* I2C0_SDA */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x01c MUX_M1 /* I2C1_SCL */ 0x020 MUX_M1 /* I2C1_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + i2c7_pmx_func: i2c7-pins { pinctrl-single,pins = < 0x024 MUX_M3 /* I2C7_SCL */ 0x028 MUX_M3 /* I2C7_SDA */ >; }; - pcie_pmx_func: pcie_pmx_func { + pcie_pmx_func: pcie-pins { pinctrl-single,pins = < 0x084 MUX_M1 /* PCIE_CLKREQ_N */ 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; - spi2_pmx_func: spi2_pmx_func { + spi2_pmx_func: spi2-pins { pinctrl-single,pins = < 0x08c MUX_M1 /* SPI2_CLK */ 0x090 MUX_M1 /* SPI2_DI */ @@ -307,7 +307,7 @@ >; }; - i2s0_pmx_func: i2s0_pmx_func { + i2s0_pmx_func: i2s0-pins { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ 0x038 MUX_M1 /* I2S0_DO */ @@ -323,7 +323,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - pmu_cfg_func: pmu_cfg_func { + pmu_cfg_func: pmu-cfg-pins { pinctrl-single,pins = < 0x010 0x0 /* PMU1_SSI */ 0x014 0x0 /* PMU2_SSI */ @@ -347,7 +347,7 @@ >; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x038 0x0 /* I2C3_SCL */ 0x03c 0x0 /* I2C3_SDA */ @@ -369,7 +369,7 @@ >; }; - csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + csi0_pwd_n_cfg_func: csi0-pwd-n-cfg-pins { pinctrl-single,pins = < 0x050 0x0 /* CSI0_PWD_N */ >; @@ -390,7 +390,7 @@ >; }; - csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + csi1_pwd_n_cfg_func: csi1-pwd-n-cfg-pins { pinctrl-single,pins = < 0x058 0x0 /* CSI1_PWD_N */ >; @@ -411,7 +411,7 @@ >; }; - isp0_cfg_func: isp0_cfg_func { + isp0_cfg_func: isp0-cfg-pins { pinctrl-single,pins = < 0x064 0x0 /* ISP_CLK0 */ 0x070 0x0 /* ISP_SCL0 */ @@ -433,7 +433,7 @@ DRIVE7_04MA DRIVE6_MASK>; }; - isp1_cfg_func: isp1_cfg_func { + isp1_cfg_func: isp1-cfg-pins { pinctrl-single,pins = < 0x068 0x0 /* ISP_CLK1 */ 0x078 0x0 /* ISP_SCL1 */ @@ -456,7 +456,7 @@ >; }; - pwr_key_cfg_func: pwr_key_cfg_func { + pwr_key_cfg_func: pwr-key-cfg-pins { pinctrl-single,pins = < 0x08c 0x0 /* GPIO_034 */ >; @@ -477,7 +477,7 @@ >; }; - uart1_cfg_func: uart1_cfg_func { + uart1_cfg_func: uart1-cfg-pins { pinctrl-single,pins = < 0x0b4 0x0 /* UART1_RXD */ 0x0b8 0x0 /* UART1_TXD */ @@ -501,7 +501,7 @@ >; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* UART2_CTS_N */ 0x0cc 0x0 /* UART2_RTS_N */ @@ -525,7 +525,7 @@ >; }; - uart5_cfg_func: uart5_cfg_func { + uart5_cfg_func: uart5-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* UART5_RXD */ 0x0cc 0x0 /* UART5_TXD */ @@ -549,7 +549,7 @@ >; }; - cam0_rst_cfg_func: cam0_rst_cfg_func { + cam0_rst_cfg_func: cam0-rst-cfg-pins { pinctrl-single,pins = < 0x0d4 0x0 /* CAM0_RST */ >; @@ -570,7 +570,7 @@ >; }; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x0d8 0x0 /* UART0_RXD */ 0x0dc 0x0 /* UART0_TXD */ @@ -592,7 +592,7 @@ >; }; - uart6_cfg_func: uart6_cfg_func { + uart6_cfg_func: uart6-cfg-pins { pinctrl-single,pins = < 0x0d8 0x0 /* UART6_CTS_N */ 0x0dc 0x0 /* UART6_RTS_N */ @@ -616,7 +616,7 @@ >; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x0e8 0x0 /* UART3_CTS_N */ 0x0ec 0x0 /* UART3_RTS_N */ @@ -640,7 +640,7 @@ >; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x0f8 0x0 /* UART4_CTS_N */ 0x0fc 0x0 /* UART4_RTS_N */ @@ -664,7 +664,7 @@ >; }; - cam1_rst_cfg_func: cam1_rst_cfg_func { + cam1_rst_cfg_func: cam1-rst-cfg-pins { pinctrl-single,pins = < 0x130 0x0 /* CAM1_RST */ >; @@ -692,7 +692,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - ufs_cfg_func: ufs_cfg_func { + ufs_cfg_func: ufs-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* UFS_REF_CLK */ 0x004 0x0 /* UFS_RST_N */ @@ -714,7 +714,7 @@ >; }; - spi3_cfg_func: spi3_cfg_func { + spi3_cfg_func: spi3-cfg-pins { pinctrl-single,pins = < 0x008 0x0 /* SPI3_CLK */ 0x00c 0x0 /* SPI3_DI */ @@ -745,7 +745,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SDIO_CLK */ >; @@ -766,7 +766,7 @@ >; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SDIO_CMD */ 0x008 0x0 /* SDIO_DATA0 */ @@ -798,7 +798,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SD_CLK */ >; @@ -820,7 +820,7 @@ >; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SD_CMD */ 0x008 0x0 /* SD_DATA0 */ @@ -853,7 +853,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x01c 0x0 /* I2C0_SCL */ 0x020 0x0 /* I2C0_SDA */ @@ -875,7 +875,7 @@ >; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x024 0x0 /* I2C1_SCL */ 0x028 0x0 /* I2C1_SDA */ @@ -897,7 +897,7 @@ >; }; - i2c7_cfg_func: i2c7_cfg_func { + i2c7_cfg_func: i2c7-cfg-pins { pinctrl-single,pins = < 0x02c 0x0 /* I2C7_SCL */ 0x030 0x0 /* I2C7_SDA */ @@ -919,7 +919,7 @@ >; }; - slimbus_cfg_func: slimbus_cfg_func { + slimbus_cfg_func: slimbus-cfg-pins { pinctrl-single,pins = < 0x034 0x0 /* SLIMBUS_CLK */ 0x038 0x0 /* SLIMBUS_DATA */ @@ -941,7 +941,7 @@ >; }; - i2s0_cfg_func: i2s0_cfg_func { + i2s0_cfg_func: i2s0-cfg-pins { pinctrl-single,pins = < 0x040 0x0 /* I2S0_DI */ 0x044 0x0 /* I2S0_DO */ @@ -965,7 +965,7 @@ >; }; - i2s2_cfg_func: i2s2_cfg_func { + i2s2_cfg_func: i2s2-cfg-pins { pinctrl-single,pins = < 0x050 0x0 /* I2S2_DI */ 0x054 0x0 /* I2S2_DO */ @@ -989,7 +989,7 @@ >; }; - pcie_cfg_func: pcie_cfg_func { + pcie_cfg_func: pcie-cfg-pins { pinctrl-single,pins = < 0x094 0x0 /* PCIE_CLKREQ_N */ 0x098 0x0 /* PCIE_WAKE_N */ @@ -1011,7 +1011,7 @@ >; }; - spi2_cfg_func: spi2_cfg_func { + spi2_cfg_func: spi2-cfg-pins { pinctrl-single,pins = < 0x09c 0x0 /* SPI2_CLK */ 0x0a0 0x0 /* SPI2_DI */ @@ -1035,7 +1035,7 @@ >; }; - usb_cfg_func: usb_cfg_func { + usb_cfg_func: usb-cfg-pins { pinctrl-single,pins = < 0x0ac 0x0 /* GPIO_219 */ >; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index 77bd8c3a8314..8f7bf80e6ece 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -21,14 +21,14 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 82 0>; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x054 MUX_M2 /* UART0_RXD */ 0x058 MUX_M2 /* UART0_TXD */ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x700 MUX_M2 /* UART2_CTS_N */ 0x704 MUX_M2 /* UART2_RTS_N */ @@ -37,7 +37,7 @@ >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x064 MUX_M1 /* UART3_CTS_N */ 0x068 MUX_M1 /* UART3_RTS_N */ @@ -46,7 +46,7 @@ >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x074 MUX_M1 /* UART4_CTS_N */ 0x078 MUX_M1 /* UART4_RTS_N */ @@ -55,52 +55,52 @@ >; }; - uart6_pmx_func: uart6_pmx_func { + uart6_pmx_func: uart6-pins { pinctrl-single,pins = < 0x05c MUX_M1 /* UART6_RXD */ 0x060 MUX_M1 /* UART6_TXD */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x010 MUX_M1 /* I2C3_SCL */ 0x014 MUX_M1 /* I2C3_SDA */ >; }; - i2c4_pmx_func: i2c4_pmx_func { + i2c4_pmx_func: i2c4-pins { pinctrl-single,pins = < 0x03c MUX_M1 /* I2C4_SCL */ 0x040 MUX_M1 /* I2C4_SDA */ >; }; - cam0_rst_pmx_func: cam0_rst_pmx_func { + cam0_rst_pmx_func: cam0-rst-pins { pinctrl-single,pins = < 0x714 MUX_M0 /* CAM0_RST */ >; }; - cam1_rst_pmx_func: cam1_rst_pmx_func { + cam1_rst_pmx_func: cam1-rst-pins { pinctrl-single,pins = < 0x048 MUX_M0 /* CAM1_RST */ >; }; - cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { + cam0_pwd_n_pmx_func: cam0-pwd-n-pins { pinctrl-single,pins = < 0x098 MUX_M0 /* CAM0_PWD_N */ >; }; - cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { + cam1_pwd_n_pmx_func: cam1-pwd-n-pins { pinctrl-single,pins = < 0x044 MUX_M0 /* CAM1_PWD_N */ >; }; - isp0_pmx_func: isp0_pmx_func { + isp0_pmx_func: isp0-pins { pinctrl-single,pins = < 0x018 MUX_M1 /* ISP_CLK0 */ 0x024 MUX_M1 /* ISP_SCL0 */ @@ -108,7 +108,7 @@ >; }; - isp1_pmx_func: isp1_pmx_func { + isp1_pmx_func: isp1-pins { pinctrl-single,pins = < 0x01c MUX_M1 /* ISP_CLK1 */ 0x02c MUX_M1 /* ISP_SCL1 */ @@ -127,19 +127,19 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 46 0>; - pwr_key_pmx_func: pwr_key_pmx_func { + pwr_key_pmx_func: pwr-key-pins { pinctrl-single,pins = < 0x064 MUX_M0 /* GPIO_203 */ >; }; - pd_pmx_func: pd_pmx_func{ + pd_pmx_func: pd-pins { pinctrl-single,pins = < 0x080 MUX_M0 /* GPIO_221 */ >; }; - i2s2_pmx_func: i2s2_pmx_func { + i2s2_pmx_func: i2s2-pins { pinctrl-single,pins = < 0x050 MUX_M1 /* I2S2_DI */ 0x054 MUX_M1 /* I2S2_DO */ @@ -148,7 +148,7 @@ >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x094 MUX_M1 /* SPI0_CLK */ 0x098 MUX_M1 /* SPI0_DI */ @@ -157,7 +157,7 @@ >; }; - spi2_pmx_func: spi2_pmx_func { + spi2_pmx_func: spi2-pins { pinctrl-single,pins = < 0x710 MUX_M1 /* SPI2_CLK */ 0x714 MUX_M1 /* SPI2_DI */ @@ -166,7 +166,7 @@ >; }; - spi3_pmx_func: spi3_pmx_func { + spi3_pmx_func: spi3-pins { pinctrl-single,pins = < 0x72c MUX_M1 /* SPI3_CLK */ 0x730 MUX_M1 /* SPI3_DI */ @@ -175,37 +175,37 @@ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x020 MUX_M1 /* I2C0_SCL */ 0x024 MUX_M1 /* I2C0_SDA */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x028 MUX_M1 /* I2C1_SCL */ 0x02c MUX_M1 /* I2C1_SDA */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0x030 MUX_M1 /* I2C2_SCL */ 0x034 MUX_M1 /* I2C2_SDA */ >; }; - pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { + pcie_clkreq_pmx_func: pcie-clkreq-pins { pinctrl-single,pins = < 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ >; }; - gpio185_pmx_func: gpio185_pmx_func { + gpio185_pmx_func: gpio185-pins { pinctrl-single,pins = <0x01C 0x1>; }; - gpio185_pmx_idle: gpio185_pmx_idle { + gpio185_pmx_idle: gpio185-idle-pins { pinctrl-single,pins = <0x01C 0x0>; }; }; @@ -216,7 +216,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x058 0x0 /* UART0_RXD */ 0x05c 0x0 /* UART0_TXD */ @@ -238,7 +238,7 @@ >; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x700 0x0 /* UART2_CTS_N */ 0x704 0x0 /* UART2_RTS_N */ @@ -262,7 +262,7 @@ >; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x068 0x0 /* UART3_CTS_N */ 0x06c 0x0 /* UART3_RTS_N */ @@ -286,7 +286,7 @@ >; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x078 0x0 /* UART4_CTS_N */ 0x07c 0x0 /* UART4_RTS_N */ @@ -310,7 +310,7 @@ >; }; - uart6_cfg_func: uart6_cfg_func { + uart6_cfg_func: uart6-cfg-pins { pinctrl-single,pins = < 0x060 0x0 /* UART6_RXD */ 0x064 0x0 /* UART6_TXD */ @@ -332,7 +332,7 @@ >; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x014 0x0 /* I2C3_SCL */ 0x018 0x0 /* I2C3_SDA */ @@ -354,7 +354,7 @@ >; }; - i2c4_cfg_func: i2c4_cfg_func { + i2c4_cfg_func: i2c4-cfg-pins { pinctrl-single,pins = < 0x040 0x0 /* I2C4_SCL */ 0x044 0x0 /* I2C4_SDA */ @@ -376,7 +376,7 @@ >; }; - cam0_rst_cfg_func: cam0_rst_cfg_func { + cam0_rst_cfg_func: cam0-rst-cfg-pins { pinctrl-single,pins = < 0x714 0x0 /* CAM0_RST */ >; @@ -397,7 +397,7 @@ >; }; - cam1_rst_cfg_func: cam1_rst_cfg_func { + cam1_rst_cfg_func: cam1-rst-cfg-pins { pinctrl-single,pins = < 0x04C 0x0 /* CAM1_RST */ >; @@ -418,7 +418,7 @@ >; }; - cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { + cam0_pwd_n_cfg_func: cam0-pwd-n-cfg-pins { pinctrl-single,pins = < 0x09C 0x0 /* CAM0_PWD_N */ >; @@ -439,7 +439,7 @@ >; }; - cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { + cam1_pwd_n_cfg_func: cam1-pwd-n-cfg-pins { pinctrl-single,pins = < 0x048 0x0 /* CAM1_PWD_N */ >; @@ -460,7 +460,7 @@ >; }; - isp0_cfg_func: isp0_cfg_func { + isp0_cfg_func: isp0-cfg-pins { pinctrl-single,pins = < 0x01C 0x0 /* ISP_CLK0 */ 0x028 0x0 /* ISP_SCL0 */ @@ -483,7 +483,7 @@ >; }; - isp1_cfg_func: isp1_cfg_func { + isp1_cfg_func: isp1-cfg-pins { pinctrl-single,pins = < 0x020 0x0 /* ISP_CLK1 */ 0x030 0x0 /* ISP_SCL1 */ @@ -517,7 +517,7 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 10 0>; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SDIO_CLK */ 0x004 MUX_M1 /* SDIO_CMD */ @@ -535,7 +535,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SDIO_CLK */ >; @@ -556,7 +556,7 @@ >; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SDIO_CMD */ 0x008 0x0 /* SDIO_DATA0 */ @@ -592,7 +592,7 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SD_CLK */ 0x004 MUX_M1 /* SD_CMD */ @@ -610,7 +610,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SD_CLK */ >; @@ -632,7 +632,7 @@ >; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SD_CMD */ 0x008 0x0 /* SD_DATA0 */ @@ -665,7 +665,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - pwr_key_cfg_func: pwr_key_cfg_func { + pwr_key_cfg_func: pwr-key-cfg-pins { pinctrl-single,pins = < 0x090 0x0 /* GPIO_203 */ >; @@ -686,7 +686,7 @@ >; }; - usb_cfg_func: usb_cfg_func { + usb_cfg_func: usb-cfg-pins { pinctrl-single,pins = < 0x0AC 0x0 /* GPIO_221 */ >; @@ -707,7 +707,7 @@ >; }; - spi0_cfg_func: spi0_cfg_func { + spi0_cfg_func: spi0-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* SPI0_DI */ 0x0cc 0x0 /* SPI0_DO */ @@ -730,7 +730,7 @@ >; }; - spi2_cfg_func: spi2_cfg_func { + spi2_cfg_func: spi2-cfg-pins { pinctrl-single,pins = < 0x714 0x0 /* SPI2_DI */ 0x718 0x0 /* SPI2_DO */ @@ -753,7 +753,7 @@ >; }; - spi3_cfg_func: spi3_cfg_func { + spi3_cfg_func: spi3-cfg-pins { pinctrl-single,pins = < 0x730 0x0 /* SPI3_DI */ 0x734 0x0 /* SPI3_DO */ @@ -776,7 +776,7 @@ >; }; - spi0_clk_cfg_func: spi0_clk_cfg_func { + spi0_clk_cfg_func: spi0-clk-cfg-pins { pinctrl-single,pins = < 0x0c4 0x0 /* SPI0_CLK */ >; @@ -797,7 +797,7 @@ >; }; - spi2_clk_cfg_func: spi2_clk_cfg_func { + spi2_clk_cfg_func: spi2-clk-cfg-pins { pinctrl-single,pins = < 0x710 0x0 /* SPI2_CLK */ >; @@ -818,7 +818,7 @@ >; }; - spi3_clk_cfg_func: spi3_clk_cfg_func { + spi3_clk_cfg_func: spi3-clk-cfg-pins { pinctrl-single,pins = < 0x72c 0x0 /* SPI3_CLK */ >; @@ -839,7 +839,7 @@ >; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x04c 0x0 /* I2C0_SCL */ 0x050 0x0 /* I2C0_SDA */ @@ -861,7 +861,7 @@ >; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x054 0x0 /* I2C1_SCL */ 0x058 0x0 /* I2C1_SDA */ @@ -883,7 +883,7 @@ >; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0x05c 0x0 /* I2C2_SCL */ 0x060 0x0 /* I2C2_SDA */ @@ -905,7 +905,7 @@ >; }; - pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { + pcie_clkreq_cfg_func: pcie-clkreq-cfg-pins { pinctrl-single,pins = < 0x0b0 0x0 >; @@ -925,7 +925,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - i2s2_cfg_func: i2s2_cfg_func { + i2s2_cfg_func: i2s2-cfg-pins { pinctrl-single,pins = < 0x07c 0x0 /* I2S2_DI */ 0x080 0x0 /* I2S2_DO */ @@ -949,7 +949,7 @@ >; }; - gpio185_cfg_func: gpio185_cfg_func { + gpio185_cfg_func: gpio185-cfg-pins { pinctrl-single,pins = <0x048 0>; pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; @@ -957,7 +957,7 @@ pinctrl-single,slew-rate = <0x0 0x80>; }; - gpio185_cfg_idle: gpio185_cfg_idle { + gpio185_cfg_idle: gpio185-cfg-idle-pins { pinctrl-single,pins = <0x048 0>; pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 5b2b1bfd0d2a..65ddc0698f82 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -212,21 +212,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 291c2ee38288..c588848bfdeb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -212,21 +212,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 8a9436ca2531..595abe339c5d 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -843,81 +843,97 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster4_l2: l2-cache4 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster5_l2: l2-cache5 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster6_l2: l2-cache6 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster7_l2: l2-cache7 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster8_l2: l2-cache8 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster9_l2: l2-cache9 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster10_l2: l2-cache10 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster11_l2: l2-cache11 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster12_l2: l2-cache12 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster13_l2: l2-cache13 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster14_l2: l2-cache14 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster15_l2: l2-cache15 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 8bce64069138..c9ce1010c415 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -50,6 +50,7 @@ l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index d29d2da95f4c..f9abef8dcc94 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -24,6 +24,8 @@ ethernet5 = &switch0port4; }; + /delete-node/ regulator; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; @@ -66,6 +68,7 @@ }; &sdhci1 { + /delete-property/ vqmmc-supply; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index ca1aeb69a892..c864df9ec84d 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -135,7 +135,7 @@ pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index eb0473503936..42a60f3dd5d1 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -285,7 +285,7 @@ pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 990f70303fe6..3ed6fba1f438 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -52,6 +52,7 @@ cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index a7b8e001cc9c..cf6a96ddcf40 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -82,6 +82,7 @@ cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 7740098fd108..8848238f9565 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -82,6 +82,7 @@ cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 0cc9ee9871e7..4ec1aae0a3a9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -468,7 +468,7 @@ status = "disabled"; }; - CP11X_LABEL(nand_controller): nand@720000 { + CP11X_LABEL(nand_controller): nand-controller@720000 { /* * Due to the limitation of the pins available * this controller is only usable on the CPM diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index d31a194124c9..fffdb7bbf889 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT2712 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi new file mode 100644 index 000000000000..d89858c73ab1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ +#include + +&pwrap { + pmic: mt6331 { + compatible = "mediatek,mt6331"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6331regulator: mt6331regulator { + compatible = "mediatek,mt6331-regulator"; + + mt6331_vdvfs11_reg: buck-vdvfs11 { + regulator-name = "vdvfs11"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs12_reg: buck-vdvfs12 { + regulator-name = "vdvfs12"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs13_reg: buck-vdvfs13 { + regulator-name = "vdvfs13"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs14_reg: buck-vdvfs14 { + regulator-name = "vdvfs14"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vcore2_reg: buck-vcore2 { + regulator-name = "vcore2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vio18_reg: buck-vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vtcxo1_reg: ldo-vtcxo1 { + regulator-name = "vtcxo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vtcxo2_reg: ldo-vtcxo2 { + regulator-name = "vtcxo2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_avdd32_aud_reg: ldo-avdd32aud { + regulator-name = "avdd32_aud"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vauxa32_reg: ldo-vauxa32 { + regulator-name = "vauxa32"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vio28_reg: ldo-vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vcamaf_reg: ldo-vcamaf { + regulator-name = "vcam_af"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vemc33_reg: ldo-vemc33 { + regulator-name = "vemc33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vgp1_reg: ldo-vgp1 { + regulator-name = "vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmipi_reg: ldo-vmipi { + regulator-name = "vmipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vgp4_reg: ldo-vgp4 { + regulator-name = "vgp4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vusb10_reg: ldo-vusb10 { + regulator-name = "vusb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vcamio_reg: ldo-vcamio { + regulator-name = "vcam_io"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vsram_reg: ldo-vsram { + regulator-name = "vsram"; + regulator-min-microvolt = <1012500>; + regulator-max-microvolt = <1012500>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vgp2_reg: ldo-vgp2 { + regulator-name = "vgp2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vgp3_reg: ldo-vgp3 { + regulator-name = "vgp3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vrtc_reg: ldo-vrtc { + regulator-name = "vrtc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vdig18_reg: ldo-vdig18 { + regulator-name = "dvdd18_dig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + }; + + mt6331rtc: mt6331rtc { + compatible = "mediatek,mt6331-rtc"; + }; + + mt6331keys: mt6331keys { + compatible = "mediatek,mt6331-keys"; + power { + linux,keycodes = ; + wakeup-source; + }; + home { + linux,keycodes = ; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts index e079b7932ba3..00b14f85c6a1 100644 --- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6755 EVB"; + chassis-type = "embedded"; compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts index 164f5cbb3821..56b1bf06e26b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -10,6 +10,7 @@ / { model = "MediaTek MT6779 EVB"; + chassis-type = "embedded"; compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts index 1ed2f81edeff..e0d4d7a63139 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6795 Evaluation Board"; + chassis-type = "embedded"; compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 507b5b567a36..b5746e6d0b15 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "mt6795.dtsi" +#include "mt6331.dtsi" / { model = "Sony Xperia M5"; @@ -16,6 +17,7 @@ aliases { mmc0 = &mmc0; mmc1 = &mmc1; + mmc2 = &mmc2; serial0 = &uart0; serial1 = &uart1; }; @@ -132,7 +134,97 @@ }; }; +&mmc0 { + /* eMMC controller */ + mediatek,latch-ck = <0x14>; /* hs400 */ + mediatek,hs200-cmd-int-delay = <1>; + mediatek,hs400-cmd-int-delay = <1>; + mediatek,hs400-ds-dly3 = <0x1a>; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <&mt6331_vemc33_reg>; + vqmmc-supply = <&mt6331_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + /* MicroSD card slot */ + vmmc-supply = <&mt6331_vmc_reg>; + vqmmc-supply = <&mt6331_vmch_reg>; + status = "okay"; +}; + +&mmc2 { + /* SDIO WiFi on MMC2 */ + vmmc-supply = <&mt6331_vmc_reg>; + vqmmc-supply = <&mt6331_vmch_reg>; + status = "okay"; +}; + &pio { + mmc0_pins_default: emmc-sdr-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + }; + }; + + mmc0_pins_uhs: emmc-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + nfc_pins: nfc-pins { pins-irq { pinmux = ; @@ -239,6 +331,15 @@ }; }; +&pmic { + /* + * Smartphones, including the Xperia M5, are equipped with a companion + * MT6332 PMIC: when this is present, the main MT6331 PMIC will fire + * an interrupt on the companion, so we use the MT6332 IRQ GPIO. + */ + interrupts = ; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 17019fbea0af..597bce2fed72 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -372,6 +374,17 @@ clocks = <&system_clk>, <&clk32k>; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt6795-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; + clock-names = "spi", "wrap"; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; @@ -389,6 +402,17 @@ clock-names = "clk13m"; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt6795-m4u"; + reg = <0 0x10205000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + #iommu-cells = <1>; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt6795-apmixedsys", "syscon"; reg = <0 0x10209000 0 0x1000>; @@ -401,6 +425,15 @@ status = "disabled"; }; + gce: mailbox@10212000 { + compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + #mbox-cells = <2>; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -644,16 +677,77 @@ status = "disabled"; }; + mmsys: syscon@14000000 { + compatible = "mediatek,mt6795-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + larb0: larb@14021000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14022000 { + compatible = "mediatek,mt6795-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6795-vdecsys"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; + }; + vencsys: clock-controller@18000000 { compatible = "mediatek,mt6795-vencsys"; reg = <0 0x18000000 0 0x1000>; #clock-cells = <1>; }; + + larb3: larb@18001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <3>; + power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts index 2327e752d164..c927932afa0d 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6797 Evaluation Board"; + chassis-type = "embedded"; compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index eff9e8dbd076..9534cf3a09d0 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -12,6 +12,7 @@ / { model = "Mediatek X20 Development Board"; + chassis-type = "embedded"; compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index af3fe61e4093..e4605d23fdc8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -15,6 +15,7 @@ / { model = "Bananapi BPI-R64"; + chassis-type = "embedded"; compatible = "bananapi,bpi-r64", "mediatek,mt7622"; aliases { @@ -150,6 +151,10 @@ switch@0 { compatible = "mediatek,mt7531"; reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&pio 54 0>; ports { @@ -248,14 +253,42 @@ status = "disabled"; }; -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; +&bch { + status = "okay"; +}; +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; flash@0 { - compatible = "jedec,spi-nor"; + compatible = "spi-nand"; reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "fip"; + reg = <0x80000 0x200000>; + read-only; + }; + + ubi: partition@280000 { + label = "ubi"; + reg = <0x280000 0x7d80000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index b74e774c6eba..dad8e683aac5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -15,6 +15,7 @@ / { model = "MediaTek MT7622 RFB1 board"; + chassis-type = "embedded"; compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 006cd639059f..36ef2dbe8add 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -101,6 +101,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 15ee8c568f3c..543c13385d6e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -29,13 +29,13 @@ partition@0 { label = "bl2"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; read-only; }; - partition@80000 { + partition@100000 { label = "reserved"; - reg = <0x80000 0x300000>; + reg = <0x100000 0x280000>; }; partition@380000 { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso index 84aa229e80f3..e48881be4ed6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -27,15 +27,10 @@ partition@0 { label = "bl2"; - reg = <0x0 0x20000>; + reg = <0x0 0x40000>; read-only; }; - partition@20000 { - label = "reserved"; - reg = <0x20000 0x20000>; - }; - partition@40000 { label = "u-boot-env"; reg = <0x40000 0x40000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 33bd6febc160..af4a4309bda4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -16,6 +16,7 @@ / { model = "Bananapi BPI-R3"; + chassis-type = "embedded"; compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; aliases { @@ -37,6 +38,15 @@ regulator-always-on; }; + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* cooling level (0, 1, 2) - pwm inverted */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000 0>; + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -132,6 +142,28 @@ }; }; +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; +}; + &crypto { status = "okay"; }; @@ -274,6 +306,13 @@ }; }; + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function = "spi"; @@ -344,6 +383,12 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; @@ -446,5 +491,9 @@ pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 4f18b4a9a8c8..3ef371ca254e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT7986a RFB"; + chassis-type = "embedded"; compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 51944690e790..68539ea788df 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -240,6 +240,20 @@ status = "disabled"; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -323,6 +337,15 @@ status = "disabled"; }; + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + ssusb: usb@11200000 { compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; @@ -361,6 +384,21 @@ status = "disabled"; }; + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; @@ -412,6 +450,17 @@ }; }; + efuse: efuse@11d00000 { + compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; + reg = <0 0x11d00000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@274 { + reg = <0x274 0xc>; + }; + }; + usb_phy: t-phy@11e10000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; @@ -554,4 +603,31 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + + trips { + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 188ce82ae56c..dde190442e38 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT7986b RFB"; + chassis-type = "embedded"; compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts index 774a2f3fb4b2..ebf1a358f42a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts @@ -11,6 +11,7 @@ / { model = "Pumpkin MT8167"; + chassis-type = "embedded"; compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; memory@40000000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts index 28433b94f7c7..256f245ac01d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts @@ -8,6 +8,7 @@ / { model = "Google Hanawl"; + chassis-type = "laptop"; compatible = "google,hana-rev7", "mediatek,mt8173"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts index c234296755e1..fcf0cb76a87c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts @@ -8,6 +8,7 @@ / { model = "Google Hana"; + chassis-type = "laptop"; compatible = "google,hana-rev6", "google,hana-rev5", "google,hana-rev4", "google,hana-rev3", "google,hana", "mediatek,mt8173"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts index e9e4ac0b74b2..2390d04204e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts @@ -8,6 +8,7 @@ / { model = "Google Elm"; + chassis-type = "laptop"; compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", "google,elm", "mediatek,mt8173"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index d77f6af19065..111495622cac 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -96,6 +96,8 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; + regulator-boot-on; + off-on-delay-us = <500000>; gpio = <&pio 41 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&panel_fixed_pins>; @@ -285,7 +287,7 @@ aux-bus { panel: panel { - compatible = "lg,lp120up1"; + compatible = "edp-panel"; power-supply = <&panel_fixed_3v3>; backlight = <&backlight>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 755df5694234..5122963d8743 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -10,6 +10,7 @@ / { model = "MediaTek MT8173 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 3e3f4b1b00f0..d8bd51807683 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT8183 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts index 1a2ec0787d3c..19c1e2bee494 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -9,6 +9,7 @@ / { model = "Google burnet board"; + chassis-type = "convertible"; compatible = "google,burnet", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts index 0eca3ff8672a..552bfc726999 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -9,6 +9,7 @@ / { model = "Google damu board"; + chassis-type = "convertible"; compatible = "google,damu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts index bc2c57f0a827..8ac6bf5b17f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts @@ -9,6 +9,7 @@ / { model = "Google juniper sku16 board"; + chassis-type = "convertible"; compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts index 3a724e6f915c..fcce8ea1232e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts @@ -9,6 +9,7 @@ / { model = "MediaTek kakadu board sku22"; + chassis-type = "tablet"; compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", "google,kakadu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts index 89a139a0ee44..ebfabba72507 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts @@ -9,6 +9,7 @@ / { model = "MediaTek kakadu board"; + chassis-type = "tablet"; compatible = "google,kakadu-rev3", "google,kakadu-rev2", "google,kakadu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts index e3dd75bdaea4..7213cdcca612 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku16 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts index d81935ae07bc..bbf0cd1aa66d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku272 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts index f4082fbe0517..a429ffeac3bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku288 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts index fb5ee91b6fe0..4ac75806fa94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts @@ -14,6 +14,7 @@ / { model = "MediaTek krane sku0 board"; + chassis-type = "tablet"; compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts index 721d16f9c3b4..095279e55d50 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts @@ -14,6 +14,7 @@ / { model = "MediaTek krane sku176 board"; + chassis-type = "tablet"; compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 63952c1251df..6ce16a265e05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -292,6 +292,10 @@ }; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { mali-supply = <&mt6358_vgpu_reg>; }; @@ -822,6 +826,8 @@ &scp { status = "okay"; + + firmware-name = "mediatek/mt8183/scp.img"; pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts index ed74a3617c13..2667a7424200 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -7,6 +7,7 @@ / { model = "MediaTek MT8186 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 5e83d4e9efa4..f04ae70c470a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -19,6 +20,308 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + + cci: cci { + compatible = "mediatek,mt8186-cci"; + clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <600000>; + }; + + cci_opp_1: opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-microvolt = <675000>; + }; + + cci_opp_2: opp-612000000 { + opp-hz = /bits/ 64 <612000000>; + opp-microvolt = <693750>; + }; + + cci_opp_3: opp-682000000 { + opp-hz = /bits/ 64 <682000000>; + opp-microvolt = <718750>; + }; + + cci_opp_4: opp-752000000 { + opp-hz = /bits/ 64 <752000000>; + opp-microvolt = <743750>; + }; + + cci_opp_5: opp-822000000 { + opp-hz = /bits/ 64 <822000000>; + opp-microvolt = <768750>; + }; + + cci_opp_6: opp-875000000 { + opp-hz = /bits/ 64 <875000000>; + opp-microvolt = <781250>; + }; + + cci_opp_7: opp-927000000 { + opp-hz = /bits/ 64 <927000000>; + opp-microvolt = <800000>; + }; + + cci_opp_8: opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + opp-microvolt = <818750>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + opp-microvolt = <843750>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz = /bits/ 64 <1120000000>; + opp-microvolt = <862500>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz = /bits/ 64 <1155000000>; + opp-microvolt = <887500>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz = /bits/ 64 <1190000000>; + opp-microvolt = <906250>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz = /bits/ 64 <1260000000>; + opp-microvolt = <950000>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz = /bits/ 64 <1330000000>; + opp-microvolt = <993750>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1031250>; + }; + }; + + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <600000>; + required-opps = <&cci_opp_0>; + }; + + opp-774000000 { + opp-hz = /bits/ 64 <774000000>; + opp-microvolt = <675000>; + required-opps = <&cci_opp_1>; + }; + + opp-875000000 { + opp-hz = /bits/ 64 <875000000>; + opp-microvolt = <700000>; + required-opps = <&cci_opp_2>; + }; + + opp-975000000 { + opp-hz = /bits/ 64 <975000000>; + opp-microvolt = <725000>; + required-opps = <&cci_opp_3>; + }; + + opp-1075000000 { + opp-hz = /bits/ 64 <1075000000>; + opp-microvolt = <750000>; + required-opps = <&cci_opp_4>; + }; + + opp-1175000000 { + opp-hz = /bits/ 64 <1175000000>; + opp-microvolt = <775000>; + required-opps = <&cci_opp_5>; + }; + + opp-1275000000 { + opp-hz = /bits/ 64 <1275000000>; + opp-microvolt = <800000>; + required-opps = <&cci_opp_6>; + }; + + opp-1375000000 { + opp-hz = /bits/ 64 <1375000000>; + opp-microvolt = <825000>; + required-opps = <&cci_opp_7>; + }; + + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <856250>; + required-opps = <&cci_opp_8>; + }; + + opp-1618000000 { + opp-hz = /bits/ 64 <1618000000>; + opp-microvolt = <875000>; + required-opps = <&cci_opp_9>; + }; + + opp-1666000000 { + opp-hz = /bits/ 64 <1666000000>; + opp-microvolt = <900000>; + required-opps = <&cci_opp_10>; + }; + + opp-1733000000 { + opp-hz = /bits/ 64 <1733000000>; + opp-microvolt = <925000>; + required-opps = <&cci_opp_11>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000>; + required-opps = <&cci_opp_12>; + }; + + opp-1866000000 { + opp-hz = /bits/ 64 <1866000000>; + opp-microvolt = <981250>; + required-opps = <&cci_opp_13>; + }; + + opp-1933000000 { + opp-hz = /bits/ 64 <1933000000>; + opp-microvolt = <1006250>; + required-opps = <&cci_opp_14>; + }; + + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <1031250>; + required-opps = <&cci_opp_15>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-774000000 { + opp-hz = /bits/ 64 <774000000>; + opp-microvolt = <675000>; + required-opps = <&cci_opp_0>; + }; + + opp-835000000 { + opp-hz = /bits/ 64 <835000000>; + opp-microvolt = <693750>; + required-opps = <&cci_opp_1>; + }; + + opp-919000000 { + opp-hz = /bits/ 64 <919000000>; + opp-microvolt = <718750>; + required-opps = <&cci_opp_2>; + }; + + opp-1002000000 { + opp-hz = /bits/ 64 <1002000000>; + opp-microvolt = <743750>; + required-opps = <&cci_opp_3>; + }; + + opp-1085000000 { + opp-hz = /bits/ 64 <1085000000>; + opp-microvolt = <775000>; + required-opps = <&cci_opp_4>; + }; + + opp-1169000000 { + opp-hz = /bits/ 64 <1169000000>; + opp-microvolt = <800000>; + required-opps = <&cci_opp_5>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <843750>; + required-opps = <&cci_opp_6>; + }; + + opp-1419000000 { + opp-hz = /bits/ 64 <1419000000>; + opp-microvolt = <875000>; + required-opps = <&cci_opp_7>; + }; + + opp-1530000000 { + opp-hz = /bits/ 64 <1530000000>; + opp-microvolt = <912500>; + required-opps = <&cci_opp_8>; + }; + + opp-1670000000 { + opp-hz = /bits/ 64 <1670000000>; + opp-microvolt = <956250>; + required-opps = <&cci_opp_9>; + }; + + opp-1733000000 { + opp-hz = /bits/ 64 <1733000000>; + opp-microvolt = <981250>; + required-opps = <&cci_opp_10>; + }; + + opp-1796000000 { + opp-hz = /bits/ 64 <1796000000>; + opp-microvolt = <1012500>; + required-opps = <&cci_opp_11>; + }; + + opp-1860000000 { + opp-hz = /bits/ 64 <1860000000>; + opp-microvolt = <1037500>; + required-opps = <&cci_opp_12>; + }; + + opp-1923000000 { + opp-hz = /bits/ 64 <1923000000>; + opp-microvolt = <1062500>; + required-opps = <&cci_opp_13>; + }; + + cluster1_opp_14: opp-1986000000 { + opp-hz = /bits/ 64 <1986000000>; + opp-microvolt = <1093750>; + required-opps = <&cci_opp_14>; + }; + + cluster1_opp_15: opp-2050000000 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1118750>; + required-opps = <&cci_opp_15>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +368,11 @@ reg = <0x000>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -75,6 +383,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@100 { @@ -83,6 +392,11 @@ reg = <0x100>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -93,6 +407,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@200 { @@ -101,6 +416,11 @@ reg = <0x200>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -111,6 +431,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@300 { @@ -119,6 +440,11 @@ reg = <0x300>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -129,6 +455,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@400 { @@ -137,6 +464,11 @@ reg = <0x400>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -147,6 +479,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@500 { @@ -155,6 +488,11 @@ reg = <0x500>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -165,6 +503,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@600 { @@ -173,6 +512,11 @@ reg = <0x600>; enable-method = "psci"; clock-frequency = <2050000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <335>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_ret_b &cpu_off_b>; i-cache-size = <65536>; @@ -183,6 +527,7 @@ d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@700 { @@ -191,6 +536,11 @@ reg = <0x700>; enable-method = "psci"; clock-frequency = <2050000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <335>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_ret_b &cpu_off_b>; i-cache-size = <65536>; @@ -201,6 +551,7 @@ d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states { @@ -250,6 +601,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -259,6 +611,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { @@ -294,6 +647,142 @@ clock-output-names = "clk32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-299000000 { + opp-hz = /bits/ 64 <299000000>; + opp-microvolt = <612500>; + opp-supported-hw = <0xff>; + }; + + opp-332000000 { + opp-hz = /bits/ 64 <332000000>; + opp-microvolt = <625000>; + opp-supported-hw = <0xff>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-microvolt = <637500>; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <643750>; + opp-supported-hw = <0xff>; + }; + + opp-434000000 { + opp-hz = /bits/ 64 <434000000>; + opp-microvolt = <656250>; + opp-supported-hw = <0xff>; + }; + + opp-484000000 { + opp-hz = /bits/ 64 <484000000>; + opp-microvolt = <668750>; + opp-supported-hw = <0xff>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + opp-microvolt = <687500>; + opp-supported-hw = <0xff>; + }; + + opp-586000000 { + opp-hz = /bits/ 64 <586000000>; + opp-microvolt = <700000>; + opp-supported-hw = <0xff>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + opp-microvolt = <712500>; + opp-supported-hw = <0xff>; + }; + + opp-690000000 { + opp-hz = /bits/ 64 <690000000>; + opp-microvolt = <737500>; + opp-supported-hw = <0xff>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <756250>; + opp-supported-hw = <0xff>; + }; + + opp-796000000 { + opp-hz = /bits/ 64 <796000000>; + opp-microvolt = <781250>; + opp-supported-hw = <0xff>; + }; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + opp-supported-hw = <0xff>; + }; + + opp-900000000-3 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8>; + }; + + opp-900000000-4 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <837500>; + opp-supported-hw = <0x10>; + }; + + opp-900000000-5 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <825000>; + opp-supported-hw = <0x30>; + }; + + opp-950000000-3 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <900000>; + opp-supported-hw = <0x8>; + }; + + opp-950000000-4 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <875000>; + opp-supported-hw = <0x10>; + }; + + opp-950000000-5 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x30>; + }; + + opp-1000000000-3 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0x8>; + }; + + opp-1000000000-4 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <912500>; + opp-supported-hw = <0x10>; + }; + + opp-1000000000-5 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <875000>; + opp-supported-hw = <0x30>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -412,7 +901,7 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8186_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { reg = ; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; @@ -603,6 +1092,21 @@ clock-names = "spi", "wrap"; }; + spmi: spmi@10015000 { + compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; + reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts = , + ; + status = "disabled"; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8186-timer", "mediatek,mt6765-timer"; @@ -611,6 +1115,15 @@ clocks = <&clk13m>; }; + gce: mailbox@1022c000 { + compatible = "mediatek,mt8186-gce"; + reg = <0 0X1022c000 0 0x4000>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names = "gce"; + interrupts = ; + #mbox-cells = <2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8186-scp"; reg = <0 0x10500000 0 0x40000>, @@ -619,6 +1132,22 @@ interrupts = ; }; + adsp: adsp@10680000 { + compatible = "mediatek,mt8186-dsp"; + reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; + reg-names = "cfg", "sram", "sec", "bus"; + clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; + clock-names = "audiodsp", "adsp_bus"; + assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; + status = "disabled"; + }; + adsp_mailbox0: mailbox@10686000 { compatible = "mediatek,mt8186-adsp-mbox"; #mbox-cells = <0>; @@ -982,6 +1511,40 @@ status = "disabled"; }; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: usb@11200000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; + wakeup-source; + status = "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -1013,6 +1576,40 @@ status = "disabled"; }; + ssusb1: usb@11281000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: usb@11280000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11280000 0 0x1000>; + reg-names = "mac"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; + wakeup-source; + status = "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; @@ -1058,6 +1655,11 @@ reg = <0 0x11cb0000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + gpu_speedbin: gpu-speed-bin@59c { + reg = <0x59c 0x4>; + bits = <0 3>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -1090,6 +1692,10 @@ <&spm MT8186_POWER_DOMAIN_MFG3>; power-domain-names = "core0", "core1"; #cooling-cells = <2>; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; + operating-points-v2 = <&gpu_opp_table>; + dynamic-power-coefficient = <4687>; status = "disabled"; }; @@ -1098,6 +1704,20 @@ reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8186-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; smi_common: smi@14002000 { @@ -1131,6 +1751,45 @@ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible = "mediatek,mt8186-dpi"; reg = <0 0x1400a000 0 0x1000>; @@ -1148,6 +1807,52 @@ }; }; + ccorr: ccorr@1400b000 { + compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible = "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible = "mediatek,mt8186-dsi"; reg = <0 0x14013000 0 0x1000>; @@ -1181,6 +1886,16 @@ #iommu-cells = <1>; }; + rdma1: rdma@1401f000 { + compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1401f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index 43a823990a92..6e23428a3ed2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -40,9 +40,90 @@ >; }; +&pio { + bt_pins: bt-pins { + pins-bt-kill { + pinmux = ; + output-low; + }; + + pins-bt-wake { + pinmux = ; + bias-pull-up; + }; + + pins-ap-wake-bt { + pinmux = ; + output-low; + }; + }; + + uart1_pins: uart1-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + + pins-rts { + pinmux = ; + }; + }; + + uart1_pins_sleep: uart1-sleep-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + + pins-rts { + pinmux = ; + }; + }; +}; + &touchscreen { compatible = "hid-over-i2c"; post-power-on-delay-ms = <10>; hid-descr-addr = <0x0001>; vdd-supply = <&pp3300_u>; }; + +&uart1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pins>; + pinctrl-1 = <&uart1_pins_sleep>; + /delete-property/ interrupts; + interrupts-extended = <&gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 94 IRQ_TYPE_EDGE_FALLING>; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + + enable-gpios = <&pio 144 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&pio 168 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&pio 22 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 5a440504d4f9..0e8b34117090 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -275,6 +275,10 @@ remote-endpoint = <&anx7625_in>; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { mali-supply = <&mt6315_7_vbuck1>; status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 5c30caf74026..69f4cded5dbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -70,7 +70,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; - capacity-dmips-mhz = <530>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; }; cpu1: cpu@100 { @@ -87,7 +88,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; - capacity-dmips-mhz = <530>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; }; cpu2: cpu@200 { @@ -104,7 +106,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; - capacity-dmips-mhz = <530>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; }; cpu3: cpu@300 { @@ -121,7 +124,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; - capacity-dmips-mhz = <530>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; }; cpu4: cpu@400 { @@ -138,6 +142,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -155,6 +160,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -172,6 +178,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -189,6 +196,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -228,6 +236,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -237,6 +246,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { @@ -401,8 +411,15 @@ #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; + dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -1625,6 +1642,65 @@ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; }; + vcodec_dec: video-codec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0x16000000 0 0x26000>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0x0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1600d000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 8ac80a136c37..37a3e9de90ff 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -255,6 +255,10 @@ }; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { status = "okay"; mali-supply = <&mt6315_7_vbuck1>; @@ -464,6 +468,13 @@ }; }; +&pcie1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins_default>; +}; + &pio { mediatek,rsel-resistance-in-si-unit; pinctrl-names = "default"; @@ -852,6 +863,24 @@ }; }; + pcie0_pins_default: pcie0-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie1_pins_default: pcie1-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + pio_default: pio-default-pins { pins-wifi-enable { pinmux = ; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a44aae4ab953..4dbbf8fdab75 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -24,6 +24,8 @@ #size-cells = <2>; aliases { + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; gce0 = &gce0; gce1 = &gce1; ethdr0 = ðdr0; @@ -283,6 +285,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -292,6 +295,7 @@ cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { @@ -2366,6 +2370,76 @@ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>; @@ -3262,5 +3336,185 @@ }; }; }; + + vpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; + + trips { + vpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; + + trips { + vpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; + + trips { + gpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; + + trips { + gpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + vdec-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; + + trips { + vdec_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vdec_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + img-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_IMG>; + + trips { + img_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + img_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + infra-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; + + trips { + infra_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + infra_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cam0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; + + trips { + cam0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cam1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; + + trips { + cam1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index ceb48eb1a6e6..50cbaefa1a99 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -12,6 +12,7 @@ #include #include #include "mt8365.dtsi" +#include "mt6357.dtsi" / { model = "MediaTek MT8365 Open Platform EVK"; @@ -87,6 +88,49 @@ }; }; +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -94,7 +138,74 @@ status = "okay"; }; +&mmc0 { + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x12012>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&mt6357_vemc_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; + max-frequency = <200000000>; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&mt6357_vmch_reg>; + vqmmc-supply = <&mt6357_vmc_reg>; + status = "okay"; +}; + +&mt6357_pmic { + interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; +}; + &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ; @@ -111,6 +222,108 @@ }; }; + mmc0_default_pins: mmc0-default-pins { + clk-pins { + pinmux = ; + bias-pull-down; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + rst-pins { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + ds-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + rst-pins { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + cd-pins { + pinmux = ; + bias-pull-up; + }; + + clk-pins { + pinmux = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = , @@ -164,6 +377,28 @@ status = "okay"; }; +&ssusb { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + usb-role-switch; + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + type = "micro"; + vbus-supply = <&usb_otg_vbus>; + }; +}; + +&usb_host { + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 1f6b48359115..413496c92069 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -20,6 +20,91 @@ #address-cells = <1>; #size-cells = <0>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + cpu-map { cluster0 { core0 { @@ -43,6 +128,7 @@ reg = <0x0>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -50,6 +136,10 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -58,6 +148,7 @@ reg = <0x1>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -65,6 +156,10 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -73,6 +168,7 @@ reg = <0x2>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -80,6 +176,10 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -88,6 +188,7 @@ reg = <0x3>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -95,6 +196,41 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_MCDI: cpu-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010001>; + entry-latency-us = <300>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + + CLUSTER_MCDI: cluster-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <350>; + exit-latency-us = <250>; + min-residency-us = <1200>; + }; + + CLUSTER_DPIDLE: cluster-dpidle { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010004>; + entry-latency-us = <300>; + exit-latency-us = <800>; + min-residency-us = <3300>; + }; }; l2: l2-cache { @@ -162,6 +298,12 @@ reg = <0 0x10005000 0 0x1000>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + pio: pinctrl@1000b000 { compatible = "mediatek,mt8365-pinctrl"; reg = <0 0x1000b000 0 0x1000>; diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b..4996499cc738 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,19 +39,21 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; @@ -61,7 +63,7 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { + psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index ed94a80bf05f..f3e226de5e5e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -325,69 +325,69 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_22"; function = "twi_scl_m"; output-high; }; - i2cmux_6: i2cmux-6 { + i2cmux_6: i2cmux-6-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_7: i2cmux-7 { + i2cmux_7: i2cmux-7-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_8: i2cmux-8 { + i2cmux_8: i2cmux-8-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_9: i2cmux-9 { + i2cmux_9: i2cmux-9-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; }; - i2cmux_10: i2cmux-10 { + i2cmux_10: i2cmux-10-pins { pins = "GPIO_56"; function = "twi_scl_m"; output-high; }; - i2cmux_11: i2cmux-11 { + i2cmux_11: i2cmux-11-pins { pins = "GPIO_57"; function = "twi_scl_m"; output-high; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 0760cf2e48bc..82ce007d9959 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -59,28 +59,28 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_35", "GPIO_36", "GPIO_50", "GPIO_51"; function = "twi_scl_m"; output-low; }; - i2cmux_s29: i2cmux-0 { + i2cmux_s29: i2cmux-0-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_s30: i2cmux-1 { + i2cmux_s30: i2cmux-1-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_s31: i2cmux-2 { + i2cmux_s31: i2cmux-2-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_s32: i2cmux-3 { + i2cmux_s32: i2cmux-3-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 9d1a082de3e2..32bb76b3202a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -6,6 +6,18 @@ /dts-v1/; #include "sparx5.dtsi" +&psci { + status = "disabled"; +}; + +&cpu0 { + enable-method = "spin-table"; +}; + +&cpu1 { + enable-method = "spin-table"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile index a99dab90472a..3bc9787801a5 100644 --- a/arch/arm64/boot/dts/nuvoton/Makefile +++ b/arch/arm64/boot/dts/nuvoton/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb +dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts new file mode 100644 index 000000000000..b89e2be6abae --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-IoT"; + compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts new file mode 100644 index 000000000000..a1ebddecb7f8 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-SOM"; + compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi new file mode 100644 index 000000000000..781cdae566a0 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "nuvoton,ma35d1"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@50801000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50801000 0 0x1000>, /* GICD */ + <0x0 0x50802000 0 0x2000>, /* GICC */ + <0x0 0x50804000 0 0x2000>, /* GICH */ + <0x0 0x50806000 0 0x2000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + interrupt-parent = <&gic>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x0 0x40460000 0x0 0x200>; + #reset-cells = <1>; + }; + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x00000000 0x40460200 0x0 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; + + uart0: serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40700000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + status = "disabled"; + }; + + uart1: serial@40710000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40710000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART1_GATE>; + status = "disabled"; + }; + + uart2: serial@40720000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40720000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART2_GATE>; + status = "disabled"; + }; + + uart3: serial@40730000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40730000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART3_GATE>; + status = "disabled"; + }; + + uart4: serial@40740000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40740000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART4_GATE>; + status = "disabled"; + }; + + uart5: serial@40750000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40750000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART5_GATE>; + status = "disabled"; + }; + + uart6: serial@40760000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40760000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART6_GATE>; + status = "disabled"; + }; + + uart7: serial@40770000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40770000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART7_GATE>; + status = "disabled"; + }; + + uart8: serial@40780000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40780000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART8_GATE>; + status = "disabled"; + }; + + uart9: serial@40790000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40790000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART9_GATE>; + status = "disabled"; + }; + + uart10: serial@407a0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407a0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART10_GATE>; + status = "disabled"; + }; + + uart11: serial@407b0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407b0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART11_GATE>; + status = "disabled"; + }; + + uart12: serial@407c0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407c0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART12_GATE>; + status = "disabled"; + }; + + uart13: serial@407d0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407d0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART13_GATE>; + status = "disabled"; + }; + + uart14: serial@407e0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407e0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART14_GATE>; + status = "disabled"; + }; + + uart15: serial@407f0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407f0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART15_GATE>; + status = "disabled"; + }; + + uart16: serial@40880000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40880000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART16_GATE>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 1406d5d40b8f..c38c809fe577 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -9,7 +9,9 @@ DTC_FLAGS_tegra194-p2972-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ +DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@ DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@ +DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb @@ -25,4 +27,6 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index d7d7c63e62e2..5a1ce432c1fb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -36,6 +36,11 @@ }; }; + gpu@57000000 { + vdd-supply = <&max77621_gpu>; + status = "okay"; + }; + pinmux: pinmux@700008d4 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1370,11 +1375,27 @@ maxim,dvs-default-state = <1>; maxim,enable-active-discharge; maxim,enable-bias-control; - maxim,enable-etr; maxim,enable-gpio = <&pmic 5 0>; maxim,externally-enable; }; + max77621_gpu: regulator@1c { + compatible = "maxim,max77621"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <1150000>; + regulator-name = "PPVAR_GPU"; + regulator-ramp-delay = <12500>; + maxim,dvs-default-state = <1>; + maxim,enable-active-discharge; + maxim,enable-bias-control; + maxim,disable-etr; + maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + maxim,externally-enable; + }; + pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0e463b3cbe01..617583ff2736 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2000,6 +2000,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 2378da324273..319b3a9cff24 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -126,7 +126,7 @@ regulator-name = "VDD_3V3_PCIE"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>; regulator-boot-on; enable-active-high; }; @@ -139,4 +139,26 @@ gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; regulator-boot-on; }; + + thermal-zones { + tj-thermal { + polling-delay = <1000>; + polling-delay-passive = <1000>; + status = "okay"; + + trips { + tj_trip_active0: active-0 { + temperature = <75000>; + hysteresis = <4000>; + type = "active"; + }; + + tj_trip_active1: active-1 { + temperature = <95000>; + hysteresis = <4000>; + type = "active"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi new file mode 100644 index 000000000000..e468352b8b7f --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + compatible = "nvidia,p3701-0008", "nvidia,tegra234"; + + bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "module"; + vcc-supply = <&vdd_1v8_hs>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + i2c@c240000 { + status = "okay"; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; + + bpmp { + i2c { + status = "okay"; + + thermal-sensor@4c { + status = "okay"; + reg = <0x4c>; + vcc-supply = <&vdd_1v8_ao>; + }; + }; + + thermal { + status = "okay"; + }; + }; + + vdd_1v8_ao: regulator-vdd-1v8-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_hs: regulator-vdd-1v8-hs { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_ls: regulator-vdd-1v8-ls { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3v3_ao: regulator-vdd-3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index caa9e952a149..cd13cf2381dd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2096,7 +2096,8 @@ ports { usb2-0 { - mode = "host"; + mode = "otg"; + usb-role-switch; status = "okay"; port { hs_typec_p1: endpoint { @@ -2152,6 +2153,14 @@ }; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-0"; + }; + usb@3610000 { status = "okay"; @@ -2238,6 +2247,7 @@ i2c@c240000 { status = "okay"; + typec@8 { compatible = "cypress,cypd4226"; reg = <0x08>; @@ -2245,22 +2255,27 @@ interrupts = ; firmware-name = "nvidia,jetson-agx-xavier"; status = "okay"; + #address-cells = <1>; #size-cells = <0>; + ccg_typec_con0: connector@0 { compatible = "usb-c-connector"; reg = <0>; label = "USB-C"; data-role = "host"; + ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; hs_ucsi_ccg_p0: endpoint { remote-endpoint = <&hs_typec_p0>; }; }; + port@1 { reg = <1>; ss_ucsi_ccg_p0: endpoint { @@ -2269,20 +2284,24 @@ }; }; }; + ccg_typec_con1: connector@1 { compatible = "usb-c-connector"; reg = <1>; label = "USB-C"; data-role = "dual"; + ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; hs_ucsi_ccg_p1: endpoint { remote-endpoint = <&hs_typec_p1>; }; }; + port@1 { reg = <1>; ss_ucsi_ccg_p1: endpoint { @@ -2324,11 +2343,7 @@ }; pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; + cooling-levels = <66 215 255>; }; serial { @@ -2336,9 +2351,8 @@ }; sound { - status = "okay"; - compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; dais = /* ADMAIF (FE) Ports */ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, @@ -2415,4 +2429,20 @@ "CVB-RT DMIC1", "CVB-RT MIC", "CVB-RT DMIC2", "CVB-RT MIC"; }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index 022a5408d869..d94147f22ebf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -33,6 +33,12 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + #cooling-cells = <2>; + }; + vdd_1v8_sys: regulator-vdd-1v8-sys { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_SYS"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts new file mode 100644 index 000000000000..43d797e5544f --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include "tegra234-p3701-0008.dtsi" +#include "tegra234-p3740-0002.dtsi" + +/ { + model = "NVIDIA IGX Orin Development Kit"; + compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234"; + + aliases { + serial0 = &tcu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bus@0 { + host1x@13e00000 { + nvdec@15480000 { + status = "okay"; + }; + }; + + pcie@140e0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_4>, <&p2u_gbe_5>; + phy-names = "p2u-0", "p2u-1"; + }; + + pcie@14100000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>, + <&p2u_hsio_4>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + + pcie@141e0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; + }; + + aconnect@2900000 { + status = "okay"; + }; + + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + status = "okay"; + }; + + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + }; + + i2c@3190000 { + status = "okay"; + }; + + i2c@31b0000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + + }; + + i2c@31e0000 { + status = "okay"; + }; + + spi@3270000 { + status = "okay"; + }; + + hda@3510000 { + nvidia,model = "NVIDIA IGX HDA"; + status = "okay"; + }; + + fuse@3810000 { + status = "okay"; + }; + + i2c@c240000 { + status = "okay"; + }; + + i2c@c250000 { + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi new file mode 100644 index 000000000000..c95063b19321 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3740-0002"; + + bus@0 { + i2c@31c0000 { + /* carrier board ID EEPROM */ + eeprom@55 { + compatible = "atmel,24c02"; + reg = <0x55>; + + label = "system"; + vcc-supply = <&vdd_1v8_ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + padctl@3520000 { + vclamp-usb-supply = <&vdd_1v8_ao>; + avdd-usb-supply = <&vdd_3v3_ao>; + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + usb-role-switch; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-2 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-0"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi new file mode 100644 index 000000000000..232fa95ef4ae --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234-p3767.dtsi" + +/ { + compatible = "nvidia,p3767-0005", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin Nano"; + + bus@0 { + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin Nano HDA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index bd60478fa75e..a8aa6e7d8fbc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -99,73 +99,23 @@ }; thermal-zones { - /* - * This monitoring is far from optimal, but it's good enough - * at this stage. - */ - cpu-thermal { + tj-thermal { polling-delay = <1000>; polling-delay-passive = <1000>; status = "okay"; trips { - critical { - temperature = <104500>; - hysteresis = <0>; - type = "critical"; + tj_trip_active0: active-0 { + temperature = <74000>; + hysteresis = <4000>; + type = "active"; }; - hot { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - - board_trip_passive: passive { + tj_trip_active1: active-1 { temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - board_trip_active2: active-2 { - temperature = <80000>; hysteresis = <4000>; type = "active"; }; - - board_trip_active1: active-1 { - temperature = <65000>; - hysteresis = <4000>; - type = "active"; - }; - - board_trip_active0: active-0 { - temperature = <50000>; - hysteresis = <4000>; - type = "active"; - }; - }; - - cooling-maps { - passive { - cooling-device = <&fan 3 3>; - trip = <&board_trip_passive>; - }; - - active2 { - cooling-device = <&fan 2 3>; - trip = <&board_trip_active2>; - }; - - active1 { - cooling-device = <&fan 1 2>; - trip = <&board_trip_active1>; - }; - - active0 { - cooling-device = <&fan 0 1>; - trip = <&board_trip_active0>; - }; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts index 7dfbc38eb3c4..65e4b51b79c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -112,11 +112,8 @@ }; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; + pwm-fan { + cooling-levels = <0 187 255>; }; vdd_3v3_pcie: regulator-vdd-3v3-pcie { @@ -131,4 +128,20 @@ serial { status = "okay"; }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts new file mode 100644 index 000000000000..9b86aa6f7dbe --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include + +#include "tegra234-p3767-0005.dtsi" +#include "tegra234-p3768-0000.dtsi" + +/ { + compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin Nano Developer Kit"; + + pwm-fan { + cooling-levels = <0 187 255>; + }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi index aee21428e1a5..c7291ba27cfa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi @@ -119,7 +119,7 @@ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; - phy-names = "usb2-0", "usb3-1"; + phy-names = "usb2-0", "usb3-0"; }; usb@3610000 { @@ -209,7 +209,6 @@ fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm3 0 45334>; - cooling-levels = <0 95 178 255>; #cooling-cells = <2>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 18b4c2b2c42c..f4974e81dd4b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra234"; @@ -108,6 +109,12 @@ interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 164>; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra234-pinmux"; + reg = <0x0 0x2430000 0x0 0x19100>; }; gpcdma: dma-controller@2600000 { @@ -1749,6 +1756,12 @@ interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux_aon 0 0 32>; + }; + + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra234-pinmux-aon"; + reg = <0x0 0xc300000 0x0 0x4000>; }; pwm4: pwm@c340000 { @@ -3015,6 +3028,11 @@ #address-cells = <1>; #size-cells = <0>; }; + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; }; cpus { @@ -3028,6 +3046,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3044,6 +3065,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3060,6 +3084,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3076,6 +3103,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3092,6 +3122,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3108,6 +3141,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3124,6 +3160,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3140,6 +3179,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3156,6 +3198,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3172,6 +3217,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3188,6 +3236,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3204,6 +3255,9 @@ enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3469,6 +3523,53 @@ <&bpmp TEGRA234_CLK_PLLA_OUT0>; }; + thermal-zones { + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; + status = "disabled"; + }; + + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; + status = "disabled"; + }; + + cv0-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; + status = "disabled"; + }; + + cv1-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; + status = "disabled"; + }; + + cv2-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; + status = "disabled"; + }; + + soc0-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; + status = "disabled"; + }; + + soc1-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; + status = "disabled"; + }; + + soc2-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; + status = "disabled"; + }; + + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; + status = "disabled"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -3478,4 +3579,244 @@ interrupt-parent = <&gic>; always-on; }; + + cl0_opp_tbl: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + cl0_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl0_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl0_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl0_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; + + cl1_opp_tbl: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + cl1_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl1_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl1_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl1_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; + + cl2_opp_tbl: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + cl2_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl2_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl2_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl2_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d42c59572ace..337abc4ceb17 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,15 +1,22 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb @@ -32,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb @@ -82,6 +90,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb @@ -140,6 +149,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb @@ -173,7 +184,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 59860a2223b8..f3d65a606194 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -18,8 +18,10 @@ compatible = "qcom,apq8016-sbc", "qcom,apq8016"; aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart1; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + serial1 = &blsp_uart1; usid0 = &pm8916_0; i2c0 = &blsp_i2c2; i2c1 = &blsp_i2c6; @@ -75,7 +77,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -101,13 +103,13 @@ button { label = "Volume Up"; linux,code = ; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; }; }; leds { pinctrl-names = "default"; - pinctrl-0 = <&msmgpio_leds>, + pinctrl-0 = <&tlmm_leds>, <&pm8916_gpios_leds>, <&pm8916_mpps_leds>; @@ -117,7 +119,7 @@ label = "apq8016-sbc:green:user1"; function = LED_FUNCTION_HEARTBEAT; color = ; - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; @@ -126,7 +128,7 @@ label = "apq8016-sbc:green:user2"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; - gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; @@ -186,14 +188,14 @@ compatible = "adi,adv7533"; reg = <0x39>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; clocks = <&rpmcc RPM_SMD_BB_CLK2>; clock-names = "cec"; - pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; avdd-supply = <&pm8916_l6>; v1p2-supply = <&pm8916_l6>; @@ -211,7 +213,7 @@ port@0 { reg = <0>; adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -243,12 +245,12 @@ label = "LS-SPI0"; }; -&blsp1_uart1 { +&blsp_uart1 { status = "okay"; label = "LS-UART0"; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; label = "LS-UART1"; }; @@ -276,8 +278,8 @@ compatible = "ovti,ov5640"; reg = <0x3b>; - enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; - reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&camera_rear_default>; @@ -301,12 +303,11 @@ }; }; -&dsi0_out { - data-lanes = <0 1 2 3>; - remote-endpoint = <&adv7533_in>; +&lpass { + status = "okay"; }; -&lpass { +&lpass_codec { status = "okay"; }; @@ -314,40 +315,78 @@ status = "okay"; }; +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + &mpss { status = "okay"; firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn"; }; +&pm8916_codec { + status = "okay"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +}; + &pm8916_resin { status = "okay"; linux,code = ; }; +&pm8916_rpm_regulators { + /* + * The 96Boards specification expects a 1.8V power rail on the low-speed + * expansion connector that is able to provide at least 0.18W / 100 mA. + * L15/L16 are connected in parallel to provide 55 mA each. A minimum load + * must be specified to ensure the regulators are not put in LPM where they + * would only provide 5 mA. + */ + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &sound { status = "okay"; - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; pinctrl-names = "default", "sleep"; model = "DB410c"; audio-routing = @@ -370,7 +409,7 @@ sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; }; }; @@ -380,7 +419,7 @@ sound-dai = <&lpass MI2S_TERTIARY>; }; codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; }; }; }; @@ -398,13 +437,6 @@ extcon = <&usb_id>; }; -&wcd_codec { - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; -}; - &wcnss { status = "okay"; firmware-name = "qcom/apq8016/wcnss.mbn"; @@ -441,130 +473,19 @@ &stm { status = "okay"; }; &tpiu { status = "okay"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l5 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l10 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l11 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l13 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l14 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - l15 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-always-on; - }; - - l16 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l17 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l18 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; -}; - /* * 2mA drive strength is not enough when connecting multiple * I2C devices with different pull up resistors. */ -&i2c2_default { +&blsp_i2c2_default { drive-strength = <16>; }; -&i2c4_default { +&blsp_i2c4_default { drive-strength = <16>; }; -&i2c6_default { +&blsp_i2c6_default { drive-strength = <16>; }; @@ -592,7 +513,7 @@ * ones actually used for GPIO. */ -&msmgpio { +&tlmm { gpio-line-names = "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ @@ -717,7 +638,14 @@ "USR_LED_2_CTRL", /* GPIO 120 */ "SB_HS_ID"; - msmgpio_leds: msmgpio-leds-state { + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tlmm_leds: tlmm-leds-state { pins = "gpio21", "gpio120"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts new file mode 100644 index 000000000000..40644c242fb7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include +#include +#include + +/ { + model = "Square, Inc. T2 Devkit"; + compatible = "square,apq8039-t2", "qcom,msm8939"; + + qcom,board-id = <0x53 0x54>; + qcom,msm-id = ; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + }; + + bl: backlight { + compatible = "gpio-backlight"; + pinctrl-0 = <&pinctrl_backlight>; + pinctrl-names = "default"; + gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + vreg_lcd_avdd_reg: lcd-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avdd"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-0 = <&pinctrl_lcd_avdd_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + vreg_lcd_avee_reg: lcd-avee-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avee"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-0 = <&pinctrl_lcd_avee_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + vreg_lcd_iovcc_reg: lcd-iovcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_iovcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-0 = <&pinctrl_lcd_iovcc_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; +}; + +&blsp_i2c1 { + status = "okay"; +}; + +&blsp_i2c2 { + status = "okay"; +}; + +&blsp_i2c3 { + status = "okay"; + + typec_pd: usb-pd@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + pinctrl-names = "default"; + pinctrl-0 = <&typec_irq>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + typec_ep: endpoint { + remote-endpoint = <&otg_ep>; + }; + }; + }; + }; +}; + +&blsp_i2c5 { + status = "okay"; +}; + +&blsp_uart1 { + status = "okay"; +}; + +&blsp_uart1_default { + pins = "gpio0", "gpio1"; +}; + +&blsp_uart1_sleep { + pins = "gpio0", "gpio1"; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&lpass_codec { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8916_codec { + qcom,hphl-jack-type-normally-open; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "PM_GPIO1", /* WIFI_GPIO1_PRE */ + "PM_GPIO2", /* WIFI_GPIO2_PRE */ + "PM_GPIO3", + "PM_GPIO4"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sound { + model = "apq8039-square-sndcard"; + audio-routing = "AMIC2", "MIC BIAS Internal2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cdc_pdm_default>; + pinctrl-1 = <&cdc_pdm_sleep>; + + internal-codec-playback-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + internal-codec-capture-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +/* + * Line names are taken from the schematic of T2, Ver X03. + * July 14, 2018. Page 4 in particular. + */ +&tlmm { + gpio-line-names = + "APQ_UART1_TX", /* GPIO_0 */ + "APQ_UART1_RX", + "APQ_I2C1_SDA", + "APQ_I2C1_SCL", + "APQ_UART2_TX_1V8", + "APQ_UART2_RX_1V8", + "APQ_I2C2_SDA", + "APQ_I2C2_SCL", + "NC", + "APQ_LCD_IOVCC_EN", + "APQ_I2C3_SDA", /* GPIO_10 */ + "APQ_I2C3_SCL", + "TOUCH_RST_1V8_L", + "NC", + "APQ_I2C4_SDA", + "APQ_I2C4_SCL", + "APQ_ID5", + "USB_DISCONNECT", + "APQ_I2C5_SDA", + "APQ_I2C5_SCL", + "APQ_USBC_SPI_MOSI", /* GPIO_20 */ + "APQ_USBC_SPI_MISO", + "APQ_USBC_SPI_SS_L", + "APQ_USBC_SPI_CLK", + "APQ_LCD_TE0", + "APQ_LCD_RST_L", + "NC", + "NC", + "ACCELEROMETER_INT1", + "APQ_CAM_I2C0_SDA", + "APQ_CAM_I2C0_SCL", /* GPIO_30 */ + "ACCELEROMETER_INT2", + "NC", + "NC", + "NC", + "APQ_K21_RST_1V8_L", + "NC", + "APQ_EDL_1V8", + "TP145", + "BT_SSBI", + "NC", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "BT_CTRL", + "BT_DAT", + "PWR_GPIO_IN", + "PWR_GPIO_OUT", /* GPIO_50 */ + "CARD_DET_MLB_L", + "HALL_SENSOR", + "TP63", + "TP64", + "TP65", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "APQ_K21_GPIO0_1V8", + "CDC_PDM_CLK", + "CDC_PDM_SYNC", + "CDC_PDM_TX", + "CDC_PDM_RX0", + "CDC_PDM_RX1", + "CDC_PDM_RX2", + "APQ_K21_GPIO1_1V8", + "NC", /* GPIO_70 */ + "APQ_HUB_SEL_1V8", + "APQ_K21_GPIO2_1V8", + "APQ_K21_GPIO3_1V8", + "APQ_ID0", + "APQ_ID1", + "APQ_ID2", + "APQ_ID3", + "APQ_ID4", + "APQ_HUB_SUSP_IND", + "BOOT_CONFIG_0", /* GPIO_80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "APQ_LCD_AVDD_EN", + "APQ_LCD_AVEE_EN", + "TP70", + "NC", + "APQ_DEBUG0", /* GPIO_90 */ + "APQ_DEBUG1", + "APQ_DEBUG2", + "APQ_DEBUG3", + "TP165", + "NC", + "APQ_LNA_PWR_EN", + "NC", + "APQ_LCD_BL_EN", + "NC", + "APQ_LCD_ID0", /* GPIO_100 */ + "APQ_LCD_ID1", + "USBC_GPIO5_1V8", + "NC", + "NC", + "NC", + "APQ_HUB_RST_1V8_L", + "USBC_I2C_IRQ_1V8_L", + "SPE_PWR_EN", + "NC", + "APQ_USB_ID", /* GPIO_110 */ + "APQ_EXT_BUCK_VSEL", + "APQ_USB_ID_OUT", + "NC", + "PRNT_RST_L", + "APQ_CRQ_I2C_RDY_1V8", + "TYPEC_RST_1V8_H", + "CHG_BACKPWR_EN", + "CHG_PROCHOT_L", + "NC", + "USBC_GPIO7_1V8", /* GPIO_120 */ + "NC"; + + pinctrl_backlight: backlight-state { + pins = "gpio98"; + function = "gpio"; + }; + + pinctrl_lcd_avdd_reg: lcd-avdd-reg-state { + pins = "gpio86"; + function = "gpio"; + }; + + pinctrl_lcd_avee_reg: lcd-avee-reg-state { + pins = "gpio87"; + function = "gpio"; + }; + + pinctrl_lcd_iovcc_reg: lcd-iovcc-reg-state { + pins = "gpio9"; + function = "gpio"; + }; + + pinctrl_lcd_rst: lcd-rst-state { + pins = "gpio25"; + function = "gpio"; + }; + + pinctrl_otg_default: otg-default-state { + function = "gpio"; + pins = "gpio17"; + output-high; + }; + + pinctrl_otg_device: otg-device-state { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + pinctrl_otg_host: otg-host-state { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + typec_irq: typec-irq-state { + function = "gpio"; + pins = "gpio107"; + bias-pull-up; + input-enable; + }; +}; + +&usb { + pinctrl-names = "default", "host", "device"; + pinctrl-0 = <&pinctrl_otg_default>; + pinctrl-1 = <&pinctrl_otg_host>; + pinctrl-2 = <&pinctrl_otg_device>; + pin-switch-delay-us = <100000>; + usb-role-switch; + status = "okay"; + + port { + otg_ep: endpoint { + remote-endpoint = <&typec_ep>; + }; + }; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3680"; +}; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index b599909c4463..537547b97459 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -208,25 +208,6 @@ status = "okay"; }; -&hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - &hsusb_phy1 { status = "okay"; @@ -251,6 +232,25 @@ status = "okay"; }; +&mdss_hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&mdss_hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; @@ -433,28 +433,28 @@ drive-strength = <2>; }; - hdmi_hpd_active: hdmi-hpd-active-state { + mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <16>; }; - hdmi_hpd_suspend: hdmi-hpd-suspend-state { + mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <2>; }; - hdmi_ddc_active: hdmi-ddc-active-state { + mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; bias-pull-up; }; - hdmi_ddc_suspend: hdmi-ddc-suspend-state { + mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; @@ -1043,7 +1043,7 @@ }; }; - hdmi-dai-link { + mdss_hdmi-dai-link { link-name = "HDMI"; cpu { sound-dai = <&q6afedai HDMI_RX>; @@ -1054,7 +1054,7 @@ }; codec { - sound-dai = <&hdmi 0>; + sound-dai = <&mdss_hdmi 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 71e0a500599c..ac6471d1db1f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -26,7 +26,7 @@ v1p05: v1p05-regulator { compatible = "regulator-fixed"; - reglator-name = "v1p05"; + regulator-name = "v1p05"; regulator-always-on; regulator-boot-on; @@ -38,7 +38,7 @@ v12_poe: v12-poe-regulator { compatible = "regulator-fixed"; - reglator-name = "v12_poe"; + regulator-name = "v12_poe"; regulator-always-on; regulator-boot-on; @@ -92,18 +92,18 @@ status = "okay"; }; -&hdmi { - status = "okay"; -}; - -&hdmi_phy { - status = "okay"; -}; - &mdss { status = "okay"; }; +&mdss_hdmi { + status = "okay"; +}; + +&mdss_hdmi_phy { + status = "okay"; +}; + &sdc2_state_on { cd-pins { pins = "gpio38"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts similarity index 100% rename from arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts rename to arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts new file mode 100644 index 000000000000..bcf3b31c20e3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP442 board device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3"; + compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_0_data_clk_pins: spi-0-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-down; + }; + + spi_0_cs_pins: spi-0-cs-state { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts new file mode 100644 index 000000000000..53c68d8c5e5d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP474 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; + compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default_state>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + gpio_keys_default_state: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index af4d97143bcf..8bfc2db44624 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -115,6 +115,16 @@ #size-cells = <2>; ranges; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz_mem: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x200000>; no-map; @@ -122,7 +132,7 @@ smem@4a800000 { compatible = "qcom,smem"; - reg = <0x0 0x4a800000 0x0 0x00100000>; + reg = <0x0 0x4a800000 0x0 0x100000>; no-map; hwlocks = <&tcsr_mutex 0>; @@ -135,6 +145,13 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qfprom: efuse@a4000 { + compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x721>; + #address-cells = <1>; + #size-cells = <1>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -219,6 +236,18 @@ status = "disabled"; }; + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index f531797f2619..7355f266742a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -91,6 +91,7 @@ firmware { scm { compatible = "qcom,scm-ipq6018", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; @@ -155,18 +156,28 @@ no-map; }; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz: memory@4a600000 { - reg = <0x0 0x4a600000 0x0 0x00400000>; + reg = <0x0 0x4a600000 0x0 0x400000>; no-map; }; smem_region: memory@4aa00000 { - reg = <0x0 0x4aa00000 0x0 0x00100000>; + reg = <0x0 0x4aa00000 0x0 0x100000>; no-map; }; q6_region: memory@4ab00000 { - reg = <0x0 0x4ab00000 0x0 0x05500000>; + reg = <0x0 0x4ab00000 0x0 0x5500000>; no-map; }; }; @@ -199,7 +210,7 @@ hwlocks = <&tcsr_mutex 0>; }; - soc: soc { + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x0 0xffffffff>; @@ -302,7 +313,14 @@ status = "disabled"; }; - prng: qrng@e1000 { + qfprom: efuse@a4000 { + compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a4000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + prng: qrng@e3000 { compatible = "qcom,prng-ee"; reg = <0x0 0x000e3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; @@ -441,7 +459,6 @@ #size-cells = <0>; reg = <0x0 0x078b5000 0x0 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -456,7 +473,6 @@ #size-cells = <0>; reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -572,7 +588,7 @@ #address-cells = <2>; #size-cells = <2>; interrupt-controller; - #interrupt-cells = <0x3>; + #interrupt-cells = <3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5b2c1986c8f4..68839acbd613 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -29,8 +29,8 @@ }; cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; @@ -86,29 +86,40 @@ #size-cells = <2>; ranges; + bootloader@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + + sbl@4aa00000 { + reg = <0x0 0x4aa00000 0x0 0x100000>; + no-map; + }; + smem@4ab00000 { compatible = "qcom,smem"; - reg = <0x0 0x4ab00000 0x0 0x00100000>; + reg = <0x0 0x4ab00000 0x0 0x100000>; no-map; hwlocks = <&tcsr_mutex 0>; }; memory@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x400000>; no-map; - reg = <0x0 0x4ac00000 0x0 0x00400000>; }; }; firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; @@ -322,9 +333,9 @@ interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 70>; - #gpio-cells = <0x2>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; serial_4_pins: serial4-state { pins = "gpio23", "gpio24"; @@ -382,6 +393,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq8074", "syscon"; + reg = <0x01937000 0x21000>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, @@ -476,7 +492,6 @@ #size-cells = <0>; reg = <0x078b5000 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -534,6 +549,20 @@ status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; @@ -667,7 +696,7 @@ #address-cells = <1>; #size-cells = <1>; interrupt-controller; - #interrupt-cells = <0x3>; + #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; ranges = <0 0xb00a000 0xffd>; @@ -904,6 +933,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 4>; + + trips { + nss-top-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; nss0-thermal { @@ -911,6 +948,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 5>; + + trips { + nss-0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; nss1-thermal { @@ -918,6 +963,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 6>; + + trips { + nss-1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phya0-thermal { @@ -925,6 +978,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 7>; + + trips { + wcss-phya0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phya1-thermal { @@ -932,6 +993,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 8>; + + trips { + wcss-phya1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu0_thermal: cpu0-thermal { @@ -939,6 +1008,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 9>; + + trips { + cpu0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu1_thermal: cpu1-thermal { @@ -946,6 +1023,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 10>; + + trips { + cpu1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu2_thermal: cpu2-thermal { @@ -953,6 +1038,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 11>; + + trips { + cpu2-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu3_thermal: cpu3-thermal { @@ -960,6 +1053,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 12>; + + trips { + cpu3-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cluster_thermal: cluster-thermal { @@ -967,6 +1068,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 13>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phyb0-thermal { @@ -974,6 +1083,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 14>; + + trips { + wcss-phyb0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phyb1-thermal { @@ -981,6 +1098,14 @@ polling-delay = <1000>; thermal-sensors = <&tsens 15>; + + trips { + wcss-phyb1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts new file mode 100644 index 000000000000..2b093e02637b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP418 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; + compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts similarity index 67% rename from arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts rename to arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 2c8430197ec0..2b3ed8d351f7 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * IPQ9574 AL02-C7 board device tree source + * IPQ9574 RDP433 board device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. @@ -29,6 +29,25 @@ status = "okay"; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts new file mode 100644 index 000000000000..c8fa54e1a62c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP449 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6"; + compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts new file mode 100644 index 000000000000..f01de6628c3b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP453 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; + compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts new file mode 100644 index 000000000000..6efae3426cb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP454 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 0ed19fbf7d87..f120c7c52351 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,8 +6,9 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ -#include +#include #include +#include #include / { @@ -16,12 +17,6 @@ #size-cells = <2>; clocks { - bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { - compatible = "fixed-clock"; - clock-frequency = <353000000>; - #clock-cells = <0>; - }; - sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -43,6 +38,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -51,6 +50,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -59,6 +62,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -67,6 +74,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -76,12 +87,60 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq9574", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + memory@40000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupts = ; @@ -97,10 +156,39 @@ #size-cells = <2>; ranges; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz_region: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x400000>; no-map; }; + + smem@4aa00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4aa00000 0x0 0x100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; }; soc: soc@0 { @@ -109,6 +197,55 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; + #address-cells = <1>; + #size-cells = <1>; + }; + + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0073a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; @@ -132,7 +269,7 @@ reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <&bias_pll_ubi_nc_clk>, + <0>, <0>, <0>, <0>, @@ -143,6 +280,17 @@ #power-domain-cells = <1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq9574", "syscon"; + reg = <0x01937000 0x21000>; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; @@ -160,6 +308,36 @@ status = "disabled"; }; + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x2b000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; @@ -170,17 +348,174 @@ status = "disabled"; }; + blsp1_uart3: serial@78b2000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b2000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart4: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b3000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart5: serial@78b4000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b4000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi1: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 18>, <&blsp_dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi3: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 18>, <&blsp_dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi4: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ - <0x0b002000 0x1000>, /* GICC */ + <0x0b002000 0x2000>, /* GICC */ <0x0b001000 0x1000>, /* GICH */ - <0x0b004000 0x1000>; /* GICV */ + <0x0b004000 0x2000>; /* GICV */ #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <3>; - interrupts = ; + interrupts = ; ranges = <0 0x0b00c000 0x3000>; v2m0: v2m@0 { @@ -202,6 +537,32 @@ }; }; + watchdog: watchdog@b017000 { + compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + timeout-sec = <30>; + }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq9574-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a73pll>, <&xo_board_clk>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a73pll: clock@b116000 { + compatible = "qcom,ipq9574-a73pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board_clk>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; @@ -261,6 +622,214 @@ }; }; + thermal-zones { + nss-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + ubi_0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + ubi_1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + ubi_2-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + ubi_3-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wcss-phyb-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + wcss_phyb-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top_glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 13cd9ad167df..5ad49fe999db 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -22,7 +22,9 @@ chassis-type = "tablet"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -39,14 +41,14 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -58,7 +60,7 @@ accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -89,10 +91,10 @@ compatible = "edt,edt-ft5406"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l16>; iovcc-supply = <&pm8916_l6>; @@ -105,7 +107,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -114,24 +116,32 @@ status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - status = "okay"; }; &sdhc_2 { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -153,110 +163,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; @@ -273,6 +180,13 @@ bias-pull-up; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { reset-pins { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index fecb69944cfa..1c43f3d6a0b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -13,7 +13,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -30,7 +32,7 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -42,7 +44,7 @@ pinctrl-0 = <&gpio_leds_default>; led-0 { - gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; linux,default-trigger = "torch"; function = LED_FUNCTION_TORCH; }; @@ -50,13 +52,13 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -66,9 +68,9 @@ touchscreen@26 { compatible = "mstar,msg2638"; reg = <0x26>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ts_int_reset_default>; vdd-supply = <&pm8916_l17>; @@ -86,7 +88,7 @@ reg = <0x0c>; vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 8 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; mount-matrix = "0", "1", "0", @@ -99,7 +101,7 @@ reg = <0x0f>; vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <31 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&accel_int_default>; @@ -111,7 +113,7 @@ proximity@48 { compatible = "sensortek,stk3310"; reg = <0x48>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&proximity_int_default>; @@ -122,7 +124,7 @@ reg = <0x68>; vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <97 IRQ_TYPE_EDGE_RISING>, <98 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -136,7 +138,7 @@ led-controller@68 { compatible = "si-en,sn3190"; reg = <0x68>; - shutdown-gpios = <&msmgpio 89 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&led_enable_default &led_shutdown_default>; #address-cells = <1>; @@ -156,26 +158,29 @@ linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -195,110 +200,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio31"; function = "gpio"; @@ -370,6 +272,13 @@ bias-pull-up; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + ts_int_reset_default: ts-int-reset-default-state { pins = "gpio13", "gpio100"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 91284a1d0966..92f695481769 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -13,7 +13,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -30,14 +32,14 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <15>; }; button-volume-down { label = "Volume Down"; - gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <15>; }; @@ -49,7 +51,7 @@ regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - gpio = <&msmgpio 87 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <200>; @@ -60,7 +62,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpios = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -76,7 +78,7 @@ vdd-supply = <&pm8916_l8>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 112 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 112 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -86,7 +88,7 @@ compatible = "invensense,mpu6515"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <36 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -108,10 +110,10 @@ compatible = "edt,edt-ft5306"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l11>; iovcc-supply = <&pm8916_l6>; @@ -124,16 +126,19 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { @@ -141,9 +146,9 @@ vmmc-supply = <®_sd_vmmc>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -163,110 +168,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio117"; function = "gpio"; @@ -299,6 +201,13 @@ bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { touch-pins { pins = "gpio13"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 525ec76efeeb..f4dbc515c47a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -14,7 +14,9 @@ chassis-type = "tablet"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -24,8 +26,8 @@ flash-led-controller { /* Actually qcom,leds-gpio-flash */ compatible = "sgmicro,sgm3140"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&camera_flash_default>; pinctrl-names = "default"; @@ -45,7 +47,7 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -59,21 +61,21 @@ led-red { function = LED_FUNCTION_CHARGING; color = ; - gpios = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; retain-state-suspended; }; led-green { function = LED_FUNCTION_CHARGING; color = ; - gpios = <&msmgpio 118 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 118 GPIO_ACTIVE_HIGH>; retain-state-suspended; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; @@ -87,10 +89,10 @@ compatible = "edt,edt-ft5406"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l17>; iovcc-supply = <&pm8916_l6>; @@ -105,7 +107,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -114,24 +116,27 @@ status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; pinctrl-names = "default", "sleep"; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -153,110 +158,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; function = "gpio"; @@ -278,6 +180,13 @@ bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { reset-pins { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 5b1bac8f5122..4239c8fda11b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -26,7 +26,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -43,7 +45,7 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -55,21 +57,21 @@ pinctrl-0 = <&gpio_leds_default>; led-0 { - gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; }; led-1 { - gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; }; led-2 { - gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -78,7 +80,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -94,7 +96,7 @@ vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -104,7 +106,7 @@ compatible = "kionix,kx023-1025"; reg = <0x1e>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -122,7 +124,7 @@ compatible = "avago,apds9930"; reg = <0x39>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <113 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8916_l17>; @@ -146,7 +148,7 @@ regulator-name = "outp"; regulator-min-microvolt = <5400000>; regulator-max-microvolt = <5400000>; - enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>; regulator-active-discharge = <1>; }; @@ -154,7 +156,7 @@ regulator-name = "outn"; regulator-min-microvolt = <5400000>; regulator-max-microvolt = <5400000>; - enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; regulator-active-discharge = <1>; }; }; @@ -169,7 +171,7 @@ #address-cells = <1>; #size-cells = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8916_l17>; @@ -199,18 +201,18 @@ compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; reg = <0x28>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&nfc_default>; }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -218,32 +220,57 @@ status = "okay"; }; +&lpass_codec { + status = "okay"; +}; + +&pm8916_codec { + status = "okay"; + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + +&pm8916_l8 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; +}; + &pm8916_resin { status = "okay"; linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; /* - * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>. + * The Huawei device tree sets cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>. * However, gpio38 does not change its state when inserting/removing the * SD card, it's just low all the time. The Huawei kernel seems to use * polling for SD card detection instead. @@ -255,7 +282,7 @@ * Maybe Huawei decided to replace the second SIM card slot with the * SD card slot and forgot to re-route to gpio38. */ - cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; }; &sound { @@ -268,8 +295,8 @@ "AMIC3", "MIC BIAS External1"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cdc_pdm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus>; + pinctrl-0 = <&cdc_pdm_default>; + pinctrl-1 = <&cdc_pdm_sleep>; primary-dai-link { link-name = "WCD"; @@ -277,7 +304,7 @@ sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; }; }; @@ -287,7 +314,7 @@ sound-dai = <&lpass MI2S_TERTIARY>; }; codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; }; }; }; @@ -301,13 +328,6 @@ extcon = <&usb_id>; }; -&wcd_codec { - qcom,micbias-lvl = <2800>; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; - qcom,hphl-jack-type-normally-open; -}; - &wcnss { status = "okay"; }; @@ -316,110 +336,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_irq_default: accel-irq-default-state { pins = "gpio115"; function = "gpio"; @@ -476,7 +393,7 @@ bias-disable; }; - sdhc2_cd_default: sdhc2-cd-default-state { + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio56"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index f1dd625e1822..97262b8519b3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -14,7 +14,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -41,7 +43,7 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -53,7 +55,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -62,8 +64,8 @@ flash-led-controller { compatible = "sgmicro,sgm3140"; - flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&camera_flash_default>; @@ -122,7 +124,7 @@ * to the BMC156. However, there are two pads next to the chip * that can be shorted to make it work if needed. * - * interrupt-parent = <&msmgpio>; + * interrupt-parent = <&tlmm>; * interrupts = <116 IRQ_TYPE_EDGE_RISING>; */ @@ -141,7 +143,7 @@ compatible = "bosch,bmc156_magn"; reg = <0x12>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <113 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -156,7 +158,7 @@ reg = <0x23>; proximity-near-level = <75>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -170,7 +172,7 @@ compatible = "bosch,bmg160"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <23 IRQ_TYPE_EDGE_RISING>, <22 IRQ_TYPE_EDGE_RISING>; @@ -191,7 +193,7 @@ #address-cells = <1>; #size-cells = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <®_ctp>; @@ -214,7 +216,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -223,6 +225,13 @@ linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_usbin { status = "okay"; }; @@ -233,19 +242,10 @@ &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; }; @@ -267,110 +267,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio116"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index b79e80913af9..9757182fba3e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -13,13 +13,30 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { stdout-path = "serial0"; }; + flash-led-controller { + compatible = "ocs,ocp8110"; + enable-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&camera_front_flash_default>; + pinctrl-names = "default"; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -30,7 +47,7 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -39,7 +56,7 @@ compatible = "gpio-leds"; led-0 { - gpios = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_KBD_BACKLIGHT; @@ -51,7 +68,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -67,7 +84,7 @@ vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -86,7 +103,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -95,26 +112,29 @@ linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -134,110 +154,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { button_backlight_default: button-backlight-default-state { pins = "gpio17"; function = "gpio"; @@ -246,6 +163,13 @@ bias-disable; }; + camera_front_flash_default: camera-front-flash-default-state { + pins = "gpio49", "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -262,6 +186,13 @@ bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index 7c0ceb3cff45..438eb1faee1d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -12,7 +12,7 @@ compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; usid0 = &pm8916_0; }; @@ -21,6 +21,6 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi deleted file mode 100644 index 33dfcf318a81..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ /dev/null @@ -1,582 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - blsp1_uart1_default: blsp1-uart1-default-state { - /* TX, RX, CTS_N, RTS_N */ - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart1_sleep: blsp1-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp1_uart2_default: blsp1-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep-state { - pins = "gpio4", "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi1_default: spi1-default-state { - spi-pins { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio2"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi1_sleep: spi1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi2_default: spi2-default-state { - spi-pins { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio6"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi2_sleep: spi2-sleep-state { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi3_default: spi3-default-state { - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio10"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi3_sleep: spi3-sleep-state { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi4_default: spi4-default-state { - spi-pins { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio14"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi4_sleep: spi4-sleep-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi5_default: spi5-default-state { - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio18"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi6_default: spi6-default-state { - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio22"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi6_sleep: spi6-sleep-state { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - i2c1_default: i2c1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c2_default: i2c2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c3_default: i2c3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - - drive-strength = <2>; - bias-disable; - }; - - i2c3_sleep: i2c3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c4_default: i2c4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - - drive-strength = <2>; - bias-disable; - }; - - i2c4_sleep: i2c4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c5_default: i2c5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - pmx-sdc1-clk-state { - sdc1_clk_on: clk-on-pins { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <16>; - }; - sdc1_clk_off: clk-off-pins { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc1-cmd-state { - sdc1_cmd_on: cmd-on-pins { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc1_cmd_off: cmd-off-pins { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc1-data-state { - sdc1_data_on: data-on-pins { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc1_data_off: data-off-pins { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-clk-state { - sdc2_clk_on: clk-on-pins { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <16>; - }; - sdc2_clk_off: clk-off-pins { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc2-cmd-state { - sdc2_cmd_on: cmd-on-pins { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc2_cmd_off: cmd-off-pins { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-data-state { - sdc2_data_on: data-on-pins { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc2_data_off: data-off-pins { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-cd-pin-state { - sdc2_cd_on: cd-on-pins { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - sdc2_cd_off: cd-off-pins { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - cdc-pdm-lines-state { - cdc_pdm_lines_act: pdm-lines-on-pins { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <8>; - bias-disable; - }; - cdc_pdm_lines_sus: pdm-lines-off-pins { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - - ext-pri-tlmm-lines-state { - ext_pri_tlmm_lines_act: ext-pa-on-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_pri_tlmm_lines_sus: ext-pa-off-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - ext-pri-ws-line-state { - ext_pri_ws_act: ext-pa-on-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <8>; - bias-disable; - }; - ext_pri_ws_sus: ext-pa-off-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <2>; - bias-disable; - }; - }; - - ext-mclk-tlmm-lines-state { - ext_mclk_tlmm_lines_act: mclk-lines-on-pins { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - /* secondary Mi2S */ - ext-sec-tlmm-lines-state { - ext_sec_tlmm_lines_act: tlmm-lines-on-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - cdc_dmic_lines_act: cdc-dmic-lines-on-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <8>; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <8>; - }; - }; - cdc_dmic_lines_sus: cdc-dmic-lines-off-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <2>; - bias-disable; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <2>; - bias-disable; - }; - }; - - wcnss_pin_a: wcnss-active-state { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - function = "wcss_wlan"; - - drive-strength = <6>; - bias-pull-up; - }; - - cci0_default: cci0-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c"; - - drive-strength = <16>; - bias-disable; - }; - - camera_front_default: camera-front-default-state { - pwdn-pins { - pins = "gpio33"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio28"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk1-pins { - pins = "gpio27"; - function = "cam_mclk1"; - - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera-rear-default-state { - pwdn-pins { - pins = "gpio34"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio35"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk0-pins { - pins = "gpio26"; - function = "cam_mclk0"; - - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 6eb5e0a39510..b1a7eafbee31 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -1,4 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only +/* + * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections) + * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC. + * Many regulators have a fixed purpose in the original reference design and + * were rarely re-used for different purposes. Devices that deviate from the + * typical reference design should not make use of this include and instead add + * the necessary properties in the board-specific device tree. + */ #include "msm8916.dtsi" #include "pm8916.dtsi" @@ -7,12 +15,12 @@ vdda-supply = <&pm8916_l2>; }; -&dsi0 { +&mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; }; -&dsi_phy0 { +&mdss_dsi0_phy { vddio-supply = <&pm8916_l6>; }; @@ -20,6 +28,12 @@ pll-supply = <&pm8916_l7>; }; +&pm8916_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + &sdhc_1 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -47,30 +61,97 @@ }; &rpm_requests { - smd_rpm_regulators: regulators { + pm8916_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; + pm8916_s3: s3 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; /* Needed for L2 */ + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; + regulator-always-on; /* Needed for L5/L7 */ + }; + + /* + * Some of the regulators are unused or managed by another + * processor (e.g. the modem). We should still define nodes for + * them to ensure the vote from the application processor can be + * dropped in case the regulators are already on during boot. + * + * The labels for these nodes are omitted on purpose because + * boards should configure a proper voltage before using them. + */ + l1 {}; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; /* Needed for LPDDR RAM */ + }; + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; + + l4 {}; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for most digital I/O */ + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for CPU PLL */ + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 {}; + + pm8916_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 {}; + l15 {}; + l16 {}; + l17 {}; + l18 {}; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 16d67749960e..019bf73178fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -8,7 +8,9 @@ / { aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -44,13 +46,13 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -65,7 +67,7 @@ event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -83,7 +85,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -96,7 +98,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -105,8 +107,8 @@ i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -118,7 +120,7 @@ compatible = "siliconmitus,sm5502-muic"; reg = <0x25>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -128,8 +130,8 @@ i2c-tkey { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&tkey_i2c_default>; @@ -142,7 +144,7 @@ compatible = "coreriver,tc360-touchkey"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <98 IRQ_TYPE_EDGE_FALLING>; /* vcc/vdd-supply are board-specific */ @@ -157,8 +159,8 @@ i2c-nfc { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&nfc_i2c_default>; @@ -170,11 +172,11 @@ compatible = "samsung,s3fwrn5-i2c"; reg = <0x27>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - en-gpios = <&msmgpio 20 GPIO_ACTIVE_LOW>; - wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + en-gpios = <&tlmm 20 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; @@ -200,7 +202,7 @@ accelerometer: accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -225,7 +227,7 @@ battery@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_BOTH>; pinctrl-names = "default"; @@ -233,41 +235,44 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; -&dsi0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_default>; - pinctrl-1 = <&mdss_sleep>; -}; - &mdss { status = "okay"; }; +&mdss_dsi0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; +}; + &pm8916_resin { status = "okay"; linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -279,110 +284,7 @@ extcon = <&muic>; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; @@ -485,6 +387,13 @@ bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index a1ca4d883420..e5a569698c4f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -15,7 +15,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -28,7 +28,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -41,7 +41,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -67,7 +67,7 @@ compatible = "zinitix,bt541"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <540>; @@ -85,7 +85,7 @@ status = "okay"; }; -&dsi0 { +&mdss_dsi0 { panel@0 { reg = <0>; @@ -93,17 +93,17 @@ vdd3-supply = <®_panel_vdd3>; vci-supply = <&pm8916_l17>; - reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { data-lanes = <0 1>; remote-endpoint = <&panel_in>; }; @@ -120,7 +120,7 @@ compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { panel_vdd3_default: panel-vdd3-default-state { pins = "gpio9"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 4e10b8a5e9f9..388482a1e3d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -15,7 +15,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -36,7 +36,7 @@ compatible = "melfas,mms345l"; reg = <0x48>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <720>; @@ -71,7 +71,7 @@ compatible = "qcom,wcn3660b"; }; -&msmgpio { +&tlmm { tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index f6c4a011fdfd..0cdd6af7817f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -18,7 +18,7 @@ compatible = "siliconmitus,sm5504-muic"; reg = <0x14>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -32,7 +32,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -66,7 +66,7 @@ compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index 4cbd68b89448..3f145dde4059 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -33,7 +33,7 @@ function = LED_FUNCTION_KBD_BACKLIGHT; color = ; - gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&gpio_leds_default>; @@ -42,14 +42,14 @@ }; ®_motor_vdd { - gpio = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; }; ®_touch_key { status = "disabled"; }; -&msmgpio { +&tlmm { gpio_leds_default: gpio-led-default-state { pins = "gpio60"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 74ffd04db8d8..7943bb619116 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -9,7 +9,9 @@ / { aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -34,13 +36,13 @@ volume-up-button { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; home-button { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -55,7 +57,7 @@ hall-sensor-switch { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -74,7 +76,7 @@ maxim,over-heat-temp = <600>; maxim,over-volt = <4400>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&fuelgauge_int_default>; @@ -97,7 +99,7 @@ vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l5>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "INT1"; @@ -111,7 +113,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -120,25 +122,28 @@ status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + /* FIXME: Replace with MAX77849 MUIC when driver is available */ &pm8916_usbin { status = "okay"; }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; pinctrl-names = "default", "sleep"; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -162,110 +167,7 @@ compatible = "qcom,wcn3660b"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; @@ -293,4 +195,11 @@ drive-strength = <2>; bias-disable; }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts index 607a5dc8a534..48111c6a2c78 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts @@ -25,7 +25,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <&motor_en_default>; @@ -38,7 +38,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <&tsp_en_default>; @@ -51,7 +51,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -71,20 +71,20 @@ touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <®_tsp_1p8v>; vdda-supply = <®_tsp_3p3v>; - reset-gpios = <&msmgpio 114 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; pinctrl-0 = <&tsp_int_rst_default>; pinctrl-names = "default"; }; }; -&msmgpio { +&tlmm { motor_en_default: motor-en-default-state { pins = "gpio76"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts index 5d6f8383306b..98ceaad7fcea 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts @@ -15,7 +15,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <®_tsp_en_default>; @@ -24,7 +24,7 @@ vibrator { compatible = "gpio-vibrator"; - enable-gpios = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&vibrator_en_default>; pinctrl-names = "default"; @@ -37,7 +37,7 @@ touchscreen@20 { compatible = "zinitix,bt532"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <768>; @@ -51,7 +51,7 @@ }; }; -&msmgpio { +&tlmm { reg_tsp_en_default: reg-tsp-en-default-state { pins = "gpio73"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index adeee0830e76..f4fd5d72b28b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -7,7 +7,9 @@ / { aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -32,7 +34,7 @@ event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -49,21 +51,21 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home Key"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; i2c_muic: i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -75,7 +77,7 @@ compatible = "siliconmitus,sm5703-muic"; reg = <0x25>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -84,7 +86,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -95,20 +97,16 @@ &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -128,110 +126,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { gpio_hall_sensor_default: gpio-hall-sensor-default-state { pins = "gpio52"; function = "gpio"; @@ -263,4 +158,11 @@ drive-strength = <2>; bias-disable; }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 1a41a4db874d..15dc246e84e2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -28,7 +28,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -53,13 +55,13 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -74,7 +76,7 @@ event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -87,7 +89,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -100,7 +102,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -113,7 +115,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -122,8 +124,8 @@ i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -135,7 +137,7 @@ compatible = "siliconmitus,sm5504-muic"; reg = <0x14>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -145,8 +147,8 @@ i2c-tkey { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&tkey_i2c_default>; @@ -158,7 +160,7 @@ compatible = "coreriver,tc360-touchkey"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <98 IRQ_TYPE_EDGE_FALLING>; vcc-supply = <®_touch_key>; @@ -174,8 +176,8 @@ i2c-nfc { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&nfc_i2c_default>; @@ -187,11 +189,11 @@ compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; reg = <0x2b>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&nfc_default>; @@ -206,7 +208,7 @@ compatible = "st,lsm6ds3"; reg = <0x6b>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -230,7 +232,7 @@ compatible = "richtek,rt5033-battery"; reg = <0x35>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -245,7 +247,7 @@ compatible = "zinitix,bt541"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <540>; @@ -259,7 +261,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -274,19 +276,10 @@ &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; /* @@ -320,110 +313,7 @@ compatible = "qcom,wcn3660b"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts index 82e260375174..6fe1850ba20e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts @@ -10,19 +10,19 @@ }; &button_restart { - gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; &led_r { - gpios = <&msmgpio 82 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 83 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 81 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; }; &button_default { diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts index 978f0abcdf8f..16d4a91022be 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -10,19 +10,19 @@ }; &button_restart { - gpios = <&msmgpio 37 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; }; &led_r { - gpios = <&msmgpio 22 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; }; &mpss { @@ -40,7 +40,7 @@ }; /* This selects the external SIM card slot by default */ -&msmgpio { +&tlmm { sim_ctrl_default: sim-ctrl-default-state { esim-sel-pins { pins = "gpio0", "gpio3"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 50bae6f214f1..004a129a2ee2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -9,7 +9,8 @@ chassis-type = "embedded"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + serial0 = &blsp_uart2; }; chosen { @@ -82,11 +83,11 @@ status = "okay"; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; -/* Remove &dsi_phy0 from clocks to make sure that gcc probes with display disabled */ +/* Remove &mdss_dsi0_phy from clocks to make sure that gcc probes with display disabled */ &gcc { clocks = <&xo_board>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>; }; @@ -100,16 +101,12 @@ }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; &usb { extcon = <&pm8916_usbin>; - dr_mode = "peripheral"; + usb-role-switch; status = "okay"; }; @@ -126,110 +123,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { /* pins are board-specific */ button_default: button-default-state { function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index ac56c7595f78..c94d36b38651 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -16,7 +16,9 @@ chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; }; chosen { @@ -25,8 +27,8 @@ flash-led-controller { compatible = "ocs,ocp8110"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&camera_flash_default>; @@ -47,14 +49,14 @@ button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -67,7 +69,7 @@ compatible = "invensense,mpu6880"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -90,10 +92,10 @@ compatible = "edt,edt-ft5506"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l17>; iovcc-supply = <&pm8916_l6>; @@ -140,7 +142,7 @@ }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; @@ -149,25 +151,32 @@ linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + /* + * L16 is only used for AW2013 which is fine with 2.5-3.3V. + * Use the recommended typical voltage of 2.8V as minimum. + */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; }; @@ -188,110 +197,7 @@ compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { +&tlmm { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts index 74ce6563be18..5e6ba8c58bb5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts @@ -10,19 +10,19 @@ }; &button_restart { - gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; }; &led_r { - gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; }; &button_default { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 834e0b66b7f2..7582c7d748fe 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -18,11 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - }; - chosen { }; memory@80000000 { @@ -993,15 +988,494 @@ }; }; - msmgpio: pinctrl@1000000 { + tlmm: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; - gpio-ranges = <&msmgpio 0 0 122>; + gpio-ranges = <&tlmm 0 0 122>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + blsp_i2c1_default: blsp-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c1_sleep: blsp-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_default: blsp-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_sleep: blsp-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_default: blsp-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_sleep: blsp-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_default: blsp-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_sleep: blsp-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_default: blsp-i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_sleep: blsp-i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_default: blsp-i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_sleep: blsp-i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_spi1_default: blsp-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi1_sleep: blsp-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi2_default: blsp-spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi2_sleep: blsp-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi3_default: blsp-spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi3_sleep: blsp-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi4_default: blsp-spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi4_sleep: blsp-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi5_default: blsp-spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi5_sleep: blsp-spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi6_default: blsp-spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi6_sleep: blsp-spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart1_default: blsp-uart1-default-state { + /* TX, RX, CTS_N, RTS_N */ + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart2_default: blsp-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart2_sleep: blsp-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio28"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk1-pins { + pins = "gpio27"; + function = "cam_mclk1"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins = "gpio34"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk0-pins { + pins = "gpio26"; + function = "cam_mclk0"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <8>; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <8>; + }; + }; + + cdc_dmic_sleep: cdc-dmic-sleep-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <2>; + bias-disable; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; + + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; + }; + + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcss_wlan_default: wcss-wlan-default-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; }; gcc: clock-controller@1800000 { @@ -1012,8 +1486,8 @@ reg = <0x01800000 0x80000>; clocks = <&xo_board>, <&sleep_clk>, - <&dsi_phy0 1>, - <&dsi_phy0 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, <0>, <0>, <0>; @@ -1062,7 +1536,7 @@ #size-cells = <1>; ranges; - mdp: display-controller@1a01000 { + mdss_mdp: display-controller@1a01000 { compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; @@ -1087,14 +1561,14 @@ port@0 { reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; }; }; }; }; - dsi0: dsi@1a98000 { + mdss_dsi0: dsi@1a98000 { compatible = "qcom,msm8916-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a98000 0x25c>; @@ -1105,8 +1579,8 @@ assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -1120,7 +1594,7 @@ "byte", "pixel", "core"; - phys = <&dsi_phy0>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -1131,20 +1605,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi_phy0: phy@1a98300 { + mdss_dsi0_phy: phy@1a98300 { compatible = "qcom,dsi-phy-28nm-lp"; reg = <0x01a98300 0xd4>, <0x01a98500 0x280>, @@ -1162,7 +1636,7 @@ }; }; - camss: camss@1b00000 { + camss: camss@1b0ac00 { compatible = "qcom,msm8916-camss"; reg = <0x01b0ac00 0x200>, <0x01b00030 0x4>, @@ -1520,20 +1994,20 @@ * Primary/Secondary MI2S both use the PRI_I2S_CLK. */ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; clock-names = "ahbix-clk", - "pcnoc-mport-clk", - "pcnoc-sway-clk", "mi2s-bit-clk0", "mi2s-bit-clk1", "mi2s-bit-clk2", - "mi2s-bit-clk3"; + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; #sound-dai-cells = <1>; interrupts = ; @@ -1552,9 +2026,10 @@ <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "ahbix-clk", "mclk"; #sound-dai-cells = <1>; + status = "disabled"; }; - sdhc_1: mmc@7824000 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc", "core"; @@ -1566,13 +2041,16 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; mmc-ddr-1_8v; bus-width = <8>; non-removable; status = "disabled"; }; - sdhc_2: mmc@7864000 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc", "core"; @@ -1584,6 +2062,9 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; bus-width = <4>; status = "disabled"; }; @@ -1598,7 +2079,7 @@ qcom,ee = <0>; }; - blsp1_uart1: serial@78af000 { + blsp_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; interrupts = ; @@ -1607,12 +2088,12 @@ dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; status = "disabled"; }; - blsp1_uart2: serial@78b0000 { + blsp_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b0000 0x200>; interrupts = ; @@ -1621,8 +2102,8 @@ dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; status = "disabled"; }; @@ -1636,8 +2117,8 @@ dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; + pinctrl-0 = <&blsp_i2c1_default>; + pinctrl-1 = <&blsp_i2c1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1653,8 +2134,8 @@ dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; + pinctrl-0 = <&blsp_spi1_default>; + pinctrl-1 = <&blsp_spi1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1670,8 +2151,8 @@ dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; + pinctrl-0 = <&blsp_i2c2_default>; + pinctrl-1 = <&blsp_i2c2_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1687,8 +2168,8 @@ dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; + pinctrl-0 = <&blsp_spi2_default>; + pinctrl-1 = <&blsp_spi2_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1704,8 +2185,8 @@ dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_default>; - pinctrl-1 = <&i2c3_sleep>; + pinctrl-0 = <&blsp_i2c3_default>; + pinctrl-1 = <&blsp_i2c3_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1721,8 +2202,8 @@ dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; + pinctrl-0 = <&blsp_spi3_default>; + pinctrl-1 = <&blsp_spi3_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1738,8 +2219,8 @@ dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; + pinctrl-0 = <&blsp_i2c4_default>; + pinctrl-1 = <&blsp_i2c4_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1755,8 +2236,8 @@ dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; + pinctrl-0 = <&blsp_spi4_default>; + pinctrl-1 = <&blsp_spi4_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1772,8 +2253,8 @@ dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; + pinctrl-0 = <&blsp_i2c5_default>; + pinctrl-1 = <&blsp_i2c5_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1789,8 +2270,8 @@ dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; + pinctrl-0 = <&blsp_spi5_default>; + pinctrl-1 = <&blsp_spi5_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1806,8 +2287,8 @@ dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; + pinctrl-0 = <&blsp_i2c6_default>; + pinctrl-1 = <&blsp_i2c6_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1823,8 +2304,8 @@ dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; + pinctrl-0 = <&blsp_spi6_default>; + pinctrl-1 = <&blsp_spi6_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1871,7 +2352,7 @@ }; }; - wcnss: remoteproc@a21b000 { + wcnss: remoteproc@a204000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -1893,7 +2374,7 @@ qcom,smem-state-names = "stop"; pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; + pinctrl-0 = <&wcss_wlan_default>; status = "disabled"; @@ -2190,5 +2671,3 @@ ; }; }; - -#include "msm8916-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi new file mode 100644 index 000000000000..adb96cd8d643 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * msm8939-pm8916.dtsi describes common properties (e.g. regulator connections) + * that apply to most devices that make use of the MSM8939 SoC and PM8916 PMIC. + * Many regulators have a fixed purpose in the original reference design and + * were rarely re-used for different purposes. Devices that deviate from the + * typical reference design should not make use of this include and instead add + * the necessary properties in the board-specific device tree. + */ + +#include "msm8939.dtsi" +#include "pm8916.dtsi" + +&mdss_dsi0 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi0_phy { + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi1 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi1_phy { + vddio-supply = <&pm8916_l6>; +}; + +&mpss { + pll-supply = <&pm8916_l7>; +}; + +&pm8916_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + +&rpm_requests { + pm8916_rpm_regulators: regulators { + compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + /* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */ + /* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */ + pm8916_s3: s3 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; /* Needed for L2 */ + }; + pm8916_s4: s4 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; + regulator-always-on; /* Needed for L5/L7 */ + }; + + /* + * Some of the regulators are unused or managed by another + * processor (e.g. the modem). We should still define nodes for + * them to ensure the vote from the application processor can be + * dropped in case the regulators are already on during boot. + * + * The labels for these nodes are omitted on purpose because + * boards should configure a proper voltage before using them. + */ + l1 {}; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; /* Needed for LPDDR RAM */ + }; + + /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */ + + l4 {}; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for most digital I/O */ + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for CPU PLL */ + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 {}; + + pm8916_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 {}; + l15 {}; + l16 {}; + l17 {}; + l18 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; +}; + +&sdhc_2 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; +}; + +&usb_hs_phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + +&wcnss { + vddpx-supply = <&pm8916_l7>; +}; + +&wcnss_iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts new file mode 100644 index 000000000000..8613cf93dac5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Bryan O'Donoghue. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include +#include + +/ { + model = "Sony Xperia M4 Aqua"; + compatible = "sony,kanuti-tulip", "qcom,msm8939"; + + qcom,board-id = ; + qcom,msm-id = , ; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&tlmm { + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi new file mode 100644 index 000000000000..895cafc11480 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -0,0 +1,2436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + /* + * Stock LK wants address-cells/size-cells = 2 + * A number of our drivers want address/size cells = 1 + * hence the disparity between top-level and /soc below. + */ + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x100>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x101>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU2: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x102>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU3: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x103>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU4: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x0>; + qcom,acc = <&acc4>; + qcom,saw = <&saw4>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x1>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc5>; + qcom,saw = <&saw5>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + CPU6: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x2>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc6>; + qcom,saw = <&saw6>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + CPU7: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x3>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc7>; + qcom,saw = <&saw7>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible ="qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + }; + + /* + * MSM8939 has a big.LITTLE heterogeneous computing architecture, + * consisting of two clusters of four ARM Cortex-A53s each. The + * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs + * at 1.5-1.7GHz. + * + * The enable method used here is spin-table which presupposes use + * of a 2nd stage boot shim such as lk2nd to have installed a + * spin-table, the downstream non-psci/non-spin-table method that + * default msm8916/msm8936/msm8939 will not be supported upstream. + */ + cpu-map { + /* LITTLE (efficiency) cluster */ + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + /* big (performance) cluster */ + /* Boot CPU is cluster 1 core 0 */ + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8916", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@86680000 { + reg = <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + + qcom,client-id = <1>; + }; + + rfsa@867e0000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + wcnss_mem: wcnss@8bd00000 { + reg = <0x0 0x8bd00000 0x0 0x600000>; + no-map; + }; + + venus_mem: venus@8c300000 { + reg = <0x0 0x8c300000 0x0 0x800000>; + no-map; + }; + + mba_mem: mba@8cb00000 { + reg = <0x0 0x8cb00000 0x0 0x100000>; + no-map; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs1_mbox 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8936"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8939-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + smp2p-hexagon { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs1_mbox 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = ; + + mboxes = <&apcs1_mbox 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs1_mbox 8 13>; + qcom,ipc-3 = <&apcs1_mbox 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@a0 { + reg = <0xa0 0x1>; + bits = <0 8>; + }; + + tsens_s6_p1: s6-p1@a1 { + reg = <0xa1 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@a1 { + reg = <0xa1 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@a2 { + reg = <0xa2 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@a3 { + reg = <0xa3 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@a4 { + reg = <0xa4 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@a4 { + reg = <0xa4 0x2>; + bits = <6 6>; + }; + + tsens_s9_p1: s9-p1@a5 { + reg = <0xa5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2: s9-p2@a6 { + reg = <0xa6 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@a7 { + reg = <0xa7 0x1>; + bits = <0 8>; + }; + + tsens_mode: mode@d0 { + reg = <0xd0 0x1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <3 6>; + }; + + tsens_s0_p2: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@d1 { + reg = <0xd1 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@d4 { + reg = <0xd4 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg = <0xd5 0x2>; + bits = <5 6>; + }; + + tsens_s5_p1: s5-p1@d6 { + reg = <0xd6 0x2>; + bits = <3 6>; + }; + + tsens_s5_p2: s5-p2@d7 { + reg = <0xd7 0x1>; + bits = <1 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8939-bimc"; + reg = <0x00400000 0x62000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + #interconnect-cells = <1>; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; + #qcom,sensors = <9>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8939-pcnoc"; + reg = <0x00500000 0x11000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + #interconnect-cells = <1>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8939-snoc"; + reg = <0x00580000 0x14080>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + #interconnect-cells = <1>; + + snoc_mm: interconnect-snoc { + compatible = "qcom,msm8939-snoc-mm"; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>, + <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; + #interconnect-cells = <1>; + }; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp_i2c1_default: blsp-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c1_sleep: blsp-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_default: blsp-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_sleep: blsp-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_default: blsp-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_sleep: blsp-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_default: blsp-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_sleep: blsp-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_default: blsp-i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_sleep: blsp-i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_default: blsp-i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_sleep: blsp-i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_spi1_default: blsp-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi1_sleep: blsp-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi2_default: blsp-spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi2_sleep: blsp-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi3_default: blsp-spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi3_sleep: blsp-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi4_default: blsp-spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi4_sleep: blsp-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi5_default: blsp-spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi5_sleep: blsp-spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi6_default: blsp-spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi6_sleep: blsp-spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart1_default: blsp-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart2_default: blsp-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart2_sleep: blsp-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst-pins { + pins = "gpio28"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + mclk1-pins { + pins = "gpio27"; + function = "cam_mclk1"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins = "gpio34"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + mclk0-pins { + pins = "gpio26"; + function = "cam_mclk0"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <8>; + }; + + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <8>; + }; + }; + + cdc_dmic_sleep: cdc-dmic-sleep-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <2>; + bias-disable; + }; + + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; + + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; + }; + + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcss_wlan_default: wcss-wlan-default-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8939"; + reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + interrupts = ; + interrupt-controller; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 4>; + + interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdss_mdp_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + + mdss_dsi1: dsi@1aa0000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01aa0000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks = <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + phys = <&mdss_dsi1_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@1aa0300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01aa0300 0xd4>, + <0x01aa0500 0x280>, + <0x01aa0780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-405.0", "qcom,adreno"; + reg = <0x01c00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + }; + + apps_iommu: iommu@1ef0000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + reg = <0x01ef0000 0x3000>; + ranges = <0 0x01e20000 0x40000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <17>; + + /* mdp_0: */ + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + /* venus_ns: */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GFX_TBU_CLK>; + clock-names = "iface", "bus", "tbu"; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <18>; + + /* gfx3d_user: */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + /* gfx3d_priv: */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil"; + reg = <0x04080000 0x100>, <0x04020000 0x040>; + reg-names = "qdsp6", "rmb"; + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "bus", + "mem", + "xo"; + power-domains = <&rpmpd MSM8939_VDDMDCX>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names = "cx", "mx"; + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + resets = <&scm 0>; + reset-names = "mss_restart"; + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = ; + + qcom,smd-edge = <0>; + mboxes = <&apcs1_mbox 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; + + sound: sound@7702000 { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, + <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + status = "disabled"; + }; + + lpass: audio-controller@7708000 { + compatible = "qcom,apq8016-lpass-cpu"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; + clock-names = "ahbix-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpass_codec: audio-codec@771c000 { + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + bus-width = <4>; + status = "disabled"; + }; + + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + + blsp_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c1_default>; + pinctrl-1 = <&blsp_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi1_default>; + pinctrl-1 = <&blsp_spi1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c2_default>; + pinctrl-1 = <&blsp_i2c2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi2_default>; + pinctrl-1 = <&blsp_spi2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c3_default>; + pinctrl-1 = <&blsp_i2c3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi3_default>; + pinctrl-1 = <&blsp_spi3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c4_default>; + pinctrl-1 = <&blsp_i2c4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi4_default>; + pinctrl-1 = <&blsp_spi4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c5_default>; + pinctrl-1 = <&blsp_i2c5_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi5_default>; + pinctrl-1 = <&blsp_spi5_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_i2c6_default>; + pinctrl-1 = <&blsp_i2c6_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp_spi6_default>; + pinctrl-1 = <&blsp_spi6_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + #reset-cells = <1>; + phy_type = "ulpi"; + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + #phy-cells = <0>; + qcom,init-seq = /bits/ 8 <0x0 0x44>, + <0x1 0x6b>, + <0x2 0x24>, + <0x3 0x13>; + }; + }; + }; + + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_mem>; + + power-domains = <&rpmpd MSM8939_VDDCX>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcss_wlan_default>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs1_mbox 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, + <0x0b001000 0x1000>, <0x0b004000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + apcs1_mbox: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + assigned-clocks = <&apcs2>; + assigned-clock-rates = <297600000>; + #mbox-cells = <1>; + }; + + a53pll_c1: clock@b016000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + }; + + acc0: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b088000 0x1000>; + }; + + saw0: power-manager@b089000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b098000 0x1000>; + }; + + saw1: power-manager@b099000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0a8000 0x1000>; + }; + + saw2: power-manager@b0a9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0b8000 0x1000>; + }; + + saw3: power-manager@b0b9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + }; + + apcs0_mbox: mailbox@b111000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b111000 0x1000>; + clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + + a53pll_c0: clock@b116000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b121000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + acc4: clock-controller@b188000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b188000 0x1000>; + }; + + saw4: power-manager@b189000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b189000 0x1000>; + }; + + acc5: clock-controller@b198000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b198000 0x1000>; + }; + + saw5: power-manager@b199000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b199000 0x1000>; + }; + + acc6: clock-controller@b1a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1a8000 0x1000>; + }; + + saw6: power-manager@b1a9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1a9000 0x1000>; + }; + + acc7: clock-controller@b1b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1b8000 0x1000>; + }; + + saw7: power-manager@b1b9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1b9000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b1d0000 0x40>; + #clock-cells = <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b1d1000 0x1000>; + clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4567-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + cpu4567_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4567_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4567_alert>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + gpu_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + modem1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modem2_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + cam_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index d44cfa0471e9..b711cf9a6dc0 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -766,10 +766,10 @@ #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "sleep", "dsi0pll", @@ -851,20 +851,20 @@ port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@1a94000 { + mdss_dsi0: dsi@1a94000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a94000 0x400>; reg-names = "dsi_ctrl"; @@ -874,8 +874,8 @@ assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -890,7 +890,7 @@ "pixel", "core"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -903,20 +903,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@1a94400 { + mdss_dsi0_phy: phy@1a94400 { compatible = "qcom,dsi-phy-14nm-8953"; reg = <0x01a94400 0x100>, <0x01a94500 0x300>, @@ -934,7 +934,7 @@ status = "disabled"; }; - dsi1: dsi@1a96000 { + mdss_dsi1: dsi@1a96000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a96000 0x400>; reg-names = "dsi_ctrl"; @@ -944,8 +944,8 @@ assigned-clocks = <&gcc BYTE1_CLK_SRC>, <&gcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -960,7 +960,7 @@ "pixel", "core"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -970,20 +970,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@1a96400 { + mdss_dsi1_phy: phy@1a96400 { compatible = "qcom,dsi-phy-14nm-8953"; reg = <0x01a96400 0x100>, <0x01a96500 0x300>, @@ -1002,7 +1002,7 @@ }; }; - apps_iommu: iommu@1e00000 { + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x01e20000 0x20000>; @@ -1276,6 +1276,19 @@ }; }; + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + num-channels = <12>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,num-ees = <4>; + qcom,controlled-remotely; + }; + uart_0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; @@ -1294,6 +1307,8 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_1_default>; @@ -1312,6 +1327,8 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_2_default>; @@ -1330,6 +1347,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_3_default>; pinctrl-1 = <&i2c_3_sleep>; @@ -1347,6 +1367,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_4_default>; pinctrl-1 = <&i2c_4_sleep>; @@ -1357,6 +1380,19 @@ status = "disabled"; }; + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + num-channels = <12>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,num-ees = <4>; + qcom,controlled-remotely; + }; + i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; @@ -1364,6 +1400,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_5_default>; pinctrl-1 = <&i2c_5_sleep>; @@ -1381,6 +1420,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_6_default>; pinctrl-1 = <&i2c_6_sleep>; @@ -1398,6 +1440,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_7_default>; pinctrl-1 = <&i2c_7_sleep>; @@ -1415,6 +1460,9 @@ clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_8_default>; pinctrl-1 = <&i2c_8_sleep>; @@ -1425,7 +1473,7 @@ status = "disabled"; }; - wcnss: remoteproc@a21b000 { + wcnss: remoteproc@a204000 { compatible = "qcom,pronto-v3-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -1507,8 +1555,8 @@ timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; - #address-cells = <0x01>; - #size-cells = <0x01>; + #address-cells = <1>; + #size-cells = <1>; ranges; frame@b121000 { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index f47fb8ea71e2..753b9a2105ed 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -822,7 +822,7 @@ #interrupt-cells = <4>; }; - sdhc_1: mmc@7824000 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x500>, <0x07824000 0x800>; reg-names = "hc", "core"; @@ -838,7 +838,7 @@ status = "disabled"; }; - sdhc_2: mmc@7864000 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc", "core"; @@ -957,7 +957,7 @@ #reset-cells = <1>; }; - sdhc_3: mmc@7a24000 { + sdhc_3: mmc@7a24900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; reg-names = "hc", "core"; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index bdc3f2ba1755..5a7923d7c62a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -342,8 +342,7 @@ }; }; - soc: soc { - + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -747,7 +746,7 @@ reg = <0xfc4ab000 0x4>; }; - spmi_bus: spmi@fc4c0000 { + spmi_bus: spmi@fc4cf000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xfc4cf000 0x1000>, <0xfc4cb000 0x1000>, diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 596ad4c896f5..495d45a16e63 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -24,10 +24,10 @@ status = "okay"; }; -&hdmi { +&mdss_hdmi { status = "okay"; }; -&hdmi_phy { +&mdss_hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 2adadc1e5b7c..ec5457508fe6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -164,21 +164,6 @@ vdda-supply = <&vreg_l2a_1p25>; }; -&dsi0 { - vdda-supply = <&vreg_l2a_1p25>; - vcca-supply = <&vreg_l22a_3p0>; - status = "okay"; -}; - -&dsi0_out { - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vcca-supply = <&vreg_l28a_0p925>; - status = "okay"; -}; - &hsusb_phy1 { vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; @@ -201,6 +186,21 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l22a_3p0>; + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l28a_0p925>; + status = "okay"; +}; + &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 7f4d493a55ff..b4b770a9277d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -11,6 +11,7 @@ #include "pmi8996.dtsi" #include #include +#include #include #include @@ -605,6 +606,34 @@ }; }; +&pmi8994_lpg { + qcom,power-source = <1>; + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pmi8994_spmi_regulators { vdd_gfx: pmi8994_s2: s2 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 1ce5df0a3405..47f55c7311e9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -235,7 +235,15 @@ }; }; -&dsi0 { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdd-supply = <&vreg_l2a_1p25>; @@ -246,26 +254,18 @@ pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; }; -&dsi0_out { +&mdss_dsi0_out { status = "okay"; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vcca-supply = <&vreg_l28a_0p925>; }; -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 100123d51494..bdedcf9dff03 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -93,7 +93,13 @@ }; -&dsi0 { +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; + }; +}; + +&mdss_dsi0 { status = "okay"; vdd-supply = <&vreg_l2a_1p25>; @@ -112,22 +118,16 @@ port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; - }; -}; - &pmi8994_wled { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 30257c07e127..0cb2d4f08c3a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -606,7 +606,7 @@ }; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -889,16 +889,16 @@ #power-domain-cells = <1>; reg = <0x008c0000 0x40000>; clocks = <&xo_board>, - <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, <&gcc GPLL0>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, - <&hdmi_phy>; + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_hdmi_phy>; clock-names = "xo", - "gcc_mmss_noc_cfg_ahb_clk", "gpll0", + "gcc_mmss_noc_cfg_ahb_clk", "dsi0pll", "dsi0pllbyte", "dsi1pll", @@ -980,27 +980,27 @@ port@0 { reg = <0>; mdp5_intf3_out: endpoint { - remote-endpoint = <&hdmi_in>; + remote-endpoint = <&mdss_hdmi_in>; }; }; port@1 { reg = <1>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@994000 { + mdss_dsi0: dsi@994000 { compatible = "qcom,msm8996-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x00994000 0x400>; @@ -1024,9 +1024,9 @@ "pixel", "core"; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; #address-cells = <1>; @@ -1038,20 +1038,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@994400 { + mdss_dsi0_phy: phy@994400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00994400 0x100>, <0x00994500 0x300>, @@ -1068,7 +1068,7 @@ status = "disabled"; }; - dsi1: dsi@996000 { + mdss_dsi1: dsi@996000 { compatible = "qcom,msm8996-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x00996000 0x400>; @@ -1092,9 +1092,9 @@ "pixel", "core"; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; #address-cells = <1>; @@ -1106,20 +1106,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@996400 { + mdss_dsi1_phy: phy@996400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00996400 0x100>, <0x00996500 0x300>, @@ -1136,8 +1136,8 @@ status = "disabled"; }; - hdmi: hdmi-tx@9a0000 { - compatible = "qcom,hdmi-tx-8996"; + mdss_hdmi: mdss_hdmi-tx@9a0000 { + compatible = "qcom,mdss_hdmi-tx-8996"; reg = <0x009a0000 0x50c>, <0x00070000 0x6158>, <0x009e0000 0xfff>; @@ -1160,7 +1160,7 @@ "alt_iface", "extp"; - phys = <&hdmi_phy>; + phys = <&mdss_hdmi_phy>; #sound-dai-cells = <1>; status = "disabled"; @@ -1171,16 +1171,16 @@ port@0 { reg = <0>; - hdmi_in: endpoint { + mdss_hdmi_in: endpoint { remote-endpoint = <&mdp5_intf3_out>; }; }; }; }; - hdmi_phy: phy@9a0600 { + mdss_hdmi_phy: phy@9a0600 { #phy-cells = <0>; - compatible = "qcom,hdmi-phy-8996"; + compatible = "qcom,mdss_hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, <0x009a0a00 0x124>, <0x009a0c00 0x124>, @@ -1832,7 +1832,7 @@ compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x0 0xffffffff>; pcie0: pcie@600000 { compatible = "qcom,pcie-msm8996"; @@ -2069,7 +2069,7 @@ }; }; - camss: camss@a00000 { + camss: camss@a34000 { compatible = "qcom,msm8996-camss"; reg = <0x00a34000 0x1000>, <0x00a00030 0x4>, diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index d18d0b0eda95..7957c8823f0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -39,7 +39,13 @@ }; }; -&dsi0 { +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; + }; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l2a_1p25>; @@ -57,22 +63,16 @@ port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; - }; -}; - &mss_pil { firmware-name = "qcom/msm8996/natrium/mba.mbn", "qcom/msm8996/natrium/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi index a679a9c0cf99..b74cff06f300 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -24,101 +24,121 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-supported-hw = <0x20>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2188800000 { opp-hz = /bits/ 64 <2188800000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; @@ -131,136 +151,163 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-748800000 { opp-hz = /bits/ 64 <748800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1286400>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1363200>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1440000>; }; opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2246400000 { opp-hz = /bits/ 64 <2246400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2342400000 { opp-hz = /bits/ 64 <2342400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; }; @@ -289,3 +336,7 @@ }; /* The rest is inherited from msm8996 */ }; + +&cbf { + compatible = "qcom,msm8996pro-cbf"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 062d56c42385..68e634f8212c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -279,10 +279,6 @@ }; }; -&pmi8998_rradc { - status = "okay"; -}; - &qusb2phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3ec941fed14f..f0e943ff0046 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -802,7 +802,7 @@ ; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -1230,6 +1230,57 @@ drive-strength = <2>; bias-pull-up; }; + + blsp1_spi_b_default: blsp1-spi-b-default-state { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_spi1"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + pins = "gpio31", "gpio34", "gpio32", "gpio33"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_spi4"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi5_default: blsp1-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "blsp_spi5"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi6_default: blsp1-spi6-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "blsp_spi6"; + drive-strength = <6>; + bias-disable; + }; + + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ blsp2_i2c1_default: blsp2-i2c1-default-state { pins = "gpio55", "gpio56"; @@ -1314,6 +1365,48 @@ drive-strength = <2>; bias-pull-up; }; + + blsp2_spi1_default: blsp2-spi1-default-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "blsp_spi7"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_spi8"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_spi9"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "blsp_spi10"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi5_default: blsp2-spi5-default-state { + pins = "gpio58", "gpio59", "gpio60", "gpio61"; + function = "blsp_spi11"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi6_default: blsp2-spi6-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "blsp_spi12"; + drive-strength = <6>; + bias-disable; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -2251,6 +2344,114 @@ #size-cells = <0>; }; + blsp1_spi1: spi@c175000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi2: spi@c176000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c176000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi3: spi@c177000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c177000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi4: spi@c178000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c178000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi5: spi@c179000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c179000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi6: spi@c17a000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c17a000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x25000>; @@ -2394,6 +2595,114 @@ #size-cells = <0>; }; + blsp2_spi1: spi@c1b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b5000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi2: spi@c1b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b6000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi3: spi@c1b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi4: spi@c1b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b8000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi5: spi@c1b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b9000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi6: spi@c1ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1ba000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-msm8998"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index d709d955a2f5..daa6f1d30efa 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Luca Weiss */ +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 46396ec1a330..db3d5c17a77d 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -55,5 +55,21 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8550_flash: led-controller@ee00 { + compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pm8550_pwm: pwm { + compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f4fb1a92ab55..1ea8920ff369 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -139,7 +139,7 @@ status = "disabled"; }; - wcd_codec: audio-codec@f000 { + pm8916_codec: audio-codec@f000 { compatible = "qcom,pm8916-wcd-analog-codec"; reg = <0xf000>; reg-names = "pmic-codec-core"; @@ -174,10 +174,8 @@ "cdc_ear_cnp_int", "cdc_hphr_cnp_int", "cdc_hphl_cnp_int"; - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; #sound-dai-cells = <1>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index a1d36f9ebbd2..2268daf27fa7 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -79,6 +79,16 @@ reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; + + pm8953_gpios: gpio@c000 { + compatible = "qcom,pm8953-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8953_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@1 { diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 340033ac3186..695d79116cde 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -55,7 +55,7 @@ pm8998_resin: resin { compatible = "qcom,pm8941-resin"; - interrupts = ; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; bias-pull-up; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi new file mode 100644 index 000000000000..4eb79e0ce40a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2023 Luca Weiss + */ + +#include +#include +#include + +/ { + thermal-zones { + pmi632-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmi632_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@2 { + compatible = "qcom,pmi632", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmi632_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + channel@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + channel@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + channel@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + channel@7 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "usb_in_i_uv"; + }; + + channel@8 { + reg = ; + qcom,pre-scaling = <1 16>; + label = "usb_in_v_div_16"; + }; + + channel@9 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "chg_temp"; + }; + + channel@4b { + reg = ; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + label = "bat_id"; + }; + + channel@83 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + + channel@84 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vbat_sns"; + }; + }; + + pmi632_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmi632_sdam_7: nvram@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb600 0x100>; + }; + + pmi632_gpios: gpio@c000 { + compatible = "qcom,pmi632-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmi632_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@3 { + compatible = "qcom,pmi632", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_lpg: pwm { + compatible = "qcom,pmi632-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index ffe587f281d8..cd3f0790fd42 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -9,6 +9,26 @@ #address-cells = <1>; #size-cells = <0>; + pmi8998_charger: charger@1000 { + compatible = "qcom,pmi8998-charger"; + reg = <0x1000>; + + interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usb-plugin", + "bat-ov", + "wdog-bark", + "usbin-icl-change"; + + io-channels = <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; + io-channel-names = "usbin_i", "usbin_v"; + + status = "disabled"; + }; + pmi8998_gpios: gpio@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; @@ -23,8 +43,6 @@ compatible = "qcom,pmi8998-rradc"; reg = <0x4500>; #io-channel-cells = <1>; - - status = "disabled"; }; }; @@ -60,6 +78,12 @@ status = "disabled"; }; + pmi8998_flash: led-controller@d300 { + compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pmi8998_wled: leds@d800 { compatible = "qcom,pmi8998-wled"; reg = <0xd800>, <0xd900>; diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index f26fb7d32faf..bc6297e7253e 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -13,6 +13,16 @@ #define PMK8350_SID 0 #endif +/ { + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; +}; + &spmi_bus { pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; @@ -66,6 +76,19 @@ status = "disabled"; }; + pmk8350_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + pmk8350_gpios: gpio@b000 { compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; reg = <0xb000>; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 201efeda7d2d..c7ac9b2eaacf 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -8,6 +8,16 @@ #include #include +/ { + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; +}; + &spmi_bus { pmk8550: pmic@0 { compatible = "qcom,pm8550", "qcom,spmi-pmic"; @@ -39,7 +49,19 @@ reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; + }; + + pmk8550_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; }; pmk8550_gpios: gpio@8800 { diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index b29bc4e4b837..0ed11e80e5e2 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -48,6 +48,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -65,6 +67,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -77,6 +81,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -89,6 +95,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu-map { @@ -110,6 +118,30 @@ }; }; }; + + domain-idle-states { + CLUSTER_SLEEP: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000043>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + }; }; firmware { @@ -135,6 +167,35 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; reserved_memory: reserved-memory { diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 59702ba24f35..358827c2fbd3 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -27,8 +27,8 @@ phy-handle = <&phy1>; phy-mode = "rgmii"; mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy1: phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 9e9fd4b8023e..1d22f87fd238 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -448,6 +448,29 @@ status = "okay"; }; +&sdhc { + pinctrl-0 = <&sdc_on_state>; + pinctrl-1 = <&sdc_off_state>; + pinctrl-names = "default", "sleep"; + + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + non-removable; + no-sd; + no-sdio; + + supports-cqe; + + vmmc-supply = <&vreg_l10a_2p95>; + vqmmc-supply = <&vreg_l7a_1p8>; + + status = "okay"; +}; + &uart7 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index fb553f0bb17a..1c0e5d271e91 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -852,6 +852,53 @@ #hwlock-cells = <1>; }; + sdhc: mmc@8804000 { + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>, + <0x0 0x08805000 0x0 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC5_AHB_CLK>, + <&gcc GCC_SDCC5_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC5_BCR>; + + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + power-domains = <&rpmhpd QDU1000_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + iommus = <&apps_smmu 0x80 0x0>; + dma-coherent; + + bus-width = <8>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <6528000 1652800>; + opp-avg-kBps = <400000 0>; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qdu1000-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; @@ -1110,10 +1157,73 @@ pins = "gpio31"; function = "gpio"; }; + + sdc_on_state: sdc-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc_off_state: sdc-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + }; + + sram@14680000 { + compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x1000>; + ranges = <0 0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; }; apps_smmu: iommu@15000000 { - compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; + compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; @@ -1252,6 +1362,7 @@ qcom,tcs-config = , , , ; label = "apps_rsc"; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index dc80f0bca767..e23a0406eacc 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -5,7 +5,9 @@ /dts-v1/; +#include #include "sm4250.dtsi" +#include "pm6125.dtsi" / { model = "Qualcomm Technologies, Inc. QRB4210 RB2"; @@ -19,21 +21,257 @@ stdout-path = "serial0:115200n8"; }; - vph_pwr: vph-pwr-regulator { + clocks { + clk40M: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-bt { + label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-user0 { + label = "green:user0"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led-wlan { + label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { + compatible = "regulator-fixed"; + regulator-name = "VREG_HDMI_OUT_1P2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_1v2>; + regulator-always-on; + regulator-boot-on; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + /* Main barrel jack input */ + vdc_12v: regulator-vdc-12v { + compatible = "regulator-fixed"; + regulator-name = "DC_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* 1.2V supply stepped down from the barrel jack input */ + vdc_1v2: regulator-vdc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "VDC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 3.3V supply stepped down from the barrel jack input */ + vdc_3v3: regulator-vdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 5V supply stepped down from the barrel jack input */ + vdc_5v: regulator-vdc-5v { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ + vdc_vbat_som: regulator-vdc-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* PMI632 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; + vin-supply = <&vdc_vbat_som>; regulator-always-on; regulator-boot-on; }; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_hdmi_out_1p2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l18a_1p232>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pm6125_gpios { + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qrb4210/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qrb4210/cdsp.mbn"; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm6125-regulators"; @@ -86,6 +324,7 @@ vreg_l5a_2p96: l5 { regulator-min-microvolt = <1648000>; regulator-max-microvolt = <3056000>; + regulator-allow-set-load; }; vreg_l6a_0p6: l6 { @@ -116,6 +355,7 @@ vreg_l11a_1p8: l11 { regulator-min-microvolt = <1704000>; regulator-max-microvolt = <1952000>; + regulator-allow-set-load; }; vreg_l12a_1p8: l12 { @@ -190,6 +430,10 @@ }; &sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l24a_2p96>; vqmmc-supply = <&vreg_l11a_1p8>; no-sdio; @@ -199,7 +443,12 @@ }; &sdhc_2 { - cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; /* card detect gpio */ + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; /* card detect gpio */ + + pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l22a_2p96>; vqmmc-supply = <&vreg_l5a_2p96>; no-sdio; @@ -207,21 +456,78 @@ status = "okay"; }; +&spi5 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk40M>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; +}; + &sleep_clk { clock-frequency = <32000>; }; &tlmm { - gpio-reserved-ranges = <37 5>, <43 2>, <47 1>, - <49 1>, <52 1>, <54 1>, + gpio-reserved-ranges = <43 2>, <49 1>, <54 1>, <56 3>, <61 2>, <64 1>, <68 1>, <72 8>, <96 1>; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; + input-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio46"; + function = "gpio"; + bias-disable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart4 { status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_dwc3 { + maximum-speed = "super-speed"; + dr_mode = "peripheral"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l15a_3p128>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l4a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + &xo_board { clock-frequency = <19200000>; }; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index dd924331b0ee..9022ad726741 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -535,30 +535,6 @@ firmware-name = "qcom/sm8250/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - -#if 0 - qcom,dual-dsi-mode; - qcom,master-dsi; -#endif - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p88>; -}; - &gmu { status = "okay"; }; @@ -604,7 +580,7 @@ reg = <0>; lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -613,7 +589,7 @@ reg = <1>; lt9611_b: endpoint { - remote-endpoint = <&dsi1_out>; + remote-endpoint = <&mdss_dsi1_out>; }; }; #endif @@ -639,8 +615,28 @@ status = "okay"; }; -&mdss_mdp { +&mdss_dsi0 { status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + +#if 0 + qcom,dual-dsi-mode; + qcom,master-dsi; +#endif + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; }; &pm8150_adc { diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 15e1ae1c1a97..5e4287f8c8cd 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -47,29 +47,6 @@ vin-supply = <&vreg_3p3>; }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - }; }; &apps_rsc { @@ -352,19 +329,40 @@ max-speed = <1000>; mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; /* Micrel KSZ9031RNZ PHY */ rgmii_phy: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x7>; - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ + interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 24fa449d48a6..5a26974dcf8f 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -151,6 +151,185 @@ }; }; +ðernet0 { + snps,mtl-rx-config = <ðernet0_mtl_rx_setup>; + snps,mtl-tx-config = <ðernet0_mtl_tx_setup>; + + max-speed = <1000>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-txid"; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_default>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Marvell 88EA1512 */ + rgmii_phy: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + + interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + + device_type = "ethernet-phy"; + + /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation + * from userspace to talk to the switch on the SGMII side of things + */ + marvell,reg-init = + /* Set MODE[2:0] to RGMII_SGMII */ + <0x12 0x14 0xfff8 0x4>, + /* Soft reset required after changing MODE[2:0] */ + <0x12 0x14 0x7fff 0x8000>; + }; + }; + + ethernet0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + ethernet0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + snps,mtl-rx-config = <ðernet1_mtl_rx_setup>; + snps,mtl-tx-config = <ðernet1_mtl_tx_setup>; + + max-speed = <1000>; + phy-mode = "rgmii-txid"; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet1_default>; + + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + ethernet1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + ethernet1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_default>; @@ -316,6 +495,66 @@ /* PINCTRL */ &tlmm { + ethernet0_default: ethernet0-default-state { + mdc-pins { + pins = "gpio175"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio176"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182"; + function = "rgmii_0"; + drive-strength = <16>; + bias-disable; + }; + }; + + ethernet1_default: ethernet1-default-state { + mdc-pins { + pins = "gpio97"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio98"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104"; + function = "rgmii_1"; + drive-strength = <16>; + bias-disable; + }; + }; + i2c0_default: i2c0-default-state { /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ pins = "gpio135", "gpio136"; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 4a990fda8fc3..bacbdec56281 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -167,6 +167,14 @@ }; }; +&gpucc { + status = "disabled"; +}; + +&gpu_smmu { + status = "disabled"; +}; + &pcie2a { compatible = "qcom,pcie-sa8540p"; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 7602cca47bae..3c3b6287cd27 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -88,6 +88,14 @@ }; }; }; + + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; }; &spmi_bus { @@ -108,8 +116,6 @@ compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>; reg-names = "hlos", "pbs"; - mode-recovery = <0x1>; - mode-bootloader = <0x2>; pmm8654au_0_pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -135,6 +141,19 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pmm8654au_0_sdam_0: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; }; pmm8654au_1: pmic@2 { diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index f238a02a5448..ab767cfa51ff 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "sa8775p.dtsi" @@ -18,8 +19,10 @@ serial0 = &uart10; serial1 = &uart12; serial2 = &uart17; + i2c11 = &i2c11; i2c18 = &i2c18; spi16 = &spi16; + ufshc1 = &ufs_mem_hc; }; chosen { @@ -258,6 +261,13 @@ }; }; +&i2c11 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>; @@ -291,6 +301,13 @@ "BT_EN", "USB2_PWR_EN", "USB2_FAULT"; + + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; }; &pmm8654au_2_gpios { @@ -306,6 +323,20 @@ "USB1_PWR_ENABLE", "USB1_FAULT", "VMON_SPX8"; + + usb0_en_state: usb0-en-state { + pins = "gpio3"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb1_en_state: usb1-en-state { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; }; &pmm8654au_3_gpios { @@ -347,6 +378,13 @@ bias-disable; }; + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4"; @@ -426,6 +464,94 @@ status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_state>; + + status = "okay"; +}; + +&usb_0_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_state>; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index c3310caf9f68..b130136acffe 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #include #include @@ -308,6 +310,11 @@ }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -469,8 +476,8 @@ <0>, <0>, <0>, - <0>, - <0>, + <&usb_0_qmpphy>, + <&usb_1_qmpphy>, <0>, <0>, <0>, @@ -503,6 +510,111 @@ #size-cells = <2>; status = "disabled"; + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x888000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + spi16: spi@888000 { compatible = "qcom,geni-spi"; reg = <0x0 0x00888000 0x0 0x4000>; @@ -524,6 +636,48 @@ status = "disabled"; }; + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart17: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x0088c000 0x0 0x4000>; @@ -559,6 +713,391 @@ #size-cells = <0>; status = "disabled"; }; + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c20: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi20: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + status = "disabled"; + + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + uart5: serial@994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x994000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -573,6 +1112,189 @@ iommus = <&apps_smmu 0x443 0x0>; status = "disabled"; + i2c7: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi7: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c8: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi8: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c9: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi9: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + uart9: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi10: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart10: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a8c000 0x0 0x4000>; @@ -589,6 +1311,90 @@ status = "disabled"; }; + i2c11: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi11: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c12: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi12: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart12: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a94000 0x0 0x4000>; @@ -603,6 +1409,376 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + i2c13: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + }; + + qupv3_id_3: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xbc0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + status = "disabled"; + + i2c21: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + spi21: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + iommus = <&apps_smmu 0x100 0x0>; + dma-coherent; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sa8775p-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_0_hsphy: phy@88e4000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e4000 0 0x120>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0_qmpphy: phy@88e8000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088e8000 0 0x2000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0: usb@a6f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x080 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_1_hsphy: phy@88e6000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e6000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@88ea000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088ea000 0 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1: usb@a8f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_EDGE_RISING>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x0a0 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2_hsphy: phy@88e7000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB3_PHY_TERT_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2: usb@a4f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x020 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + }; }; tcsr_mutex: hwlock@1f40000 { @@ -611,6 +1787,56 @@ #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, @@ -658,6 +1884,16 @@ interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells = <0>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, @@ -829,6 +2065,80 @@ ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ @@ -840,6 +2150,13 @@ redistributor-stride = <0x0 0x20000>; }; + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; + reg = <0x0 0x17c10000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + memtimer: timer@17c20000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts new file mode 100644 index 000000000000..b637b4270f88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include +#include + +#include "sc7180.dtsi" + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &tz_mem; +/delete-node/ &ipa_fw_mem; + +/ { + model = "Acer Aspire 1"; + compatible = "acer,aspire1", "qcom,sc7180"; + chassis-type = "laptop"; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + zap_mem: zap-shader@80840000 { + reg = <0x0 0x80840000 0 0x2000>; + no-map; + }; + + venus_mem: venus@85b00000 { + reg = <0x0 0x85b00000 0 0x500000>; + no-map; + }; + + mpss_mem: mpss@86000000 { + reg = <0x0 0x86000000 0x0 0x2000000>; + no-map; + }; + + adsp_mem: adsp@8e400000 { + reg = <0x0 0x8e400000 0x0 0x2800000>; + no-map; + }; + + wlan_mem: wlan@93900000 { + reg = <0x0 0x93900000 0x0 0x200000>; + no-map; + }; + }; + + max98357a: audio-codec { + compatible = "maxim,max98357a"; + sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&_sd_mode_default>; + pinctrl-names = "default"; + + #sound-dai-cells = <0>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&sn65dsi86_bridge 1000000>; + enable-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&soc_bkoff_default>; + pinctrl-names = "default"; + }; + + reg_brij_1p2: bridge-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "brij_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_edp_1p2_en_default>; + pinctrl-names = "default"; + }; + + reg_brij_1p8: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "brij_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l8c_1p8>; + + gpio = <&tlmm 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_edp_1p8_en_default>; + pinctrl-names = "default"; + }; + + reg_codec_3p3: codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "codec_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_audio_en_default>; + pinctrl-names = "default"; + }; + + reg_lcm_3p3: panel-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcm_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_lcm_en_default>; + pinctrl-names = "default"; + }; + + reg_tp_3p3: touchpad-regulator { + compatible = "regulator-fixed"; + regulator-name = "tp_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tp_en_default>; + pinctrl-names = "default"; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + /* embedded-controller@76 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* + * NOTE: DSDT defines two possible touchpads, other one is + * + * reg = <0x15>; + * hid-descr-addr = <0x1>; + */ + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + vdd-supply = <®_tp_3p3>; + + interrupts-extended = <&tlmm 94 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&hid_touchpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 33 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&hid_keyboard_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + alc5682: codec@1a { + compatible = "realtek,rt5682i"; + reg = <0x1a>; + + #sound-dai-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <28 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-0 = <&codec_irq_default>; + pinctrl-names = "default"; + + AVDD-supply = <&vreg_l15a_1p8>; + MICVDD-supply = <®_codec_3p3>; + VBAT-supply = <®_codec_3p3>; + + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <1>; + realtek,jd-src = <1>; + }; +}; + +&i2c10 { + clock-frequency = <400000>; + status = "okay"; + + sn65dsi86_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + suspend-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&bridge_en_default>, + <&edp_bridge_irq_default>, + <&bridge_suspend_default>; + pinctrl-names = "default"; + + vpll-supply = <®_brij_1p8>; + vccio-supply = <®_brij_1p8>; + vcca-supply = <®_brij_1p2>; + vcc-supply = <®_brij_1p2>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK3>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi86_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sn65dsi86_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <®_lcm_3p3>; + backlight = <&backlight>; + hpd-absent-delay-ms = <200>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&zap_mem>; + firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3c_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a_0p8>; + status = "okay"; +}; + +&pm6150_adc { + thermistor@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + charger-thermistor@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + charger-thermistor@0 { + reg = <0>; + io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm6150_pon { + status = "disabled"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l19a_2p9>; + vqmmc-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + +&uart3 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart3_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3991-bt"; + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vreg_l2c_1p3>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_2_x: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + peer-hub = <&usb_hub_3_x>; + }; + + usb_hub_3_x: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + peer-hub = <&usb_hub_2_x>; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; + qcom,imp-res-offset-value = <8>; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l4a_0p8>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sc7180/acer/aspire1/qcvss7180.mbn"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&qup_i2c2_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c4_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c9_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c10_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&tlmm { + /* + * The TZ seem to protect those because some boards can have + * fingerprint sensor connected to this range. Not connected + * on this board + */ + gpio-reserved-ranges = <58 5>; + + amp_sd_mode_default: amp-sd-mode-deault-state { + pins = "gpio23"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + bridge_en_default: bridge-en-default-state { + pins = "gpio51"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + bridge_suspend_default: bridge-suspend-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + codec_irq_default: codec-irq-deault-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_bridge_irq_default: edp-bridge-irq-default-state { + pins = "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + hid_keyboard_default: hid-keyboard-default-state { + pins = "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hid_touchpad_default: hid-touchpad-default-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; + + reg_edp_1p2_en_default: reg-edp-1p2-en-deault-state { + pins = "gpio19"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_edp_1p8_en_default: reg-edp-1p8-en-deault-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_lcm_en_default: reg-lcm-en-deault-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_audio_en_default: reg-audio-en-deault-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tp_en_default: reg-tp-en-deault-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + soc_bkoff_default: soc-bkoff-deault-state { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <16>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 299ef5dc225a..a1c50be4ad95 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -295,7 +295,11 @@ }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l3c_1p2>; @@ -314,7 +318,7 @@ port { panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; @@ -329,19 +333,11 @@ }; }; -&dsi_phy { +&mdss_dsi0_phy { status = "okay"; vdds-supply = <&vreg_l4a_0p8>; }; -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &qfprom { vcc-supply = <&vreg_l11a_1p8>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index 5aa7949b5328..bede23369fed 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -46,10 +46,6 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&dsi0_out { - remote-endpoint = <&ps8640_in>; -}; - edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; @@ -74,7 +70,7 @@ edp_brij_i2c: &i2c2 { port@0 { reg = <0>; ps8640_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -102,6 +98,10 @@ edp_brij_i2c: &i2c2 { }; }; +&mdss_dsi0_out { + remote-endpoint = <&ps8640_in>; +}; + &tlmm { edp_brij_ps8640_rst: edp-brij-ps8640-rst-state { pins = "gpio11"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts index 5c81e44ed4a5..0a7f2286b541 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -15,7 +15,7 @@ compatible = "google,quackingstick-sku1537", "qcom,sc7180"; }; -&dsi_phy { +&mdss_dsi0_phy { qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; qcom,phy-drive-ldo-level = <375>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 8e7b42f843d4..62ab6427dd65 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -52,36 +52,6 @@ }; }; -&dsi0 { - panel: panel@0 { - /* Compatible will be filled in per-board */ - reg = <0>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst>; - avdd-supply = <&ppvar_lcd>; - pp1800-supply = <&v1p8_disp>; - pp3300-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - rotation = <270>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - &gpio_keys { status = "okay"; }; @@ -106,6 +76,36 @@ }; }; +&mdss_dsi0 { + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + avdd-supply = <&ppvar_lcd>; + pp1800-supply = <&v1p8_disp>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + &sdhc_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index e52b8776755d..b0c3be4c3bb4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -27,10 +27,6 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&dsi0_out { - remote-endpoint = <&sn65dsi86_in>; -}; - edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; @@ -65,7 +61,7 @@ edp_brij_i2c: &i2c2 { port@0 { reg = <0>; sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -95,6 +91,10 @@ edp_brij_i2c: &i2c2 { }; }; +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; +}; + &tlmm { edp_brij_irq: edp-brij-irq-state { pins = "gpio11"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts index c5b0658bd632..6eeead70d3eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -17,7 +17,7 @@ compatible = "google,wormdingler-sku1024", "qcom,sc7180"; }; -&dsi_phy { +&mdss_dsi0_phy { qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; qcom,phy-drive-ldo-level = <450>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 262d6691abd9..2efa8a4bcda6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -110,37 +110,6 @@ }; }; -&dsi0 { - - panel: panel@0 { - reg = <0>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_reset_1800>; - avdd-supply = <&avdd_lcd>; - avee-supply = <&avee_lcd>; - pp1800-supply = <&v1p8_mipi>; - pp3300-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - rotation = <270>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - &i2c4 { status = "okay"; clock-frequency = <400000>; @@ -162,6 +131,37 @@ }; }; +&mdss_dsi0 { + + panel: panel@0 { + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + &pm6150_adc { skin-temp-thermistor@4d { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 1472e7f10831..681637cf6c4a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -705,20 +705,6 @@ ap_h1_spi: &spi0 { status = "disabled"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; -}; - -&dsi0_out { - data-lanes = <0 1 2 3>; -}; - -&dsi_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - ap_sar_sensor_i2c: &i2c5 { clock-frequency = <400000>; @@ -788,6 +774,10 @@ hp_i2c: &i2c9 { }; }; +&lpasscc { + status = "okay"; +}; + &lpass_cpu { status = "okay"; @@ -813,7 +803,7 @@ hp_i2c: &i2c9 { }; }; -&mdp { +&lpass_hm { status = "okay"; }; @@ -832,6 +822,20 @@ hp_i2c: &i2c9 { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + &pm6150_adc { charger-thermistor@4f { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a65be760d1a7..e25dc2bb52a7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2700,6 +2700,7 @@ qspi: spi@88dc000 { compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; + iommus = <&apps_smmu 0x20 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; @@ -2997,8 +2998,6 @@ interrupt-parent = <&mdss>; interrupts = <0>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; @@ -3006,7 +3005,7 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; @@ -3043,7 +3042,7 @@ }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -3066,12 +3065,12 @@ "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; - phys = <&dsi_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -3084,14 +3083,14 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -3116,13 +3115,13 @@ }; }; - dsi_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", + reg-names = "dsi0_phy", + "dsi0_phy_lane", "dsi_pll"; #clock-cells = <1>; @@ -3213,8 +3212,8 @@ reg = <0 0x0af00000 0 0x200000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&dsi_phy 0>, - <&dsi_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", @@ -3636,6 +3635,8 @@ power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; #clock-cells = <1>; #power-domain-cells = <1>; + + status = "reserved"; /* Controlled by ADSP */ }; lpass_cpu: lpass@62d87000 { @@ -3684,6 +3685,8 @@ #clock-cells = <1>; #power-domain-cells = <1>; + + status = "reserved"; /* Controlled by ADSP */ }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5b1c175c47f1..9ea6636125ad 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -467,10 +467,6 @@ ap_i2c_tpm: &i2c14 { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; -&mdss_mdp { - status = "okay"; -}; - /* NVMe drive, enabled on a per-board basis */ &pcie1 { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 36f0bb9b3cbb..a0e8db8270e7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -649,6 +649,18 @@ }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -3430,6 +3442,7 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; + port { usb2_role_switch: endpoint { remote-endpoint = <&eud_ep>; @@ -3441,6 +3454,7 @@ qspi: spi@88dc000 { compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x1000>; + iommus = <&apps_smmu 0x20 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; @@ -3605,10 +3619,11 @@ }; eud: eud@88e0000 { - compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x088e0000 0 0x2000>, - <0 0x088e2000 0 0x1000>; + compatible = "qcom,sc7280-eud", "qcom,eud"; + reg = <0 0x88e0000 0 0x2000>, + <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -3619,6 +3634,7 @@ remote-endpoint = <&usb2_role_switch>; }; }; + port@1 { reg = <1>; eud_con: endpoint { @@ -3628,21 +3644,6 @@ }; }; - eud_typec: connector { - compatible = "usb-c-connector"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - con_eud: endpoint { - remote-endpoint = <&eud_con>; - }; - }; - }; - }; - nsp_noc: interconnect@a0c0000 { reg = <0 0x0a0c0000 0 0x10000>; compatible = "qcom,sc7280-nsp-noc"; @@ -3880,8 +3881,6 @@ interrupt-parent = <&mdss>; interrupts = <0>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; @@ -3889,7 +3888,7 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; @@ -3974,14 +3973,14 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts new file mode 100644 index 000000000000..fe3b366e1435 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model = "Lenovo Flex 5G"; + compatible = "lenovo,flex-5g", "qcom,sc8180x"; + + aliases { + serial0 = &uart13; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8180c_lpg 4 1000000>; + enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bl_pwm_default>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_active_state>; + pinctrl-names = "default"; + + lid { + gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg = <0x0 0x8d800000 0x0 0x3000000>; + no-map; + }; + + adsp_mem: adsp-region@90800000 { + reg = <0x0 0x90800000 0x0 0x1c00000>; + no-map; + }; + + gpu_mem: gpu-region@98715000 { + reg = <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + + cdsp_mem: cdsp-region@98900000 { + reg = <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s5-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt = <1296000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s6-supply = <&vph_pwr>; + vdd-l2-l3-supply = <&vreg_s6c_1p35>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt = <992000>; + regulator-max-microvolt = <992000>; + regulator-initial-mode = ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@5 { + compatible = "hid-over-i2c"; + reg = <0x5>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + }; + + hid@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_edp { + data-lanes = <0 1 2 3>; + + pinctrl-0 = <&edp_hpd_active>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + no-hpd; + + backlight = <&backlight>; + + ports { + port { + auo_b140han06_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_edp_out: endpoint { + remote-endpoint = <&auo_b140han06_in>; + }; + }; + }; +}; + +&pcie3 { + perst-gpio = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 180 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie3_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&pmc8180c_lpg { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcadsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + memory-region = <&cdsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qccdsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcmpss8180_nm.mbn"; + + status = "okay"; +}; + +&uart13 { + pinctrl-0 = <&uart13_state>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l9a_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10e_2p9>; + vcc-max-microamp = <155000>; + + vccq2-supply = <&vreg_l7e_1p8>; + vccq2-max-microamp = <425000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_prim { + status = "okay"; +}; + +&usb_prim_dwc3 { + dr_mode = "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_sec { + status = "okay"; +}; + +&usb_sec_dwc3 { + dr_mode = "host"; +}; + +&wifi { + memory-region = <&wlan_mem>; + + vdd-0.8-cx-mx-supply = <&vreg_l1e_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l10c_3p3>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default: bl-pwm-default-state { + en-pins { + pins = "gpio8"; + function = "normal"; + }; + + pwm-pins { + pins = "gpio10"; + function = "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <47 4>, <126 4>; + + edp_hpd_active: epd-hpd-active-state { + pins = "gpio10"; + function = "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins = "gpio121"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + i2c1_active: i2c1-active-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + + bias-pull-up = <1>; + drive-strength = <2>; + }; + + i2c1_hid_active: i2c1-hid-active-state { + pins = "gpio122"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_active: i2c7-active-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_hid_active: i2c7-hid-active-state { + pins = "gpio37", "gpio24"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + pcie3_default_state: pcie3-default-state { + clkreq-pins { + pins = "gpio179"; + function = "pci_e3"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio178"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio180"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart13_state: uart13-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio44", "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi new file mode 100644 index 000000000000..8247af01c84a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + thermal-zones { + pmc8180-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmc8180c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180c_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmc8180_0: pmic@0 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon: power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + + status = "disabled"; + }; + }; + + pmc8180_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pmc8180_gpios: gpio@c000 { + compatible = "qcom,pmc8180-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmc8180", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@2 { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin2"; + }; + }; + }; + + pmic@6 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@8 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@a { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin"; + }; + }; + }; + + pmic@4 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmc8180c_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180c_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180c_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180c_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmc8180c_gpios: gpio@c000 { + compatible = "qcom,pmc8180c-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmc8180c", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + + pmc8180c_lpg: lpg { + compatible = "qcom,pmc8180c-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts new file mode 100644 index 000000000000..fc038474cb71 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -0,0 +1,702 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model = "Qualcomm SC8180x Primus"; + compatible = "qcom,sc8180x-primus", "qcom,sc8180x"; + + aliases { + serial0 = &uart12; + serial1 = &uart13; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8180c_lpg 4 1000000>; + enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwm_default>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&hall_int_active_state>; + + lid-switch { + gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + adsp_mem: adsp-region@96e00000 { + reg = <0x0 0x96e00000 0x0 0x1c00000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg = <0x0 0x8d800000 0x0 0x9600000>; + no-map; + }; + + gpu_mem: gpu-region@98a00000 { + reg = <0x0 0x98a00000 0x0 0x2000>; + no-map; + }; + + reserved-region@9a500000 { + reg = <0x0 0x9a500000 0x0 0x600000>; + no-map; + }; + }; + + vreg_nvme_0p9: nvme-0p9-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_nvme_0p9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-always-on; + }; + + vreg_nvme_3p3: nvme-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_nvme_3p3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8180c_gpios 11 0>; + enable-active-high; + + regulator-always-on; + }; + + vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_kb_tp_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-always-on; + + pinctrl-names = "default"; + pinctrl-0 = <&kb_tp_3v3_en_active_state>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s5-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt = <1296000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s6-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l2-l3-supply = <&vreg_s6c_1p35>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p8: smps8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l4c_3p3: ldo4 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt = <992000>; + regulator-max-microvolt = <992000>; + regulator-initial-mode = ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l12e: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_i2c_active_state>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + + vdd-supply = <&vreg_l4c_3p3>; + vddl-supply = <&vreg_l12e>; + + post-power-on-delay-ms = <20>; + + interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_active_state>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&aux_i2c_active_state>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_active_state>; + + vdd-supply = <&vdd_kb_tp_3v3>; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&kb_int_active_state>; + + vdd-supply = <&vdd_kb_tp_3v3>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_edp { + data-lanes = <0 1 2 3>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd_active>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + ports { + port { + auo_b133han05_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_edp_out: endpoint { + remote-endpoint = <&auo_b133han05_in>; + }; + }; + }; +}; + +&pcie1 { + perst-gpio = <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 177 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&pmc8180c_lpg { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc8180x/qcadsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; + firmware-name = "qcom/sc8180x/qcmpss8180.mbn"; + + status = "okay"; +}; + +&uart12 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart13 { + pinctrl-names = "default"; + pinctrl-0 = <&uart13_state>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l9a_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10e_2p9>; + vcc-max-microamp = <155000>; + + vccq2-supply = <&vreg_l7e_1p8>; + vccq2-max-microamp = <425000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_prim { + status = "okay"; +}; + +&usb_prim_dwc3 { + dr_mode = "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_sec { + status = "okay"; +}; + +&usb_sec_dwc3 { + dr_mode = "host"; +}; + +&wifi { + memory-region = <&wlan_mem>; + + vdd-0.8-cx-mx-supply = <&vreg_l1e_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l10c_3p3>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default: bl-pwm-default-state { + en-pins { + pins = "gpio8"; + function = "normal"; + }; + + pwm-pins { + pins = "gpio10"; + function = "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <47 4>, <126 4>; + + aux_i2c_active_state: aux-i2c-active-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + + bias-disable; + drive-strength = <16>; + }; + + edp_hpd_active: epd-hpd-active-state { + pins = "gpio10"; + function = "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins = "gpio121"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + kb_int_active_state: kb-int-active-state { + int-n-pins { + pins = "gpio37"; + function = "gpio"; + + bias-pull-up; + intput-enable; + }; + + kp-disable-pins { + pins = "gpio135"; + function = "gpio"; + + output-high; + }; + }; + + kb_tp_3v3_en_active_state: kb-tp-3v3-en-active-state { + pins = "gpio4"; + function = "gpio"; + + bias-disable; + }; + + pcie2_default_state: pcie2-default-state { + clkreq-pins { + pins = "gpio176"; + function = "pci_e2"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio175"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio177"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + tp_int_active_state: tp-int-active-state { + tp-int-pins { + pins = "gpio24"; + function = "gpio"; + + bias-disable; + input-enable; + }; + + tp-close-n-pins { + pins = "gpio116"; + function = "gpio"; + + bias-disable; + input-enable; + }; + }; + + ts_active_state: ts-active-state { + int-n-pins { + pins = "gpio122"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + reset-n-pins { + pins = "gpio54"; + function = "gpio"; + + output-high; + }; + }; + + ts_i2c_active_state: ts-i2c-active-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + + /* External pull up */ + bias-disable; + drive-strength = <2>; + }; + + uart13_state: uart13-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio44", "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi new file mode 100644 index 000000000000..d3ae18535636 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -0,0 +1,4032 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_300: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_400: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_500: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_600: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_700: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <241>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <800000 9600000>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-peak-kBps = <800000 12902400>; + }; + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <800000 12902400>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <800000 15974400>; + }; + + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <1804000 19660800>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <1804000 19660800>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <1804000 22732800>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <1804000 22732800>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <2188000 31948800>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <3072000 31948800>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1804000 15974400>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 19660800>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <2188000 22732800>; + }; + + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 25804800>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <4068000 31948800>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <4068000 31948800>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <4068000 40550400>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <4068000 40550400>; + }; + + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <4068000 43008000>; + }; + + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <6220000 49152000>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 49152000>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <8368000 49152000>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2918400000 { + opp-hz = /bits/ 64 <2918400000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sc8180x", "qcom,scm"; + }; + }; + + camnoc_virt: interconnect-camnoc-virt { + compatible = "qcom,sc8180x-camnoc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sc8180x-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qup_virt: interconnect-qup-virt { + compatible = "qcom,sc8180x-qup-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@85700000 { + reg = <0x0 0x85700000 0x0 0x600000>; + no-map; + }; + + xbl_mem: xbl@85d00000 { + reg = <0x0 0x85d00000 0x0 0x140000>; + no-map; + }; + + aop_mem: aop@85f00000 { + reg = <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db: cmd-db@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + reserved@85f40000 { + reg = <0x0 0x85f40000 0x0 0x10000>; + no-map; + }; + + smem_mem: smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + reserved@86200000 { + reg = <0x0 0x86200000 0x0 0x3900000>; + no-map; + }; + + reserved@89b00000 { + reg = <0x0 0x89b00000 0x0 0x1c00000>; + no-map; + }; + + reserved@9d400000 { + reg = <0x0 0x9d400000 0x0 0x1000000>; + no-map; + }; + + reserved@9e400000 { + reg = <0x0 0x9e400000 0x0 0x1400000>; + no-map; + }; + + reserved@9f800000 { + reg = <0x0 0x9f800000 0x0 0x800000>; + no-map; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apss_shared 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lpass { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apss_shared 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apss_shared 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + modem_smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + modem_smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + + interrupts = ; + + mboxes = <&apss_shared 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc8180x"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x4c3 0>; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart2: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart5: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart6: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart7: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x603 0>; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c16: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi16: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart16: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + qupv3_id_2: geniqup@cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00cc0000 0x0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x7a3 0>; + status = "disabled"; + + i2c17: i2c@c80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi17: spi@c80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart17: serial@c80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c18: i2c@c84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi18: spi@c84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart18: serial@c84000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c19: i2c@c88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi19: spi@c88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart19: serial@c88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c13: i2c@c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@c8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@c8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c14: i2c@c90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@c90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart14: serial@c90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c15: i2c@c94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@c94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart15: serial@c94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sc8180x-config-noc"; + reg = <0 0x01500000 0 0x7400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sc8180x-system-noc"; + reg = <0 0x01620000 0 0x19400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sc8180x-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sc8180x-aggre2-noc"; + reg = <0 0x01700000 0 0x20000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1720000 { + compatible = "qcom,sc8180x-compute-noc"; + reg = <0 0x01720000 0 0x7000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sc8180x-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy-wrapper@1c06000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx0 */ + <0 0x1c06400 0 0x200>, /* rx0 */ + <0 0x1c06a00 0 0x1f0>, /* pcs */ + <0 0x1c06600 0 0x170>, /* tx1 */ + <0 0x1c06800 0 0x200>, /* rx1 */ + <0 0x1c06e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie3: pci@1c08000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1e00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets = <&gcc GCC_PCIE_3_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_3_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie3_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie3_phy: phy-wrapper@1c0c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c0c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_3_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie3_lane: phy@1c0c200 { + reg = <0 0x1c0c200 0 0x170>, /* tx0 */ + <0 0x1c0c400 0 0x200>, /* rx0 */ + <0 0x1c0ca00 0 0x1f0>, /* pcs */ + <0 0x1c0c600 0 0x170>, /* tx1 */ + <0 0x1c0c800 0 0x200>, /* rx1 */ + <0 0x1c0ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_3_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie1: pci@1c10000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c10000 0 0x3000>, + <0 0x68000000 0 0xf1d>, + <0 0x68000f20 0 0xa8>, + <0 0x68001000 0 0x1000>, + <0 0x68100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy-wrapper@1c16000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c16000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: phy@1c0e200 { + reg = <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ + <0 0x1c16600 0 0x170>, /* tx1 */ + <0 0x1c16800 0 0x200>, /* rx1 */ + <0 0x1c16e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + }; + }; + + pcie2: pci@1c18000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c18000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>; + + resets = <&gcc GCC_PCIE_2_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2_phy: phy-wrapper@1c1c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c1c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie2_lane: phy@1c0e200 { + reg = <0 0x1c1c200 0 0x170>, /* tx0 */ + <0 0x1c1c400 0 0x200>, /* rx0 */ + <0 0x1c1ca00 0 0x1f0>, /* pcs */ + <0 0x1c1c600 0 0x170>, /* tx1 */ + <0 0x1c1c800 0 0x200>, /* rx1 */ + <0 0x1c1ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk"; + + #phy-cells = <0>; + }; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x2500>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x300 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy-wrapper@1d87000 { + compatible = "qcom,sc8180x-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + ipa_virt: interconnect@1e00000 { + compatible = "qcom,sc8180x-ipa-virt"; + reg = <0 0x01e00000 0 0x1000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + gpu: gpu@2c00000 { + compatible = "qcom,adreno-680.1", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0 0x02c00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0xc01>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-level = ; + }; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = ; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + opp-level = ; + }; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + + reg = <0 0x02c6a000 0 0x30000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0xc00>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sc8180x-gpucc"; + reg = <0 0x02c90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@2ca0000 { + compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x02ca0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + tlmm: pinctrl@3100000 { + compatible = "qcom,sc8180x-tlmm"; + reg = <0 0x03100000 0 0x300000>, + <0 0x03500000 0 0x700000>, + <0 0x03d00000 0 0x300000>; + reg-names = "west", "east", "south"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 191>; + wakeup-parent = <&pdc>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc8180x-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>, + <&rpmhpd SC8180X_MSS>; + power-domain-names = "cx", "mss"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible = "qcom,sc8180x-cdsp-pas"; + reg = <0x0 0x08300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + }; + }; + + usb_prim_hsphy: phy@88e2000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e2000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_sec_hsphy: phy@88e3000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_prim_qmpphy: phy@88e9000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_prim_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + }; + + usb_prim_dpphy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + usb_sec_qmpphy: phy@88ee000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088ee000 0 0x18c>, + <0 0x088ed000 0 0x10>, + <0 0x088ef000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_sec_ssphy: usb3-phy@88e9200 { + reg = <0 0x088ee200 0 0x200>, + <0 0x088ee400 0 0x200>, + <0 0x088eec00 0 0x218>, + <0 0x088ee600 0 0x200>, + <0 0x088ee800 0 0x200>, + <0 0x088eea00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + }; + + usb_sec_dpphy: dp-phy@88ef200 { + reg = <0 0x088ef200 0 0x200>, + <0 0x088ef400 0 0x200>, + <0 0x088efa00 0 0x200>, + <0 0x088ef600 0 0x200>, + <0 0x088ef800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + clock-output-names = "qmp_dptx1_phy_pll_link_clk", + "qmp_dptx1_phy_pll_vco_div_clk"; + }; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sc8180x-llcc"; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + + gem_noc: interconnect@9680000 { + compatible = "qcom,sc8180x-gem-noc"; + reg = <0 0x09680000 0 0x58200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + usb_prim: usb@a6f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc USB30_PRIM_GDSC>; + + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_prim_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x140 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_sec: usb@a8f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc USB30_SEC_GDSC>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_sec_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + mdss: mdss@ae00000 { + compatible = "qcom,sc8180x-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "nrt_bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@4 { + reg = <4>; + dpu_intf4_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@5 { + reg = <5>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae90a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + + phys = <&usb_prim_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae98a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <13>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + + phys = <&usb_sec_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp: displayport-controller@ae9a000 { + compatible = "qcom,sc8180x-edp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9aa00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <14>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; + + phys = <&edp_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + edp_phy: phy@aec2a00 { + compatible = "qcom,sc8180x-edp-phy"; + reg = <0 0x0aec2a00 0 0x1c0>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x19c>; + + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&dispcc MDSS_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc8180x-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_prim_dpphy 0>, + <&usb_prim_dpphy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + clock-names = "bi_tcxo", + "sleep_clk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SC8180X_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc8180x-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <9>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + }; + + remoteproc_adsp: remoteproc@17300000 { + compatible = "qcom,sc8180x-adsp-pas"; + reg = <0x0 0x17300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sc8180x-apss-shared"; + reg = <0x0 0x17c00000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17c21000{ + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c26000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + power-domains = <&CLUSTER_PD>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sc8180x-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sc8180x-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + osm_l3: interconnect@18321000 { + compatible = "qcom,sc8180x-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + lmh@18350800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18350800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh@18358800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18358800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + clock-names = "cxo_ref_clk_pin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x0640 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 13>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 14>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + compute-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mdm-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 5b25d54b9591..b566e403d1db 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -64,7 +64,7 @@ reg = <1>; pmic_glink_con0_ss: endpoint { - remote-endpoint = <&mdss0_dp0_out>; + remote-endpoint = <&usb_0_qmpphy_out>; }; }; @@ -99,7 +99,7 @@ reg = <1>; pmic_glink_con1_ss: endpoint { - remote-endpoint = <&mdss0_dp1_out>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; @@ -210,6 +210,11 @@ }; reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -308,6 +313,13 @@ regulator-initial-mode = ; }; + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + vreg_l7c: ldo7 { regulator-name = "vreg_l7c"; regulator-min-microvolt = <2504000>; @@ -318,6 +330,13 @@ RPMH_REGULATOR_MODE_HPM>; }; + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + vreg_l13c: ldo13 { regulator-name = "vreg_l13c"; regulator-min-microvolt = <3072000>; @@ -376,6 +395,15 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; + }; +}; + &mdss0 { status = "okay"; }; @@ -386,7 +414,7 @@ &mdss0_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con0_ss>; + remote-endpoint = <&usb_0_qmpphy_dp_in>; }; &mdss0_dp1 { @@ -395,7 +423,7 @@ &mdss0_dp1_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con1_ss>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss0_dp3 { @@ -600,6 +628,19 @@ status = "okay"; }; +&sdc2 { + pinctrl-0 = <&sdc2_default_state>; + pinctrl-1 = <&sdc2_sleep_state>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l9c>; + vqmmc-supply = <&vreg_l6c>; + + cd-gpios = <&tlmm 131 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &uart17 { compatible = "qcom,geni-debug-uart"; @@ -644,9 +685,19 @@ vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + orientation-switch; + status = "okay"; }; +&usb_0_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp0_out>; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + &usb_0_role_switch { remote-endpoint = <&pmic_glink_con0_hs>; }; @@ -671,9 +722,19 @@ vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + orientation-switch; + status = "okay"; }; +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp1_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + &usb_1_role_switch { remote-endpoint = <&pmic_glink_con1_hs>; }; @@ -842,6 +903,60 @@ }; }; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + tpad_default: tpad-default-state { int-n-pins { pins = "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index bdcba719fc38..7cc3028440b6 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -106,7 +106,7 @@ reg = <1>; pmic_glink_con0_ss: endpoint { - remote-endpoint = <&mdss0_dp0_out>; + remote-endpoint = <&usb_0_qmpphy_out>; }; }; @@ -141,7 +141,7 @@ reg = <1>; pmic_glink_con1_ss: endpoint { - remote-endpoint = <&mdss0_dp1_out>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; @@ -264,6 +264,11 @@ }; reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -518,6 +523,15 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; + }; +}; + &mdss0 { status = "okay"; }; @@ -528,7 +542,7 @@ &mdss0_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con0_ss>; + remote-endpoint = <&usb_0_qmpphy_dp_in>; }; &mdss0_dp1 { @@ -537,7 +551,7 @@ &mdss0_dp1_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con1_ss>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss0_dp3 { @@ -1114,9 +1128,19 @@ vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + orientation-switch; + status = "okay"; }; +&usb_0_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp0_out>; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + &usb_0_role_switch { remote-endpoint = <&pmic_glink_con0_hs>; }; @@ -1141,9 +1165,19 @@ vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + orientation-switch; + status = "okay"; }; +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp1_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + &usb_1_role_switch { remote-endpoint = <&pmic_glink_con1_hs>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index cc4aef21e617..ac0596dfdbc4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,7 +6,9 @@ #include #include +#include #include +#include #include #include #include @@ -777,6 +779,36 @@ ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; + ethernet0: ethernet@20000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + iommus = <&apps_smmu 0x4c0 0xf>; + power-domains = <&gcc EMAC_0_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,gcc-sc8280xp"; reg = <0x0 0x00100000 0x0 0x1f0000>; @@ -2310,6 +2342,180 @@ reg = <0x0 0x01fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-690.0", "qcom,adreno"; + + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + opp-level = ; + opp-peak-kBps = <451000>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-547000000 { + opp-hz = /bits/ 64 <547000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-606000000 { + opp-hz = /bits/ 64 <606000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-690000000 { + opp-hz = /bits/ 64 <690000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&gpu_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sc8280xp-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + + power-domains = <&rpmhpd SC8280XP_GFX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpu_smmu: iommu@3da0000 { + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + usb_0_hsphy: phy@88e5000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -2530,6 +2736,8 @@ interrupts = ; clocks = <&rxmacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "RX"; qcom,din-ports = <0>; @@ -2604,6 +2812,8 @@ interrupts = ; clocks = <&wsamacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; label = "WSA"; qcom,din-ports = <2>; @@ -2626,6 +2836,13 @@ status = "disabled"; }; + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x032a9000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; @@ -2635,6 +2852,8 @@ clocks = <&txmacro>; clock-names = "iface"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "TX"; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2828,6 +3047,56 @@ }; }; + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0 0x033e0000 0 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sdc2: mmc@8804000 { + compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4e0 0x0>; + power-domains = <&rpmhpd SC8280XP_CX>; + operating-points-v2 = <&sdc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; + }; + }; + }; + usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088eb000 0 0x4000>; @@ -2848,6 +3117,23 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_0_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_hsphy: phy@8902000 { @@ -2884,6 +3170,23 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint {}; + }; + }; }; mdss1_dp0_phy: phy@8909a00 { @@ -3908,7 +4211,7 @@ #size-cells = <2>; ranges; - gic-its@17a40000 { + msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; @@ -4720,6 +5023,36 @@ status = "disabled"; }; + + ethernet1: ethernet@23000000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + iommus = <&apps_smmu 0x40 0xf>; + power-domains = <&gcc EMAC_1_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; }; sound: sound { diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 7459525d9982..0b23d5bb3f26 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -134,7 +134,7 @@ reg = <0>; adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -183,25 +183,25 @@ }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l1a_1p225>; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&adv7533_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vcca-supply = <&vreg_l1b_0p925>; }; -&mdss { - status = "okay"; -}; - &mmss_smmu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 2ca713a3902a..3033723fc6ff 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -138,11 +138,6 @@ no-map; }; - reserved@85800000 { - reg = <0x00 0x85800000 0x00 0x3700000>; - no-map; - }; - cont_splash_mem: splash@9d400000 { reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; no-map; @@ -256,6 +251,10 @@ linux,code = ; }; +&qhee_code { + reg = <0x00 0x85800000 0x00 0x3700000>; +}; + &qusb2phy0 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index eaead2f7beb4..bba0f366ef03 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -550,7 +550,7 @@ }; }; - soc { + soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -1463,8 +1463,8 @@ <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, <0>, <0>, <0>, @@ -1536,7 +1536,7 @@ port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; }; @@ -1572,7 +1572,7 @@ }; }; - dsi0: dsi@c994000 { + mdss_dsi0: dsi@c994000 { compatible = "qcom,sdm660-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c994000 0x400>; @@ -1586,8 +1586,8 @@ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE0_CLK>, @@ -1608,7 +1608,7 @@ "pixel", "core"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1618,20 +1618,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@c994400 { + mdss_dsi0_phy: phy@c994400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c994400 0x100>, <0x0c994500 0x300>, @@ -1894,7 +1894,7 @@ }; }; - camss: camss@ca00000 { + camss: camss@ca00020 { compatible = "qcom,sdm660-camss"; reg = <0x0ca00020 0x10>, <0x0ca30000 0x100>, diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 70e683b7e4fc..301eca9a4f31 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -4,8 +4,10 @@ */ /dts-v1/; +#include #include "sdm632.dtsi" #include "pm8953.dtsi" +#include "pmi632.dtsi" / { model = "Fairphone 3"; @@ -83,6 +85,33 @@ linux,code = ; }; +&pmi632_lpg { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index f0f27fc12c18..f89b27c99f40 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -148,14 +148,14 @@ port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; &mdss { - dsi1: dsi@c996000 { + mdss_dsi1: dsi@c996000 { compatible = "qcom,sdm660-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c996000 0x400>; @@ -170,8 +170,8 @@ assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE1_CLK>, @@ -192,7 +192,7 @@ "pixel", "core"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -202,20 +202,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@c996400 { + mdss_dsi1_phy: phy@c996400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c996400 0x100>, <0x0c996500 0x300>, @@ -239,10 +239,10 @@ <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index b61e13db89bd..a1c207c0266d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1282,6 +1282,7 @@ , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index d05c511718df..1ce413263b7f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -636,25 +636,6 @@ }; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - edp_brij_i2c: &i2c3 { status = "okay"; clock-frequency = <400000>; @@ -687,7 +668,7 @@ edp_brij_i2c: &i2c3 { port@0 { reg = <0>; sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -767,6 +748,25 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + /* * Cheza fw does not properly program the GPU aperture to allow the * GPU to update the SMMU pagetables for context switches. Work diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index e14fe9bbb386..d6b464cb61d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -415,25 +415,6 @@ firmware-name = "qcom/sdm845/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - &gcc { protected-clocks = , , @@ -489,7 +470,15 @@ reg = <0>; lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&mdss_dsi1_out>; }; }; @@ -520,6 +509,53 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + qcom,master-dsi; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l1a_0p875>; + status = "okay"; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; @@ -649,10 +685,6 @@ }; }; -&pmi8998_rradc { - status = "okay"; -}; - /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { dai@22 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index d1440b790fa6..b2d4336e764b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -417,80 +417,6 @@ firmware-name = "qcom/sdm845/cdsp.mdt"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - qcom,dual-dsi-mode; - qcom,master-dsi; - - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_0>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel@0 { - compatible = "truly,nt35597-2K-display"; - reg = <0>; - vdda-supply = <&vreg_l14a_1p88>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - truly_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - truly_in_1: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -&dsi1 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi1_1p2>; - - qcom,dual-dsi-mode; - - /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_1>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi1_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi1_pll>; -}; - &gcc { protected-clocks = , , @@ -527,6 +453,80 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + qcom,dual-dsi-mode; + qcom,master-dsi; + + ports { + port@1 { + endpoint { + remote-endpoint = <&truly_in_0>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel@0 { + compatible = "truly,nt35597-2K-display"; + reg = <0>; + vdda-supply = <&vreg_l14a_1p88>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + truly_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + truly_in_1: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&mdss_dsi1 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi1_1p2>; + + qcom,dual-dsi-mode; + + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&truly_in_1>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi1_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi1_pll>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 5c384345c05d..122c7128dea9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -336,44 +336,6 @@ firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - /* - * Both devices use different panels but all other properties - * are common. Compatible line is declared in device dts. - */ - display_panel: panel@0 { - status = "disabled"; - - reg = <0>; - - vddio-supply = <&vreg_l14a_1p88>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - &gcc { protected-clocks = , , @@ -452,6 +414,44 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + /* + * Both devices use different panels but all other properties + * are common. Compatible line is declared in device dts. + */ + display_panel: panel@0 { + status = "disabled"; + + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + /* Modem/wifi */ &mss_pil { status = "okay"; @@ -480,7 +480,7 @@ }; }; -&pmi8998_rradc { +&pmi8998_charger { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 6cdda971bb4b..623a826b18a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -51,6 +51,10 @@ }; }; +&pmi8998_charger { + monitored-battery = <&battery>; +}; + &sound { model = "OnePlus 6"; audio-routing = "RX_BIAS", "MCLK", diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index d82c0d4407f0..9471ada0d6ad 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -47,6 +47,10 @@ "AMIC5", "MIC BIAS3"; }; +&pmi8998_charger { + monitored-battery = <&battery>; +}; + /* * The TFA9894 codec is currently unsupported. * We need to delete the node to allow the soundcard diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 0ad891348e0c..dce0141f3719 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -411,44 +411,6 @@ firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - panel@0 { - compatible = "visionox,rm69299-shift"; - status = "okay"; - reg = <0>; - vdda-supply = <&vreg_l14a_1p88>; - vdd3p3-supply = <&vreg_l28a_3p0>; - - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - port { - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in_0>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - &gcc { protected-clocks = , , @@ -494,6 +456,10 @@ }; }; +&i2c10 { + /* SMB1355@0x0C */ +}; + &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; @@ -505,6 +471,44 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + panel@0 { + compatible = "visionox,rm69299-shift"; + status = "okay"; + reg = <0>; + vdda-supply = <&vreg_l14a_1p88>; + vdd3p3-supply = <&vreg_l28a_3p0>; + + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; @@ -522,6 +526,12 @@ }; }; +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; +}; + &pm8998_resin { linux,code = ; status = "okay"; @@ -554,6 +564,28 @@ }; }; +&pmi8998_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>; + led-max-microamp = <100000>; + flash-max-microamp = <1100000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>; + led-max-microamp = <100000>; + flash-max-microamp = <1100000>; + flash-max-timeout-us = <1280000>; + }; +}; + &qup_uart9_rx { drive-strength = <2>; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 420ffede3e80..3bc187a066ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -368,43 +368,6 @@ status = "okay"; }; -&dsi0 { - vdda-supply = <&vreg_l26a_1p2>; - status = "okay"; - - panel: panel@0 { - /* The compatible is assigned in device DTs. */ - reg = <0>; - - backlight = <&pmi8998_wled>; - vddio-supply = <&vreg_l14a_1p8>; - vsp-supply = <&lab>; - vsn-supply = <&ibb>; - panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; - pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; - pinctrl-names = "default", "sleep"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vdds-supply = <&vreg_l1a_0p9>; - status = "okay"; -}; - &gcc { protected-clocks = , , @@ -515,6 +478,43 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l26a_1p2>; + status = "okay"; + + panel: panel@0 { + /* The compatible is assigned in device DTs. */ + reg = <0>; + + backlight = <&pmi8998_wled>; + vddio-supply = <&vreg_l14a_1p8>; + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1a_0p9>; + status = "okay"; +}; + &pm8998_gpios { focus_n: focus-n-state { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 5ed975cc6ecb..9d6faeb65624 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -115,6 +115,14 @@ }; }; + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + vreg_s4a_1p8: vreg-s4a-1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_s4a_1p8"; @@ -223,39 +231,6 @@ firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - display_panel: panel@0 { - reg = <0>; - vddio-supply = <&vreg_l14a_1p8>; - vddpos-supply = <&lab>; - vddneg-supply = <&ibb>; - - backlight = <&pmi8998_wled>; - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - status = "disabled"; - - port { - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in_0>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - &gcc { protected-clocks = , , @@ -298,6 +273,39 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + display_panel: panel@0 { + reg = <0>; + vddio-supply = <&vreg_l14a_1p8>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + backlight = <&pmi8998_wled>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + status = "disabled"; + + port { + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; @@ -341,12 +349,14 @@ qcom,cabc; }; -&pm8998_resin { - linux,code = ; +&pmi8998_charger { + monitored-battery = <&battery>; + status = "okay"; }; -&pmi8998_rradc { +&pm8998_resin { + linux,code = ; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 8ae0ffccaab2..6db12abaa88d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -373,44 +373,6 @@ status = "okay"; }; -&dsi0 { - vdda-supply = <&vdda_mipi_dsi0_1p2>; - status = "okay"; - - display_panel: panel@0 { - compatible = "jdi,fhd-nt35596s"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - vddio-supply = <&vreg_l14a_1p8>; - backlight = <&pmi8998_wled>; - vddpos-supply = <&lab>; - vddneg-supply = <&ibb>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active>; - pinctrl-1 = <&sde_dsi_suspend>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vdds-supply = <&vdda_mipi_dsi0_pll>; - status = "okay"; -}; - &gcc { protected-clocks = , , @@ -483,6 +445,7 @@ }; rmi4-f12@12 { + reg = <0x12>; syna,rezero-wait-ms = <0xc8>; syna,clip-x-high = <0x438>; syna,clip-y-high = <0x870>; @@ -504,6 +467,44 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + display_panel: panel@0 { + compatible = "jdi,fhd-nt35596s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + vddio-supply = <&vreg_l14a_1p8>; + backlight = <&pmi8998_wled>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>; + pinctrl-1 = <&sde_dsi_suspend>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + &mss_pil { firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdeb05e95674..02a6ea0b8b2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3899,6 +3899,7 @@ qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; reg = <0 0x088df000 0 0x600>; + iommus = <&apps_smmu 0x160 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; @@ -4238,7 +4239,7 @@ #reset-cells = <1>; }; - camss: camss@a00000 { + camss: camss@acb3000 { compatible = "qcom,sdm845-camss"; reg = <0 0x0acb3000 0 0x1000>, @@ -4509,14 +4510,14 @@ port@1 { reg = <1>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; @@ -4616,7 +4617,7 @@ }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -4638,12 +4639,12 @@ "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -4656,20 +4657,20 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -4688,7 +4689,7 @@ status = "disabled"; }; - dsi1: dsi@ae96000 { + mdss_dsi1: dsi@ae96000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; @@ -4710,12 +4711,12 @@ "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -4728,20 +4729,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, @@ -4903,10 +4904,10 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", @@ -5137,6 +5138,7 @@ , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -5221,7 +5223,7 @@ }; slimbam: dma-controller@17184000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; num-channels = <31>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 1326c171fe72..cfbc4fc1eba9 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -311,25 +311,6 @@ status = "okay"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - &gcc { protected-clocks = , , @@ -422,7 +403,7 @@ port@0 { reg = <0>; sn65dsi86_in_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -475,6 +456,25 @@ status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts new file mode 100644 index 000000000000..cbe5cdf5a228 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdx75.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX75 IDP"; + compatible = "qcom,sdx75-idp", "qcom,sdx75"; + + aliases { + serial0 = &uart1; + }; +}; + +&chosen { + stdout-path = "serial0:115200n8"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <110 6>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi new file mode 100644 index 000000000000..21d5d55da5eb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX75 SoC device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_100>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_200>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_300>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <235>; + exit-latency-us = <428>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + CPU_RAIL_OFF: cpu-rail-sleep-1 { + compatible = "arm,idle-state"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; + entry-latency-us = <2761>; + exit-latency-us = <3964>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_2: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <2793>; + exit-latency-us = <4023>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sdx75", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + hyp_elf_package_mem: hyp-elf-package@80800000 { + reg = <0x0 0x80800000 0x0 0x200000>; + no-map; + }; + + access_control_db_mem: access-control-db@81380000 { + reg = <0x0 0x81380000 0x0 0x80000>; + no-map; + }; + + qteetz_mem: qteetz@814e0000 { + reg = <0x0 0x814e0000 0x0 0x2a0000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@81780000 { + reg = <0x0 0x81780000 0x0 0xa00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@87a00000 { + reg = <0x0 0x87a00000 0x0 0x1c0000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@87c00000 { + reg = <0x0 0x87c00000 0x0 0x100000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@87d00000 { + reg = <0x0 0x87d00000 0x0 0x40000>; + no-map; + }; + + xbl_sc_mem: xbl-sc@87d40000 { + reg = <0x0 0x87d40000 0x0 0x40000>; + no-map; + }; + + modem_efs_shared_mem: modem-efs-shared@87d80000 { + reg = <0x0 0x87d80000 0x0 0x10000>; + no-map; + }; + + aop_image_mem: aop-image@87e00000 { + reg = <0x0 0x87e00000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@87e20000 { + reg = <0x0 0x87e20000 0x0 0xc0000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@87ee0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87ee0000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@87f00000 { + reg = <0x0 0x87f00000 0x0 0x20000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@87f20000 { + reg = <0x0 0x87f20000 0x0 0x10000>; + no-map; + }; + + secdata_mem: secdata@87f30000 { + reg = <0x0 0x87f30000 0x0 0x1000>; + no-map; + }; + + tme_crashdump_mem: tme-crashdump@87f31000 { + reg = <0x0 0x87f31000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@87f71000 { + reg = <0x0 0x87f71000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@87f75000 { + reg = <0x0 0x87f75000 0x0 0x10000>; + no-map; + }; + + qdss_mem: qdss@88800000 { + reg = <0x0 0x88800000 0x0 0x300000>; + no-map; + }; + + audio_heap_mem: audio-heap@88b00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88b00000 0x0 0x400000>; + no-map; + }; + + mpss_dsmharq_mem: mpss-dsmharq@88f00000 { + reg = <0x0 0x88f00000 0x0 0x5080000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { + reg = <0x0 0x8df80000 0x0 0x80000>; + no-map; + }; + + mpssadsp_mem: mpssadsp@8e000000 { + reg = <0x0 0x8e000000 0x0 0xf400000>; + no-map; + }; + + gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { + reg = <0x0 0xbdb00000 0x0 0x2000000>; + no-map; + }; + + smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { + reg = <0x0 0xbfb00000 0x0 0x100000>; + no-map; + }; + + hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x0 0x0080000 0x0 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart1: serial@984000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qupv3_se1_2uart_active>; + pinctrl-1 = <&qupv3_se1_2uart_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdx75-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 147 52>, + <52 266 32>, + <84 500 59>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0 0x0f000000 0x0 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { + tx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + drive-strength= <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + drive-strength= <2>; + bias-disable; + }; + }; + + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, + <0x0 0x17260000 0x0 0x80000>; + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + power-domains = <&CLUSTER_PD>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index a1f0622db5a0..75951fd439df 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -242,6 +242,9 @@ &usb_dwc3 { maximum-speed = "high-speed"; dr_mode = "peripheral"; + + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; }; &usb_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts new file mode 100644 index 000000000000..3ce9875e932c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Dang Huynh + */ + +/dts-v1/; + +#include "sm6115.dtsi" +#include "pm6125.dtsi" +#include + +/ { + model = "F(x)tec Pro1X (QX1050)"; + compatible = "fxtec,pro1x", "qcom,sm6115"; + chassis-type = "handset"; + + qcom,msm-id = ; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x5c000000 0x0 (1080 * 2160 * 4)>; + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&dispcc { + /* HACK: disable until a panel driver is ready to retain simplefb */ + status = "disabled"; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s6a: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + pm6125_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + pm6125_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + pm6125_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + pm6125_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + pm6125_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + regulator-allow-set-load; + }; + + pm6125_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + pm6125_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + pm6125_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + pm6125_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + pm6125_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l23a: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + regulator-allow-set-load; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&pm6125_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&pm6125_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&pm6125_l4a>; + vdda-pll-supply = <&pm6125_l12a>; + vddp-ref-clk-supply = <&pm6125_l18a>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + +&usb_hsphy { + vdd-supply = <&pm6125_l4a>; + vdda-pll-supply = <&pm6125_l12a>; + vdda-phy-dpdm-supply = <&pm6125_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 43f31c1b9d5a..55118577bf92 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -47,6 +47,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -64,6 +66,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -76,6 +80,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -88,6 +94,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; CPU4: cpu@100 { @@ -100,6 +108,8 @@ dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -117,6 +127,8 @@ enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; }; CPU6: cpu@102 { @@ -129,6 +141,8 @@ enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; }; CPU7: cpu@103 { @@ -141,6 +155,8 @@ enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; }; cpu-map { @@ -180,6 +196,68 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <297>; + exit-latency-us = <324>; + min-residency-us = <1110>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { + /* GDHS */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40000022>; + entry-latency-us = <360>; + exit-latency-us = <421>; + min-residency-us = <782>; + }; + + CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { + /* Power Collapse */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + + CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { + /* GDHS */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40000042>; + entry-latency-us = <314>; + exit-latency-us = <345>; + min-residency-us = <660>; + }; + + CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { + /* Power Collapse */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <640>; + exit-latency-us = <1654>; + min-residency-us = <8094>; + }; + }; }; firmware { @@ -203,6 +281,64 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_0_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; + }; + + CLUSTER_1_PD: power-domain-cpu-cluster1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; + }; }; reserved_memory: reserved-memory { @@ -663,6 +799,62 @@ status = "disabled"; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = ; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + }; + + usb_qmpphy: phy@1615000 { + compatible = "qcom,sm6115-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; reg = <0x0 0x01b40000 0x0 0x7000>; @@ -700,7 +892,7 @@ #interrupt-cells = <4>; }; - tsens0: thermal-sensor@4410000 { + tsens0: thermal-sensor@4411000 { compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ <0x0 0x04410000 0x0 0x8>; /* SROT */ @@ -1113,8 +1305,8 @@ compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; - phys = <&usb_hsphy>; - phy-names = "usb2-phy"; + phys = <&usb_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index ea3340d31110..81fdcaf48926 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -306,6 +306,9 @@ &usb_dwc3 { maximum-speed = "high-speed"; dr_mode = "peripheral"; + + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; }; &usb_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index b1038eb8cebc..a7f4aeae9c1a 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -138,7 +138,7 @@ pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; - adc-chan@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -146,7 +146,7 @@ label = "rf_pa0_therm"; }; - adc-chan@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -154,7 +154,7 @@ label = "quiet_therm"; }; - adc-chan@52 { + channel@52 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -162,7 +162,7 @@ label = "camera_flash_therm"; }; - adc-chan@54 { + channel@54 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 2aa093d16858..a596baa6ce3e 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -366,7 +366,7 @@ hwlocks = <&tcsr_mutex 3>; }; - soc { + soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00 0xffffffff>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ad34301f6cdd..30e77010aed5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -56,6 +56,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -84,6 +86,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -107,6 +111,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -130,6 +136,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -153,6 +161,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -176,6 +186,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -199,6 +211,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -222,6 +236,8 @@ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -266,6 +282,76 @@ }; }; }; + + domain-idle-states { + CLUSTER_SLEEP_PC: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + + cpu_idle_states: idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; }; firmware { @@ -387,6 +473,25 @@ }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -395,6 +500,61 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_PC + &CLUSTER_SLEEP_CX_RET + &CLUSTER_AOSS_SLEEP>; + }; }; reserved_memory: reserved-memory { @@ -750,6 +910,22 @@ status = "disabled"; }; + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; + interrupts = ; + power-domains = <&rpmhpd SM6350_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; @@ -1735,6 +1911,34 @@ drive-strength = <2>; bias-pull-up; }; + + qup_uart1_cts: qup-uart1-cts-default-state { + pins = "gpio61"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_rts: qup-uart1-rts-default-state { + pins = "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart1_rx: qup-uart1-rx-default-state { + pins = "gpio64"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_tx: qup-uart1-tx-default-state { + pins = "gpio63"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; }; apps_smmu: iommu@15000000 { @@ -1900,28 +2104,6 @@ }; }; - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_fw_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x20 0x1>; - qcom,msa-fixed-perm; - status = "disabled"; - }; - apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; label = "apps_rsc"; @@ -1936,6 +2118,7 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm6350-rpmh-clk"; @@ -2019,6 +2202,28 @@ #freq-domain-cells = <1>; #clock-cells = <1>; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_fw_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x20 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f8d9c34d3b2f..3dba34210a6d 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1276,6 +1277,42 @@ }; }; + adreno_smmu: iommu@5940000 { + compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05940000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "bus"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mss: remoteproc@6000000 { compatible = "qcom,sm6375-mpss-pas"; reg = <0 0x06000000 0 0x4040>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 7ae6aba5d2ec..e3dc49951523 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -31,6 +31,7 @@ aliases { serial0 = &uart9; + serial1 = &uart1; }; chosen { @@ -524,6 +525,39 @@ }; }; +&qup_uart1_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart1_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart1_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart1_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -561,6 +595,75 @@ &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; + + qup_uart1_sleep_cts: qup-uart1-sleep-cts-state { + pins = "gpio61"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart1_sleep_rts: qup-uart1-sleep-rts-state { + pins = "gpio62"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart1_sleep_rx: qup-uart1-sleep-rx-state { + pins = "gpio64"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart1_sleep_tx: qup-uart1-sleep-tx-state { + pins = "gpio63"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; +}; + +&uart1 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 64 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart1_sleep_cts>, <&qup_uart1_sleep_rts>, <&qup_uart1_sleep_tx>, <&qup_uart1_sleep_rx>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + vddio-supply = <&vreg_l11a>; + vddxo-supply = <&vreg_l7a>; + vddrf-supply = <&vreg_l2e>; + vddch0-supply = <&vreg_l10e>; + swctrl-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + + max-speed = <3200000>; + }; }; &uart9 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 47e2430991ca..baafea53770b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "sm8150.dtsi" #include "pm8150.dtsi" @@ -81,6 +82,66 @@ }; }; + cam0_vdig_vreg: cam0-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera0_vdig_vreg"; + gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&main_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam1_vdig_vreg: cam1-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera1_vdig_vreg"; + gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&sub_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam2_vdig_vreg: cam2-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera2_vdig_vreg"; + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&chat_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam3_vdig_vreg: cam3-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera3_vdig_vreg"; + gpio = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&supwc_pwr_en>; + pinctrl-names = "default"; + }; + + cam_vmdr_vreg: cam-vmdr-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vmdr_vreg"; + gpio = <&pm8150l_gpios 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&main_cam_pwr_vmdr_en>; + pinctrl-names = "default"; + }; + + rgbcir_vreg: rgbcir-regulator { + compatible = "regulator-fixed"; + regulator-name = "rgbcir_vreg"; + gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rgbc_ir_pwr_en>; + pinctrl-names = "default"; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -456,6 +517,17 @@ }; &pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "", + "NC", + "NC", + "", + "NC", + "SUPWC_PWR_EN", + "", + "NC", + "NC"; /* GPIO_10 */ + vol_down_n: vol-down-n-state { pins = "gpio1"; function = "normal"; @@ -463,9 +535,31 @@ bias-pull-up; input-enable; }; + + supwc_pwr_en: supwc-pwr-en-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = <1>; + power-source = <1>; + drive-push-pull; + output-low; + }; }; &pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "TS_VDDH_EN", + "LCD_ID", + "", + "NC", /* GPIO_10 */ + "NC", + "RF_ID"; + snapshot_n: snapshot-n-state { pins = "gpio1"; function = "normal"; @@ -483,6 +577,30 @@ }; }; +&pm8150l_gpios { + gpio-line-names = "TS_VDDIO_EN", /* GPIO_1 */ + "NC", + "MAIN_CAM_PWR_VMDR_EN", + "NC", + "", + "NC", + "NC", + "FP_LDO_EN", + "NC", + "NC", /* GPIO_10 */ + "NC", + "NC"; + + main_cam_pwr_vmdr_en: main-cam-pwr-vmdr-en-state { + pins = "gpio3"; + function = "normal"; + qcom,drive-strength = ; + power-source = <0>; + drive-push-pull; + output-low; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -500,8 +618,225 @@ status = "okay"; }; +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <126 4>; + gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", + "NFC_ESE_SPI_CS_N", + "NC", + "NC", + "DISP_RESET_N", + "DEBUG_GPIO0", + "MDP_VSYNC_P", + "TS_I2C_SDA", + "TS_I2C_SCL", /* GPIO_10 */ + "CAM_SOF", + "CAM2_RST_N", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "NC", + "MAIN_CAM_PWR_EN", + "CAM3_RST_N", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "NC", + "CAM0_RST_N", + "RGBC_IR_PWR_EN", + "CAM1_RST_N", /* GPIO_30 */ + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "NC", + "DEBUG_GPIO1", + "RGBC_IR_INT", + "USB_CC_DIR", + "NC", + "NC", /* GPIO_40 */ + "NFC_EN", + "NFC_ESE_PWR_REQ", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "NFC_IRQ", + "NFC_DWL_REQ", + "UIM2_DETECT_EN", + "WLAN_SW_CTRL", /* GPIO_50 */ + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "NC", + "TS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "HW_ID_0", + "NC", /* GPIO_60 */ + "QLINK_REQUEST", + "QLINK_ENABLE", + "WMSS_RESET_N", + "SDM_GRFC_8", + "WDOG_DISABLE", + "NC", + "NC", + "PA_INDICATOR_OR", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", /* GPIO_70 */ + "SDM_RFFE0_DATA", + "SDM_RFFE0_CLK", + "SDM_RFFE1_DATA", + "SDM_RFFE1_CLK", + "SDM_RFFE2_DATA", + "SDM_RFFE2_CLK", + "SDM_RFFE3_DATA", + "SDM_RFFE3_CLK", + "SUB_CAM_PWR_EN", + "FP_RESET_N", /* GPIO_80 */ + "NC", + "NC", + "NC", + "NC", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "DVDT_WRT_DET_AND", + "NC", + "NC", + "NC", /* GPIO_90 */ + "NC", + "NC", + "NC", + "NC", + "UDON_SWITCH_SEL", + "SD_CARD_DET_N", + "NC", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "USB_AUDIO_EN1", /* GPIO_100 */ + "DISP_ERR_FG", + "NC", + "NC", + "NC", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_DET", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", + "UIM1_PRESENT", + "NFC_CLK_REQ", + "SW_SERVICE", + "NC", + "RF_ID_EXTENSION", + "ALS_PROX_INT_N", + "FP_INT", + "DVDT_WRT_DET_OR", + "BAROMETER_INT", /* GPIO_120 */ + "ACC_COVER_OPEN", + "TS_INT_N", + "CODEC_INT1_N", + "CODEC_INT2_N", + "TX_GTR_THRES_IN", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "NC", /* GPIO_130 */ + "DVDT_ENABLE", + "ACCEL_INT", + "NC", + "MAG_INT_N", + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "HW_ID_1", + "NC", /* GPIO_140 */ + "NC", + "NC", + "CODEC_RST_N", + "CDC_SPI_MISO", + "CDC_SPI_MOSI", + "CDC_SPI_SCLK", + "CDC_SPI_CS_N", + "NC", + "LPASS_SLIMBUS_CLK", + "LPASS_SLIMBUS_DATA0", /* GPIO_150 */ + "LPASS_SLIMBUS_DATA1", + "USB_AUDIO_EN2", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "COMPASS_I2C_SDA", + "COMPASS_I2C_SCL", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", /* GPIO_160 */ + "SSC_SENSOR_I2C_SDA", + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "SSC_UART_1_TX", + "SSC_UART_1_RX", + "WL_CMD_CLK_CHAIN0", + "WL_CMD_DATA_CHAIN0", /* GPIO_170 */ + "WL_CMD_CLK_CHAIN1", + "WL_CMD_DATA_CHAIN1", + "WL_BT_COEX_CLK", + "WL_BT_COEX_DATA"; + + main_cam_pwr_en: main-cam-pwr-en-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + chat_cam_pwr_en: chat-cam-pwr-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + rgbc_ir_pwr_en: rgbc-ir-pwr-en-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + sub_cam_pwr_en: sub-cam-pwr-en-state { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart2 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 27dcda0d4288..18c822abdb88 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -55,8 +55,8 @@ next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -84,8 +84,8 @@ next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -108,8 +108,8 @@ next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -132,8 +132,8 @@ next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -156,8 +156,8 @@ next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -180,8 +180,8 @@ next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -204,8 +204,8 @@ next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -228,8 +228,8 @@ next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -1362,14 +1362,11 @@ uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a84000 0x0 0x4000>; - reg-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart9_default>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1763,49 +1760,49 @@ config_noc: interconnect@1500000 { compatible = "qcom,sm8150-config-noc"; reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8150-system-noc"; reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163a000 { compatible = "qcom,sm8150-mc-virt"; reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8150-aggre1-noc"; reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8150-aggre2-noc"; reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1720000 { compatible = "qcom,sm8150-compute-noc"; reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8150-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1826,7 +1823,7 @@ }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8150"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -1921,7 +1918,7 @@ }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8150"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, @@ -2097,6 +2094,36 @@ }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x502 0x0641>, + <&apps_smmu 0x504 0x0011>, + <&apps_smmu 0x506 0x0011>, + <&apps_smmu 0x508 0x0011>, + <&apps_smmu 0x512 0x0000>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x502 0x0641>, + <&apps_smmu 0x504 0x0011>, + <&apps_smmu 0x506 0x0011>, + <&apps_smmu 0x508 0x0011>, + <&apps_smmu 0x512 0x0000>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; @@ -3520,14 +3547,14 @@ dc_noc: interconnect@9160000 { compatible = "qcom,sm8150-dc-noc"; reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9680000 { compatible = "qcom,sm8150-gem-noc"; reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3568,6 +3595,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3617,6 +3648,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; @@ -3632,7 +3667,7 @@ camnoc_virt: interconnect@ac00000 { compatible = "qcom,sm8150-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3641,8 +3676,8 @@ reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; @@ -3986,7 +4021,7 @@ }; apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -4307,7 +4342,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - #interconnect-cells = <1>; + #interconnect-cells = <2>; }; cpufreq_hw: cpufreq@18323000 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 2f22d348d45d..8ab82bacba81 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -26,9 +26,10 @@ framebuffer: framebuffer@9c000000 { compatible = "simple-framebuffer"; reg = <0 0x9c000000 0 0x2300000>; - width = <1644>; - height = <3840>; - stride = <(1644 * 4)>; + /* pdx203 BL initializes in 2.5k mode, not 4k */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; format = "a8r8g8b8"; /* * That's a lot of clocks, but it's necessary due @@ -672,3 +673,8 @@ vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p9>; }; + +&venus { + firmware-name = "qcom/sm8250/Sony/edo/venus.mbn"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 8af6a0120a50..b841ea9192ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -470,76 +470,6 @@ status = "okay"; }; -&dsi0 { - vdda-supply = <&vreg_l9a_1p2>; - qcom,dual-dsi-mode; - qcom,sync-dual-dsi; - qcom,master-dsi; - status = "okay"; - - display_panel: panel@0 { - reg = <0>; - vddio-supply = <&vreg_l14a_1p88>; - reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; - backlight = <&backlight>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1{ - reg = <1>; - - panel_in_1: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - - }; - }; -}; - -&dsi0_out { - data-lanes = <0 1 2>; - remote-endpoint = <&panel_in_0>; -}; - -&dsi0_phy { - vdds-supply = <&vreg_l5a_0p88>; - phy-type = ; - status = "okay"; -}; - -&dsi1 { - vdda-supply = <&vreg_l9a_1p2>; - qcom,dual-dsi-mode; - qcom,sync-dual-dsi; - /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - status = "okay"; -}; - -&dsi1_out { - data-lanes = <0 1 2>; - remote-endpoint = <&panel_in_1>; -}; - -&dsi1_phy { - vdds-supply = <&vreg_l5a_0p88>; - phy-type = ; - status = "okay"; -}; - &gmu { status = "okay"; }; @@ -608,6 +538,75 @@ status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + qcom,master-dsi; + status = "okay"; + + display_panel: panel@0 { + reg = <0>; + vddio-supply = <&vreg_l14a_1p88>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + + panel_in_1: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_0>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + status = "okay"; +}; + +&mdss_dsi1_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_1>; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7bea916900e2..83ab6de459bc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -106,8 +106,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -137,8 +137,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -162,8 +162,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -187,8 +187,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -212,8 +212,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -237,8 +237,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -262,8 +262,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -287,8 +287,8 @@ power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -1789,49 +1789,49 @@ config_noc: interconnect@1500000 { compatible = "qcom,sm8250-config-noc"; reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8250-system-noc"; reg = <0 0x01620000 0 0x1c200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163d000 { compatible = "qcom,sm8250-mc-virt"; reg = <0 0x0163d000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8250-aggre1-noc"; reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8250-aggre2-noc"; reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1733000 { compatible = "qcom,sm8250-compute-noc"; reg = <0 0x01733000 0 0xa180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8250-mmss-noc"; reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2232,6 +2232,38 @@ }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x592 0x0000>, + <&apps_smmu 0x598 0x0000>, + <&apps_smmu 0x599 0x0000>, + <&apps_smmu 0x59f 0x0000>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x596 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x592 0x0000>, + <&apps_smmu 0x598 0x0000>, + <&apps_smmu 0x599 0x0000>, + <&apps_smmu 0x59f 0x0000>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -3661,21 +3693,21 @@ dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { compatible = "qcom,sm8250-gem-noc"; reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sm8250-npu-noc"; reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3718,6 +3750,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3778,6 +3814,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; @@ -3805,8 +3845,8 @@ <&videocc VIDEO_CC_MVS0_CLK>; clock-names = "iface", "core", "vcodec0_core"; - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, - <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "cpu-cfg", "video-mem"; iommus = <&apps_smmu 0x2100 0x0400>; @@ -4090,10 +4130,10 @@ <&apps_smmu 0xc40 0x400>, <&apps_smmu 0xc41 0x400>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, - <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "cam_ahb", "cam_hf_0_mnoc", "cam_sf_0_mnoc", @@ -4150,8 +4190,8 @@ reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; @@ -4202,14 +4242,14 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; @@ -4239,7 +4279,7 @@ }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -4262,12 +4302,12 @@ "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -4280,14 +4320,14 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -4312,7 +4352,7 @@ }; }; - dsi0_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -4331,7 +4371,7 @@ status = "disabled"; }; - dsi1: dsi@ae96000 { + mdss_dsi1: dsi@ae96000 { compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; @@ -4354,12 +4394,12 @@ "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -4372,20 +4412,20 @@ port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, @@ -4411,10 +4451,10 @@ power-domains = <&rpmhpd SM8250_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", @@ -5254,7 +5294,7 @@ }; apps_smmu: iommu@15000000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; @@ -5639,7 +5679,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - #interconnect-cells = <1>; + #interconnect-cells = <2>; }; cpufreq_hw: cpufreq@18591000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 2ee1b121686a..61dd9663fabe 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -58,7 +58,15 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -326,6 +334,37 @@ }; }; +&i2c13 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + &i2c15 { clock-frequency = <400000>; status = "okay"; @@ -370,8 +409,19 @@ status = "okay"; }; -&mdss_mdp { +&mdss_dp { status = "okay"; + + ports { + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; }; &mpss { @@ -416,6 +466,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &qupv3_id_2 { status = "okay"; }; @@ -716,7 +770,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -732,6 +786,20 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p88>; + + orientation-switch; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; }; &usb_2 { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3efdc03ed0f1..88ef478cb5cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -907,7 +907,7 @@ }; }; - gpi_dma0: dma-controller@900000 { + gpi_dma0: dma-controller@9800000 { compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x09800000 0 0x60000>; interrupts = , @@ -1638,7 +1638,7 @@ status = "disabled"; }; - pcie1_phy: phy@1c0f000 { + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, @@ -1735,6 +1735,28 @@ }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm8350-ipa"; @@ -2140,7 +2162,7 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; - usb_1_qmpphy: phy@88e9000 { + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8350-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -2158,6 +2180,32 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_2_qmpphy: phy-wrapper@88eb000 { @@ -2256,6 +2304,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -2325,6 +2377,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index e931545a2cac..bc4c125d1832 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -114,9 +114,18 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; }; }; @@ -494,6 +503,37 @@ }; }; +&i2c5 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + &mdss { status = "okay"; }; @@ -513,8 +553,19 @@ status = "okay"; }; -&mdss_mdp { +&mdss_dp0 { status = "okay"; + + ports { + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; }; &pcie0 { @@ -766,7 +817,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -782,6 +833,20 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; + + orientation-switch; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; }; &vamacro { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d59ea8ee7111..5cd7296c7660 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -2053,6 +2054,32 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; remoteproc_slpi: remoteproc@2400000 { @@ -2581,6 +2608,18 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac15000 { compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; @@ -4002,31 +4041,43 @@ opp-level = ; }; - rpmhpd_opp_svs: opp5 { + rpmhpd_opp_low_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp6 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp6 { + rpmhpd_opp_svs_l0: opp7 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp8 { opp-level = ; }; - rpmhpd_opp_nom: opp7 { + rpmhpd_opp_svs_l2: opp9 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp10 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp8 { + rpmhpd_opp_nom_l1: opp11 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp9 { + rpmhpd_opp_nom_l2: opp12 { opp-level = ; }; - rpmhpd_opp_turbo: opp10 { + rpmhpd_opp_turbo: opp13 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp11 { + rpmhpd_opp_turbo_l1: opp14 { opp-level = ; }; }; @@ -4147,6 +4198,34 @@ }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x584 0x11>, + <&apps_smmu 0x588 0x0>, + <&apps_smmu 0x598 0x5>, + <&apps_smmu 0x59a 0x0>, + <&apps_smmu 0x59f 0x0>; + }; + + crypto: crypto@1de0000 { + compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x584 0x11>, + <&apps_smmu 0x588 0x0>, + <&apps_smmu 0x598 0x5>, + <&apps_smmu 0x59a 0x0>, + <&apps_smmu 0x59f 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -4227,6 +4306,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index e2b9bb6b1e27..ec86c5f38045 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -23,6 +23,32 @@ serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -61,6 +87,87 @@ }; }; + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-MTP"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -393,8 +500,22 @@ }; }; -&dispcc { - status = "okay"; +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &mdss { @@ -437,10 +558,6 @@ status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; @@ -535,6 +652,58 @@ clock-frequency = <32000>; }; +&swr0 { + status = "okay"; + + /* WSA8845 */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; + + /* WSA8845 */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 8>; @@ -565,6 +734,14 @@ drive-strength = <2>; bias-pull-down; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index d5a645ee2a61..ec4feee6837d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "sm8550.dtsi" #include "pm8010.dtsi" @@ -23,10 +24,167 @@ serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-QRD"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -359,6 +517,176 @@ }; }; +&gcc { + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + pinctrl-names = "default", "sleep"; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + status = "disabled"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -385,8 +713,96 @@ clock-frequency = <32000>; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart7 { @@ -417,13 +833,24 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&pm8550b_eusb2_repeater>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 558cbc430708..41d60af93692 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include #include @@ -1848,7 +1850,7 @@ }; cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; interrupts = ; #dma-cells = <1>; @@ -1858,7 +1860,7 @@ <&apps_smmu 0x481 0x0>; }; - crypto: crypto@1de0000 { + crypto: crypto@1dfa000 { compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0x0 0x01dfa000 0x0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; @@ -1960,6 +1962,17 @@ #reset-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8550-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; @@ -2394,6 +2407,18 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8550-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -2470,6 +2495,13 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2497,6 +2529,84 @@ }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -2680,8 +2790,8 @@ <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ @@ -2693,7 +2803,6 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; usb_1_hsphy: phy@88e3000 { @@ -2769,6 +2878,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + status = "disabled"; usb_1_dwc3: usb@a600000 { @@ -2883,7 +2996,7 @@ #interrupt-cells = <4>; }; - tlmm: pinctrl@f000000 { + tlmm: pinctrl@f100000 { compatible = "qcom,sm8550-tlmm"; reg = <0 0x0f100000 0 0x300000>; interrupts = ; @@ -3597,6 +3710,7 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -3617,43 +3731,63 @@ rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; - rpmhpd_opp_ret: opp1 { + rpmhpd_opp_ret: opp-16 { opp-level = ; }; - rpmhpd_opp_min_svs: opp2 { + rpmhpd_opp_min_svs: opp-48 { opp-level = ; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { opp-level = ; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { opp-level = ; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp-256 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp-320 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp-336 { opp-level = ; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp-384 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp-416 { opp-level = ; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi index 2d92b56ac94d..d0c9387ac17a 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -30,6 +30,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 1402abe80ea1..b7f63102f2dd 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi index fb864a139c97..4f805f576cef 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi index 05c9216a87ee..2efe5b25c83c 100644 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index bf4d9e917925..34802cc62983 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -88,11 +88,15 @@ l2: l2-cache { compatible = "cache"; next-level-cache = <&l3>; + cache-level = <2>; + cache-unified; }; l3: l3-cache { compatible = "cache"; + cache-level = <3>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f130165577a8..7114cbbd8713 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -79,10 +79,12 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c21b78685123..9065dc243428 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2359,8 +2359,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2371,6 +2371,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2386,8 +2388,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2398,6 +2400,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 82216ce7a92a..75776decd218 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2238,8 +2238,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2250,6 +2250,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2265,8 +2267,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2277,6 +2279,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 10abfde329d0..ad2e87b039ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1704,8 +1704,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1716,6 +1716,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 2828e05b40b3..2acf4067ab2f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2471,8 +2471,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2483,6 +2483,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2498,8 +2500,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2510,6 +2512,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 10b91e9733bf..6d15229d25ab 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2778,8 +2778,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2790,6 +2790,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2805,8 +2807,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2817,6 +2819,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 3ea8572e917f..17062ec506be 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2565,8 +2565,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2577,6 +2577,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2592,8 +2594,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2604,6 +2606,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d52cb0b67d80..d3f47da1b626 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2445,8 +2445,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2457,6 +2457,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2472,8 +2474,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2484,6 +2486,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9584115c6b17..c75820038491 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2423,8 +2423,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2435,6 +2435,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2450,8 +2452,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2462,6 +2464,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index c4ac28a0f716..5ed2daaca1f0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1386,7 +1386,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1399,6 +1400,8 @@ resets = <&cpg 319>; phys = <&pcie_phy>; phy-names = "pcie"; + iommu-map = <0 &ipmmu_vi0 5 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 4529e9b57c33..1be0b99c15ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1870,8 +1870,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1882,6 +1882,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index bf587a14ec19..4e67a0356497 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -943,6 +943,56 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", "renesas,rcar-gen4-scif", "renesas,scif"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 1315be5167b9..232910e07444 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -174,6 +174,76 @@ #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g044-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tgiv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tgiv1", "tgiu1", + "tgia2", "tgib2", "tgiv2", "tgiu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tgiv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tgiv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tgiv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tgiv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tgiv8", "tgiu8"; + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g044-ssi", "renesas,rz-ssi"; @@ -697,6 +767,59 @@ }; }; + dsi: dsi@10850000 { + compatible = "renesas,r9a07g044-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + + vspd: vsp@10870000 { + compatible = "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g044-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 000000000000..f983bdd3ea30 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2LC SMARC EVK with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso index d834bff9bda2..736c1e688cc8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera + * Device Tree overlay for the RZ/{G2L, V2L} SMARC EVK with OV5645 camera * connected to CSI and CRU enabled. * * Copyright (C) 2023 Renesas Electronics Corp. diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index cc11e5855d62..2eba3a8a100d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -174,6 +174,76 @@ #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g054-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tgiv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tgiv1", "tgiu1", + "tgia2", "tgib2", "tgiv2", "tgiu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tgiv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tgiv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tgiv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tgiv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tgiv8", "tgiu8"; + clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g054-ssi", "renesas,rz-ssi"; @@ -623,6 +693,139 @@ status = "disabled"; }; + cru: video@10830000 { + compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>, + <&cpg CPG_MOD R9A07G054_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + cruparallel: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + + dsi: dsi@10850000 { + compatible = "renesas,r9a07g054-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G054_MIPI_DSI_ARESET_N>, + <&cpg R9A07G054_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + + vspd: vsp@10870000 { + compatible = "renesas,r9a07g054-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g054-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g054-cpg"; reg = <0 0x11010000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso new file mode 120000 index 000000000000..0f175341d3ed --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1 @@ +r9a07g044l2-smarc-cru-csi-ov5645.dtso \ No newline at end of file diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index e180a955b6ac..2a158a954b2f 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -16,12 +16,91 @@ serial1 = &scif2; i2c3 = &i2c3; }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; }; &cpu_dai { sound-dai = <&ssi0>; }; +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index b6bd27196d88..6818fd49b2be 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -17,6 +17,23 @@ serial1 = &scif1; i2c2 = &i2c2; }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; }; #if (SW_SCIF_CAN || SW_RSPI_CAN) @@ -36,6 +53,68 @@ sound-dai = <&ssi0>; }; +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index efc80960380f..3885ef3454ff 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -10,6 +10,7 @@ aliases { serial1 = &hscif0; serial2 = &scif1; + serial3 = &hscif1; mmc2 = &sdhi3; }; @@ -114,6 +115,14 @@ status = "okay"; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -366,8 +375,13 @@ function = "hscif0"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; + groups = "scif1_data_b"; function = "scif1"; }; @@ -397,7 +411,6 @@ &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; - uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 2d585bbb8f3a..b7fb908eb92d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb @@ -69,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb @@ -85,6 +87,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb @@ -92,7 +96,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts new file mode 100644 index 000000000000..16a1958e4572 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-nanopi-r2c.dts" + +/ { + model = "FriendlyElec NanoPi R2C Plus"; + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io_33>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts index 369de5dc0ebd..c58fb7658d7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include +#include #include "rk3399pro-vmarc-som.dtsi" / { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts new file mode 100644 index 000000000000..b211973e36c2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-anbernic-rg353x.dtsi" + +/ { + model = "RG353PS"; + compatible = "anbernic,rg353ps", "rockchip,rk3566"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdmmc2; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; +}; + +&gpio_keys_control { + button-r1 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; +}; + +&panel { + compatible = "anbernic,rg353v-panel-v2"; + iovcc-supply = <&vcc3v3_lcd0_n>; + vcc-supply = <&vcc3v3_lcd0_n>; + /delete-property/ vdd-supply; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index 8fadd8afb190..a2c31d53b45b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -191,30 +191,30 @@ }; }; - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; + leds: pwm-leds { + compatible = "pwm-leds"; green_led: led-0 { color = ; default-state = "on"; function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; }; amber_led: led-1 { color = ; function = LED_FUNCTION_CHARGING; - gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - retain-state-suspended; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; }; red_led: led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; }; }; @@ -597,15 +597,6 @@ }; }; - gpio-led { - led_pins: led-pins { - rockchip,pins = - <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - joy-mux { joy_mux_en: joy-mux-en { rockchip,pins = @@ -654,10 +645,24 @@ vccio7-supply = <&vcc_3v3>; }; +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pwm5 { status = "okay"; }; +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; @@ -716,7 +721,7 @@ status = "okay"; bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8822cs-bt"; + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts new file mode 100644 index 000000000000..58ab7e9971db --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-fastrhino-r66s.dtsi" + +/ { + model = "Lunzn FastRhino R66S"; + compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568"; + + aliases { + mmc0 = &sdmmc0; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi new file mode 100644 index 000000000000..25e205632a68 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&status_led_pin>; + + status_led: led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-init-microvolt = <950000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + status_led_pin: status-led-pin { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts new file mode 100644 index 000000000000..e1fe5e442689 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-fastrhino-r66s.dtsi" + +/ { + model = "Lunzn FastRhino R68S"; + compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x4f>; + rx_delay = <0x26>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 61680c7ac489..abee88911982 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -613,6 +613,17 @@ #iommu-cells = <0>; }; + rga: rga@fdeb0000 { + compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; + reg = <0x0 0xfdeb0000 0x0 0x180>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3568_PD_RGA>; + }; + vepu: video-codec@fdee0000 { compatible = "rockchip,rk3568-vepu"; reg = <0x0 0xfdee0000 0x0 0x800>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts new file mode 100644 index 000000000000..e9d5a8bab581 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588j.dtsi" +#include "rk3588-edgeble-neu6b.dtsi" + +/ { + model = "Edgeble Neu6B IO Board"; + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi new file mode 100644 index 000000000000..1c5bcf1280b4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index b91af0204dbe..4b2d857ee219 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -49,6 +49,38 @@ }; }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + &gmac0 { clock_in_out = "output"; phy-handle = <&rgmii_phy>; @@ -123,6 +155,611 @@ status = "okay"; }; +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 3e4aee8f70c1..afda976680bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -51,6 +51,16 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu_b0 { @@ -69,6 +79,22 @@ cpu-supply = <&vdd_cpu_big1_s0>; }; +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -133,6 +159,8 @@ reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; #sound-dai-cells = <0>; port { @@ -179,6 +207,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; @@ -190,6 +223,344 @@ status = "okay"; }; +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi new file mode 100644 index 000000000000..38b9dbf38a21 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts new file mode 100644 index 000000000000..4d9ed2a02736 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -0,0 +1,763 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "Indiedroid Nova"; + compatible = "indiedroid,nova", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&rtc_hym8563>; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,es8388-codec"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + routing = "LINPUT2", "Mic Jack", + "Headphones", "LOUT1", + "Headphones", "ROUT1"; + dais = <&i2s0_8ch_p0>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&typec5v_pwren>; + pinctrl-names = "default"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + /* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */ + vcc_3v3_s0: vcc-3v3-s0-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usbdcin"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +/* + * Add labels for each GPIO pin exposed on the 40 pin header. Note that + * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by + * label). + */ +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 D0-D7 */ + "HEADER_12_1v8", "", "", "HEADER_24_1v8", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27_3v3", "HEADER_28_3v3", "", "", + "HEADER_29_1v8", "", "HEADER_7_1v8", "", + /* GPIO1 B0-B7 */ + "", "HEADER_31_1v8", "HEADER_33_1v8", "", + "HEADER_11_1v8", "HEADER_13_1v8", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_5_3v3", "HEADER_3_3v3"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "HEADER_16_1v8", "HEADER_18_1v8", "", "", + "", "", "", "HEADER_19_1v8", + /* GPIO3 C0-C7 */ + "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8", + "HEADER_15_1v8", "HEADER_22_1v8", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "", "", "HEADER_37_3v3", "HEADER_32_3v3", + "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3", + /* GPIO4 B0-B7 */ + "", "", "", "HEADER_40_3v3", + "HEADER_8_3v3", "HEADER_10_3v3", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + }; + }; + + rtc_hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&hym8563_int>; + pinctrl-names = "default"; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s3>; + clock-names = "mclk"; + clocks = <&cru I2S0_8CH_MCLKOUT>; + DVDD-supply = <&vcc_1v8_s3>; + HPVDD-supply = <&vcc_3v3_s3>; + PVDD-supply = <&vcc_1v8_s3>; + #sound-dai-cells = <0>; + + port { + es8388_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8388_p0_0>; + }; + }; +}; + +&pinctrl { + bluetooth-pins { + bt_reset: bt-reset { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hym8563 { + + hym8563_int: hym8563-int { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* HS400 modes seemed to cause io errors. */ +&sdhci { + bus-width = <8>; + no-mmc-hs400; + no-sd; + no-sdio; + non-removable; + max-frequency = <200000000>; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>; + pinctrl-names = "default"; + #size-cells = <0>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <675000>; + regulator-name = "vdd_logic_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_vdenc_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <600000>; + regulator-min-microvolt = <600000>; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3_pldo6: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3_pldo6"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Schematics show not in use */ + nldo-reg5 { + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* DMA seems to interfere with bluetooth device normal operation. */ +&uart9 { + pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; + pinctrl-names = "default"; + /delete-property/ dma-names; + /delete-property/ dmas; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", + "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>; + pinctrl-names = "default"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index a3124bd2e092..1576f9bfd6de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1185,6 +1185,21 @@ status = "disabled"; }; + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; @@ -1196,6 +1211,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1309,7 +1327,24 @@ mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; + ranges; + #address-cells = <2>; #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; ppi-partitions { ppi_partition0: interrupt-partition-0 { @@ -1409,6 +1444,14 @@ status = "disabled"; }; + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@feaf0000 { compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; reg = <0x0 0xfeaf0000 0x0 0x100>; @@ -1768,6 +1811,18 @@ status = "disabled"; }; + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1823,6 +1878,60 @@ status = "disabled"; }; + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi index 9caabbb8bae3..3e1132204c7d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi index e66d999d9f5d..8afbe5ce45f2 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi index 28c5b4ed1d95..6d0e3226a966 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile new file mode 100644 index 000000000000..881fe1296c58 --- /dev/null +++ b/arch/arm64/boot/dts/st/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi new file mode 100644 index 000000000000..d34a1d5e79c0 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = ; /* USART2_TX */ + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi new file mode 100644 index 000000000000..5268a4321841 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi new file mode 100644 index 000000000000..af48e82efe8a --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi new file mode 100644 index 000000000000..e6fa596211f5 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257.dtsi b/arch/arm64/boot/dts/st/stm32mp257.dtsi new file mode 100644 index 000000000000..5c5000d3d9db --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts new file mode 100644 index 000000000000..39b4726cc098 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi new file mode 100644 index 000000000000..5e83a6926485 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xf.dtsi b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi new file mode 100644 index 000000000000..5e83a6926485 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 000000000000..abdbc7aebc7f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 000000000000..2e0d4d349d14 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 000000000000..2406e972554c --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index dc12350b9fc8..53d616c3cfed 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,8 @@ l2: cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..6dd7b6f1d6ab 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -10,7 +10,14 @@ # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC @@ -22,12 +29,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb # Boards with AM65x SoC +k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 4b94f7a86316..5e6feb8cd125 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -73,19 +73,19 @@ }; &main_pmx0 { - vddshv_sdio_pins_default: vddshv-sdio-pins-default { + vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index b3e4857bbbe4..2488e3a537fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -184,6 +184,21 @@ dma-names = "tx", "rx1", "rx2"; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -192,6 +207,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + }; + main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 076601a41e84..19fc38157d94 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -14,6 +14,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + }; + /* * The MCU domain timer interrupts are routed only to the ESM module, * and not currently available for Linux. The MCU domain timers are diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi new file mode 100644 index 000000000000..aa43e7407eee --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62x + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-AM62x"; + compatible = "phytec,am62-phycore-som", "ti,am625"; + + aliases { + ethernet0 = &cpsw_port1; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + rtc1 = &wkup_rtc0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v0_som>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = ; + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; +}; + +&main_pmx0 { + leds_pins_default: leds-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_5v0_som>; + buck2-supply = <&vcc_5v0_som>; + buck3-supply = <&vcc_5v0_som>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&vdd_1v8>; + ldo3-supply = <&vcc_5v0_som>; + ldo4-supply = <&vcc_5v0_som>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + ti,power-button; + system-power-controller; + + regulators { + vdd_core: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_3v3: buck2 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr4: buck3 { + regulator-name = "VDD_DDR4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vddshv5_sdio: ldo1 { + regulator-name = "VDDSHV5_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + vddr_core: ldo2 { + regulator-name = "VDDR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdda_1v8: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_2v5: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi new file mode 100644 index 000000000000..a358757e26f0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi new file mode 100644 index 000000000000..3abd8d1d6761 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi new file mode 100644 index 000000000000..846caee7dfa4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + cpsw3g_phy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&main_gpio0>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&cpsw3g_phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* IO Expander */ + gpio_expander_21: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver. */ +&main_uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..68d07695e1db --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +&sdhci2 { + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + status = "disabled"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi new file mode 100644 index 000000000000..90ddc71bcd30 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +/ { + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_en>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + ti,fails-without-test-cd; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi new file mode 100644 index 000000000000..cb11d6e7f525 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>, + <&pinctrl_qspi1_cs2_gpio>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi new file mode 100644 index 000000000000..57dd061911ab --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -0,0 +1,1401 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart5; + usb0 = &usb0; + usb1 = &usb1; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + /* Non PMIC On-module Supplies */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3"; + vin-supply = <®_vsodimm>; + }; + + reg_1v2_dsi: regulator-1v2-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V1.2_DSI */ + reg_1v8_dsi: regulator-1v8-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v0_eth: regulator-1v0-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "On-module +V1.0_ETH"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v8_eth: regulator-1v8-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_ETH"; + vin-supply = <®_1v8>; + }; + + /* Verdin SD_1 Power Supply */ + reg_sdhc1_vmmc: regulator-sdhci1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vsel_sd>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_1 */ + pinctrl_epwm0_a: main-epwm0a-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm0_b: main-epwm0b-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_3_DSI */ + pinctrl_epwm1_a: main-epwm1a-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* WiFi_W_WKUP_HOST# */ + pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ + >; + }; + + /* WiFi_BT_WKUP_HOST# */ + pinctrl_bt_wkup_host: main-gpio0-16-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ + >; + }; + + /* PMIC_ETH_RESET# */ + pinctrl_eth_reset: main-gpio0-17-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ + >; + }; + + /* PMIC_BRIDGE_RESET# */ + pinctrl_bridge_reset: main-gpio0-20-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ + >; + }; + + /* PMIC_VSEL_SD */ + pinctrl_vsel_sd: main-gpio0-21-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + /* PMIC_EN_WIFI */ + pinctrl_wifi_en: main-gpio0-22-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ + >; + }; + + /* PMIC_ETH_INT# */ + pinctrl_eth_int: main-gpio0-25-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ + >; + }; + + /* WiFi_WKUP_BT# */ + pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ + >; + }; + + /* WiFi_WKUP_WLAN# */ + pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-29-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ + >; + }; + + /* Verdin DSI_1_BKL_EN */ + pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ + >; + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-36-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-40-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-41-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-42-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-71-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-72-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO */ + pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio1-19-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ + >; + }; + + /* Verdin DSI_1_INT# (pulled-up as active-low) */ + pinctrl_dsi1_int: main-gpio1-49-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ + AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* I2S_1_MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: main-mcasp0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ + AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ + >; + }; + + /* On-module eMMC */ + pinctrl_sdhci0: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ + AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_spi1: main-spi1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* ETH_25MHz_CLK */ + pinctrl_eth_clock: main-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + /* PMIC_EXTINT# */ + pinctrl_pmic_extint: main-system-extint-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + >; + }; + + /* Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ + AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ + AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */ + AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */ + >; + }; + + /* Verdin USB_1 */ + pinctrl_usb0: main-usb0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ + >; + }; + + /* Verdin USB_2 */ + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* DSS VOUT0 RGB */ + pinctrl_parallel_rgb: main-vout-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ + >; + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin UART_4 - Reserved to Cortex-M4 */ + pinctrl_mcu_uart0: mcu-uart0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: wkup-clkout0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&cpsw3g_phy0>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>; + status = "disabled"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>; + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <1000>; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm1_a>; + status = "disabled"; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", /* 0 */ + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "", + "", + "SODIMM_174", + "SODIMM_172", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_76", + "SODIMM_21", /* 30 */ + "SODIMM_256", + "SODIMM_252", + "", + "SODIMM_46", + "SODIMM_42", + "SODIMM_218", + "", + "SODIMM_189", + "", + "SODIMM_216", /* 40 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "SODIMM_157", + "SODIMM_187", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + ""; + + verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <31 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "SODIMM_15", + "SODIMM_16", + "SODIMM_19", + "SODIMM_66", + "SODIMM_161", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_17", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + ""; +}; + +/* On-module I2C - PMIC_I2C */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + dsi_bridge: dsi@e { + compatible = "toshiba,tc358778"; + reg = <0xe>; + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bridge_reset>; + clocks = <&k3_clks 157 20>; + clock-names = "refclk"; + reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + vddc-supply = <®_1v2_dsi>; + vddmipi-supply = <®_1v2_dsi>; + vddio-supply = <®_1v8_dsi>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + rgb_in: endpoint { + data-lines = <18>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_vdd_core: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_CORE (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + reg_vdd_ddr: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + reg_vddr_core: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDDR_CORE (PMIC LDO2)"; + }; + + reg_1v8a: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + reg_eth_2v5: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + status = "disabled"; +}; + +/* Verdin CAN_2 - Reserved to Cortex-M4 */ + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "SODIMM_244", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin UART_4 - Cortex-M4 UART */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + disable-wp; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +/* TODO: role swich using ID pin */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + status = "disabled"; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 7726ebae2539..eae052887186 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -61,4 +61,12 @@ /* Used by DM firmware */ status = "reserved"; }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index a401f5225243..5e72c445f37a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -81,6 +81,7 @@ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; @@ -91,14 +92,17 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; - cbass_wakeup: bus@2b000000 { + cbass_wakeup: bus@b00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; }; }; + + #include "k3-am62-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index cb46c38ce2cc..589bf998bc52 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -216,7 +216,7 @@ }; &main_pmx0 { - gpio0_pins_default: gpio0-pins-default { + gpio0_pins_default: gpio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ @@ -235,47 +235,47 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-pins-default { + vdd_sd_dv_pins_default: vdd-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; - usr_button_pins_default: usr-button-pins-default { + usr_button_pins_default: usr-button-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ >; }; - grove_pins_default: grove-pins-default { + grove_pins_default: grove-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - local_i2c_pins_default: local-i2c-pins-default { + local_i2c_pins_default: local-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - i2c2_1v8_pins_default: i2c2-pins-default { + i2c2_1v8_pins_default: i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -292,7 +292,7 @@ >; }; - emmc_pins_default: emmc-pins-default { + emmc_pins_default: emmc-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -307,13 +307,13 @@ >; }; - vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ >; }; - sd_pins_default: sd-pins-default { + sd_pins_default: sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -325,7 +325,7 @@ >; }; - wifi_pins_default: wifi-pins-default { + wifi_pins_default: wifi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ @@ -338,19 +338,19 @@ >; }; - wifi_en_pins_default: wifi-en-pins-default { + wifi_en_pins_default: wifi-en-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ >; }; - wifi_wlirq_pins_default: wifi-wlirq-pins-default { + wifi_wlirq_pins_default: wifi-wlirq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ >; }; - spe_pins_default: spe-pins-default { + spe_pins_default: spe-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ @@ -366,21 +366,21 @@ >; }; - mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { + mikrobus_i2c_pins_default: mikrobus-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ >; }; - mikrobus_uart_pins_default: mikrobus-uart-pins-default { + mikrobus_uart_pins_default: mikrobus-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ >; }; - mikrobus_spi_pins_default: mikrobus-spi-pins-default { + mikrobus_spi_pins_default: mikrobus-spi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ @@ -389,7 +389,7 @@ >; }; - mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { + mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ @@ -397,27 +397,27 @@ >; }; - console_pins_default: console-pins-default { + console_pins_default: console-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; }; - wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { + wifi_debug_uart_pins_default: wifi-debug-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ >; @@ -425,7 +425,7 @@ }; &mcu_pmx0 { - i2c_qwiic_pins_default: i2c-qwiic-pins-default { + i2c_qwiic_pins_default: i2c-qwiic-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ @@ -438,14 +438,14 @@ >; }; - i2c_csi_pins_default: i2c-csi-pins-default { + i2c_csi_pins_default: i2c-csi-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ >; }; - wifi_32k_clk: mcu-clk-out-pins-default { + wifi_32k_clk: mcu-clk-out-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts new file mode 100644 index 000000000000..a438baf542c2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am62x + */ + +#include +#include +#include +#include +#include "k3-am625.dtsi" +#include "k3-am62-phycore-som.dtsi" + +/ { + compatible = "phytec,am625-phyboard-lyra-rdk", + "phytec,am62-phycore-som", "ti,am625"; + model = "PHYTEC phyBOARD-Lyra AM625"; + + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + ethernet1 = &cpsw_port2; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = ; + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = ; + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; + + led-1 { + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + vcc_3v3_mmc: regulator-vcc-3v3-mmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + gpio_keys_pins_default: gpio-keys-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; + + gpio_exp_int_pins_default: gpio-exp-int-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + user_leds_pins_default: user-leds-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + gpio_exp: gpio-expander@21 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_exp_int_pins_default>; + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN", + "GPIO2_LED2", "GPIO3_LVDS_GPIO", + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 may be used by TIFS firmware */ + status = "okay"; +}; + +&sdhci1 { + vmmc-supply = <&vcc_3v3_mmc>; + vqmmc-supply = <&vddshv5_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 2a1adda9bff6..3f9ef4053aa6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -101,7 +101,7 @@ }; &main_pmx0 { - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -118,7 +118,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -134,13 +134,13 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; @@ -161,7 +161,7 @@ "UART1_FET_BUF_EN", "WL_LT_EN", "GPIO_HDMI_RSTn", "CSI_GPIO1", "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "TEST_GPIO2", + "HDMI_INTn", "PD_I2C_IRQ", "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "TSINT#", "IO_EXP_TEST_LED"; @@ -183,8 +183,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default - &main_rgmii2_pins_default>; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; &cpsw_port2 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..d38bfef29d71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Dahlia Board"; + compatible = "toradex,verdin-am62-nonwifi-dahlia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..31d2a3066d43 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 on Verdin Development Board"; + compatible = "toradex,verdin-am62-nonwifi-dev", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..e80332e1f030 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Yavia Board"; + compatible = "toradex,verdin-am62-nonwifi-yavia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..3850a706edb7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Dahlia Board"; + compatible = "toradex,verdin-am62-wifi-dahlia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts new file mode 100644 index 000000000000..4b657d6d3e0d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Verdin Development Board"; + compatible = "toradex,verdin-am62-wifi-dev", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..8a2506068ac4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Yavia Board"; + compatible = "toradex,verdin-am62-wifi-yavia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 393a1a40b68b..8b315cc61550 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -169,6 +169,21 @@ }; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -177,6 +192,102 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -601,6 +712,51 @@ status = "disabled"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti4: watchdog@e040000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e040000 0x00 0x100>; + clocks = <&k3_clks 205 0>; + power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 205 0>; + assigned-clock-parents = <&k3_clks 205 2>; + }; + epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 2bb813e784a2..04599762c2b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -15,6 +15,51 @@ status = "disabled"; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -87,4 +132,15 @@ clock-names = "gpio"; status = "disabled"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi new file mode 100644 index 000000000000..85ce545633ea --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 81d984414fd4..4e8279fa01e1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -51,4 +51,23 @@ wakeup-source; status = "disabled"; }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi index fe60c9ce21e3..61a210ecd5ff 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi @@ -115,6 +115,8 @@ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62a-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f6a67f072dca..ecc0e13331c4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -17,7 +17,9 @@ model = "Texas Instruments AM62A7 SK"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; + serial3 = &main_uart1; mmc1 = &sdhci1; }; @@ -114,36 +116,63 @@ }; }; -&main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ + AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ + AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ + AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -155,26 +184,26 @@ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ @@ -254,6 +283,13 @@ pinctrl-0 = <&main_uart0_pins_default>; }; +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "reserved"; +}; + &usbss1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 976f8303c84f..34c8ffc553ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -25,14 +25,12 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { @@ -120,35 +118,44 @@ &main_pmx0 { /* First pad number is ALW package and second is AMC package */ - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ @@ -163,7 +170,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ @@ -175,20 +182,20 @@ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ @@ -205,18 +212,29 @@ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; - main_mcasp1_pins_default: main-mcasp1-pins-default { + main_mcasp1_pins_default: main-mcasp1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ - AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ - AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ - AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + >; + }; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ >; }; }; @@ -224,6 +242,8 @@ &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { @@ -235,6 +255,8 @@ &main_uart1 { /* Main UART1 is used by TIFS firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { @@ -242,6 +264,36 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; }; &main_i2c1 { @@ -321,7 +373,16 @@ }; &usb0 { - dr_mode = "peripheral"; + #address-cells = <1>; + #size-cells = <0>; + usb-role-switch; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; }; &usb1 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5e8036f32d79..1664d9f0241c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -228,12 +228,161 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 1>; + assigned-clock-parents = <&k3_clks 36 2>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 1>; + assigned-clock-parents = <&k3_clks 37 2>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 1>; + assigned-clock-parents = <&k3_clks 38 2>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 1>; + assigned-clock-parents = <&k3_clks 39 2>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 1>; + assigned-clock-parents = <&k3_clks 40 2>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 1>; + assigned-clock-parents = <&k3_clks 41 2>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 1>; + assigned-clock-parents = <&k3_clks 42 2>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 1>; + assigned-clock-parents = <&k3_clks 43 2>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 44 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 44 1>; + assigned-clock-parents = <&k3_clks 44 2>; + power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 45 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 45 1>; + assigned-clock-parents = <&k3_clks 45 2>; + power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 46 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 46 1>; + assigned-clock-parents = <&k3_clks 46 2>; + power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 47 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 47 1>; + assigned-clock-parents = <&k3_clks 47 2>; + power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; @@ -245,7 +394,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; @@ -257,7 +405,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; @@ -269,7 +416,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; @@ -281,7 +427,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; @@ -293,7 +438,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; @@ -305,7 +449,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; @@ -676,6 +819,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -686,6 +830,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster4: mailbox@29040000 { @@ -696,6 +841,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster5: mailbox@29050000 { @@ -706,6 +852,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster6: mailbox@29060000 { @@ -715,6 +862,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster7: mailbox@29070000 { @@ -724,6 +872,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; main_r5fss0: r5fss@78000000 { @@ -1392,4 +1541,12 @@ clock-names = "fck"; status = "disabled"; }; + + main_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 38ddf0b3b8a0..686d49790721 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -6,11 +6,55 @@ */ &cbass_mcu { + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 1>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; @@ -21,7 +65,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; @@ -109,4 +152,10 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 8dfb6301b17d..5606d775153d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -66,7 +66,7 @@ }; &main_pmx0 { - cpsw_mdio_pins_default: cpsw-mdio-pins-default { + cpsw_mdio_pins_default: cpsw-mdio-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ @@ -74,7 +74,7 @@ >; }; - cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default { + cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ @@ -92,26 +92,26 @@ >; }; - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */ >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ @@ -160,30 +160,6 @@ status = "disabled"; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi new file mode 100644 index 000000000000..036db56ba797 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 60fe95b48312..8e9c2bc70f4d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -19,22 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &mcu_uart0; - serial1 = &mcu_uart1; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { @@ -70,6 +54,7 @@ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ @@ -106,6 +91,8 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; }; + + #include "k3-am64-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 39feea78a084..15c282c93467 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -17,15 +17,26 @@ model = "Texas Instruments AM642 EVM"; chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + stdout-path = &main_uart0; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + serial3 = &main_uart3; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { @@ -94,7 +105,7 @@ }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main DC jack */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -104,7 +115,7 @@ regulator-boot-on; }; - vsys_5v0: fixedregulator-vsys5v0 { + vsys_5v0: regulator-1 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; @@ -115,7 +126,7 @@ regulator-boot-on; }; - vsys_3v3: fixedregulator-vsys3v3 { + vsys_3v3: regulator-2 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; @@ -126,7 +137,7 @@ regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-3 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -138,7 +149,7 @@ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; }; - vddb: fixedregulator-vddb { + vddb: regulator-4 { compatible = "regulator-fixed"; regulator-name = "vddb_3v3_display"; regulator-min-microvolt = <3300000>; @@ -148,6 +159,20 @@ regulator-boot-on; }; + vtt_supply: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; + vin-supply = <&vsys_3v3>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; @@ -201,7 +226,7 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ @@ -215,7 +240,16 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -224,7 +258,7 @@ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ @@ -233,21 +267,28 @@ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ @@ -264,7 +305,7 @@ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -281,13 +322,13 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -303,36 +344,58 @@ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; + + ddr_vtt_pins_default: ddr-vtt-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ + >; + }; }; &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; /* main_uart1 is reserved for firmware usage */ &main_uart1 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; }; &main_i2c1 { @@ -425,8 +488,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -471,10 +533,53 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -486,11 +591,9 @@ }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -502,41 +605,35 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8d3114d14a8b..9c418abd29d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "k3-am642.dtsi" @@ -75,7 +76,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default &user_leds_pins_default>; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; led-1 { color = ; @@ -104,47 +105,47 @@ }; &main_pmx0 { - can_tc1_pins_default: can-tc1-pins-default { + can_tc1_pins_default: can-tc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */ >; }; - can_tc2_pins_default: can-tc2-pins-default { + can_tc2_pins_default: can-tc2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */ >; }; - gpio_keys_pins_default: gpio-keys-pins-default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */ AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ @@ -157,14 +158,14 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -173,25 +174,25 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - pcie_usb_sel_pins_default: pcie-usb-sel-pins-default { + pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ >; }; - pcie0_pins_default: pcie0-pins-default { + pcie0_pins_default: pcie0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ >; }; - user_leds_pins_default: user-leds-pins-default { + user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */ @@ -210,6 +211,26 @@ pagesize = <16>; reg = <0x51>; }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-3 { + label = "red:user"; + type = ; + }; + + led-4 { + label = "green:user"; + type = ; + }; + + led-5 { + label = "blue:user"; + type = ; + }; + }; }; &main_mcan0 { @@ -230,6 +251,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { @@ -237,6 +259,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + current-speed = <115200>; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 2e2d40da360a..cbce43dbe3f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -17,15 +17,25 @@ model = "Texas Instruments AM642 SK"; chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + stdout-path = &main_uart0; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { @@ -94,7 +104,7 @@ }; }; - vusb_main: fixed-regulator-vusb-main5v0 { + vusb_main: regulator-0 { /* USB MAIN INPUT 5V DC */ compatible = "regulator-fixed"; regulator-name = "vusb_main5v0"; @@ -104,7 +114,7 @@ regulator-boot-on; }; - vcc_3v3_sys: fixedregulator-vcc-3v3-sys { + vcc_3v3_sys: regulator-1 { /* output of LP8733xx */ compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; @@ -115,7 +125,7 @@ regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-2 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -127,7 +137,7 @@ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; - com8_ls_en: regulator-1 { + com8_ls_en: regulator-3 { compatible = "regulator-fixed"; regulator-name = "com8_ls_en"; regulator-min-microvolt = <3300000>; @@ -139,7 +149,7 @@ gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; }; - wlan_en: regulator-2 { + wlan_en: regulator-4 { /* output of SN74AVC4T245RSVR */ compatible = "regulator-fixed"; regulator-name = "wlan_en"; @@ -222,20 +232,21 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < - AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ - AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ - AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -244,27 +255,43 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ @@ -281,7 +308,7 @@ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -298,7 +325,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -314,24 +341,24 @@ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_wlan_en_pins_default: main-wlan-en-pins-default { + main_wlan_en_pins_default: main-wlan-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ >; }; - main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + main_com8_ls_en_pins_default: main-com8-ls-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ >; }; - main_wlan_pins_default: main-wlan-pins-default { + main_wlan_pins_default: main-wlan-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; @@ -342,11 +369,26 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { /* main_uart1 is reserved for firmware usage */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + }; }; &main_i2c1 { @@ -439,8 +481,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -490,10 +531,53 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -505,11 +589,9 @@ }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -521,41 +603,35 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 96ac2b476b11..e26bd988e522 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -21,7 +21,6 @@ chosen { stdout-path = "serial3:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02810000"; }; reserved-memory { @@ -105,7 +104,7 @@ }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) @@ -114,7 +113,7 @@ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) @@ -123,21 +122,21 @@ >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { pinctrl-single,pins = < /* (R2) WKUP_GPIO0_21 */ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) >; }; - arduino_uart_pins_default: arduino-uart-pins-default { + arduino_uart_pins_default: arduino-uart-default-pins { pinctrl-single,pins = < /* (P4) MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) @@ -146,7 +145,7 @@ >; }; - arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { + arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins { pinctrl-single,pins = < /* (P1) WKUP_GPIO0_31 */ AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) @@ -155,7 +154,7 @@ >; }; - arduino_io_oe_pins_default: arduino-io-oe-pins-default { + arduino_io_oe_pins_default: arduino-io-oe-default-pins { pinctrl-single,pins = < /* (N4) WKUP_GPIO0_34 */ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) @@ -170,7 +169,7 @@ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) @@ -185,7 +184,7 @@ >; }; - db9_com_mode_pins_default: db9-com-mode-pins-default { + db9_com_mode_pins_default: db9-com-mode-default-pins { pinctrl-single,pins = < /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) @@ -198,7 +197,7 @@ >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < /* (T2) WKUP_GPIO0_17, used as user led1 red */ AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) @@ -211,7 +210,7 @@ >; }; - mcu_spi0_pins_default: mcu-spi0-pins-default { + mcu_spi0_pins_default: mcu-spi0-default-pins { pinctrl-single,pins = < /* (Y1) MCU_SPI0_CLK */ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) @@ -224,7 +223,7 @@ >; }; - minipcie_pins_default: minipcie-pins-default { + minipcie_pins_default: minipcie-default-pins { pinctrl-single,pins = < /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) @@ -233,7 +232,7 @@ }; &main_pmx0 { - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ @@ -242,14 +241,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -262,19 +261,19 @@ >; }; - usb0_pins_default: usb0-pins-default { + usb0_pins_default: usb0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; - arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { + arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ @@ -285,7 +284,7 @@ >; }; - dss_vout1_pins_default: dss-vout1-pins-default { + dss_vout1_pins_default: dss-vout1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ @@ -318,13 +317,13 @@ >; }; - dp_pins_default: dp-pins-default { + dp_pins_default: dp-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ @@ -333,21 +332,21 @@ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; @@ -385,13 +384,12 @@ &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &arduino_io_d2_to_d3_pins_default - &arduino_i2c_aio_switch_pins_default - &arduino_io_oe_pins_default - &push_button_pins_default - &db9_com_mode_pins_default - >; + pinctrl-0 = + <&arduino_io_d2_to_d3_pins_default>, + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; gpio-line-names = /* 0..9 */ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", @@ -483,7 +481,7 @@ pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; - rtc: rtc8564@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -712,11 +710,11 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 1adba2f2c153..3f8ff2589842 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -469,7 +469,6 @@ ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; ti,clkbuf-sel = <0x7>; - ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; }; @@ -481,21 +480,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_mode: pcie-mode@4060 { - compatible = "syscon"; - reg = <0x00004060 0x4>; - }; - - pcie1_mode: pcie-mode@4070 { - compatible = "syscon"; - reg = <0x00004070 0x4>; - }; - - pcie_devid: pcie-devid@210 { - compatible = "syscon"; - reg = <0x00000210 0x4>; - }; - serdes0_clk: clock@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; @@ -883,8 +867,8 @@ #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -900,7 +884,7 @@ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; @@ -918,8 +902,8 @@ #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -935,7 +919,7 @@ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 5dfa31840e9c..b7a4b5a89aaf 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -227,7 +227,22 @@ }; }; - m_can0: mcan@40528000 { + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + + m_can0: can@40528000 { compatible = "bosch,m_can"; reg = <0x0 0x40528000 0x0 0x400>, <0x0 0x40500000 0x0 0x4400>; @@ -243,7 +258,7 @@ status = "disabled"; }; - m_can1: mcan@40568000 { + m_can1: can@40568000 { compatible = "bosch,m_can"; reg = <0x0 0x40568000 0x0 0x400>, <0x0 0x40540000 0x0 0x4400>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3093ef6b9b23..4d7b6155a76b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -19,23 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - ethernet0 = &cpsw_port1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index cd43fd11a5c2..5ab434c02ab6 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -35,7 +35,7 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso new file mode 100644 index 000000000000..3be92c39ecba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. + * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT + * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + display0 { + compatible = "rocktech,rk101ii01d-ct"; + backlight = <&lcd_bl>; + enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + port { + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = + <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + + interrupt-parent = <&pca9554>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + + reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 592ab2b54cb3..973a89b04a22 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -13,9 +13,22 @@ compatible = "ti,am654-evm", "ti,am654"; model = "Texas Instruments AM654 Base Board"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + i2c0 = &wkup_i2c0; + i2c1 = &mcu_i2c0; + i2c2 = &main_i2c0; + i2c3 = &main_i2c1; + i2c4 = &main_i2c2; + ethernet0 = &cpsw_port1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { @@ -86,7 +99,7 @@ }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -96,7 +109,7 @@ regulator-boot-on; }; - vcc3v3_io: fixedregulator-vcc3v3io { + vcc3v3_io: regulator-1 { /* Output of TPS54334 */ compatible = "regulator-fixed"; regulator-name = "vcc3v3_io"; @@ -107,7 +120,7 @@ vin-supply = <&evm_12v0>; }; - vdd_mmc1_sd: fixedregulator-sd { + vdd_mmc1_sd: regulator-2 { compatible = "regulator-fixed"; regulator-name = "vdd_mmc1_sd"; regulator-min-microvolt = <3300000>; @@ -117,24 +130,53 @@ vin-supply = <&vcc3v3_io>; gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; }; + + vtt_supply: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_io>; + gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; + }; }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + >; + }; + + ddr_vtt_pins_default: ddr-vtt-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ @@ -156,7 +198,16 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ @@ -173,16 +224,23 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ + >; + }; }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ @@ -191,14 +249,14 @@ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ @@ -207,7 +265,7 @@ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ @@ -224,7 +282,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -237,7 +295,7 @@ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; @@ -245,21 +303,21 @@ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; @@ -269,11 +327,14 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -289,6 +350,25 @@ pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; + + vdd_mpu: regulator@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-always-on; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + }; + pca9554: gpio@39 { compatible = "nxp,pca9554"; reg = <0x39>; @@ -305,7 +385,9 @@ &mcu_i2c0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_i2c0 { @@ -438,13 +520,13 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; &ospi0 { @@ -462,6 +544,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi index 4cc329b271ac..888567b921f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -113,6 +113,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; thermal_zones: thermal-zones { diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index 0f67e1ec0fb8..be55494b1f3f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -22,7 +22,7 @@ }; &main_pmx0 { - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 9400e35882a6..cbe44634914f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -27,7 +27,7 @@ }; &main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-pins-default { + main_m2_enable_pins_default: main-m2-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ >; @@ -39,7 +39,7 @@ >; }; - main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default { + main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ @@ -56,7 +56,7 @@ }; &main_pmx1 { - main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default { + main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ @@ -66,20 +66,18 @@ &main_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_pcie_mux_control - &arduino_io_d4_to_d9_pins_default - >; + pinctrl-0 = + <&main_m2_pcie_mux_control>, + <&arduino_io_d4_to_d9_pins_default>; }; &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_enable_pins_default - &main_pmx0_m2_config_pins_default - &main_pmx1_m2_config_pins_default - &cp2102n_reset_pin_default - >; + pinctrl-0 = + <&main_m2_enable_pins_default>, + <&main_pmx0_m2_config_pins_default>, + <&main_pmx1_m2_config_pins_default>, + <&cp2102n_reset_pin_default>; }; /* diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 27a43a8ecffd..d5889ba3fa46 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -22,6 +22,8 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; can0 = &mcu_mcan0; @@ -122,21 +124,21 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -148,78 +150,154 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; - main_mcan6_pins_default: main-mcan6-pins-default { + main_mcan6_pins_default: main-mcan6-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ >; }; - main_mcan7_pins_default: main-mcan7-pins-default { + main_mcan7_pins_default: main-mcan7-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ >; }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ + >; + }; }; -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_i2c1_pins_default: mcu-i2c1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; + + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ + J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ + J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ + J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &main_gpio2 { @@ -235,7 +313,8 @@ }; &wkup_gpio0 { - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; &wkup_gpio1 { @@ -244,6 +323,14 @@ &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { @@ -271,6 +358,20 @@ }; }; +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_sdhci0 { /* Unused */ status = "disabled"; @@ -287,7 +388,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index e92431250729..6c9139f73201 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,3 +27,25 @@ }; }; }; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790..d282c2c633c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -21,9 +21,14 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; + mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c0 = &wkup_i2c0; + i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; }; memory@80000000 { @@ -105,21 +110,21 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -132,11 +137,147 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; +}; + +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + >; + }; +}; + +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_uart8 { @@ -165,6 +306,14 @@ }; }; +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &main_sdhci1 { /* SD card */ status = "okay"; @@ -177,4 +326,27 @@ &main_gpio0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; +}; + +&davinci_mdio { + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0d39d6b8cc0c..3cf288128c3f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -15,9 +15,18 @@ compatible = "ti,j7200-evm", "ti,j7200"; model = "Texas Instruments J7200 EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial5 = &main_uart3; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; evm_12v0: fixedregulator-evm12v0 { @@ -80,48 +89,88 @@ }; }; -&wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { +&wkup_pmx0 { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ + J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ + >; + }; + + main_uart3_pins_default: main-uart3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ + J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ @@ -134,7 +183,7 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; @@ -142,7 +191,7 @@ }; &main_pmx1 { - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; @@ -152,22 +201,30 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { status = "okay"; /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { @@ -175,6 +232,13 @@ status = "reserved"; }; +&main_uart3 { + /* Shared with MCAN Interface */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; +}; + &main_gpio2 { status = "disabled"; }; @@ -187,13 +251,18 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 31b932eebc0a..34a0747cbe69 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -92,7 +92,7 @@ }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d..ac62bbc1660d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ @@ -971,6 +989,246 @@ assigned-clock-parents = <&k3_clks 253 5>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; @@ -1010,4 +1268,10 @@ ti,loczrama = <1>; }; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <656>, <657>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 331b4e482e41..c5e4c41effd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,136 @@ }; }; + mcu_timer0: timer@40400000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; @@ -53,6 +183,26 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ @@ -62,7 +212,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx1: pinctrl@0x4301c038 { + wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; @@ -71,7 +221,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx2: pinctrl@0x4301c068 { + wkup_pmx2: pinctrl@4301c068 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; @@ -80,7 +230,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx3: pinctrl@0x4301c174 { + wkup_pmx3: pinctrl@4301c174 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; @@ -209,6 +359,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -459,4 +624,12 @@ status = "disabled"; /* Used by OP-TEE */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index fa44ed4c17d5..b37f4f88ece4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -83,7 +83,7 @@ }; &wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ @@ -101,7 +101,7 @@ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ @@ -118,8 +118,17 @@ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ @@ -140,6 +149,37 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "hbmc.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "hbmc.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "hbmc.env"; + reg = <0x700000 0x40000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; @@ -174,25 +214,25 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; @@ -214,6 +254,18 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -229,5 +281,46 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi new file mode 100644 index 000000000000..e7e3a643a6f0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + mcu_thermal: mcu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main_thermal: main-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index bbe380c72a7e..ef73e6d7e858 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -18,23 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - chosen { }; cpus { @@ -95,6 +78,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -128,6 +112,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ @@ -170,6 +155,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ }; }; + + #include "k3-j7200-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 37c24b077b6a..66aac145e753 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -20,6 +20,7 @@ model = "BeagleBoard.org BeagleBone AI-64"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -304,7 +305,7 @@ }; &main_pmx0 { - led_pins_default: led-pins-default { + led_pins_default: led-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ @@ -314,7 +315,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -327,64 +328,64 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; - sd_pwr_en_pins_default: sd-pwr-en-pins-default { + sd_pwr_en_pins_default: sd-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ >; }; - dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { + dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ @@ -393,14 +394,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c4_pins_default: main-i2c4-pins-default { + main_i2c4_pins_default: main-i2c4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ @@ -409,14 +410,14 @@ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ @@ -425,21 +426,21 @@ >; }; - csi0_gpio_pins_default: csi0-gpio-pins-default { + csi0_gpio_pins_default: csi0-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ >; }; - csi1_gpio_pins_default: csi1-gpio-pins-default { + csi1_gpio_pins_default: csi1-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ >; }; - pcie1_rst_pins_default: pcie1-rst-pins-default { + pcie1_rst_pins_default: pcie1-rst-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ >; @@ -447,13 +448,13 @@ }; &wkup_pmx0 { - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ @@ -465,13 +466,13 @@ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ >; }; - mikro_bus_pins_default: mikro-bus-pins-default { + mikro_bus_pins_default: mikro-bus-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ @@ -494,7 +495,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -511,27 +512,34 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - sw_pwr_pins_default: sw-pwr-pins-default { + sw_pwr_pins_default: sw-pwr-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - mcu_usbss1_pins_default: mcu-usbss1-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_usbss1_pins_default: mcu-usbss1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ >; @@ -541,6 +549,8 @@ &wkup_uart0 { /* Wakeup UART is used by TIFS firmware. */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { @@ -593,7 +603,7 @@ &main_i2c1 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; + pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; @@ -623,7 +633,7 @@ &main_i2c5 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; + pinctrl-0 = <&main_i2c5_pins_default>; clock-frequency = <400000>; }; @@ -639,12 +649,14 @@ &wkup_i2c0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; + pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; }; }; @@ -680,7 +692,8 @@ &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; + pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, + <&mikro_bus_pins_default>; }; &wkup_gpio1 { @@ -688,6 +701,11 @@ status = "disabled"; }; +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; +}; + &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; @@ -759,7 +777,7 @@ &usbss1 { pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; + pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; ti,vbus-divider; }; @@ -872,12 +890,8 @@ }; }; -&pcie0_rc { - /* Unused */ - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_rst_pins_default>; phys = <&serdes1_pcie_link>; @@ -887,55 +901,12 @@ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - -&icssg0_mdio { - /* Unused */ - status = "disabled"; -}; - -&icssg1_mdio { - /* Unused */ - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -950,6 +921,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -964,6 +936,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -978,6 +951,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -992,6 +966,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { @@ -1001,55 +976,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7db0603125aa..c1cbbae76182 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; @@ -15,16 +17,27 @@ compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial6 = &main_uart4; + ethernet0 = &cpsw_port1; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; gpio_keys: gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; + pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; sw10: switch-10 { label = "GPIO Key USER1"; @@ -173,13 +186,43 @@ }; &main_pmx0 { - sw10_button_pins_default: sw10-button-pins-default { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ + J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ + >; + }; + + main_uart4_pins_default: main-uart4-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ + J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ + >; + }; + + sw10_button_pins_default: sw10-button-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -193,66 +236,66 @@ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { + main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ >; }; - mcasp10_pins_default: mcasp10-pins-default { + mcasp10_pins_default: mcasp10-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ @@ -266,27 +309,27 @@ >; }; - audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { + audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ >; }; - main_mcan2_pins_default: main-mcan2-pins-default { + main_mcan2_pins_default: main-mcan2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ >; }; - main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { + main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; @@ -294,13 +337,29 @@ }; &wkup_pmx0 { - sw11_button_pins_default: sw11-button-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + sw11_button_pins_default: sw11-button-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ @@ -313,7 +372,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -330,70 +389,84 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; + + wkup_gpio_pins_default: wkup-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ + >; + }; }; &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; }; &main_uart4 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins_default>; }; &main_gpio2 { @@ -420,6 +493,11 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; @@ -513,6 +591,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "qspi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "qspi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "qspi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; @@ -646,7 +770,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -820,6 +944,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -827,6 +952,7 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; @@ -834,49 +960,13 @@ }; &pcie2_rc { + status = "okay"; reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; - status = "disabled"; -}; - -&pcie1_ep { - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie2_ep { - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie3_rc { - status = "disabled"; -}; - -&pcie3_ep { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso index 6ff7b6ad33ed..6f0adf591b98 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -94,7 +94,7 @@ }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 10c8a5fb4ee2..2ded1ee1a854 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -548,6 +548,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; @@ -814,26 +832,7 @@ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie0_ep: pcie-ep@2900000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; pcie1_rc: pcie@2910000 { @@ -862,26 +861,7 @@ ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; pcie2_rc: pcie@2920000 { @@ -910,26 +890,7 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie2_ep: pcie-ep@2920000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; pcie3_rc: pcie@2930000 { @@ -958,28 +919,7 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie3_ep: pcie-ep@2930000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - #address-cells = <2>; - #size-cells = <2>; + status = "disabled"; }; serdes_wiz4: wiz@5050000 { @@ -1023,6 +963,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -1287,8 +1467,8 @@ bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1309,11 +1489,12 @@ assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1335,11 +1516,12 @@ assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -2091,6 +2273,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -2232,6 +2415,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -2532,4 +2716,10 @@ clocks = <&k3_clks 273 1>; status = "disabled"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 24e8125db8c4..ea5b9e104491 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -62,6 +62,28 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -70,6 +92,145 @@ #size-cells = <1>; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; @@ -181,6 +342,27 @@ #size-cells = <2>; ranges; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x2>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x00 0x47034000 0x00 0x100>, + <0x05 0x00000000 0x01 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 0>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + status = "disabled"; + }; + ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, @@ -296,6 +478,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -458,4 +655,13 @@ clocks = <&k3_clks 276 0>; status = "disabled"; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j721e-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index f650a7fd66b4..0ee4f38ec8f0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -16,9 +16,17 @@ compatible = "ti,j721e-sk", "ti,j721e"; model = "Texas Instruments J721E SK"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + ethernet0 = &cpsw_port1; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { @@ -281,7 +289,7 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -294,7 +302,7 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ @@ -303,53 +311,60 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - dp_pwr_en_pins_default: dp-pwr-en-pins-default { + dp_pwr_en_pins_default: dp-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ >; }; - dss_vout0_pins_default: dss-vout0-pins-default { + dss_vout0_pins_default: dss-vout0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ @@ -382,33 +397,33 @@ >; }; - hdmi_hpd_pins_default: hdmi-hpd-pins-default { + hdmi_hpd_pins_default: hdmi-hpd-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ >; }; - hdmi_pdn_pins_default: hdmi-pdn-pins-default { + hdmi_pdn_pins_default: hdmi-pdn-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; }; /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-pins-default { + ekey_reset_pins_default: ekey-reset-pns-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ @@ -436,7 +451,7 @@ >; }; - rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ >; @@ -444,7 +459,7 @@ }; &wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -461,14 +476,14 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ @@ -484,19 +499,35 @@ >; }; - vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { + vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ @@ -504,7 +535,7 @@ }; /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-pins-default { + mkey_reset_pins_default: mkey-reset-pns-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ >; @@ -514,11 +545,27 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -531,7 +578,8 @@ &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_sdhci0 { @@ -569,6 +617,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@7c0000 { + label = "ospi.env.backup"; + reg = <0x7c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; @@ -781,7 +875,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -872,6 +966,7 @@ }; &pcie0_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ekey_reset_pins_default>; reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; @@ -882,6 +977,7 @@ }; &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mkey_reset_pins_default>; reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; @@ -891,48 +987,6 @@ num-lanes = <2>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; @@ -1008,55 +1062,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e289d5b44356..38ae13cc3aa3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ /dts-v1/; @@ -143,14 +145,14 @@ }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ @@ -165,6 +167,51 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; }; &ospi0 { @@ -182,6 +229,104 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; + }; +}; + +&hbmc { + /* OSPI and HBMC are muxed inside FSS, Bootloader will enable + * appropriate node based on board detection + */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "hbmc.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "hbmc.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "hbmc.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "hbmc.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; @@ -256,55 +401,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi new file mode 100644 index 000000000000..c2523279001b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + wkup_thermal: wkup-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + c7x_thermal: c7x-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + gpu_crit: gpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + r5f_thermal: r5f-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + r5f_crit: r5f-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index b912143b6a11..a200810df54a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -18,25 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - mmc2 = &main_sdhci2; - }; - chosen { }; cpus { @@ -97,6 +78,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -131,6 +113,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ @@ -184,6 +167,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + #include "k3-j721e-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b4b9edfe2d12..04d4739d7245 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -16,7 +19,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000"; }; aliases { @@ -110,7 +112,7 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ @@ -119,14 +121,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -139,88 +141,126 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; }; }; @@ -243,11 +283,14 @@ &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { @@ -305,7 +348,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -322,6 +365,70 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..ed79ab3a3271 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +37,29 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -72,6 +106,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x04e00000 0x00 0x1200>; @@ -91,6 +143,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>; + assigned-clock-parents = <&k3_clks 64 2>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 80 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 80 1>; + assigned-clock-parents = <&k3_clks 80 2>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 81 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 81 1>; + assigned-clock-parents = <&k3_clks 81 2>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 82 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 82 1>; + assigned-clock-parents = <&k3_clks 82 2>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -738,6 +1030,8 @@ reg-names = "cpts"; clocks = <&k3_clks 226 5>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; @@ -745,6 +1039,117 @@ }; }; + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..e7dd947a1814 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -50,12 +65,61 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02C>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; reg = <0x00 0x42200000 0x00 0x400>; @@ -83,6 +147,146 @@ }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 83 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 83 1>; + assigned-clock-parents = <&k3_clks 83 2>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 84 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 84 1>; + assigned-clock-parents = <&k3_clks 84 2>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 85 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 85 1>; + assigned-clock-parents = <&k3_clks 85 2>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 86 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 86 1>; + assigned-clock-parents = <&k3_clks 86 2>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 87 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 87 1>; + assigned-clock-parents = <&k3_clks 87 2>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 88 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 88 1>; + assigned-clock-parents = <&k3_clks 88 2>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 89 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 89 1>; + assigned-clock-parents = <&k3_clks 89 2>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 90 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 90 1>; + assigned-clock-parents = <&k3_clks 90 2>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 91 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 91 1>; + assigned-clock-parents = <&k3_clks 91 2>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; @@ -280,6 +484,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -333,6 +552,8 @@ reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 29 3>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; @@ -379,4 +600,56 @@ compatible = "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x0 0x350>, + <0x00 0x42050000 0x0 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..d57dd43da0ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,15 +39,46 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ >; }; - main_mcan16_pins_default: main-mcan16-pins-default { + main_mcan16_pins_default: main-mcan16-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ @@ -55,6 +86,19 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -79,3 +123,22 @@ pinctrl-names = "default"; phys = <&transceiver0>; }; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi new file mode 100644 index 000000000000..f7b1a15b8fa0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 376924726f1f..1f636acd4eee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721S2 SoC Family * - * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * @@ -81,6 +81,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -163,6 +164,10 @@ }; }; + + thermal_zones: thermal-zones { + #include "k3-j721s2-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f33815953e77..430b8a2c5df5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -20,10 +20,13 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c0 = &wkup_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { @@ -42,6 +45,150 @@ reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; }; evm_12v0: regulator-evm12v0 { @@ -105,7 +252,7 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -114,14 +261,14 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -134,37 +281,147 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; }; -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { @@ -173,6 +430,131 @@ pinctrl-0 = <&main_uart8_pins_default>; }; +&fss { + status = "okay"; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -253,3 +635,195 @@ phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..2ea0adae6832 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -72,6 +72,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x4e00000 0x00 0x1200>; @@ -91,6 +109,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 97 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 97 2>; + assigned-clock-parents = <&k3_clks 97 3>; + power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 98 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 98 2>; + assigned-clock-parents = <&k3_clks 98 3>; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 99 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 99 2>; + assigned-clock-parents = <&k3_clks 99 3>; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 100 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 100 2>; + assigned-clock-parents = <&k3_clks 100 3>; + power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 101 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 101 2>; + assigned-clock-parents = <&k3_clks 101 3>; + power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 102 2>; + assigned-clock-parents = <&k3_clks 102 3>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 103 2>; + assigned-clock-parents = <&k3_clks 103 3>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 104 2>; + assigned-clock-parents = <&k3_clks 104 3>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 105 2>; + assigned-clock-parents = <&k3_clks 105 3>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 106 2>; + assigned-clock-parents = <&k3_clks 106 3>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 107 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 107 2>; + assigned-clock-parents = <&k3_clks 107 3>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 108 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 108 2>; + assigned-clock-parents = <&k3_clks 108 3>; + power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 109 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 109 2>; + assigned-clock-parents = <&k3_clks 109 3>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 110 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 110 2>; + assigned-clock-parents = <&k3_clks 110 3>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 111 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 111 2>; + assigned-clock-parents = <&k3_clks 111 3>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 112 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 112 2>; + assigned-clock-parents = <&k3_clks 112 3>; + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 113 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 113 2>; + assigned-clock-parents = <&k3_clks 113 3>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 114 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 114 2>; + assigned-clock-parents = <&k3_clks 114 3>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 115 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 115 2>; + assigned-clock-parents = <&k3_clks 115 3>; + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 116 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 116 2>; + assigned-clock-parents = <&k3_clks 116 3>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -378,7 +636,6 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; - no-1-8-v; status = "disabled"; }; @@ -1112,4 +1369,172 @@ clocks = <&k3_clks 383 1>; status = "disabled"; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <339>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 339 1>; + firmware-name = "j784s4-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <340>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 340 1>; + firmware-name = "j784s4-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <341>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 341 1>; + firmware-name = "j784s4-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <342>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 342 1>; + firmware-name = "j784s4-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss2: r5fss@5900000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5900000 0x00 0x5900000 0x20000>, + <0x5a00000 0x00 0x5a00000 0x20000>; + power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss2_core0: r5f@5900000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5900000 0x00010000>, + <0x5910000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <343>; + ti,sci-proc-ids = <0x0a 0xff>; + resets = <&k3_reset 343 1>; + firmware-name = "j784s4-main-r5f2_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss2_core1: r5f@5a00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5a00000 0x00010000>, + <0x5a10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <344>; + ti,sci-proc-ids = <0x0b 0xff>; + resets = <&k3_reset 344 1>; + firmware-name = "j784s4-main-r5f2_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <30>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 30 1>; + firmware-name = "j784s4-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <33>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 33 1>; + firmware-name = "j784s4-c71_1-fw"; + }; + + c71_2: dsp@66800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x66800000 0x00 0x00080000>, + <0x00 0x66e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <37>; + ti,sci-proc-ids = <0x32 0xff>; + resets = <&k3_reset 37 1>; + firmware-name = "j784s4-c71_2-fw"; + }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index f04fcb614cbe..657fb1d72512 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -50,7 +65,34 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -68,6 +110,28 @@ ti,interrupt-ranges = <16 928 16>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_conf: syscon@40f00000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; @@ -82,6 +146,146 @@ }; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 2>; + assigned-clock-parents = <&k3_clks 35 3>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 117 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 117 2>; + assigned-clock-parents = <&k3_clks 117 3>; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 118 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 118 2>; + assigned-clock-parents = <&k3_clks 118 3>; + power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 119 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 119 2>; + assigned-clock-parents = <&k3_clks 119 3>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 120 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 120 2>; + assigned-clock-parents = <&k3_clks 120 3>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 121 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 121 2>; + assigned-clock-parents = <&k3_clks 121 3>; + power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 122 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 122 2>; + assigned-clock-parents = <&k3_clks 122 3>; + power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 123 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 123 2>; + assigned-clock-parents = <&k3_clks 123 3>; + power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 124 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 124 2>; + assigned-clock-parents = <&k3_clks 124 3>; + power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 125 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 125 2>; + assigned-clock-parents = <&k3_clks 125 3>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; @@ -280,6 +484,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -342,4 +561,133 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <346>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 346 1>; + firmware-name = "j784s4-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <347>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 347 1>; + firmware-name = "j784s4-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + fss: bus@47000000 { + compatible = "simple-bus"; + reg = <0x00 0x47000000 0x00 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 161 7>; + assigned-clocks = <&k3_clks 161 7>; + assigned-clock-parents = <&k3_clks 161 9>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 162 7>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi new file mode 100644 index 000000000000..f7b1a15b8fa0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 2e03d84da7d2..8b5974d92e33 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J784S4 SoC Family * - * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52 + * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * @@ -281,6 +281,10 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + thermal_zones: thermal-zones { + #include "k3-j784s4-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 4e159540d031..5e40c0b4fa0a 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb @@ -17,16 +16,17 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb -sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo -sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo -smk-k26-revA-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo -smk-k26-revA-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo -dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revB.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revB.dtb +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts index 88aa06fa78a8..4c1bd69e7553 100644 --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 3e9979ab60bb..f04716841a0c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -2,38 +2,44 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ #include / { pss_ref_clk: pss_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -42,6 +48,7 @@ &zynqmp_firmware { zynqmp_clk: clock-controller { + bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, @@ -95,6 +102,10 @@ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; +&gpu { + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; +}; + &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; @@ -181,10 +192,12 @@ &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { @@ -241,10 +254,14 @@ &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; + assigned-clocks = <&zynqmp_clk DP_STC_REF>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b610e65e0cdf..603839c82599 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -2,14 +2,15 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * - * Michal Simek + * Michal Simek */ #include @@ -95,13 +96,15 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { @@ -132,6 +135,8 @@ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; + assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ @@ -144,16 +149,18 @@ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; @@ -259,19 +266,22 @@ pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a52dafbfd59e..a91d09e7da4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -2,9 +2,10 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ #include @@ -76,13 +77,15 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { @@ -115,6 +118,8 @@ clk-phase-sd-hs = <126>, <60>; clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; + assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ @@ -127,16 +132,18 @@ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; @@ -242,19 +249,22 @@ pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 20e83ca47b5d..dfd1a18f5a10 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "ZynqMP SM-K26 Rev1/B/A"; @@ -55,6 +56,9 @@ key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + autorepeat; }; }; @@ -72,109 +76,158 @@ default-state = "on"; }; }; + + ams { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, + <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, + <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, + <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, + <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, + <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, + <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + }; +}; + +&modepin_gpio { + label = "modepin"; }; &uart1 { /* MIO36/MIO37 */ status = "okay"; }; +&pinctrl0 { + status = "okay"; + pinctrl_sdhci0_default: sdhci0-default { + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + }; +}; + &qspi { /* MIO 0-5 - U143 */ status = "okay"; - flash@0 { /* MT25QU512A */ + spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xC0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xD00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xF00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xF80000 0xD00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1C80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1D00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1E00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ - read-only; - lock; - }; - partition@2250000 { - label = "User"; - reg = <0x2250000 0x1db0000>; /* 29.5 MB */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xC0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xD00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xF00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xF80000 0xD00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1C80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1D00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1E00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { + label = "User"; + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; + assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ @@ -190,17 +243,20 @@ &i2c1 { status = "okay"; + bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; @@ -287,3 +343,114 @@ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts index c70966c1f344..85b0d1677240 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-sm-k26-revA.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index f1598527e5ec..04079d1704f1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 04efa1683eaa..3dec57cf18be 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu */ /dts-v1/; @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index b05be2552826..d9d1de5f313c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -108,6 +109,9 @@ pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; &i2c1 { status = "okay"; @@ -184,19 +188,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -348,7 +355,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 938b76bd0527..6503f4985f8d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -281,19 +282,22 @@ conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -485,8 +489,6 @@ &dwc3_1 { status = "okay"; dr_mode = "host"; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; }; &uart0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 381cc682cef9..38b0a312171b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05a2b79738af..6636e76545a5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -152,6 +152,10 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -169,7 +173,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index ae2d03d98322..b1e933b8a2cd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad Paladugu + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 6948fd40554b..44d1f351bb75 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek * Nathalie Chan King Choy */ @@ -58,6 +59,15 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, + <&xilinx_ams 11>, <&xilinx_ams 12>; + }; + leds { compatible = "gpio-leds"; led-ds2 { @@ -161,6 +171,10 @@ "", "", "", ""; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; pinctrl-names = "default", "gpio"; @@ -419,19 +433,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -443,19 +460,22 @@ conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; @@ -541,6 +561,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; }; &dwc3_0 { @@ -556,6 +577,7 @@ pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { @@ -568,6 +590,14 @@ status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts index 6647e97edba3..c8f71a1aec89 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2018, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts index b6798394fcf4..705369766a55 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-rev1.0.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5fd6b70a154a..8767f147cbe3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -200,13 +201,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; @@ -216,6 +223,10 @@ pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; @@ -772,19 +783,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -943,7 +957,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; @@ -1013,6 +1027,18 @@ status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index f7d718ff116b..3c28130909bc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revA.dts" @@ -16,16 +17,20 @@ &gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index bd8f20f3223d..e185709c0d84 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -109,12 +110,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; @@ -122,6 +130,10 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -398,20 +410,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; @@ -430,7 +444,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; @@ -497,6 +511,18 @@ status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 96feaad30166..7fceebd1815c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -114,12 +115,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; @@ -127,6 +135,10 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -410,20 +422,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; @@ -442,7 +456,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; @@ -509,6 +523,18 @@ status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 24a252317150..27b2416cb6d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -212,12 +213,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; @@ -227,6 +235,10 @@ pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; @@ -782,19 +794,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -949,7 +964,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d685d8fbc36a..6224365826d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,9 +2,10 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; @@ -172,12 +173,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; }; @@ -187,6 +195,10 @@ pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; @@ -648,19 +660,22 @@ conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -779,7 +794,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts similarity index 73% rename from arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts rename to arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index e971ba8c1418..c406017b0348 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu */ /dts-v1/; @@ -14,8 +14,8 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevA"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; @@ -47,7 +47,7 @@ flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 153db59dc4b3..02cfcc716936 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2014 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -118,6 +118,7 @@ }; zynqmp_ipi: zynqmp_ipi { + bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -126,7 +127,8 @@ #size-cells = <2>; ranges; - ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { + bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, @@ -143,6 +145,7 @@ dcc: dcc { compatible = "arm,dcc"; status = "disabled"; + bootph-all; }; pmu { @@ -152,6 +155,10 @@ <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci { @@ -164,8 +171,10 @@ compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; + bootph-all; zynqmp_power: zynqmp-power { + bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -245,6 +254,7 @@ amba: axi { compatible = "simple-bus"; + bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; @@ -400,7 +410,6 @@ gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; - #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, @@ -411,6 +420,18 @@ interrupts = <1 9 0xf04>; }; + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; + reg = <0x0 0xfd4b0000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, + <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; + power-domains = <&zynqmp_firmware PD_GPU>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. @@ -602,7 +623,6 @@ gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; - #address-cells = <0>; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; @@ -674,6 +694,7 @@ }; qspi: spi@ff0f0000 { + bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -720,6 +741,7 @@ }; sdhci0: mmc@ff160000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -730,9 +752,11 @@ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -743,6 +767,7 @@ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: iommu@fd800000 { @@ -824,6 +849,7 @@ }; uart0: serial@ff000000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -834,6 +860,7 @@ }; uart1: serial@ff010000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -928,13 +955,13 @@ #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; - ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; @@ -955,6 +982,7 @@ }; zynqmp_dpsub: display@fd4a0000 { + bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a24609e14d50..0777bcae9104 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -41,6 +41,7 @@ CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BRCMSTB=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_SPARX5=y CONFIG_ARCH_K3=y CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y @@ -52,12 +53,15 @@ CONFIG_ARCH_NXP=y CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y CONFIG_ARCH_S32=y +CONFIG_ARCH_MA35=y CONFIG_ARCH_NPCM=y CONFIG_ARCH_QCOM=y +CONFIG_ARCH_REALTEK=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_STM32=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TESLA_FSD=y @@ -267,6 +271,8 @@ CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=m +CONFIG_UBIFS_FS=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y @@ -413,6 +419,7 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_SNVS_PWRKEY=m CONFIG_KEYBOARD_IMX_SC_KEY=m CONFIG_KEYBOARD_CROS_EC=y +CONFIG_KEYBOARD_MTK_PMIC=m CONFIG_MOUSE_ELAN_I2C=m CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m @@ -461,6 +468,8 @@ CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_OWL=y CONFIG_SERIAL_DEV_BUS=y @@ -688,9 +697,11 @@ CONFIG_MFD_MAX77620=y CONFIG_MFD_MT6360=y CONFIG_MFD_MT6397=y CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_RK808=y +CONFIG_MFD_RK8XX_I2C=y +CONFIG_MFD_RK8XX_SPI=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y +CONFIG_RZ_MTU3=y CONFIG_MFD_TPS65219=y CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_ROHM_BD718XX=y @@ -708,6 +719,7 @@ CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6357=y CONFIG_REGULATOR_MT6358=y CONFIG_REGULATOR_MT6359=y CONFIG_REGULATOR_MT6360=y @@ -743,6 +755,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEDIATEK_JPEG=m CONFIG_VIDEO_MEDIATEK_VCODEC=m +CONFIG_VIDEO_IMX7_CSI=m +CONFIG_VIDEO_IMX_MIPI_CSIS=m +CONFIG_VIDEO_IMX8_ISI=m +CONFIG_VIDEO_IMX8_ISI_M2M=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m CONFIG_VIDEO_RCAR_ISP=m @@ -810,7 +826,9 @@ CONFIG_DRM_PARADE_PS8640=m CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358768=m CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m CONFIG_DRM_TI_SN65DSI86=m CONFIG_DRM_ANALOGIX_ANX7625=m CONFIG_DRM_I2C_ADV7511=m @@ -870,6 +888,7 @@ CONFIG_SND_SOC_SM8250=m CONFIG_SND_SOC_SC7180=m CONFIG_SND_SOC_SC7280=m CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m @@ -900,6 +919,7 @@ CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m @@ -992,6 +1012,7 @@ CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_MUX_FSA4480=m CONFIG_UCSI_CCG=m CONFIG_TYPEC_MUX_GPIO_SBU=m CONFIG_MMC=y @@ -1003,6 +1024,7 @@ CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y +CONFIG_MMC_SDHCI_OF_SPARX5=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_TEGRA=y @@ -1153,6 +1175,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y @@ -1163,19 +1186,24 @@ CONFIG_MSM_MMCC_8994=m CONFIG_MSM_MMCC_8996=m CONFIG_MSM_MMCC_8998=m CONFIG_MSM_GCC_8998=y +CONFIG_QCM_GCC_2290=y +CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y CONFIG_SC_DISPCC_8280XP=m +CONFIG_SA_GPUCC_8775P=m CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y CONFIG_SC_GCC_8280XP=y +CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y CONFIG_SDM_LPASSCC_845=m CONFIG_SM_CAMCC_8250=m +CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_8450=m CONFIG_SM_DISPCC_8550=m @@ -1184,6 +1212,7 @@ CONFIG_SM_GCC_8350=y CONFIG_SM_GCC_8450=y CONFIG_SM_GCC_8550=y CONFIG_SM_TCSRCC_8550=y +CONFIG_SM_GPUCC_6115=m CONFIG_SM_GPUCC_8150=y CONFIG_SM_GPUCC_8250=y CONFIG_SM_VIDEOCC_8250=y @@ -1319,9 +1348,11 @@ CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=m CONFIG_PWM_TEGRA=m +CONFIG_PWM_TIEHRPWM=m CONFIG_PWM_VISCONTI=m CONFIG_SL28CPLD_INTC=y CONFIG_QCOM_PDC=y +CONFIG_QCOM_MPM=y CONFIG_RESET_IMX7=y CONFIG_RESET_QCOM_AOSS=y CONFIG_RESET_QCOM_PDC=m @@ -1412,6 +1443,7 @@ CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_MSM8916=m CONFIG_INTERCONNECT_QCOM_MSM8996=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m +CONFIG_INTERCONNECT_QCOM_QCM2290=m CONFIG_INTERCONNECT_QCOM_QCS404=m CONFIG_INTERCONNECT_QCOM_SA8775P=y CONFIG_INTERCONNECT_QCOM_SC7180=y @@ -1424,6 +1456,8 @@ CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=y CONFIG_INTERCONNECT_QCOM_SM8550=y +CONFIG_COUNTER=m +CONFIG_RZ_MTU3_CNT=m CONFIG_HTE=y CONFIG_HTE_TEGRA194=y CONFIG_HTE_TEGRA194_TEST=m diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig index 62fdca7efce4..4383ed851063 100644 --- a/arch/m68k/configs/amiga_defconfig +++ b/arch/m68k/configs/amiga_defconfig @@ -41,7 +41,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig index 5bfbd0444bb5..ec0f9c9f9562 100644 --- a/arch/m68k/configs/apollo_defconfig +++ b/arch/m68k/configs/apollo_defconfig @@ -37,7 +37,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig index 44302f11c9ea..8656ae1f239e 100644 --- a/arch/m68k/configs/atari_defconfig +++ b/arch/m68k/configs/atari_defconfig @@ -44,7 +44,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig index f3336f1774ec..496fb6a415ea 100644 --- a/arch/m68k/configs/bvme6000_defconfig +++ b/arch/m68k/configs/bvme6000_defconfig @@ -34,7 +34,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig index 2d1bbac68066..4add7ab9973b 100644 --- a/arch/m68k/configs/hp300_defconfig +++ b/arch/m68k/configs/hp300_defconfig @@ -36,7 +36,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig index b4428dc36102..5845f1f71fd1 100644 --- a/arch/m68k/configs/mac_defconfig +++ b/arch/m68k/configs/mac_defconfig @@ -35,7 +35,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig index 4cd9fa4cb10c..bbb251bab81a 100644 --- a/arch/m68k/configs/multi_defconfig +++ b/arch/m68k/configs/multi_defconfig @@ -55,7 +55,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig index 7ee9ad50f0ad..4f9cfc70c66d 100644 --- a/arch/m68k/configs/mvme147_defconfig +++ b/arch/m68k/configs/mvme147_defconfig @@ -33,7 +33,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig index 2488893616dc..67c42b4822f0 100644 --- a/arch/m68k/configs/mvme16x_defconfig +++ b/arch/m68k/configs/mvme16x_defconfig @@ -34,7 +34,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig index ffc676289f87..85f19515200b 100644 --- a/arch/m68k/configs/q40_defconfig +++ b/arch/m68k/configs/q40_defconfig @@ -35,7 +35,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig index 198179657ce0..b1b15acb5d5f 100644 --- a/arch/m68k/configs/sun3_defconfig +++ b/arch/m68k/configs/sun3_defconfig @@ -31,7 +31,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_USERFAULTFD=y CONFIG_NET=y diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig index 85364f6178d4..91d66c0f5ab6 100644 --- a/arch/m68k/configs/sun3x_defconfig +++ b/arch/m68k/configs/sun3x_defconfig @@ -31,7 +31,6 @@ CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y # CONFIG_COMPACTION is not set CONFIG_DMAPOOL_TEST=m CONFIG_USERFAULTFD=y diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig index 756feb9369a6..38dcdce367ec 100644 --- a/arch/microblaze/configs/mmu_defconfig +++ b/arch/microblaze/configs/mmu_defconfig @@ -8,7 +8,6 @@ CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_BASE_FULL is not set CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d49d5fc40021..fc6fba925aea 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -45,6 +45,7 @@ config MIPS select GENERIC_LIB_UCMPDI2 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC select GENERIC_SMP_IDLE_THREAD + select GENERIC_IDLE_POLL_SETUP select GENERIC_TIME_VSYSCALL select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT select HAS_IOPORT if !NO_IOPORT_MAP || ISA @@ -80,7 +81,6 @@ config MIPS select HAVE_LD_DEAD_CODE_DATA_ELIMINATION select HAVE_MOD_ARCH_SPECIFIC select HAVE_NMI - select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP @@ -155,9 +155,11 @@ config MIPS_GENERIC_KERNEL select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS32_R5 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 + select SYS_HAS_CPU_MIPS64_R5 select SYS_HAS_CPU_MIPS64_R6 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 69734120ada1..6ca81e1bd35c 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -14,6 +14,7 @@ config MIPS_DB1XXX bool "Alchemy DB1XXX / PB1XXX boards" select GPIOLIB select HAVE_PCI + select HAVE_PATA_PLATFORM select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK help diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 239c4537484d..a141a699b790 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -67,14 +67,14 @@ }; }; - eth0_power: fixedregulator@0 { + eth0_power: fixedregulator-0 { compatible = "regulator-fixed"; regulator-name = "eth0_power"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpb 25 GPIO_ACTIVE_LOW>; + gpio = <&gpb 25 0>; enable-active-high; }; @@ -97,25 +97,64 @@ gpios = <&gpe 3 GPIO_ACTIVE_LOW>; }; - wlan0_power: fixedregulator@1 { + bt_power: fixedregulator-1 { compatible = "regulator-fixed"; - regulator-name = "wlan0_power"; + regulator-name = "bt_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <1400>; - gpio = <&gpb 19 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc_50>; + + gpio = <&gpb 19 0>; enable-active-high; }; - otg_power: fixedregulator@2 { + otg_power: fixedregulator-2 { compatible = "regulator-fixed"; regulator-name = "otg_power"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpf 15 GPIO_ACTIVE_LOW>; + gpio = <&gpf 15 0>; enable-active-high; }; + + wifi_power: fixedregulator-4 { + compatible = "regulator-fixed"; + + regulator-name = "wifi_power"; + + /* + * Technically it's 5V, the WiFi chip has its own internal + * regulators; but the MMC/SD subsystem won't accept such a + * value. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <150000>; + + vin-supply = <&bt_power>; + }; + + vcc_33v: fixedregulator-5 { + compatible = "regulator-fixed"; + + regulator-name = "vcc_33v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpf 7 GPIO_ACTIVE_LOW>; + + clocks = <&rtc_dev>; + clock-names = "ext_clock"; + }; }; &ext { @@ -129,10 +168,11 @@ */ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>, - <&cgu JZ4780_CLK_HDMI>; + <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>; assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>, <&cgu JZ4780_CLK_MPLL>, - <&cgu JZ4780_CLK_SSIPLL>; + <&cgu JZ4780_CLK_SSIPLL>, + <0>, <&cgu JZ4780_CLK_MPLL>; assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>; }; @@ -160,24 +200,33 @@ pinctrl-0 = <&pins_mmc0>; cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vcc_33v>; + vqmmc-supply = <&vcc_33v>; }; &mmc1 { status = "okay"; bus-width = <4>; - max-frequency = <50000000>; + max-frequency = <25000000>; + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&wifi_power>; + vqmmc-supply = <&wifi_io>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&pins_mmc1>; - brcmf: wifi@1 { -/* reg = <4>;*/ - compatible = "brcm,bcm4330-fmac"; - vcc-supply = <&wlan0_power>; - device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpd>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; }; }; @@ -204,11 +253,20 @@ bluetooth { compatible = "brcm,bcm4330-bt"; - reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>; - vcc-supply = <&wlan0_power>; + + vbat-supply = <&bt_power>; + vddio-supply = <&wifi_io>; + + interrupt-parent = <&gpf>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; + + clocks = <&rtc_dev>; + clock-names = "lpo"; + + reset-gpios = <&gpf 8 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>; + shutdown-gpios = <&gpf 4 GPIO_ACTIVE_HIGH>; }; }; @@ -237,59 +295,54 @@ act8600: act8600@5a { compatible = "active-semi,act8600"; reg = <0x5a>; - status = "okay"; regulators { - vddcore: SUDCDC1 { - regulator-name = "DCDC_REG1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + vddcore: DCDC1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + vp1-supply = <&vcc_33v>; regulator-always-on; }; - vddmem: SUDCDC2 { - regulator-name = "DCDC_REG2"; + vddmem: DCDC2 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; + vp2-supply = <&vcc_33v>; regulator-always-on; }; - vcc_33: SUDCDC3 { - regulator-name = "DCDC_REG3"; + vcc_33: DCDC3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vp3-supply = <&vcc_33v>; regulator-always-on; }; - vcc_50: SUDCDC4 { - regulator-name = "SUDCDC_REG4"; + vcc_50: SUDCDC_REG4 { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; - vcc_25: LDO_REG5 { - regulator-name = "LDO_REG5"; + vcc_25: LDO5 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; + inl-supply = <&vcc_33v>; regulator-always-on; }; - wifi_io: LDO_REG6 { - regulator-name = "LDO_REG6"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; + wifi_io: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-settling-time-us = <150000>; + inl-supply = <&vcc_33v>; }; - vcc_28: LDO_REG7 { - regulator-name = "LDO_REG7"; + cim_io_28: LDO7 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; + inl-supply = <&vcc_33v>; }; - vcc_15: LDO_REG8 { - regulator-name = "LDO_REG8"; + cim_io_15: LDO8 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - regulator-always-on; + inl-supply = <&vcc_33v>; }; vrtc_18: LDO_REG9 { - regulator-name = "LDO_REG9"; /* Despite the datasheet stating 3.3V * for REG9 and the driver expecting that, * REG9 outputs 1.8V. @@ -303,7 +356,6 @@ regulator-always-on; }; vcc_11: LDO_REG10 { - regulator-name = "LDO_REG10"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -363,7 +415,7 @@ #address-cells = <1>; #size-cells = <0>; - ingenic,bch-controller = <&bch>; + ecc-engine = <&bch>; ingenic,nemc-tAS = <10>; ingenic,nemc-tAH = <5>; @@ -429,8 +481,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pins_nemc_cs6>; - reg = <6 0 1 /* addr */ - 6 2 1>; /* data */ + reg = <6 0 1>, /* addr */ + <6 2 1>; /* data */ ingenic,nemc-tAS = <15>; ingenic,nemc-tAH = <10>; @@ -442,7 +494,7 @@ vcc-supply = <ð0_power>; interrupt-parent = <&gpe>; - interrupts = <19 4>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi b/arch/mips/boot/dts/ingenic/jz4725b.dtsi index e9e48022f631..acbbe8c4664c 100644 --- a/arch/mips/boot/dts/ingenic/jz4725b.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi @@ -198,11 +198,8 @@ #sound-dai-cells = <0>; - clocks = <&cgu JZ4725B_CLK_AIC>, - <&cgu JZ4725B_CLK_I2S>, - <&cgu JZ4725B_CLK_EXT>, - <&cgu JZ4725B_CLK_PLL_HALF>; - clock-names = "aic", "i2s", "ext", "pll half"; + clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>; + clock-names = "aic", "i2s"; interrupt-parent = <&intc>; interrupts = <10>; diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 7f76cba03a08..bdd6f4d82ec9 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -192,11 +192,8 @@ interrupt-parent = <&intc>; interrupts = <18>; - clocks = <&cgu JZ4740_CLK_AIC>, - <&cgu JZ4740_CLK_I2S>, - <&cgu JZ4740_CLK_EXT>, - <&cgu JZ4740_CLK_PLL_HALF>; - clock-names = "aic", "i2s", "ext", "pll half"; + clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>; + clock-names = "aic", "i2s"; dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; dma-names = "rx", "tx"; diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi index bda0a3a86ed5..9c0099919db7 100644 --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi @@ -238,9 +238,8 @@ #sound-dai-cells = <0>; - clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>, - <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>; - clock-names = "aic", "i2s", "ext", "pll half"; + clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>; + clock-names = "aic", "i2s"; interrupt-parent = <&intc>; interrupts = <34>; diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts index ba0218971572..24f987244a12 100644 --- a/arch/mips/boot/dts/ingenic/qi_lb60.dts +++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts @@ -27,7 +27,7 @@ stdout-path = &uart0; }; - vcc: regulator@0 { + vcc: regulator-0 { compatible = "regulator-fixed"; regulator-name = "vcc"; @@ -36,7 +36,7 @@ regulator-always-on; }; - mmc_power: regulator@1 { + mmc_power: regulator-1 { compatible = "regulator-fixed"; regulator-name = "mmc_vcc"; gpio = <&gpd 2 0>; @@ -45,7 +45,7 @@ regulator-max-microvolt = <3300000>; }; - amp_supply: regulator@2 { + amp_supply: regulator-2 { compatible = "regulator-fixed"; regulator-name = "amp_supply"; gpio = <&gpd 4 0>; diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index 42e69664efd9..cc264cfff826 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -417,4 +417,22 @@ status = "disabled"; }; + + aic: audio-controller@10020000 { + compatible = "ingenic,x1000-i2s"; + reg = <0x10020000 0x38>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <1>; + + clocks = <&cgu X1000_CLK_AIC>, + <&cgu X1000_CLK_I2S>; + clock-names = "aic", "i2s"; + + dmas = <&pdma X1000_DMA_I2S0_RX 0xffffffff>, + <&pdma X1000_DMA_I2S0_TX 0xffffffff>; + dma-names = "rx", "tx"; + }; }; diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index 8143a61111e3..f878f47e4501 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -97,6 +97,13 @@ <0x00000000>; /* int3 */ }; + rtc0: rtc@1fe07800 { + compatible = "loongson,ls2k1000-rtc"; + reg = <0 0x1fe07800 0 0x78>; + interrupt-parent = <&liointc0>; + interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + }; + uart0: serial@1fe00000 { compatible = "ns16550a"; reg = <0 0x1fe00000 0 0x8>; diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi index 2f45fce2cdc4..7c69e8245c2f 100644 --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -19,6 +19,13 @@ #interrupt-cells = <2>; }; + rtc0: rtc@100d0100 { + compatible = "loongson,ls7a-rtc"; + reg = <0 0x100d0100 0 0x78>; + interrupt-parent = <&pic>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; + }; + ls7a_uart0: serial@10080000 { compatible = "ns16550a"; reg = <0 0x10080000 0 0x100>; diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile index 11732b8c8163..d27d7e8c700f 100644 --- a/arch/mips/boot/dts/ralink/Makefile +++ b/arch/mips/boot/dts/ralink/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb dtb-$(CONFIG_SOC_MT7621) += \ mt7621-gnubee-gb-pc1.dtb \ - mt7621-gnubee-gb-pc2.dtb + mt7621-gnubee-gb-pc2.dtb \ + mt7621-tplink-hc220-g5-v1.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dts b/arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dts new file mode 100644 index 000000000000..2d2eadc6b95f --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "mt7621.dtsi" + +#include +#include +#include + +/ { + compatible = "tplink,hc220-g5-v1", "mediatek,mt7621-soc"; + model = "TP-Link HC220 G5 v1"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + bootargs = "earlycon console=ttyS0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-wps { + label = "wps"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-fault { + color = ; + function = LED_FUNCTION_FAULT; + gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; + }; + + led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-wps { + color = ; + function = LED_FUNCTION_WPS; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan2"; + }; + + port@1 { + status = "okay"; + label = "lan1"; + }; + + port@2 { + status = "okay"; + label = "wan"; + }; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi index 45bf96a3d17a..45a15e005cc4 100644 --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi @@ -51,85 +51,85 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x1>; - pinmux_gpio_gpio: pinmux_gpio_gpio { + pinmux_gpio_gpio: gpio-gpio-pins { pinctrl-single,bits = <0x0 0x0 0x3>; }; - pinmux_spi_cs1_cs: pinmux_spi_cs1_cs { + pinmux_spi_cs1_cs: spi-cs1-cs-pins { pinctrl-single,bits = <0x0 0x0 0x30>; }; - pinmux_i2s_gpio: pinmux_i2s_gpio { + pinmux_i2s_gpio: i2s-gpio-pins { pinctrl-single,bits = <0x0 0x40 0xc0>; }; - pinmux_uart0_uart: pinmux_uart0_uart0 { + pinmux_uart0_uart: uart0-uart0-pins { pinctrl-single,bits = <0x0 0x0 0x300>; }; - pinmux_sdmode_sdxc: pinmux_sdmode_sdxc { + pinmux_sdmode_sdxc: sdmode-sdxc-pins { pinctrl-single,bits = <0x0 0x0 0xc00>; }; - pinmux_sdmode_gpio: pinmux_sdmode_gpio { + pinmux_sdmode_gpio: sdmode-gpio-pins { pinctrl-single,bits = <0x0 0x400 0xc00>; }; - pinmux_spi_spi: pinmux_spi_spi { + pinmux_spi_spi: spi-spi-pins { pinctrl-single,bits = <0x0 0x0 0x1000>; }; - pinmux_refclk_gpio: pinmux_refclk_gpio { + pinmux_refclk_gpio: refclk-gpio-pins { pinctrl-single,bits = <0x0 0x40000 0x40000>; }; - pinmux_i2c_i2c: pinmux_i2c_i2c { + pinmux_i2c_i2c: i2c-i2c-pins { pinctrl-single,bits = <0x0 0x0 0x300000>; }; - pinmux_uart1_uart: pinmux_uart1_uart1 { + pinmux_uart1_uart: uart1-uart1-pins { pinctrl-single,bits = <0x0 0x0 0x3000000>; }; - pinmux_uart2_uart: pinmux_uart2_uart { + pinmux_uart2_uart: uart2-uart-pins { pinctrl-single,bits = <0x0 0x0 0xc000000>; }; - pinmux_pwm0_pwm: pinmux_pwm0_pwm { + pinmux_pwm0_pwm: pwm0-pwm-pins { pinctrl-single,bits = <0x0 0x0 0x30000000>; }; - pinmux_pwm0_gpio: pinmux_pwm0_gpio { + pinmux_pwm0_gpio: pwm0-gpio-pins { pinctrl-single,bits = <0x0 0x10000000 0x30000000>; }; - pinmux_pwm1_pwm: pinmux_pwm1_pwm { + pinmux_pwm1_pwm: pwm1-pwm-pins { pinctrl-single,bits = <0x0 0x0 0xc0000000>; }; - pinmux_pwm1_gpio: pinmux_pwm1_gpio { + pinmux_pwm1_gpio: pwm1-gpio-pins { pinctrl-single,bits = <0x0 0x40000000 0xc0000000>; }; - pinmux_p0led_an_gpio: pinmux_p0led_an_gpio { + pinmux_p0led_an_gpio: p0led-an-gpio-pins { pinctrl-single,bits = <0x4 0x4 0xc>; }; - pinmux_p1led_an_gpio: pinmux_p1led_an_gpio { + pinmux_p1led_an_gpio: p1led-an-gpio-pins { pinctrl-single,bits = <0x4 0x10 0x30>; }; - pinmux_p2led_an_gpio: pinmux_p2led_an_gpio { + pinmux_p2led_an_gpio: p2led-an-gpio-pins { pinctrl-single,bits = <0x4 0x40 0xc0>; }; - pinmux_p3led_an_gpio: pinmux_p3led_an_gpio { + pinmux_p3led_an_gpio: p3led-an-gpio-pins { pinctrl-single,bits = <0x4 0x100 0x300>; }; - pinmux_p4led_an_gpio: pinmux_p4led_an_gpio { + pinmux_p4led_an_gpio: p4led-an-gpio-pins { pinctrl-single,bits = <0x4 0x400 0xc00>; }; }; diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 28677c615175..2add435ad038 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -8,232 +8,255 @@ * for more details. */ -#include +#include +#include #include -#include #include -#include #include +#include +#include +#include -#include +/* + * USB Control Register + */ +#define USBDRD_UCTL_CTL 0x00 +/* BIST fast-clear mode select. A BIST run with this bit set + * clears all entries in USBH RAMs to 0x0. + */ +# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63) +/* 1 = Start BIST and cleared by hardware */ +# define USBDRD_UCTL_CTL_START_BIST BIT(62) +/* Reference clock select for SuperSpeed and HighSpeed PLLs: + * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock + * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock + * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + */ +# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60) +/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ +# define USBDRD_UCTL_CTL_SSC_EN BIT(59) +/* Spread-spectrum clock modulation range: + * 0x0 = -4980 ppm downspread + * 0x1 = -4492 ppm downspread + * 0x2 = -4003 ppm downspread + * 0x3 - 0x7 = Reserved + */ +# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56) +/* Enable non-standard oscillator frequencies: + * [55:53] = modules -1 + * [52:47] = 2's complement push amount, 0 = Feature disabled + */ +# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47) +/* Reference clock multiplier for non-standard frequencies: + * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * Other Values = Reserved + */ +# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40) +/* Enable reference clock to prescaler for SuperSpeed functionality. + * Should always be set to "1" + */ +# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39) +/* Divide the reference clock by 2 before entering the + * REF_CLK_FSEL divider: + * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal + * If REF_CLK_SEL = 0x2 or 0x3, then: + * 0x1 = DLMC_REF_CLK* is 125MHz + * 0x0 = DLMC_REF_CLK* is another supported frequency + */ +# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38) +/* Select reference clock freqnuency for both PLL blocks: + * 0x27 = REF_CLK_SEL is 0x0 or 0x1 + * 0x07 = REF_CLK_SEL is 0x2 or 0x3 + */ +# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32) +/* Controller clock enable. */ +# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30) +/* Select bypass input to controller clock divider: + * 0x0 = Use divided coprocessor clock from H_CLKDIV + * 0x1 = Use clock from GPIO pins + */ +# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29) +/* Reset controller clock divider. */ +# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28) +/* Clock divider select: + * 0x0 = divide by 1 + * 0x1 = divide by 2 + * 0x2 = divide by 4 + * 0x3 = divide by 6 + * 0x4 = divide by 8 + * 0x5 = divide by 16 + * 0x6 = divide by 24 + * 0x7 = divide by 32 + */ +# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24) +/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21) +/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20) +/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18) +/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16) +/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14) +/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12) +/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4) +/* Controller mode: 0x0 = Host, 0x1 = Device */ +# define USBDRD_UCTL_CTL_DRD_MODE BIT(3) +/* PHY reset */ +# define USBDRD_UCTL_CTL_UPHY_RST BIT(2) +/* Software reset UAHC */ +# define USBDRD_UCTL_CTL_UAHC_RST BIT(1) +/* Software resets UCTL */ +# define USBDRD_UCTL_CTL_UCTL_RST BIT(0) -/* USB Control Register */ -union cvm_usbdrd_uctl_ctl { - uint64_t u64; - struct cvm_usbdrd_uctl_ctl_s { - /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */ - __BITFIELD_FIELD(uint64_t clear_bist:1, - /* 1 = Start BIST and cleared by hardware */ - __BITFIELD_FIELD(uint64_t start_bist:1, - /* Reference clock select for SuperSpeed and HighSpeed PLLs: - * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock - * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock - * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & - * HighSpeed PLL uses PLL_REF_CLK for reference clck - * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & - * HighSpeed PLL uses PLL_REF_CLK for reference clck - */ - __BITFIELD_FIELD(uint64_t ref_clk_sel:2, - /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ - __BITFIELD_FIELD(uint64_t ssc_en:1, - /* Spread-spectrum clock modulation range: - * 0x0 = -4980 ppm downspread - * 0x1 = -4492 ppm downspread - * 0x2 = -4003 ppm downspread - * 0x3 - 0x7 = Reserved - */ - __BITFIELD_FIELD(uint64_t ssc_range:3, - /* Enable non-standard oscillator frequencies: - * [55:53] = modules -1 - * [52:47] = 2's complement push amount, 0 = Feature disabled - */ - __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9, - /* Reference clock multiplier for non-standard frequencies: - * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * Other Values = Reserved - */ - __BITFIELD_FIELD(uint64_t mpll_multiplier:7, - /* Enable reference clock to prescaler for SuperSpeed functionality. - * Should always be set to "1" - */ - __BITFIELD_FIELD(uint64_t ref_ssp_en:1, - /* Divide the reference clock by 2 before entering the - * REF_CLK_FSEL divider: - * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal - * If REF_CLK_SEL = 0x2 or 0x3, then: - * 0x1 = DLMC_REF_CLK* is 125MHz - * 0x0 = DLMC_REF_CLK* is another supported frequency - */ - __BITFIELD_FIELD(uint64_t ref_clk_div2:1, - /* Select reference clock freqnuency for both PLL blocks: - * 0x27 = REF_CLK_SEL is 0x0 or 0x1 - * 0x07 = REF_CLK_SEL is 0x2 or 0x3 - */ - __BITFIELD_FIELD(uint64_t ref_clk_fsel:6, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_31_31:1, - /* Controller clock enable. */ - __BITFIELD_FIELD(uint64_t h_clk_en:1, - /* Select bypass input to controller clock divider: - * 0x0 = Use divided coprocessor clock from H_CLKDIV - * 0x1 = Use clock from GPIO pins - */ - __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1, - /* Reset controller clock divider. */ - __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_27_27:1, - /* Clock divider select: - * 0x0 = divide by 1 - * 0x1 = divide by 2 - * 0x2 = divide by 4 - * 0x3 = divide by 6 - * 0x4 = divide by 8 - * 0x5 = divide by 16 - * 0x6 = divide by 24 - * 0x7 = divide by 32 - */ - __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_22_23:2, - /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1, - /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_19_19:1, - /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb3_port_disable:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_17_17:1, - /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb2_port_disable:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_15_15:1, - /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t ss_power_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_13_13:1, - /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t hs_power_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_5_11:7, - /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t csclk_en:1, - /* Controller mode: 0x0 = Host, 0x1 = Device */ - __BITFIELD_FIELD(uint64_t drd_mode:1, - /* PHY reset */ - __BITFIELD_FIELD(uint64_t uphy_rst:1, - /* Software reset UAHC */ - __BITFIELD_FIELD(uint64_t uahc_rst:1, - /* Software resets UCTL */ - __BITFIELD_FIELD(uint64_t uctl_rst:1, - ;))))))))))))))))))))))))))))))))) - } s; -}; +#define USBDRD_UCTL_BIST_STATUS 0x08 +#define USBDRD_UCTL_SPARE0 0x10 +#define USBDRD_UCTL_INTSTAT 0x30 +#define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port)) -/* UAHC Configuration Register */ -union cvm_usbdrd_uctl_host_cfg { - uint64_t u64; - struct cvm_usbdrd_uctl_host_cfg_s { - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_60_63:4, - /* Indicates minimum value of all received BELT values */ - __BITFIELD_FIELD(uint64_t host_current_belt:12, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_38_47:10, - /* HS jitter adjustment */ - __BITFIELD_FIELD(uint64_t fla:6, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_29_31:3, - /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ - __BITFIELD_FIELD(uint64_t bme:1, - /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ - __BITFIELD_FIELD(uint64_t oci_en:1, - /* Overcurrent sene selection: - * 0x0 = Overcurrent indication from off-chip is active-low - * 0x1 = Overcurrent indication from off-chip is active-high - */ - __BITFIELD_FIELD(uint64_t oci_active_high_en:1, - /* Port power control enable: 0x0 = unavailable, 0x1 = available */ - __BITFIELD_FIELD(uint64_t ppc_en:1, - /* Port power control sense selection: - * 0x0 = Port power to off-chip is active-low - * 0x1 = Port power to off-chip is active-high - */ - __BITFIELD_FIELD(uint64_t ppc_active_high_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_0_23:24, - ;))))))))))) - } s; -}; +/* + * UCTL Configuration Register + */ +#define USBDRD_UCTL_HOST_CFG 0xe0 +/* Indicates minimum value of all received BELT values */ +# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48) +/* HS jitter adjustment */ +# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32) +/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ +# define USBDRD_UCTL_HOST_CFG_BME BIT(28) +/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ +# define USBDRD_UCTL_HOST_OCI_EN BIT(27) +/* Overcurrent sene selection: + * 0x0 = Overcurrent indication from off-chip is active-low + * 0x1 = Overcurrent indication from off-chip is active-high + */ +# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26) +/* Port power control enable: 0x0 = unavailable, 0x1 = available */ +# define USBDRD_UCTL_HOST_PPC_EN BIT(25) +/* Port power control sense selection: + * 0x0 = Port power to off-chip is active-low + * 0x1 = Port power to off-chip is active-high + */ +# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24) -/* UCTL Shim Features Register */ -union cvm_usbdrd_uctl_shim_cfg { - uint64_t u64; - struct cvm_usbdrd_uctl_shim_cfg_s { - /* Out-of-bound UAHC register access: 0 = read, 1 = write */ - __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_60_62:3, - /* SRCID error log for out-of-bound UAHC register access: - * [59:58] = chipID - * [57] = Request source: 0 = core, 1 = NCB-device - * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices - * [50:48] = SubID - */ - __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12, - /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ - __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_44_46:3, - /* Encoded error type for bad UAHC DMA */ - __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_13_39:27, - /* Select the IOI read command used by DMA accesses */ - __BITFIELD_FIELD(uint64_t dma_read_cmd:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_10_11:2, - /* Select endian format for DMA accesses to the L2c: - * 0x0 = Little endian - *` 0x1 = Big endian - * 0x2 = Reserved - * 0x3 = Reserved - */ - __BITFIELD_FIELD(uint64_t dma_endian_mode:2, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_2_7:6, - /* Select endian format for IOI CSR access to UAHC: - * 0x0 = Little endian - *` 0x1 = Big endian - * 0x2 = Reserved - * 0x3 = Reserved - */ - __BITFIELD_FIELD(uint64_t csr_endian_mode:2, - ;)))))))))))) - } s; -}; +/* + * UCTL Shim Features Register + */ +#define USBDRD_UCTL_SHIM_CFG 0xe8 +/* Out-of-bound UAHC register access: 0 = read, 1 = write */ +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63) +/* SRCID error log for out-of-bound UAHC register access: + * [59:58] = chipID + * [57] = Request source: 0 = core, 1 = NCB-device + * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices + * [50:48] = SubID + */ +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48) +/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47) +/* Encoded error type for bad UAHC DMA */ +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40) +/* Select the IOI read command used by DMA accesses */ +# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12) +/* Select endian format for DMA accesses to the L2C: + * 0x0 = Little endian + * 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ +# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8) +/* Select endian format for IOI CSR access to UAHC: + * 0x0 = Little endian + * 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ +# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0) -#define OCTEON_H_CLKDIV_SEL 8 -#define OCTEON_MIN_H_CLK_RATE 150000000 -#define OCTEON_MAX_H_CLK_RATE 300000000 +#define USBDRD_UCTL_ECC 0xf0 +#define USBDRD_UCTL_SPARE1 0xf8 static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); -static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; - -static int dwc3_octeon_config_power(struct device *dev, u64 base) +#ifdef CONFIG_CAVIUM_OCTEON_SOC +#include +static inline uint64_t dwc3_octeon_readq(void __iomem *addr) +{ + return cvmx_readq_csr(addr); +} + +static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) +{ + cvmx_writeq_csr(base, val); +} + +static void dwc3_octeon_config_gpio(int index, int gpio) { -#define UCTL_HOST_CFG 0xe0 - union cvm_usbdrd_uctl_host_cfg uctl_host_cfg; union cvmx_gpio_bit_cfgx gpio_bit; + + if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || + OCTEON_IS_MODEL(OCTEON_CNF75XX)) + && gpio <= 31) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else if (gpio <= 15) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); + } +} +#else +static inline uint64_t dwc3_octeon_readq(void __iomem *addr) +{ + return 0; +} + +static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } + +static inline void dwc3_octeon_config_gpio(int index, int gpio) { } +#endif + +static int dwc3_octeon_get_divider(void) +{ + static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 }; + int div = 0; + + while (div < ARRAY_SIZE(clk_div)) { + uint64_t rate = octeon_get_io_clock_rate() / clk_div[div]; + if (rate <= 300000000 && rate >= 150000000) + break; + div++; + } + + return div; +} + +static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) +{ uint32_t gpio_pwr[3]; int gpio, len, power_active_low; struct device_node *node = dev->of_node; - int index = (base >> 24) & 1; + u64 val; + void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; if (of_find_property(node, "power", &len) != NULL) { if (len == 12) { @@ -248,51 +271,33 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) dev_err(dev, "invalid power configuration\n"); return -EINVAL; } - if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || - OCTEON_IS_MODEL(OCTEON_CNF75XX)) - && gpio <= 31) { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); - } else if (gpio <= 15) { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); - } else { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); - cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); - } + dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio); /* Enable XHCI power control and set if active high or low. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); - uctl_host_cfg.s.ppc_en = 1; - uctl_host_cfg.s.ppc_active_high_en = !power_active_low; - cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + val = dwc3_octeon_readq(uctl_host_cfg_reg); + val |= USBDRD_UCTL_HOST_PPC_EN; + if (power_active_low) + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + else + val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + dwc3_octeon_writeq(uctl_host_cfg_reg, val); } else { /* Disable XHCI power control and set if active high. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); - uctl_host_cfg.s.ppc_en = 0; - uctl_host_cfg.s.ppc_active_high_en = 0; - cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + val = dwc3_octeon_readq(uctl_host_cfg_reg); + val &= ~USBDRD_UCTL_HOST_PPC_EN; + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + dwc3_octeon_writeq(uctl_host_cfg_reg, val); dev_info(dev, "power control disabled\n"); } return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, u64 base) +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) { - union cvm_usbdrd_uctl_ctl uctl_ctl; - int ref_clk_sel = 2; - u64 div; + int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; - int mpll_mul; - int i; - u64 h_clk_rate; - u64 uctl_ctl_reg = base; + u64 val; + void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; if (dev->of_node) { const char *ss_clock_type; @@ -356,44 +361,42 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ /* Step 3: Assert all resets. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uphy_rst = 1; - uctl_ctl.s.uahc_rst = 1; - uctl_ctl.s.uctl_rst = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_UPHY_RST | + USBDRD_UCTL_CTL_UAHC_RST | + USBDRD_UCTL_CTL_UCTL_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 4a: Reset the clock dividers. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_rst = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_H_CLKDIV_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 4b: Select controller clock frequency. */ - for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) { - h_clk_rate = octeon_get_io_clock_rate() / clk_div[div]; - if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE && - h_clk_rate >= OCTEON_MIN_H_CLK_RATE) - break; - } - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_sel = div; - uctl_ctl.s.h_clk_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) { + div = dwc3_octeon_get_divider(); + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); + val |= USBDRD_UCTL_CTL_H_CLK_EN; + dwc3_octeon_writeq(uctl_ctl_reg, val); + val = dwc3_octeon_readq(uctl_ctl_reg); + if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || + (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { dev_err(dev, "dwc3 controller clock init failure.\n"); return -EINVAL; } /* Step 4c: Deassert the controller clock divider reset. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 5a: Reference clock configuration. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.ref_clk_sel = ref_clk_sel; - uctl_ctl.s.ref_clk_fsel = 0x07; - uctl_ctl.s.ref_clk_div2 = 0; + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2; + val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); + + ref_clk_fsel = 0x07; switch (clock_rate) { default: dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", @@ -402,7 +405,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) case 100000000: mpll_mul = 0x19; if (ref_clk_sel < 2) - uctl_ctl.s.ref_clk_fsel = 0x27; + ref_clk_fsel = 0x27; break; case 50000000: mpll_mul = 0x32; @@ -411,28 +414,32 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) mpll_mul = 0x28; break; } - uctl_ctl.s.mpll_multiplier = mpll_mul; + val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); + + val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER; + val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ - uctl_ctl.s.ssc_en = 1; + val |= USBDRD_UCTL_CTL_SSC_EN; /* Step 5c: Enable SuperSpeed. */ - uctl_ctl.s.ref_ssp_en = 1; + val |= USBDRD_UCTL_CTL_REF_SSP_EN; /* Step 5d: Configure PHYs. SKIP */ /* Step 6a & 6b: Power up PHYs. */ - uctl_ctl.s.hs_power_en = 1; - uctl_ctl.s.ss_power_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val |= USBDRD_UCTL_CTL_HS_POWER_EN; + val |= USBDRD_UCTL_CTL_SS_POWER_EN; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 7: Wait 10 controller-clock cycles to take effect. */ udelay(10); /* Step 8a: Deassert UCTL reset signal. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uctl_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UCTL_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 8b: Wait 10 controller-clock cycles. */ udelay(10); @@ -442,53 +449,49 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) return -EINVAL; /* Step 8d: Deassert UAHC reset signal. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uahc_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UAHC_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 8e: Wait 10 controller-clock cycles. */ udelay(10); /* Step 9: Enable conditional coprocessor clock of UCTL. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.csclk_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_CSCLK_EN; + dwc3_octeon_writeq(uctl_ctl_reg, val); /*Step 10: Set for host mode only. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.drd_mode = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_DRD_MODE; + dwc3_octeon_writeq(uctl_ctl_reg, val); return 0; } -static void __init dwc3_octeon_set_endian_mode(u64 base) +static void __init dwc3_octeon_set_endian_mode(void __iomem *base) { -#define UCTL_SHIM_CFG 0xe8 - union cvm_usbdrd_uctl_shim_cfg shim_cfg; + u64 val; + void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; - shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); + val = dwc3_octeon_readq(uctl_shim_cfg_reg); + val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; + val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE; #ifdef __BIG_ENDIAN - shim_cfg.s.dma_endian_mode = 1; - shim_cfg.s.csr_endian_mode = 1; -#else - shim_cfg.s.dma_endian_mode = 0; - shim_cfg.s.csr_endian_mode = 0; + val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); + val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); #endif - cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); + dwc3_octeon_writeq(uctl_shim_cfg_reg, val); } -#define CVMX_USBDRDX_UCTL_CTL(index) \ - (CVMX_ADD_IO_SEG(0x0001180068000000ull) + \ - ((index & 1) * 0x1000000ull)) -static void __init dwc3_octeon_phy_reset(u64 base) +static void __init dwc3_octeon_phy_reset(void __iomem *base) { - union cvm_usbdrd_uctl_ctl uctl_ctl; - int index = (base >> 24) & 1; + u64 val; + void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; - uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index)); - uctl_ctl.s.uphy_rst = 0; - cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64); + val = dwc3_octeon_readq(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UPHY_RST; + dwc3_octeon_writeq(uctl_ctl_reg, val); } static int __init dwc3_octeon_device_init(void) @@ -527,10 +530,10 @@ static int __init dwc3_octeon_device_init(void) } mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0) + if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode((u64)base); - dwc3_octeon_phy_reset((u64)base); + dwc3_octeon_set_endian_mode(base); + dwc3_octeon_phy_reset(base); mutex_unlock(&dwc3_octeon_clocks_mutex); devm_iounmap(&pdev->dev, base); devm_release_mem_region(&pdev->dev, res->start, diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig index ed4a6388791e..329c60aa570a 100644 --- a/arch/mips/configs/ar7_defconfig +++ b/arch/mips/configs/ar7_defconfig @@ -11,7 +11,6 @@ CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_AR7=y CONFIG_HZ_100=y CONFIG_KEXEC=y diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 22ffde722bb9..62c462a23edc 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -3,7 +3,6 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_BCM47XX=y CONFIG_PCI=y # CONFIG_SUSPEND is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index d15961f00ece..b0cbfa781ffc 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -17,7 +17,6 @@ CONFIG_USER_NS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_SIBYTE_BIGSUR=y CONFIG_64BIT=y CONFIG_SMP=y diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 0bc2e3cc573b..f523ee6f25bf 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -9,7 +9,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_CAVIUM_OCTEON_SOC=y CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 11f08b6a3013..812287a5b4fd 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -19,19 +19,18 @@ CONFIG_USER_NS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_INGENIC_SOC=y CONFIG_JZ4780_CI20=y CONFIG_HIGHMEM=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set # CONFIG_SUSPEND is not set +# CONFIG_SECCOMP is not set CONFIG_MODULES=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set # CONFIG_COMPACTION is not set CONFIG_CMA=y +# CONFIG_VM_EVENT_COUNTERS is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -40,7 +39,12 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set +CONFIG_BT=m +# CONFIG_BT_LE is not set +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y CONFIG_DEVTMPFS=y CONFIG_FW_LOADER=m # CONFIG_ALLOW_DEV_COREDUMP is not set @@ -68,10 +72,27 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_BRCMFMAC=m +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_PURELIFI is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_SILABS is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set CONFIG_KEYBOARD_GPIO=m # CONFIG_INPUT_MOUSE is not set -CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_LEGACY_PTY_COUNT=2 CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y @@ -79,6 +100,7 @@ CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_INGENIC=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_DEV_BUS=y CONFIG_I2C=y CONFIG_I2C_JZ4780=y CONFIG_SPI=y @@ -99,13 +121,12 @@ CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m CONFIG_DRM=m +CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_INGENIC=m CONFIG_DRM_INGENIC_DW_HDMI=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -# CONFIG_VGA_CONSOLE is not set CONFIG_FB=y +# CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_HID is not set CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC2=y @@ -125,7 +146,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=y -CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=m @@ -144,7 +164,6 @@ CONFIG_JZ4780_NEMC=y CONFIG_PWM=y CONFIG_PWM_JZ4740=m CONFIG_NVMEM_JZ4780_EFUSE=y -CONFIG_JZ4770_PHY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_AUTOFS_FS=y @@ -157,7 +176,6 @@ CONFIG_CONFIGFS_FS=y CONFIG_UBIFS_FS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y -CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=y CONFIG_NLS_CODEPAGE_775=y @@ -196,6 +214,7 @@ CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=y CONFIG_NLS_UTF8=y +# CONFIG_CRYPTO_AES is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=32 CONFIG_PRINTK_TIME=y @@ -206,7 +225,6 @@ CONFIG_DEBUG_FS=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=10 # CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=y diff --git a/arch/mips/configs/cu1000-neo_defconfig b/arch/mips/configs/cu1000-neo_defconfig index 1cbc9302e1d1..afe39ce7568e 100644 --- a/arch/mips/configs/cu1000-neo_defconfig +++ b/arch/mips/configs/cu1000-neo_defconfig @@ -18,7 +18,6 @@ CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_INGENIC_SOC=y CONFIG_X1000_CU1000_NEO=y CONFIG_HIGHMEM=y diff --git a/arch/mips/configs/cu1830-neo_defconfig b/arch/mips/configs/cu1830-neo_defconfig index a0f73f3cd6ce..347c9fd1c21d 100644 --- a/arch/mips/configs/cu1830-neo_defconfig +++ b/arch/mips/configs/cu1830-neo_defconfig @@ -18,7 +18,6 @@ CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_INGENIC_SOC=y CONFIG_X1830_CU1830_NEO=y CONFIG_HIGHMEM=y diff --git a/arch/mips/configs/db1xxx_defconfig b/arch/mips/configs/db1xxx_defconfig index af070be1b583..08d29b56e175 100644 --- a/arch/mips/configs/db1xxx_defconfig +++ b/arch/mips/configs/db1xxx_defconfig @@ -18,7 +18,6 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_ALCHEMY=y CONFIG_HZ_100=y CONFIG_PCI=y diff --git a/arch/mips/configs/decstation_64_defconfig b/arch/mips/configs/decstation_64_defconfig index 49ec1575234e..92a1d0aea38c 100644 --- a/arch/mips/configs/decstation_64_defconfig +++ b/arch/mips/configs/decstation_64_defconfig @@ -9,7 +9,6 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_DECSTATION=y CONFIG_64BIT=y CONFIG_PAGE_SIZE_16KB=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 5cec4c096e2c..db214fcebcbe 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -9,7 +9,6 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_DECSTATION=y CONFIG_CPU_R3000=y CONFIG_TC=y diff --git a/arch/mips/configs/decstation_r4k_defconfig b/arch/mips/configs/decstation_r4k_defconfig index af37e26d9b5b..15b769e96d5b 100644 --- a/arch/mips/configs/decstation_r4k_defconfig +++ b/arch/mips/configs/decstation_r4k_defconfig @@ -9,7 +9,6 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_DECSTATION=y CONFIG_TC=y # CONFIG_SUSPEND is not set diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 843d6a5a4f61..5458573286a2 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -13,7 +13,6 @@ CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MACH_LOONGSON2EF=y CONFIG_PCI=y diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index eb755650f821..92fc0edbac47 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -8,7 +8,6 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MIPS_ALCHEMY=y CONFIG_MIPS_GPR=y diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 13df29901237..897e55579af0 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -10,7 +10,6 @@ CONFIG_USER_NS=y CONFIG_RELAY=y CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_SGI_IP22=y CONFIG_ARC_CONSOLE=y CONFIG_CPU_R5000=y diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 3e86f8106ba0..b51f738a39a0 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -9,7 +9,6 @@ CONFIG_CGROUPS=y CONFIG_CPUSETS=y CONFIG_RELAY=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_SGI_IP27=y CONFIG_NUMA=y CONFIG_SMP=y diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index ba13eea0509f..e0040110a3ee 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -5,7 +5,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_SGI_IP28=y CONFIG_ARC_CONSOLE=y CONFIG_EISA=y diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 8ced2224c328..418a4181e2fe 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -7,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_SGI_IP32=y # CONFIG_SECCOMP is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 106b21cb677f..6b5d7e963ed9 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -7,7 +7,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_MACH_JAZZ=y CONFIG_OLIVETTI_M700=y CONFIG_MIPS_MAGNUM_4000=y diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 6f4a52608ea4..3087e64e6ebe 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -276,6 +276,13 @@ CONFIG_MEDIA_SUPPORT=m CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_DRM=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_SI=y CONFIG_DRM_RADEON=m CONFIG_DRM_QXL=y CONFIG_DRM_VIRTIO_GPU=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 265d38dffbf6..743209047792 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -7,7 +7,6 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig index 1d2b248c7cd3..dd2b9c181f32 100644 --- a/arch/mips/configs/malta_kvm_defconfig +++ b/arch/mips/configs/malta_kvm_defconfig @@ -7,7 +7,6 @@ CONFIG_RELAY=y CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig b/arch/mips/configs/malta_qemu_32r6_defconfig index fd63a2b152f6..82183ec6bc31 100644 --- a/arch/mips/configs/malta_qemu_32r6_defconfig +++ b/arch/mips/configs/malta_qemu_32r6_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R6=y diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig index 1f07e354c954..9a199867a5e7 100644 --- a/arch/mips/configs/maltaaprp_defconfig +++ b/arch/mips/configs/maltaaprp_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig index 5cd3eca236de..e5502d66a474 100644 --- a/arch/mips/configs/maltasmvp_defconfig +++ b/arch/mips/configs/maltasmvp_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig index 45688e742a15..a378aad97138 100644 --- a/arch/mips/configs/maltasmvp_eva_defconfig +++ b/arch/mips/configs/maltasmvp_eva_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig index 136f965784db..fc6f88cae7be 100644 --- a/arch/mips/configs/maltaup_defconfig +++ b/arch/mips/configs/maltaup_defconfig @@ -7,7 +7,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig index 75b8da8d9927..97c2d7f530b3 100644 --- a/arch/mips/configs/maltaup_xpa_defconfig +++ b/arch/mips/configs/maltaup_xpa_defconfig @@ -8,7 +8,6 @@ CONFIG_NAMESPACES=y CONFIG_RELAY=y CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MIPS_MALTA=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R2=y diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index a5c68e9b0482..b64172179160 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -8,7 +8,6 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MIPS_ALCHEMY=y CONFIG_MIPS_MTX1=y diff --git a/arch/mips/configs/pic32mzda_defconfig b/arch/mips/configs/pic32mzda_defconfig index 48dd02d01ac1..8397f28355d5 100644 --- a/arch/mips/configs/pic32mzda_defconfig +++ b/arch/mips/configs/pic32mzda_defconfig @@ -9,7 +9,6 @@ CONFIG_RELAY=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_PIC32=y CONFIG_DTB_PIC32_MZDA_SK=y CONFIG_HZ_100=y diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig index 7e5d9741bd5d..c27c8c7151a1 100644 --- a/arch/mips/configs/qi_lb60_defconfig +++ b/arch/mips/configs/qi_lb60_defconfig @@ -6,7 +6,6 @@ CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MACH_INGENIC_SOC=y CONFIG_JZ4740_QI_LB60=y CONFIG_HZ_100=y diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index 93306f5e045b..02ec6c1a5116 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -11,7 +11,6 @@ CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set # CONFIG_KALLSYMS is not set # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y CONFIG_MIKROTIK_RB532=y CONFIG_HZ_100=y # CONFIG_SECCOMP is not set diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index 30c195f28278..03a7bbe28a53 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig @@ -7,7 +7,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_EPOLL is not set -CONFIG_SLAB=y CONFIG_MACH_TX49XX=y CONFIG_TOSHIBA_RBTX4927=y # CONFIG_SECCOMP is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 9932a593e3c3..7475c2cbea89 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -7,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_SNI_RM=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_ARC_CONSOLE=y diff --git a/arch/mips/configs/rs90_defconfig b/arch/mips/configs/rs90_defconfig index 7ce3b814fdc8..85ea2a6775f5 100644 --- a/arch/mips/configs/rs90_defconfig +++ b/arch/mips/configs/rs90_defconfig @@ -17,7 +17,6 @@ CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y # CONFIG_KALLSYMS is not set CONFIG_EMBEDDED=y # CONFIG_PERF_EVENTS is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MACH_INGENIC_SOC=y CONFIG_JZ4740_RS90=y diff --git a/arch/mips/configs/sb1250_swarm_defconfig b/arch/mips/configs/sb1250_swarm_defconfig index 030186f89501..ce855b644bb0 100644 --- a/arch/mips/configs/sb1250_swarm_defconfig +++ b/arch/mips/configs/sb1250_swarm_defconfig @@ -10,7 +10,6 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_SIBYTE_SWARM=y CONFIG_CPU_SB1_PASS_2_2=y CONFIG_64BIT=y diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c index c422bbc890ed..1f4906875e7b 100644 --- a/arch/mips/generic/board-ingenic.c +++ b/arch/mips/generic/board-ingenic.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -60,6 +61,50 @@ static __init char *ingenic_get_system_type(unsigned long machtype) } } +#define INGENIC_CGU_BASE 0x10000000 +#define JZ4750_CGU_CPCCR_ECS BIT(30) +#define JZ4760_CGU_CPCCR_ECS BIT(31) + +static __init void ingenic_force_12M_ext(const void *fdt, unsigned int mask) +{ + const __be32 *prop; + unsigned int cpccr; + void __iomem *cgu; + bool use_div; + int offset; + + offset = fdt_path_offset(fdt, "/ext"); + if (offset < 0) + return; + + prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); + if (!prop) + return; + + /* + * If the external oscillator is 24 MHz, enable the /2 divider to + * drive it down to 12 MHz, since this is what the hardware can work + * with. + * The 16 MHz cutoff value is arbitrary; setting it to 12 MHz would not + * work as the crystal frequency (as reported in the Device Tree) might + * be slightly above this value. + */ + use_div = be32_to_cpup(prop) >= 16000000; + + cgu = ioremap(INGENIC_CGU_BASE, 0x4); + if (!cgu) + return; + + cpccr = ioread32(cgu); + if (use_div) + cpccr |= mask; + else + cpccr &= ~mask; + iowrite32(cpccr, cgu); + + iounmap(cgu); +} + static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data) { /* @@ -73,6 +118,18 @@ static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_d mips_machtype = (unsigned long)match_data; system_type = ingenic_get_system_type(mips_machtype); + switch (mips_machtype) { + case MACH_INGENIC_JZ4750: + case MACH_INGENIC_JZ4755: + ingenic_force_12M_ext(fdt, JZ4750_CGU_CPCCR_ECS); + break; + case MACH_INGENIC_JZ4760: + ingenic_force_12M_ext(fdt, JZ4760_CGU_CPCCR_ECS); + break; + default: + break; + } + return fdt; } @@ -117,14 +174,14 @@ static void ingenic_halt(void) ingenic_wait_instr(); } -static int __maybe_unused ingenic_pm_enter(suspend_state_t state) +static int ingenic_pm_enter(suspend_state_t state) { ingenic_wait_instr(); return 0; } -static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = { +static const struct platform_suspend_ops ingenic_pm_ops = { .valid = suspend_valid_only_mem, .enter = ingenic_pm_enter, }; diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 51a1737b03d0..404390bb87ea 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -125,7 +125,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_CAVIUM_OCTEON: \ case CPU_CAVIUM_OCTEON_PLUS: \ case CPU_CAVIUM_OCTEON2: \ @@ -368,7 +368,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_M14KC: \ case CPU_74K: \ case CPU_1074K: \ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index 1e1247add1cf..908e96e3a311 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -70,7 +70,7 @@ static inline bool prom_is_rex(u32 magic) */ typedef struct { int pagesize; - unsigned char bitmap[0]; + unsigned char bitmap[]; } memmap; diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index cc28d207a061..affd21e9c20b 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -554,6 +554,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); * access */ #define xlate_dev_mem_ptr(p) __va(p) +#define unxlate_dev_mem_ptr(p, v) do { } while (0) void __ioread64_copy(void *to, const void __iomem *from, size_t count); diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h index d8f9dec0ecc3..7971272345d3 100644 --- a/arch/mips/include/asm/mach-loongson32/loongson1.h +++ b/arch/mips/include/asm/mach-loongson32/loongson1.h @@ -48,6 +48,5 @@ #include #include #include -#include #endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */ diff --git a/arch/mips/include/asm/mach-loongson32/regs-wdt.h b/arch/mips/include/asm/mach-loongson32/regs-wdt.h deleted file mode 100644 index c6d345fe13f2..000000000000 --- a/arch/mips/include/asm/mach-loongson32/regs-wdt.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2011 Zhang, Keguang - * - * Loongson 1 Watchdog Register Definitions. - */ - -#ifndef __ASM_MACH_LOONGSON32_REGS_WDT_H -#define __ASM_MACH_LOONGSON32_REGS_WDT_H - -#define WDT_EN 0x0 -#define WDT_TIMER 0x4 -#define WDT_SET 0x8 - -#endif /* __ASM_MACH_LOONGSON32_REGS_WDT_H */ diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 3e37705ea9cf..62f4f072c003 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -20,52 +20,17 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 -#define SYSC_REG_CLKCFG0 0x2c -#define SYSC_REG_CPU_SYS_CLKCFG 0x3c -#define SYSC_REG_CPLL_CONFIG0 0x54 -#define SYSC_REG_CPLL_CONFIG1 0x58 #define MT7620_CHIP_NAME0 0x3637544d #define MT7620_CHIP_NAME1 0x20203032 #define MT7628_CHIP_NAME1 0x20203832 -#define SYSCFG0_XTAL_FREQ_SEL BIT(6) - #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 #define CHIP_REV_VER_MASK 0xf #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf -#define CLKCFG0_PERI_CLK_SEL BIT(4) - -#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 -#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf -#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ -#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 -#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f -#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 -#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f - -#define CPLL_CFG0_SW_CFG BIT(31) -#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 -#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 -#define CPLL_CFG0_LC_CURFCK BIT(15) -#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) -#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 -#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 - -#define CPLL_CFG1_CPU_AUX1 BIT(25) -#define CPLL_CFG1_CPU_AUX0 BIT(24) - #define SYSCFG0_DRAM_TYPE_MASK 0x3 #define SYSCFG0_DRAM_TYPE_SHIFT 4 #define SYSCFG0_DRAM_TYPE_SDRAM 0 diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h index 66a999cd1d80..66d190358e3a 100644 --- a/arch/mips/include/asm/mach-ralink/rt288x.h +++ b/arch/mips/include/asm/mach-ralink/rt288x.h @@ -18,7 +18,6 @@ #define SYSC_REG_CHIP_NAME1 0x04 #define SYSC_REG_CHIP_ID 0x0c #define SYSC_REG_SYSTEM_CONFIG 0x10 -#define SYSC_REG_CLKCFG 0x30 #define RT2880_CHIP_NAME0 0x38325452 #define RT2880_CHIP_NAME1 0x20203038 @@ -27,15 +26,6 @@ #define CHIP_ID_ID_SHIFT 8 #define CHIP_ID_REV_MASK 0xff -#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 -#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 -#define SYSTEM_CONFIG_CPUCLK_250 0x0 -#define SYSTEM_CONFIG_CPUCLK_266 0x1 -#define SYSTEM_CONFIG_CPUCLK_280 0x2 -#define SYSTEM_CONFIG_CPUCLK_300 0x3 - -#define CLKCFG_SRAM_CS_N_WDT BIT(9) - #define RT2880_SDRAM_BASE 0x08000000 #define RT2880_MEM_SIZE_MIN 2 #define RT2880_MEM_SIZE_MAX 128 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index ef58f7bff957..4fc5c279cd75 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -67,26 +67,9 @@ static inline int soc_is_rt5350(void) #define CHIP_ID_ID_SHIFT 8 #define CHIP_ID_REV_MASK 0xff -#define RT305X_SYSCFG_CPUCLK_SHIFT 18 -#define RT305X_SYSCFG_CPUCLK_MASK 0x1 -#define RT305X_SYSCFG_CPUCLK_LOW 0x0 -#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 - #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 -#define RT305X_SYSCFG_CPUCLK_MASK 0x1 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 -#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 -#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 -#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 -#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 - -#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 -#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 -#define RT5350_SYSCFG0_CPUCLK_360 0x0 -#define RT5350_SYSCFG0_CPUCLK_320 0x2 -#define RT5350_SYSCFG0_CPUCLK_300 0x3 - #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 @@ -117,13 +100,9 @@ static inline int soc_is_rt5350(void) #define RT3352_SYSC_REG_SYSCFG0 0x010 #define RT3352_SYSC_REG_SYSCFG1 0x014 -#define RT3352_SYSC_REG_CLKCFG1 0x030 #define RT3352_SYSC_REG_RSTCTRL 0x034 #define RT3352_SYSC_REG_USB_PS 0x05c -#define RT3352_CLKCFG0_XTAL_SEL BIT(20) -#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) -#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) #define RT3352_RSTCTRL_UHST BIT(22) #define RT3352_RSTCTRL_UDEV BIT(25) #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h index ad25d5e8d2dc..4a835b178925 100644 --- a/arch/mips/include/asm/mach-ralink/rt3883.h +++ b/arch/mips/include/asm/mach-ralink/rt3883.h @@ -92,14 +92,6 @@ #define RT3883_REVID_VER_ID_SHIFT 8 #define RT3883_REVID_ECO_ID_MASK 0x0f -#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) -#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 -#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 -#define RT3883_SYSCFG0_CPUCLK_250 0x0 -#define RT3883_SYSCFG0_CPUCLK_384 0x1 -#define RT3883_SYSCFG0_CPUCLK_480 0x2 -#define RT3883_SYSCFG0_CPUCLK_500 0x3 - #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index aab8981bc32c..a40d8c0e4b87 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -57,6 +57,8 @@ extern int __cpu_logical_map[NR_CPUS]; /* Mask of CPUs which are currently definitely operating coherently */ extern cpumask_t cpu_coherent_mask; +extern unsigned int smp_max_threads __initdata; + extern asmlinkage void smp_bootstrap(void); extern void calculate_cpu_foreign_map(void); diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 43d1faa02933..c29dbc8c1d49 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -272,6 +272,27 @@ enum lx_func { lbx_op = 0x16, }; +/* + * func field for special2 MXU opcodes (Ingenic XBurst MXU). + */ +enum mxu_func { + /* TODO, other MXU funcs */ + mxu_lx_op = 0x28, +}; + +/* + * op field for special2 MXU LX opcodes (Ingenic XBurst MXU). + */ +enum lx_ingenic_func { + mxu_lxb_op, + mxu_lxh_op, + /* reserved */ + mxu_lxw_op = 3, + mxu_lxbu_op, + mxu_lxhu_op, + /* more reserved */ +}; + /* * BSHFL opcodes */ @@ -774,6 +795,17 @@ struct dsp_format { /* SPEC3 DSP format instructions */ ;)))))) }; +struct mxu_lx_format { /* SPEC2 MXU LX format instructions */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int strd : 2, + __BITFIELD_FIELD(unsigned int op : 3, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + struct spec3_format { /* SPEC3 */ __BITFIELD_FIELD(unsigned int opcode:6, __BITFIELD_FIELD(unsigned int rs:5, @@ -1125,6 +1157,7 @@ union mips_instruction { struct loongson3_lswc2_format loongson3_lswc2_format; struct loongson3_lsdc2_format loongson3_lsdc2_format; struct loongson3_lscsr_format loongson3_lscsr_format; + struct mxu_lx_format mxu_lx_format; }; union mips16e_instruction { diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 40fd4051bb3d..d1b11f66f748 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -23,6 +23,7 @@ #include +void output_ptreg_defines(void); void output_ptreg_defines(void) { COMMENT("MIPS pt_regs offsets."); @@ -75,6 +76,7 @@ void output_ptreg_defines(void) BLANK(); } +void output_task_defines(void); void output_task_defines(void) { COMMENT("MIPS task_struct offsets."); @@ -89,6 +91,7 @@ void output_task_defines(void) BLANK(); } +void output_thread_info_defines(void); void output_thread_info_defines(void) { COMMENT("MIPS thread_info offsets."); @@ -105,6 +108,7 @@ void output_thread_info_defines(void) BLANK(); } +void output_thread_defines(void); void output_thread_defines(void) { COMMENT("MIPS specific thread_struct offsets."); @@ -133,6 +137,7 @@ void output_thread_defines(void) } #ifdef CONFIG_MIPS_FP_SUPPORT +void output_thread_fpu_defines(void); void output_thread_fpu_defines(void) { OFFSET(THREAD_FPU, task_struct, thread.fpu); @@ -176,6 +181,7 @@ void output_thread_fpu_defines(void) } #endif +void output_mm_defines(void); void output_mm_defines(void) { COMMENT("Size of struct page"); @@ -210,6 +216,7 @@ void output_mm_defines(void) } #ifdef CONFIG_32BIT +void output_sc_defines(void); void output_sc_defines(void) { COMMENT("Linux sigcontext offsets."); @@ -232,6 +239,7 @@ void output_sc_defines(void) #endif #ifdef CONFIG_64BIT +void output_sc_defines(void); void output_sc_defines(void) { COMMENT("Linux sigcontext offsets."); @@ -245,6 +253,7 @@ void output_sc_defines(void) } #endif +void output_signal_defined(void); void output_signal_defined(void) { COMMENT("Linux signal numbers."); @@ -284,6 +293,7 @@ void output_signal_defined(void) } #ifdef CONFIG_CPU_CAVIUM_OCTEON +void output_octeon_cop2_state_defines(void); void output_octeon_cop2_state_defines(void) { COMMENT("Octeon specific octeon_cop2_state offsets."); @@ -315,6 +325,7 @@ void output_octeon_cop2_state_defines(void) #endif #ifdef CONFIG_HIBERNATION +void output_pbe_defines(void); void output_pbe_defines(void) { COMMENT(" Linux struct pbe offsets. "); @@ -327,6 +338,7 @@ void output_pbe_defines(void) #endif #ifdef CONFIG_CPU_PM +void output_pm_defines(void); void output_pm_defines(void) { COMMENT(" PM offsets. "); @@ -341,6 +353,7 @@ void output_pm_defines(void) #endif #ifdef CONFIG_MIPS_FP_SUPPORT +void output_kvm_defines(void); void output_kvm_defines(void) { COMMENT(" KVM/MIPS Specific offsets. "); @@ -385,6 +398,7 @@ void output_kvm_defines(void) #endif #ifdef CONFIG_MIPS_CPS +void output_cps_defines(void); void output_cps_defines(void) { COMMENT(" MIPS CPS offsets. "); diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index d7fdbec232da..dd55d59b88db 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -25,24 +25,13 @@ #include #include -static bool threads_disabled; static DECLARE_BITMAP(core_power, NR_CPUS); struct core_boot_config *mips_cps_core_bootcfg; -static int __init setup_nothreads(char *s) +static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) { - threads_disabled = true; - return 0; -} -early_param("nothreads", setup_nothreads); - -static unsigned core_vpe_count(unsigned int cluster, unsigned core) -{ - if (threads_disabled) - return 1; - - return mips_cps_numvps(cluster, core); + return min(smp_max_threads, mips_cps_numvps(cluster, core)); } static void __init cps_smp_setup(void) diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 5f04a0141068..7729cc733421 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -46,7 +46,8 @@ static void __init smvp_copy_vpe_config(void) static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, unsigned int ncpu) { - if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) + if (tc >= smp_max_threads || + (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))) return ncpu; /* Deactivate all but VPE 0 */ diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 90c71d800b59..8fbef537fb88 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -73,6 +73,24 @@ static cpumask_t cpu_core_setup_map; cpumask_t cpu_coherent_mask; +unsigned int smp_max_threads __initdata = UINT_MAX; + +static int __init early_nosmt(char *s) +{ + smp_max_threads = 1; + return 0; +} +early_param("nosmt", early_nosmt); + +static int __init early_smt(char *s) +{ + get_option(&s, &smp_max_threads); + /* Ensure at least one thread is available */ + smp_max_threads = clamp_val(smp_max_threads, 1U, UINT_MAX); + return 0; +} +early_param("smt", early_smt); + #ifdef CONFIG_GENERIC_IRQ_IPI static struct irq_desc *call_desc; static struct irq_desc *sched_desc; diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 7b5aba5df02e..f4cf94e92ec3 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -160,6 +160,47 @@ static void emulate_load_store_insn(struct pt_regs *regs, * The remaining opcodes are the ones that are really of * interest. */ +#ifdef CONFIG_MACH_INGENIC + case spec2_op: + if (insn.mxu_lx_format.func != mxu_lx_op) + goto sigbus; /* other MXU instructions we don't care */ + + switch (insn.mxu_lx_format.op) { + case mxu_lxw_op: + if (user && !access_ok(addr, 4)) + goto sigbus; + LoadW(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.mxu_lx_format.rd] = value; + break; + case mxu_lxh_op: + if (user && !access_ok(addr, 2)) + goto sigbus; + LoadHW(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.dsp_format.rd] = value; + break; + case mxu_lxhu_op: + if (user && !access_ok(addr, 2)) + goto sigbus; + LoadHWU(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.dsp_format.rd] = value; + break; + case mxu_lxb_op: + case mxu_lxbu_op: + goto sigbus; + default: + goto sigill; + } + break; +#endif case spec3_op: if (insn.dsp_format.func == lx_op) { switch (insn.dsp_format.op) { diff --git a/arch/mips/loongson32/common/Makefile b/arch/mips/loongson32/common/Makefile index 7b49c8260706..f3950d308187 100644 --- a/arch/mips/loongson32/common/Makefile +++ b/arch/mips/loongson32/common/Makefile @@ -3,4 +3,4 @@ # Makefile for common code of loongson1 based machines. # -obj-y += time.o irq.o platform.o prom.o reset.o setup.o +obj-y += time.o irq.o platform.o prom.o setup.o diff --git a/arch/mips/loongson32/common/reset.c b/arch/mips/loongson32/common/reset.c deleted file mode 100644 index 0c7399b303fb..000000000000 --- a/arch/mips/loongson32/common/reset.c +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2011 Zhang, Keguang - */ - -#include -#include -#include -#include -#include - -#include - -static void __iomem *wdt_reg_base; - -static void ls1x_halt(void) -{ - while (1) { - if (cpu_wait) - cpu_wait(); - } -} - -static void ls1x_restart(char *command) -{ - __raw_writel(0x1, wdt_reg_base + WDT_EN); - __raw_writel(0x1, wdt_reg_base + WDT_TIMER); - __raw_writel(0x1, wdt_reg_base + WDT_SET); - - ls1x_halt(); -} - -static void ls1x_power_off(void) -{ - ls1x_halt(); -} - -static int __init ls1x_reboot_setup(void) -{ - wdt_reg_base = ioremap(LS1X_WDT_BASE, (SZ_4 + SZ_8)); - if (!wdt_reg_base) - panic("Failed to remap watchdog registers"); - - _machine_restart = ls1x_restart; - _machine_halt = ls1x_halt; - pm_power_off = ls1x_power_off; - - return 0; -} - -arch_initcall(ls1x_reboot_setup); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 80e05ee98d62..8d514a9082c6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); - switch (current_cpu_type()) { - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - break; - default: - if (cpu_has_mips_r2_exec_hazard) - uasm_i_ehb(&p); - break; - } + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { @@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void) uasm_i_tlbr(&p); - switch (current_cpu_type()) { - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - break; - default: - if (cpu_has_mips_r2_exec_hazard) - uasm_i_ehb(&p); - break; - } + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(&p); /* Examine entrylo 0 or 1 based on ptr. */ if (use_bbit_insns()) { diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c index 2700d75d41c5..5c4bdf6919e5 100644 --- a/arch/mips/pci/pci-mt7620.c +++ b/arch/mips/pci/pci-mt7620.c @@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct platform_device *pdev) val |= 0x50 << 8; pci_config_write(NULL, 0, 0x70c, 4, val); - pci_config_read(NULL, 0, 0x70c, 4, &val); - dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val); - return 0; } @@ -330,7 +327,7 @@ static int mt7620_pci_probe(struct platform_device *pdev) rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); if (ralink_soc == MT762X_SOC_MT7620A) rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV); - dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); + dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); return -1; } @@ -373,7 +370,7 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) dev->bus->number, slot); return 0; } - dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", + dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq); /* configure the cache line size to 0x14 */ diff --git a/arch/mips/pci/pci-xtalk-bridge.c b/arch/mips/pci/pci-xtalk-bridge.c index ab9bedb82b28..68d5211afea8 100644 --- a/arch/mips/pci/pci-xtalk-bridge.c +++ b/arch/mips/pci/pci-xtalk-bridge.c @@ -733,7 +733,7 @@ err_remove_domain: return err; } -static int bridge_remove(struct platform_device *pdev) +static void bridge_remove(struct platform_device *pdev) { struct pci_bus *bus = platform_get_drvdata(pdev); struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); @@ -745,13 +745,11 @@ static int bridge_remove(struct platform_device *pdev) pci_stop_root_bus(bus); pci_remove_root_bus(bus); pci_unlock_rescan_remove(); - - return 0; } static struct platform_driver bridge_driver = { - .probe = bridge_probe, - .remove = bridge_remove, + .probe = bridge_probe, + .remove_new = bridge_remove, .driver = { .name = "xtalk-bridge", } diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index 5b02bb7e0829..9db73fcac522 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -11,29 +11,72 @@ #include #include #include +#include #include #include "common.h" -void ralink_clk_add(const char *dev, unsigned long rate) +static const char *clk_cpu(int *idx) { - struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate); - - if (!clk) - panic("failed to add clock"); - - clkdev_create(clk, NULL, "%s", dev); + switch (ralink_soc) { + case RT2880_SOC: + *idx = 0; + return "ralink,rt2880-sysc"; + case RT3883_SOC: + *idx = 0; + return "ralink,rt3883-sysc"; + case RT305X_SOC_RT3050: + *idx = 0; + return "ralink,rt3050-sysc"; + case RT305X_SOC_RT3052: + *idx = 0; + return "ralink,rt3052-sysc"; + case RT305X_SOC_RT3350: + *idx = 1; + return "ralink,rt3350-sysc"; + case RT305X_SOC_RT3352: + *idx = 1; + return "ralink,rt3352-sysc"; + case RT305X_SOC_RT5350: + *idx = 1; + return "ralink,rt5350-sysc"; + case MT762X_SOC_MT7620A: + *idx = 2; + return "ralink,mt7620-sysc"; + case MT762X_SOC_MT7620N: + *idx = 2; + return "ralink,mt7620-sysc"; + case MT762X_SOC_MT7628AN: + *idx = 1; + return "ralink,mt7628-sysc"; + case MT762X_SOC_MT7688: + *idx = 1; + return "ralink,mt7688-sysc"; + default: + *idx = -1; + return "invalid"; + } } void __init plat_time_init(void) { + struct of_phandle_args clkspec; + const char *compatible; struct clk *clk; + int cpu_clk_idx; ralink_of_remap(); - ralink_clk_init(); - clk = clk_get_sys("cpu", NULL); + compatible = clk_cpu(&cpu_clk_idx); + if (cpu_clk_idx == -1) + panic("unable to get CPU clock index"); + + of_clk_init(NULL); + clkspec.np = of_find_compatible_node(NULL, NULL, compatible); + clkspec.args_count = 1; + clkspec.args[0] = cpu_clk_idx; + clk = of_clk_get_from_provider(&clkspec); if (IS_ERR(clk)) panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h index 87fc16751281..893981a0ca7d 100644 --- a/arch/mips/ralink/common.h +++ b/arch/mips/ralink/common.h @@ -23,13 +23,6 @@ extern struct ralink_soc_info soc_info; extern void ralink_of_remap(void); -extern void ralink_clk_init(void); -extern void ralink_clk_add(const char *dev, unsigned long rate); - -extern void ralink_rst_init(void); - extern void __init prom_soc_init(struct ralink_soc_info *soc_info); -__iomem void *plat_of_remap_node(const char *node); - #endif /* _RALINK_COMMON_H__ */ diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 4435f50b8d24..672249a13a09 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -36,12 +36,6 @@ #define PMU1_CFG 0x8C #define DIG_SW_SEL BIT(25) -/* clock scaling */ -#define CLKCFG_FDIV_MASK 0x1f00 -#define CLKCFG_FDIV_USB_VAL 0x0300 -#define CLKCFG_FFRAC_MASK 0x001f -#define CLKCFG_FFRAC_USB_VAL 0x0003 - /* EFUSE bits */ #define EFUSE_MT7688 0x100000 @@ -53,235 +47,6 @@ static int dram_type; static struct ralink_soc_info *soc_info_ptr; -static __init u32 -mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) -{ - u64 t; - - t = ref_rate; - t *= mul; - do_div(t, div); - - return t; -} - -#define MHZ(x) ((x) * 1000 * 1000) - -static __init unsigned long -mt7620_get_xtal_rate(void) -{ - u32 reg; - - reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); - if (reg & SYSCFG0_XTAL_FREQ_SEL) - return MHZ(40); - - return MHZ(20); -} - -static __init unsigned long -mt7620_get_periph_rate(unsigned long xtal_rate) -{ - u32 reg; - - reg = rt_sysc_r32(SYSC_REG_CLKCFG0); - if (reg & CLKCFG0_PERI_CLK_SEL) - return xtal_rate; - - return MHZ(40); -} - -static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; - -static __init unsigned long -mt7620_get_cpu_pll_rate(unsigned long xtal_rate) -{ - u32 reg; - u32 mul; - u32 div; - - reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); - if (reg & CPLL_CFG0_BYPASS_REF_CLK) - return xtal_rate; - - if ((reg & CPLL_CFG0_SW_CFG) == 0) - return MHZ(600); - - mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & - CPLL_CFG0_PLL_MULT_RATIO_MASK; - mul += 24; - if (reg & CPLL_CFG0_LC_CURFCK) - mul *= 2; - - div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & - CPLL_CFG0_PLL_DIV_RATIO_MASK; - - WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); - - return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); -} - -static __init unsigned long -mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) -{ - u32 reg; - - reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); - if (reg & CPLL_CFG1_CPU_AUX1) - return xtal_rate; - - if (reg & CPLL_CFG1_CPU_AUX0) - return MHZ(480); - - return cpu_pll_rate; -} - -static __init unsigned long -mt7620_get_cpu_rate(unsigned long pll_rate) -{ - u32 reg; - u32 mul; - u32 div; - - reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); - - mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; - div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & - CPU_SYS_CLKCFG_CPU_FDIV_MASK; - - return mt7620_calc_rate(pll_rate, mul, div); -} - -static const u32 mt7620_ocp_dividers[16] __initconst = { - [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, - [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, - [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, - [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, - [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, -}; - -static __init unsigned long -mt7620_get_dram_rate(unsigned long pll_rate) -{ - if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) - return pll_rate / 4; - - return pll_rate / 3; -} - -static __init unsigned long -mt7620_get_sys_rate(unsigned long cpu_rate) -{ - u32 reg; - u32 ocp_ratio; - u32 div; - - reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); - - ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & - CPU_SYS_CLKCFG_OCP_RATIO_MASK; - - if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) - return cpu_rate; - - div = mt7620_ocp_dividers[ocp_ratio]; - if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) - return cpu_rate; - - return cpu_rate / div; -} - -void __init ralink_clk_init(void) -{ - unsigned long xtal_rate; - unsigned long cpu_pll_rate; - unsigned long pll_rate; - unsigned long cpu_rate; - unsigned long sys_rate; - unsigned long dram_rate; - unsigned long periph_rate; - unsigned long pcmi2s_rate; - - xtal_rate = mt7620_get_xtal_rate(); - -#define RFMT(label) label ":%lu.%03luMHz " -#define RINT(x) ((x) / 1000000) -#define RFRAC(x) (((x) / 1000) % 1000) - - if (is_mt76x8()) { - if (xtal_rate == MHZ(40)) - cpu_rate = MHZ(580); - else - cpu_rate = MHZ(575); - dram_rate = sys_rate = cpu_rate / 3; - periph_rate = MHZ(40); - pcmi2s_rate = MHZ(480); - - ralink_clk_add("10000d00.uartlite", periph_rate); - ralink_clk_add("10000e00.uartlite", periph_rate); - } else { - cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); - pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); - - cpu_rate = mt7620_get_cpu_rate(pll_rate); - dram_rate = mt7620_get_dram_rate(pll_rate); - sys_rate = mt7620_get_sys_rate(cpu_rate); - periph_rate = mt7620_get_periph_rate(xtal_rate); - pcmi2s_rate = periph_rate; - - pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), - RINT(xtal_rate), RFRAC(xtal_rate), - RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), - RINT(pll_rate), RFRAC(pll_rate)); - - ralink_clk_add("10000500.uart", periph_rate); - } - - pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), - RINT(cpu_rate), RFRAC(cpu_rate), - RINT(dram_rate), RFRAC(dram_rate), - RINT(sys_rate), RFRAC(sys_rate), - RINT(periph_rate), RFRAC(periph_rate)); -#undef RFRAC -#undef RINT -#undef RFMT - - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", periph_rate); - ralink_clk_add("10000120.watchdog", periph_rate); - ralink_clk_add("10000900.i2c", periph_rate); - ralink_clk_add("10000a00.i2s", pcmi2s_rate); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000b40.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", periph_rate); - ralink_clk_add("10000d00.uart1", periph_rate); - ralink_clk_add("10000e00.uart2", periph_rate); - ralink_clk_add("10180000.wmac", xtal_rate); - - if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { - /* - * When the CPU goes into sleep mode, the BUS clock will be - * too low for USB to function properly. Adjust the busses - * fractional divider to fix this - */ - u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); - - val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); - val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; - - rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); - } -} - -void __init ralink_of_remap(void) -{ - rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); - rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); - - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); -} - static __init void mt7620_dram_init(struct ralink_soc_info *soc_info) { diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index c3fbab50b95c..137781d0bd0a 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(void) memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); } -void __init ralink_of_remap(void) -{ - rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); - rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); - - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); -} - static unsigned int __init mt7621_get_soc_name0(void) { return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 4d06de77d92a..45d60c094496 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -29,28 +29,61 @@ __iomem void *rt_sysc_membase; __iomem void *rt_memc_membase; EXPORT_SYMBOL_GPL(rt_sysc_membase); -__iomem void *plat_of_remap_node(const char *node) +static const struct of_device_id mtmips_memc_match[] = { + { .compatible = "mediatek,mt7621-memc" }, + { .compatible = "ralink,mt7620a-memc" }, + { .compatible = "ralink,rt2880-memc" }, + { .compatible = "ralink,rt3050-memc" }, + { .compatible = "ralink,rt3883-memc" }, + {} +}; + +static const struct of_device_id mtmips_sysc_match[] = { + { .compatible = "mediatek,mt7621-sysc" }, + { .compatible = "ralink,mt7620-sysc" }, + { .compatible = "ralink,mt7628-sysc" }, + { .compatible = "ralink,mt7688-sysc" }, + { .compatible = "ralink,rt2880-sysc" }, + { .compatible = "ralink,rt3050-sysc" }, + { .compatible = "ralink,rt3052-sysc" }, + { .compatible = "ralink,rt3352-sysc" }, + { .compatible = "ralink,rt3883-sysc" }, + { .compatible = "ralink,rt5350-sysc" }, + {} +}; + +static __iomem void * +mtmips_of_remap_node(const struct of_device_id *match, const char *type) { struct resource res; struct device_node *np; - np = of_find_compatible_node(NULL, NULL, node); + np = of_find_matching_node(NULL, match); if (!np) - panic("Failed to find %s node", node); + panic("Failed to find %s controller node", type); if (of_address_to_resource(np, 0, &res)) - panic("Failed to get resource for %s", node); - - of_node_put(np); + panic("Failed to get resource for %s node", np->name); if (!request_mem_region(res.start, resource_size(&res), res.name)) - panic("Failed to request resources for %s", node); + panic("Failed to request resources for %s node", np->name); + + of_node_put(np); return ioremap(res.start, resource_size(&res)); } +void __init ralink_of_remap(void) +{ + rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system"); + rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory"); + + if (!rt_sysc_membase || !rt_memc_membase) + panic("Failed to remap core resources"); +} + void __init plat_mem_setup(void) { void *dtb; @@ -81,10 +114,6 @@ static int __init plat_of_setup(void) { __dt_register_buses(soc_info.compatible, "palmbus"); - /* make sure that the reset controller is setup early */ - if (ralink_soc != MT762X_SOC_MT7621AT) - ralink_rst_init(); - return 0; } diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index 274d33078c5e..4875637ef469 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -10,7 +10,6 @@ #include #include #include -#include #include @@ -22,66 +21,6 @@ #define RSTCTL_RESET_PCI BIT(26) #define RSTCTL_RESET_SYSTEM BIT(0) -static int ralink_assert_device(struct reset_controller_dev *rcdev, - unsigned long id) -{ - u32 val; - - if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - val |= BIT(id); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); - - return 0; -} - -static int ralink_deassert_device(struct reset_controller_dev *rcdev, - unsigned long id) -{ - u32 val; - - if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - val &= ~BIT(id); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); - - return 0; -} - -static int ralink_reset_device(struct reset_controller_dev *rcdev, - unsigned long id) -{ - ralink_assert_device(rcdev, id); - return ralink_deassert_device(rcdev, id); -} - -static const struct reset_control_ops reset_ops = { - .reset = ralink_reset_device, - .assert = ralink_assert_device, - .deassert = ralink_deassert_device, -}; - -static struct reset_controller_dev reset_dev = { - .ops = &reset_ops, - .owner = THIS_MODULE, - .nr_resets = 32, - .of_reset_n_cells = 1, -}; - -void ralink_rst_init(void) -{ - reset_dev.of_node = of_find_compatible_node(NULL, NULL, - "ralink,rt2880-reset"); - if (!reset_dev.of_node) - pr_err("Failed to find reset controller node"); - else - reset_controller_register(&reset_dev); -} - static void ralink_restart(char *command) { if (IS_ENABLED(CONFIG_PCI)) { diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 456ba0b2599e..ce8b5b6025bb 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -21,46 +21,6 @@ static struct ralink_soc_info *soc_info_ptr; -void __init ralink_clk_init(void) -{ - unsigned long cpu_rate, wmac_rate = 40000000; - u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); - t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); - - switch (t) { - case SYSTEM_CONFIG_CPUCLK_250: - cpu_rate = 250000000; - break; - case SYSTEM_CONFIG_CPUCLK_266: - cpu_rate = 266666667; - break; - case SYSTEM_CONFIG_CPUCLK_280: - cpu_rate = 280000000; - break; - case SYSTEM_CONFIG_CPUCLK_300: - cpu_rate = 300000000; - break; - } - - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("300100.timer", cpu_rate / 2); - ralink_clk_add("300120.watchdog", cpu_rate / 2); - ralink_clk_add("300500.uart", cpu_rate / 2); - ralink_clk_add("300900.i2c", cpu_rate / 2); - ralink_clk_add("300c00.uartlite", cpu_rate / 2); - ralink_clk_add("400000.ethernet", cpu_rate / 2); - ralink_clk_add("480000.wmac", wmac_rate); -} - -void __init ralink_of_remap(void) -{ - rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); - rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); - - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); -} - static unsigned int __init rt2880_get_soc_name0(void) { return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index d8dcc5cc66cc..1f422470b029 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -56,93 +56,6 @@ static unsigned long rt5350_get_mem_size(void) return ret; } -void __init ralink_clk_init(void) -{ - unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; - unsigned long wmac_rate = 40000000; - - u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); - - if (soc_is_rt305x() || soc_is_rt3350()) { - t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & - RT305X_SYSCFG_CPUCLK_MASK; - switch (t) { - case RT305X_SYSCFG_CPUCLK_LOW: - cpu_rate = 320000000; - break; - case RT305X_SYSCFG_CPUCLK_HIGH: - cpu_rate = 384000000; - break; - } - sys_rate = uart_rate = wdt_rate = cpu_rate / 3; - } else if (soc_is_rt3352()) { - t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & - RT3352_SYSCFG0_CPUCLK_MASK; - switch (t) { - case RT3352_SYSCFG0_CPUCLK_LOW: - cpu_rate = 384000000; - break; - case RT3352_SYSCFG0_CPUCLK_HIGH: - cpu_rate = 400000000; - break; - } - sys_rate = wdt_rate = cpu_rate / 3; - uart_rate = 40000000; - } else if (soc_is_rt5350()) { - t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & - RT5350_SYSCFG0_CPUCLK_MASK; - switch (t) { - case RT5350_SYSCFG0_CPUCLK_360: - cpu_rate = 360000000; - sys_rate = cpu_rate / 3; - break; - case RT5350_SYSCFG0_CPUCLK_320: - cpu_rate = 320000000; - sys_rate = cpu_rate / 4; - break; - case RT5350_SYSCFG0_CPUCLK_300: - cpu_rate = 300000000; - sys_rate = cpu_rate / 3; - break; - default: - BUG(); - } - uart_rate = 40000000; - wdt_rate = sys_rate; - } else { - BUG(); - } - - if (soc_is_rt3352() || soc_is_rt5350()) { - u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); - - if (!(val & RT3352_CLKCFG0_XTAL_SEL)) - wmac_rate = 20000000; - } - - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("sys", sys_rate); - ralink_clk_add("10000900.i2c", uart_rate); - ralink_clk_add("10000a00.i2s", uart_rate); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000b40.spi", sys_rate); - ralink_clk_add("10000100.timer", wdt_rate); - ralink_clk_add("10000120.watchdog", wdt_rate); - ralink_clk_add("10000500.uart", uart_rate); - ralink_clk_add("10000c00.uartlite", uart_rate); - ralink_clk_add("10100000.ethernet", sys_rate); - ralink_clk_add("10180000.wmac", wmac_rate); -} - -void __init ralink_of_remap(void) -{ - rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); - rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); - - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); -} - static unsigned int __init rt305x_get_soc_name0(void) { return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0); diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index cca887af378f..21ce00da5758 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -21,59 +21,6 @@ static struct ralink_soc_info *soc_info_ptr; -void __init ralink_clk_init(void) -{ - unsigned long cpu_rate, sys_rate; - u32 syscfg0; - u32 clksel; - u32 ddr2; - - syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); - clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & - RT3883_SYSCFG0_CPUCLK_MASK); - ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; - - switch (clksel) { - case RT3883_SYSCFG0_CPUCLK_250: - cpu_rate = 250000000; - sys_rate = (ddr2) ? 125000000 : 83000000; - break; - case RT3883_SYSCFG0_CPUCLK_384: - cpu_rate = 384000000; - sys_rate = (ddr2) ? 128000000 : 96000000; - break; - case RT3883_SYSCFG0_CPUCLK_480: - cpu_rate = 480000000; - sys_rate = (ddr2) ? 160000000 : 120000000; - break; - case RT3883_SYSCFG0_CPUCLK_500: - cpu_rate = 500000000; - sys_rate = (ddr2) ? 166000000 : 125000000; - break; - } - - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", sys_rate); - ralink_clk_add("10000120.watchdog", sys_rate); - ralink_clk_add("10000500.uart", 40000000); - ralink_clk_add("10000900.i2c", 40000000); - ralink_clk_add("10000a00.i2s", 40000000); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000b40.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", 40000000); - ralink_clk_add("10100000.ethernet", sys_rate); - ralink_clk_add("10180000.wmac", 40000000); -} - -void __init ralink_of_remap(void) -{ - rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); - rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc"); - - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); -} - static unsigned int __init rt3883_get_soc_name0(void) { return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3); diff --git a/arch/mips/sibyte/swarm/platform.c b/arch/mips/sibyte/swarm/platform.c index 484969db7713..339d77a0a08f 100644 --- a/arch/mips/sibyte/swarm/platform.c +++ b/arch/mips/sibyte/swarm/platform.c @@ -88,15 +88,15 @@ device_initcall(swarm_pata_init); #define sb1250_dev_struct(num) \ static struct resource sb1250_res##num = { \ .name = "SB1250 MAC " __stringify(num), \ - .flags = IORESOURCE_MEM, \ - .start = A_MAC_CHANNEL_BASE(num), \ - .end = A_MAC_CHANNEL_BASE(num + 1) -1, \ + .flags = IORESOURCE_MEM, \ + .start = A_MAC_CHANNEL_BASE(num), \ + .end = A_MAC_CHANNEL_BASE(num + 1) - 1, \ };\ static struct platform_device sb1250_dev##num = { \ - .name = "sb1250-mac", \ - .id = num, \ - .resource = &sb1250_res##num, \ - .num_resources = 1, \ + .name = "sb1250-mac", \ + .id = num, \ + .resource = &sb1250_res##num, \ + .num_resources = 1, \ } sb1250_dev_struct(0); diff --git a/arch/nios2/configs/10m50_defconfig b/arch/nios2/configs/10m50_defconfig index 91c3fce4dc7f..63151ebf1470 100644 --- a/arch/nios2/configs/10m50_defconfig +++ b/arch/nios2/configs/10m50_defconfig @@ -10,7 +10,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_SHMEM is not set # CONFIG_AIO is not set CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_NIOS2_MEM_BASE=0x8000000 diff --git a/arch/nios2/configs/3c120_defconfig b/arch/nios2/configs/3c120_defconfig index c42ad7e162a3..0daf3038d7aa 100644 --- a/arch/nios2/configs/3c120_defconfig +++ b/arch/nios2/configs/3c120_defconfig @@ -10,7 +10,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_SHMEM is not set # CONFIG_AIO is not set CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_NIOS2_MEM_BASE=0x10000000 diff --git a/arch/parisc/configs/generic-32bit_defconfig b/arch/parisc/configs/generic-32bit_defconfig index 8ce0ae370680..8c4d4844321f 100644 --- a/arch/parisc/configs/generic-32bit_defconfig +++ b/arch/parisc/configs/generic-32bit_defconfig @@ -12,7 +12,6 @@ CONFIG_USER_NS=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y CONFIG_PA7100LC=y CONFIG_SMP=y CONFIG_HZ_100=y diff --git a/arch/powerpc/configs/40x/klondike_defconfig b/arch/powerpc/configs/40x/klondike_defconfig index 6a735ee75715..acafbb8f6808 100644 --- a/arch/powerpc/configs/40x/klondike_defconfig +++ b/arch/powerpc/configs/40x/klondike_defconfig @@ -5,7 +5,6 @@ CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_APM8018X=y diff --git a/arch/powerpc/configs/52xx/pcm030_defconfig b/arch/powerpc/configs/52xx/pcm030_defconfig index 789622ffd844..88fbe0d42e11 100644 --- a/arch/powerpc/configs/52xx/pcm030_defconfig +++ b/arch/powerpc/configs/52xx/pcm030_defconfig @@ -10,7 +10,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig index 24bf1bde1bb4..487e5e1bbf4c 100644 --- a/arch/powerpc/configs/83xx/kmeter1_defconfig +++ b/arch/powerpc/configs/83xx/kmeter1_defconfig @@ -5,7 +5,6 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig index 4e3373381ab6..58fae5131fa7 100644 --- a/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig @@ -2,7 +2,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/85xx/ge_imp3a_defconfig b/arch/powerpc/configs/85xx/ge_imp3a_defconfig index 6cb7e90d52c1..da6fc203e2dc 100644 --- a/arch/powerpc/configs/85xx/ge_imp3a_defconfig +++ b/arch/powerpc/configs/85xx/ge_imp3a_defconfig @@ -17,7 +17,6 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/ep8248e_defconfig b/arch/powerpc/configs/ep8248e_defconfig index 8df6d3a293e3..b9dfa3a0713b 100644 --- a/arch/powerpc/configs/ep8248e_defconfig +++ b/arch/powerpc/configs/ep8248e_defconfig @@ -4,7 +4,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y -CONFIG_SLAB=y CONFIG_PARTITION_ADVANCED=y # CONFIG_PPC_CHRP is not set # CONFIG_PPC_PMAC is not set diff --git a/arch/powerpc/configs/gamecube_defconfig b/arch/powerpc/configs/gamecube_defconfig index 91a1b99f4e8f..d77eeb525366 100644 --- a/arch/powerpc/configs/gamecube_defconfig +++ b/arch/powerpc/configs/gamecube_defconfig @@ -8,7 +8,6 @@ CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig index 498d35db7833..ce220ceeb91c 100644 --- a/arch/powerpc/configs/mgcoge_defconfig +++ b/arch/powerpc/configs/mgcoge_defconfig @@ -10,7 +10,6 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_EMBEDDED=y -CONFIG_SLAB=y CONFIG_PARTITION_ADVANCED=y # CONFIG_PPC_PMAC is not set CONFIG_PPC_82xx=y diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig index 10fe061c5e6d..d24457bc5791 100644 --- a/arch/powerpc/configs/mpc512x_defconfig +++ b/arch/powerpc/configs/mpc512x_defconfig @@ -4,7 +4,6 @@ CONFIG_NO_HZ=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig index 8779f03bced1..83c4710017e9 100644 --- a/arch/powerpc/configs/mpc83xx_defconfig +++ b/arch/powerpc/configs/mpc83xx_defconfig @@ -2,7 +2,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index 52a8c5450ecb..ea3ee0719bb2 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig @@ -33,7 +33,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_BINFMT_MISC=y -CONFIG_SLAB=y # CONFIG_COMPAT_BRK is not set # CONFIG_SPARSEMEM_VMEMMAP is not set # CONFIG_COMPACTION is not set diff --git a/arch/powerpc/configs/wii_defconfig b/arch/powerpc/configs/wii_defconfig index 0ab78c51455d..5017a697b67b 100644 --- a/arch/powerpc/configs/wii_defconfig +++ b/arch/powerpc/configs/wii_defconfig @@ -9,7 +9,6 @@ CONFIG_EXPERT=y # CONFIG_ELF_CORE is not set CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_PPC_CHRP is not set diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..f60a280abb15 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner -subdir-y += sifive -subdir-y += starfive subdir-y += canaan subdir-y += microchip subdir-y += renesas +subdir-y += sifive +subdir-y += starfive +subdir-y += thead obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..1bb1e5cae602 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -108,6 +108,12 @@ function = "emac"; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5"; + function = "spi0"; + }; + /omit-if-no-ref/ uart1_pg6_pins: uart1-pg6-pins { pins = "PG6", "PG7"; @@ -447,6 +453,37 @@ #size-cells = <0>; }; + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x04025000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x04026000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@4100000 { compatible = "allwinner,sun20i-d1-musb", "allwinner,sun8i-a33-musb"; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..4218621ea3b9 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -238,5 +238,15 @@ #size-cells = <0>; status = "disabled"; }; + + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x0 0x12480000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, + <&clkgen JH7100_CLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, + <&rstgen JH7100_RSTN_WDT>; + }; }; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 2a6d81609284..fa0061eb33a7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -114,6 +114,23 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; status = "okay"; + + axp15060: pmic@36 { + compatible = "x-powers,axp15060"; + reg = <0x36>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-name = "vdd-cpu"; + }; + }; + }; }; &i2c6 { @@ -213,3 +230,19 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..ec2e70011a73 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; @@ -469,6 +502,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; @@ -496,5 +539,12 @@ gpio-controller; #gpio-cells = <2>; }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; }; }; diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..4b0249ac710f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..a1248b2ee3a3 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi new file mode 100644 index 000000000000..56a73134b49e --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible = "thead,th1520"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,th1520-plic", "thead,c900-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <240>; + }; + + clint: timer@ffdc000000 { + compatible = "thead,th1520-clint", "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x100>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb_clk>, <&apb_clk>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..109e4b5b003c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_THEAD=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig index 4d83576b89c6..4464a2ad42ed 100644 --- a/arch/sh/configs/ap325rxa_defconfig +++ b/arch/sh/configs/ap325rxa_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/apsh4a3a_defconfig b/arch/sh/configs/apsh4a3a_defconfig index 99931a13a74d..cc909f347877 100644 --- a/arch/sh/configs/apsh4a3a_defconfig +++ b/arch/sh/configs/apsh4a3a_defconfig @@ -6,7 +6,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig index d9fb124bf015..64558bf60e10 100644 --- a/arch/sh/configs/apsh4ad0a_defconfig +++ b/arch/sh/configs/apsh4ad0a_defconfig @@ -15,7 +15,6 @@ CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig index 6a82c7b8ff32..0c9f2030bb7c 100644 --- a/arch/sh/configs/dreamcast_defconfig +++ b/arch/sh/configs/dreamcast_defconfig @@ -1,7 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig index 5c60e71d839e..13fec4338416 100644 --- a/arch/sh/configs/ecovec24-romimage_defconfig +++ b/arch/sh/configs/ecovec24-romimage_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7724=y CONFIG_MEMORY_SIZE=0x10000000 diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig index 4d655e8d4d74..ee1b36682155 100644 --- a/arch/sh/configs/ecovec24_defconfig +++ b/arch/sh/configs/ecovec24_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig index 2804cb760a76..623012d9af9d 100644 --- a/arch/sh/configs/espt_defconfig +++ b/arch/sh/configs/espt_defconfig @@ -5,7 +5,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig index 70e6605d7f7e..0c45f2a0f9bd 100644 --- a/arch/sh/configs/hp6xx_defconfig +++ b/arch/sh/configs/hp6xx_defconfig @@ -3,7 +3,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7709=y CONFIG_MEMORY_START=0x0d000000 diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig index 04436b4fbd76..42bf34181a3e 100644 --- a/arch/sh/configs/kfr2r09-romimage_defconfig +++ b/arch/sh/configs/kfr2r09-romimage_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y # CONFIG_BLOCK is not set CONFIG_CPU_SUBTYPE_SH7724=y CONFIG_MEMORY_SIZE=0x08000000 diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig index 833404490cfe..d80e83e7ec38 100644 --- a/arch/sh/configs/kfr2r09_defconfig +++ b/arch/sh/configs/kfr2r09_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig index 7037320b654a..541082090918 100644 --- a/arch/sh/configs/landisk_defconfig +++ b/arch/sh/configs/landisk_defconfig @@ -1,7 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig index 05e4ac6fed5f..6a234761bfd7 100644 --- a/arch/sh/configs/lboxre2_defconfig +++ b/arch/sh/configs/lboxre2_defconfig @@ -1,7 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig index ef1d98e35c91..52937f9cc2ab 100644 --- a/arch/sh/configs/magicpanelr2_defconfig +++ b/arch/sh/configs/magicpanelr2_defconfig @@ -8,7 +8,6 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig index e9825196dd66..39a83d832cac 100644 --- a/arch/sh/configs/microdev_defconfig +++ b/arch/sh/configs/microdev_defconfig @@ -2,7 +2,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH4_202=y CONFIG_FLATMEM_MANUAL=y diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig index 4859cd30cfc4..2d1e65cad239 100644 --- a/arch/sh/configs/migor_defconfig +++ b/arch/sh/configs/migor_defconfig @@ -4,7 +4,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig index f42e4867ddc1..4f0396c2ac79 100644 --- a/arch/sh/configs/polaris_defconfig +++ b/arch/sh/configs/polaris_defconfig @@ -7,7 +7,6 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_AUDIT=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig index e527cd60a191..6bd6c0ae85d7 100644 --- a/arch/sh/configs/r7780mp_defconfig +++ b/arch/sh/configs/r7780mp_defconfig @@ -5,7 +5,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig index a3f952a83d97..cde668569cc1 100644 --- a/arch/sh/configs/r7785rp_defconfig +++ b/arch/sh/configs/r7785rp_defconfig @@ -7,7 +7,6 @@ CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_KPROBES=y CONFIG_MODULES=y diff --git a/arch/sh/configs/rsk7264_defconfig b/arch/sh/configs/rsk7264_defconfig index f7b9c528c6df..de9e350cdf28 100644 --- a/arch/sh/configs/rsk7264_defconfig +++ b/arch/sh/configs/rsk7264_defconfig @@ -12,7 +12,6 @@ CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y CONFIG_PERF_COUNTERS=y # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_PROFILING=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/rsk7269_defconfig b/arch/sh/configs/rsk7269_defconfig index 4bff14fb185d..7ca6a5c25a9f 100644 --- a/arch/sh/configs/rsk7269_defconfig +++ b/arch/sh/configs/rsk7269_defconfig @@ -2,7 +2,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EMBEDDED=y # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_SWAP_IO_SPACE=y CONFIG_CPU_SUBTYPE_SH7269=y diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig index 96263a4912b7..c863a11c7592 100644 --- a/arch/sh/configs/rts7751r2d1_defconfig +++ b/arch/sh/configs/rts7751r2d1_defconfig @@ -1,7 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig index 92e586e6c974..7e4f710d46c7 100644 --- a/arch/sh/configs/rts7751r2dplus_defconfig +++ b/arch/sh/configs/rts7751r2dplus_defconfig @@ -1,7 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig index 97b7356639ed..a080c5d05a7b 100644 --- a/arch/sh/configs/sdk7786_defconfig +++ b/arch/sh/configs/sdk7786_defconfig @@ -31,7 +31,6 @@ CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_LZO=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_KPROBES=y CONFIG_MODULES=y diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig index 5d6c19338ebf..75db12fb9ad1 100644 --- a/arch/sh/configs/se7343_defconfig +++ b/arch/sh/configs/se7343_defconfig @@ -5,7 +5,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set # CONFIG_SHMEM is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/sh/configs/se7619_defconfig b/arch/sh/configs/se7619_defconfig index 71a672c30716..14d0f5ead502 100644 --- a/arch/sh/configs/se7619_defconfig +++ b/arch/sh/configs/se7619_defconfig @@ -8,7 +8,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set # CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_MEMORY_START=0x0c000000 CONFIG_FLATMEM_MANUAL=y diff --git a/arch/sh/configs/se7705_defconfig b/arch/sh/configs/se7705_defconfig index ed00a6eeadf5..16a0f72f0822 100644 --- a/arch/sh/configs/se7705_defconfig +++ b/arch/sh/configs/se7705_defconfig @@ -4,7 +4,6 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set -CONFIG_SLAB=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7705=y diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig index 36356223d51c..dc854293da43 100644 --- a/arch/sh/configs/se7712_defconfig +++ b/arch/sh/configs/se7712_defconfig @@ -9,7 +9,6 @@ CONFIG_KALLSYMS_ALL=y # CONFIG_BUG is not set # CONFIG_BASE_FULL is not set # CONFIG_SHMEM is not set -CONFIG_SLAB=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7712=y diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig index 46c5a263a239..c891945b8a90 100644 --- a/arch/sh/configs/se7721_defconfig +++ b/arch/sh/configs/se7721_defconfig @@ -9,7 +9,6 @@ CONFIG_KALLSYMS_ALL=y # CONFIG_BUG is not set # CONFIG_BASE_FULL is not set # CONFIG_SHMEM is not set -CONFIG_SLAB=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7721=y diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig index d817df7cc4a7..96521271758c 100644 --- a/arch/sh/configs/se7724_defconfig +++ b/arch/sh/configs/se7724_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_KALLSYMS is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig index 4defc7628a49..5fa6239ae4ea 100644 --- a/arch/sh/configs/se7750_defconfig +++ b/arch/sh/configs/se7750_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_HOTPLUG is not set -CONFIG_SLAB=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7750=y diff --git a/arch/sh/configs/se7751_defconfig b/arch/sh/configs/se7751_defconfig index 4a024065bb75..8b5fe4ec16bc 100644 --- a/arch/sh/configs/se7751_defconfig +++ b/arch/sh/configs/se7751_defconfig @@ -4,7 +4,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_HOTPLUG is not set -CONFIG_SLAB=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7751=y diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig index dcd85b858ac8..21303304eda2 100644 --- a/arch/sh/configs/se7780_defconfig +++ b/arch/sh/configs/se7780_defconfig @@ -6,7 +6,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_CPU_SUBTYPE_SH7780=y diff --git a/arch/sh/configs/secureedge5410_defconfig b/arch/sh/configs/secureedge5410_defconfig index 8422599cfb04..120176afe3f6 100644 --- a/arch/sh/configs/secureedge5410_defconfig +++ b/arch/sh/configs/secureedge5410_defconfig @@ -2,7 +2,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y # CONFIG_HOTPLUG is not set -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7751R=y CONFIG_MEMORY_SIZE=0x01000000 diff --git a/arch/sh/configs/sh03_defconfig b/arch/sh/configs/sh03_defconfig index 9fcf68b22dba..f661ef816f09 100644 --- a/arch/sh/configs/sh03_defconfig +++ b/arch/sh/configs/sh03_defconfig @@ -3,7 +3,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig index 259c69e3fa22..977ae405a75e 100644 --- a/arch/sh/configs/sh2007_defconfig +++ b/arch/sh/configs/sh2007_defconfig @@ -8,7 +8,6 @@ CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y -CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set CONFIG_CPU_SUBTYPE_SH7780=y CONFIG_MEMORY_SIZE=0x08000000 diff --git a/arch/sh/configs/sh7710voipgw_defconfig b/arch/sh/configs/sh7710voipgw_defconfig index 0d814770b07f..7f742729df69 100644 --- a/arch/sh/configs/sh7710voipgw_defconfig +++ b/arch/sh/configs/sh7710voipgw_defconfig @@ -5,7 +5,6 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set # CONFIG_SHMEM is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig index 2579dc4bc0c8..48a0f9beb116 100644 --- a/arch/sh/configs/sh7757lcr_defconfig +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -9,7 +9,6 @@ CONFIG_TASK_IO_ACCOUNTING=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig index 8a6a446f9eb8..ae726745d9a0 100644 --- a/arch/sh/configs/sh7763rdp_defconfig +++ b/arch/sh/configs/sh7763rdp_defconfig @@ -5,7 +5,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig index 781ff13227fc..59262f42abe6 100644 --- a/arch/sh/configs/sh7785lcr_32bit_defconfig +++ b/arch/sh/configs/sh7785lcr_32bit_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_GCOV_KERNEL=y CONFIG_MODULES=y diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig index 1b88929083f7..94381f8268ff 100644 --- a/arch/sh/configs/sh7785lcr_defconfig +++ b/arch/sh/configs/sh7785lcr_defconfig @@ -3,7 +3,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index 73a0d68b0de6..871092753591 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -6,7 +6,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig index 8fc687c98fd1..445bb451a5ec 100644 --- a/arch/sh/configs/urquell_defconfig +++ b/arch/sh/configs/urquell_defconfig @@ -17,7 +17,6 @@ CONFIG_CGROUP_MEMCG=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/sparc/configs/sparc32_defconfig b/arch/sparc/configs/sparc32_defconfig index 7b3efe5edc1a..7c489e7f19b7 100644 --- a/arch/sparc/configs/sparc32_defconfig +++ b/arch/sparc/configs/sparc32_defconfig @@ -4,7 +4,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig index 18099099583e..0bb0d4da5227 100644 --- a/arch/sparc/configs/sparc64_defconfig +++ b/arch/sparc/configs/sparc64_defconfig @@ -6,7 +6,6 @@ CONFIG_LOG_BUF_SHIFT=18 CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_KPROBES=y CONFIG_MODULES=y diff --git a/arch/um/configs/i386_defconfig b/arch/um/configs/i386_defconfig index c0162286d68b..05ae535ba0dc 100644 --- a/arch/um/configs/i386_defconfig +++ b/arch/um/configs/i386_defconfig @@ -22,7 +22,6 @@ CONFIG_BLK_CGROUP=y # CONFIG_PID_NS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/um/configs/x86_64_defconfig b/arch/um/configs/x86_64_defconfig index bec6e5d95687..1c757238be7f 100644 --- a/arch/um/configs/x86_64_defconfig +++ b/arch/um/configs/x86_64_defconfig @@ -20,7 +20,6 @@ CONFIG_BLK_CGROUP=y # CONFIG_PID_NS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 8569f55e55b6..660834a49c1f 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -1267,12 +1267,8 @@ static void acpi_ec_event_handler(struct work_struct *work) spin_unlock_irq(&ec->lock); } -static void acpi_ec_handle_interrupt(struct acpi_ec *ec) +static void clear_gpe_and_advance_transaction(struct acpi_ec *ec, bool interrupt) { - unsigned long flags; - - spin_lock_irqsave(&ec->lock, flags); - /* * Clear GPE_STS upfront to allow subsequent hardware GPE_STS 0->1 * changes to always trigger a GPE interrupt. @@ -1289,6 +1285,16 @@ static void acpi_ec_handle_interrupt(struct acpi_ec *ec) acpi_clear_gpe(NULL, ec->gpe); advance_transaction(ec, true); +} + +static void acpi_ec_handle_interrupt(struct acpi_ec *ec) +{ + unsigned long flags; + + spin_lock_irqsave(&ec->lock, flags); + + clear_gpe_and_advance_transaction(ec, true); + spin_unlock_irqrestore(&ec->lock, flags); } @@ -2083,7 +2089,7 @@ bool acpi_ec_dispatch_gpe(void) if (acpi_ec_gpe_status_set(first_ec)) { pm_pr_dbg("ACPI EC GPE status set\n"); - advance_transaction(first_ec, false); + clear_gpe_and_advance_transaction(first_ec, false); work_in_progress = acpi_ec_work_in_progress(first_ec); } diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index 4c84be378bf2..595d4cecd041 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -835,15 +835,14 @@ EXPORT_SYMBOL_GPL(dprc_cleanup); * It tears down the interrupts that were configured for the DPRC device. * It destroys the interrupt pool associated with this MC bus. */ -static int dprc_remove(struct fsl_mc_device *mc_dev) +static void dprc_remove(struct fsl_mc_device *mc_dev) { struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - if (!is_fsl_mc_bus_dprc(mc_dev)) - return -EINVAL; - - if (!mc_bus->irq_resources) - return -EINVAL; + if (!mc_bus->irq_resources) { + dev_err(&mc_dev->dev, "No irq resources, so unbinding the device failed\n"); + return; + } if (dev_get_msi_domain(&mc_dev->dev)) dprc_teardown_irq(mc_dev); @@ -853,7 +852,6 @@ static int dprc_remove(struct fsl_mc_device *mc_dev) dprc_cleanup(mc_dev); dev_info(&mc_dev->dev, "DPRC device unbound from driver"); - return 0; } static const struct fsl_mc_device_id match_id_table[] = { diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index dced427ca8ba..b5e8c021fa1f 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -103,26 +103,32 @@ static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device struct fsl_mc_resource *resource; int error = -EINVAL; - if (!fsl_mc_is_allocatable(mc_dev)) - goto out; - - resource = mc_dev->resource; - if (!resource || resource->data != mc_dev) - goto out; - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); mc_bus = to_fsl_mc_bus(mc_bus_dev); - res_pool = resource->parent_pool; - if (res_pool != &mc_bus->resource_pools[resource->type]) + + resource = mc_dev->resource; + if (!resource || resource->data != mc_dev) { + dev_err(&mc_bus_dev->dev, "resource mismatch\n"); goto out; + } + + res_pool = resource->parent_pool; + if (res_pool != &mc_bus->resource_pools[resource->type]) { + dev_err(&mc_bus_dev->dev, "pool mismatch\n"); + goto out; + } mutex_lock(&res_pool->mutex); - if (res_pool->max_count <= 0) + if (res_pool->max_count <= 0) { + dev_err(&mc_bus_dev->dev, "max_count underflow\n"); goto out_unlock; + } if (res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count) + res_pool->free_count > res_pool->max_count) { + dev_err(&mc_bus_dev->dev, "free_count mismatch\n"); goto out_unlock; + } /* * If the device is currently allocated, its resource is not @@ -557,12 +563,9 @@ static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); struct fsl_mc_resource_pool *res_pool = &mc_bus->resource_pools[pool_type]; - int free_count = 0; - list_for_each_entry_safe(resource, next, &res_pool->free_list, node) { - free_count++; + list_for_each_entry_safe(resource, next, &res_pool->free_list, node) devm_kfree(&mc_bus_dev->dev, resource); - } } void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) @@ -609,22 +612,18 @@ static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) * fsl_mc_allocator_remove - callback invoked when an allocatable device is * being removed from the system */ -static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) +static void fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) { int error; - if (!fsl_mc_is_allocatable(mc_dev)) - return -EINVAL; - if (mc_dev->resource) { error = fsl_mc_resource_pool_remove_device(mc_dev); if (error < 0) - return error; + return; } dev_dbg(&mc_dev->dev, "Allocatable fsl-mc device unbound from fsl_mc_allocator driver"); - return 0; } static const struct fsl_mc_device_id match_id_table[] = { diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 653e2d4c116f..4352745a923c 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -454,13 +454,8 @@ static int fsl_mc_driver_remove(struct device *dev) { struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - int error; - error = mc_drv->remove(mc_dev); - if (error < 0) { - dev_err(dev, "%s failed: %d\n", __func__, error); - return error; - } + mc_drv->remove(mc_dev); return 0; } diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 6c49de37d5e9..21fe9854703f 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1791,7 +1791,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, if (!ddata->module_va) return -EIO; - /* DISP_CONTROL */ + /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ val = sysc_read(ddata, dispc_offset + 0x40); lcd_en = val & lcd_en_mask; digit_en = val & digit_en_mask; @@ -1803,7 +1803,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, else irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ } - if (disable & (lcd_en | digit_en)) + if (disable && (lcd_en || digit_en)) sysc_write(ddata, dispc_offset + 0x40, val & ~(lcd_en_mask | digit_en_mask)); diff --git a/drivers/char/mem.c b/drivers/char/mem.c index f494d31f2b98..94eff6a2a7b6 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -90,13 +90,6 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size) } #endif -#ifndef unxlate_dev_mem_ptr -#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr -void __weak unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) -{ -} -#endif - static inline bool should_stop_iteration(void) { if (need_resched()) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c0c8e526a1e9..93f38a8178ba 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -478,6 +478,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mstar/Kconfig" source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" +source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0aebef17edc6..7cb000549b61 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -106,6 +106,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_MA35) += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig new file mode 100644 index 000000000000..fe4b7f62f467 --- /dev/null +++ b/drivers/clk/nuvoton/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for Nuvoton SoC family. + +config COMMON_CLK_NUVOTON + bool "Nuvoton clock controller common support" + depends on ARCH_MA35 || COMPILE_TEST + default y + help + Say y here to enable common clock controller for Nuvoton platforms. + +if COMMON_CLK_NUVOTON + +config CLK_MA35D1 + bool "Nuvoton MA35D1 clock controller support" + default y + help + Build the clock controller driver for MA35D1 SoC. + +endif diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile new file mode 100644 index 000000000000..c3c59dd9f2aa --- /dev/null +++ b/drivers/clk/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c new file mode 100644 index 000000000000..bb8c23d2b895 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +struct ma35d1_adc_clk_div { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u32 mask; + const struct clk_div_table *table; + /* protects concurrent access to clock divider registers */ + spinlock_t *lock; +}; + +static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_adc_clk_div, hw); +} + +static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + unsigned int val; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + val = readl_relaxed(dclk->reg) >> dclk->shift; + val &= clk_div_mask(dclk->width); + val += 1; + return divider_recalc_rate(hw, parent_rate, val, dclk->table, + CLK_DIVIDER_ROUND_CLOSEST, dclk->width); +} + +static long ma35d1_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + return divider_round_rate(hw, rate, prate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); +} + +static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + int value; + unsigned long flags = 0; + u32 data; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + value = divider_get_val(rate, parent_rate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); + + spin_lock_irqsave(dclk->lock, flags); + + data = readl_relaxed(dclk->reg); + data &= ~(clk_div_mask(dclk->width) << dclk->shift); + data |= (value - 1) << dclk->shift; + data |= dclk->mask; + writel_relaxed(data, dclk->reg); + + spin_unlock_irqrestore(dclk->lock, flags); + return 0; +} + +static const struct clk_ops ma35d1_adc_clkdiv_ops = { + .recalc_rate = ma35d1_clkdiv_recalc_rate, + .round_rate = ma35d1_clkdiv_round_rate, + .set_rate = ma35d1_clkdiv_set_rate, +}; + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + struct clk_hw *parent_hw, spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit) +{ + struct ma35d1_adc_clk_div *div; + struct clk_init_data init; + struct clk_div_table *table; + struct clk_parent_data pdata = { .index = 0 }; + u32 max_div, min_div; + struct clk_hw *hw; + int ret; + int i; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + max_div = clk_div_mask(width) + 1; + min_div = 1; + + table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < max_div; i++) { + table[i].val = min_div + i; + table[i].div = 2 * table[i].val; + } + table[max_div].val = 0; + table[max_div].div = 0; + + memset(&init, 0, sizeof(init)); + init.name = name; + init.ops = &ma35d1_adc_clkdiv_ops; + init.flags |= flags; + pdata.hw = parent_hw; + init.parent_data = &pdata; + init.num_parents = 1; + + div->reg = reg; + div->shift = shift; + div->width = width; + div->mask = mask_bit ? BIT(mask_bit) : 0; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + return hw; +} +EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv); diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c new file mode 100644 index 000000000000..ff3fb8b87c24 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +/* PLL frequency limits */ +#define PLL_FREF_MAX_FREQ (200 * HZ_PER_MHZ) +#define PLL_FREF_MIN_FREQ (1 * HZ_PER_MHZ) +#define PLL_FREF_M_MAX_FREQ (40 * HZ_PER_MHZ) +#define PLL_FREF_M_MIN_FREQ (10 * HZ_PER_MHZ) +#define PLL_FCLK_MAX_FREQ (2400 * HZ_PER_MHZ) +#define PLL_FCLK_MIN_FREQ (600 * HZ_PER_MHZ) +#define PLL_FCLKO_MAX_FREQ (2400 * HZ_PER_MHZ) +#define PLL_FCLKO_MIN_FREQ (85700 * HZ_PER_KHZ) +#define PLL_SS_RATE 0x77 +#define PLL_SLOPE 0x58CFA + +#define REG_PLL_CTL0_OFFSET 0x0 +#define REG_PLL_CTL1_OFFSET 0x4 +#define REG_PLL_CTL2_OFFSET 0x8 + +/* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */ +#define SPLL0_CTL0_FBDIV GENMASK(7, 0) +#define SPLL0_CTL0_INDIV GENMASK(11, 8) +#define SPLL0_CTL0_OUTDIV GENMASK(13, 12) +#define SPLL0_CTL0_PD BIT(16) +#define SPLL0_CTL0_BP BIT(17) + +/* bit fields for REG_CLK_PLLxCTL0 ~ REG_CLK_PLLxCTL2, where x = 2 ~ 5 */ +#define PLL_CTL0_FBDIV GENMASK(10, 0) +#define PLL_CTL0_INDIV GENMASK(17, 12) +#define PLL_CTL0_MODE GENMASK(19, 18) +#define PLL_CTL0_SSRATE GENMASK(30, 20) +#define PLL_CTL1_PD BIT(0) +#define PLL_CTL1_BP BIT(1) +#define PLL_CTL1_OUTDIV GENMASK(6, 4) +#define PLL_CTL1_FRAC GENMASK(31, 24) +#define PLL_CTL2_SLOPE GENMASK(23, 0) + +#define INDIV_MIN 1 +#define INDIV_MAX 63 +#define FBDIV_MIN 16 +#define FBDIV_MAX 2047 +#define FBDIV_FRAC_MIN 1600 +#define FBDIV_FRAC_MAX 204700 +#define OUTDIV_MIN 1 +#define OUTDIV_MAX 7 + +#define PLL_MODE_INT 0 +#define PLL_MODE_FRAC 1 +#define PLL_MODE_SS 2 + +struct ma35d1_clk_pll { + struct clk_hw hw; + u32 id; + u8 mode; + void __iomem *ctl0_base; + void __iomem *ctl1_base; + void __iomem *ctl2_base; +}; + +static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_clk_pll, hw); +} + +static unsigned long ma35d1_calc_smic_pll_freq(u32 pll0_ctl0, + unsigned long parent_rate) +{ + u32 m, n, p, outdiv; + u64 pll_freq; + + if (pll0_ctl0 & SPLL0_CTL0_BP) + return parent_rate; + + n = FIELD_GET(SPLL0_CTL0_FBDIV, pll0_ctl0); + m = FIELD_GET(SPLL0_CTL0_INDIV, pll0_ctl0); + p = FIELD_GET(SPLL0_CTL0_OUTDIV, pll0_ctl0); + outdiv = 1 << p; + pll_freq = (u64)parent_rate * n; + div_u64(pll_freq, m * outdiv); + return pll_freq; +} + +static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) +{ + unsigned long pll_freq, x; + u32 m, n, p; + + if (reg_ctl[1] & PLL_CTL1_BP) + return parent_rate; + + n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); + m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); + p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); + + if (mode == PLL_MODE_INT) { + pll_freq = (u64)parent_rate * n; + div_u64(pll_freq, m * p); + } else { + x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); + /* 2 decimal places floating to integer (ex. 1.23 to 123) */ + n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC)); + pll_freq = div_u64(parent_rate * n, 100 * m * p); + } + return pll_freq; +} + +static int ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate, + unsigned long parent_rate, u32 *reg_ctl, + unsigned long *freq) +{ + unsigned long min_diff = ULONG_MAX; + int fbdiv_min, fbdiv_max; + int p, m, n; + + *freq = 0; + if (rate < PLL_FCLKO_MIN_FREQ || rate > PLL_FCLKO_MAX_FREQ) + return -EINVAL; + + if (pll->mode == PLL_MODE_INT) { + fbdiv_min = FBDIV_MIN; + fbdiv_max = FBDIV_MAX; + } else { + fbdiv_min = FBDIV_FRAC_MIN; + fbdiv_max = FBDIV_FRAC_MAX; + } + + for (m = INDIV_MIN; m <= INDIV_MAX; m++) { + for (n = fbdiv_min; n <= fbdiv_max; n++) { + for (p = OUTDIV_MIN; p <= OUTDIV_MAX; p++) { + unsigned long tmp, fout, fclk, diff; + + tmp = div_u64(parent_rate, m); + if (tmp < PLL_FREF_M_MIN_FREQ || + tmp > PLL_FREF_M_MAX_FREQ) + continue; /* constrain */ + + fclk = div_u64(parent_rate * n, m); + /* for 2 decimal places */ + if (pll->mode != PLL_MODE_INT) + fclk = div_u64(fclk, 100); + + if (fclk < PLL_FCLK_MIN_FREQ || + fclk > PLL_FCLK_MAX_FREQ) + continue; /* constrain */ + + fout = div_u64(fclk, p); + if (fout < PLL_FCLKO_MIN_FREQ || + fout > PLL_FCLKO_MAX_FREQ) + continue; /* constrain */ + + diff = abs(rate - fout); + if (diff < min_diff) { + reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) | + FIELD_PREP(PLL_CTL0_FBDIV, n); + reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p); + *freq = fout; + min_diff = diff; + if (min_diff == 0) + break; + } + } + } + } + if (*freq == 0) + return -EINVAL; /* cannot find even one valid setting */ + return 0; +} + +static int ma35d1_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + int ret; + + if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ) + return -EINVAL; + + ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq); + if (ret != 0) + return ret; + + switch (pll->mode) { + case PLL_MODE_INT: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT); + break; + case PLL_MODE_FRAC: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC); + break; + case PLL_MODE_SS: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) | + FIELD_PREP(PLL_CTL0_SSRATE, PLL_SS_RATE); + reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE); + break; + } + reg_ctl[1] |= PLL_CTL1_PD; + + writel_relaxed(reg_ctl[0], pll->ctl0_base); + writel_relaxed(reg_ctl[1], pll->ctl1_base); + writel_relaxed(reg_ctl[2], pll->ctl2_base); + return 0; +} + +static unsigned long ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3]; + unsigned long pll_freq; + + if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ) + return 0; + + switch (pll->id) { + case CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate); + return pll_freq; + case DDRPLL: + case APLL: + case EPLL: + case VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate); + return pll_freq; + } + return 0; +} + +static long ma35d1_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + long ret; + + if (*parent_rate < PLL_FREF_MIN_FREQ || *parent_rate > PLL_FREF_MAX_FREQ) + return -EINVAL; + + ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq); + if (ret < 0) + return ret; + + switch (pll->id) { + case CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate); + return pll_freq; + case DDRPLL: + case APLL: + case EPLL: + case VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate); + return pll_freq; + } + return 0; +} + +static int ma35d1_clk_pll_is_prepared(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val = readl_relaxed(pll->ctl1_base); + + return !(val & PLL_CTL1_PD); +} + +static int ma35d1_clk_pll_prepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + val = readl_relaxed(pll->ctl1_base); + val &= ~PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); + return 0; +} + +static void ma35d1_clk_pll_unprepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + val = readl_relaxed(pll->ctl1_base); + val |= PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); +} + +static const struct clk_ops ma35d1_clk_pll_ops = { + .is_prepared = ma35d1_clk_pll_is_prepared, + .prepare = ma35d1_clk_pll_prepare, + .unprepare = ma35d1_clk_pll_unprepare, + .set_rate = ma35d1_clk_pll_set_rate, + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +static const struct clk_ops ma35d1_clk_fixed_pll_ops = { + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, + struct clk_hw *parent_hw, void __iomem *base) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = {}; + struct ma35d1_clk_pll *pll; + struct clk_hw *hw; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->id = id; + pll->mode = u8mode; + pll->ctl0_base = base + REG_PLL_CTL0_OFFSET; + pll->ctl1_base = base + REG_PLL_CTL1_OFFSET; + pll->ctl2_base = base + REG_PLL_CTL2_OFFSET; + + init.name = name; + init.flags = 0; + pdata.hw = parent_hw; + init.parent_data = &pdata; + init.num_parents = 1; + + if (id == CAPLL || id == DDRPLL) + init.ops = &ma35d1_clk_fixed_pll_ops; + else + init.ops = &ma35d1_clk_pll_ops; + + pll->hw.init = &init; + hw = &pll->hw; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + return hw; +} +EXPORT_SYMBOL_GPL(ma35d1_reg_clk_pll); diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c new file mode 100644 index 000000000000..f1fe7edd21b5 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -0,0 +1,1059 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +static DEFINE_SPINLOCK(ma35d1_lock); + +#define PLL_MAX_NUM 5 + +/* Clock Control Registers Offset */ +#define REG_CLK_PWRCTL 0x00 +#define REG_CLK_SYSCLK0 0x04 +#define REG_CLK_SYSCLK1 0x08 +#define REG_CLK_APBCLK0 0x0c +#define REG_CLK_APBCLK1 0x10 +#define REG_CLK_APBCLK2 0x14 +#define REG_CLK_CLKSEL0 0x18 +#define REG_CLK_CLKSEL1 0x1c +#define REG_CLK_CLKSEL2 0x20 +#define REG_CLK_CLKSEL3 0x24 +#define REG_CLK_CLKSEL4 0x28 +#define REG_CLK_CLKDIV0 0x2c +#define REG_CLK_CLKDIV1 0x30 +#define REG_CLK_CLKDIV2 0x34 +#define REG_CLK_CLKDIV3 0x38 +#define REG_CLK_CLKDIV4 0x3c +#define REG_CLK_CLKOCTL 0x40 +#define REG_CLK_STATUS 0x50 +#define REG_CLK_PLL0CTL0 0x60 +#define REG_CLK_PLL2CTL0 0x80 +#define REG_CLK_PLL2CTL1 0x84 +#define REG_CLK_PLL2CTL2 0x88 +#define REG_CLK_PLL3CTL0 0x90 +#define REG_CLK_PLL3CTL1 0x94 +#define REG_CLK_PLL3CTL2 0x98 +#define REG_CLK_PLL4CTL0 0xa0 +#define REG_CLK_PLL4CTL1 0xa4 +#define REG_CLK_PLL4CTL2 0xa8 +#define REG_CLK_PLL5CTL0 0xb0 +#define REG_CLK_PLL5CTL1 0xb4 +#define REG_CLK_PLL5CTL2 0xb8 +#define REG_CLK_CLKDCTL 0xc0 +#define REG_CLK_CLKDSTS 0xc4 +#define REG_CLK_CDUPB 0xc8 +#define REG_CLK_CDLOWB 0xcc +#define REG_CLK_CKFLTRCTL 0xd0 +#define REG_CLK_TESTCLK 0xf0 +#define REG_CLK_PLLCTL 0x40 + +#define PLL_MODE_INT 0 +#define PLL_MODE_FRAC 1 +#define PLL_MODE_SS 2 + +static const struct clk_parent_data ca35clk_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "capll", }, + { .fw_name = "ddrpll", }, +}; + +static const struct clk_parent_data sysclk0_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data sysclk1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data axiclk_sel_clks[] = { + { .fw_name = "capll_div2", }, + { .fw_name = "capll_div4", }, +}; + +static const struct clk_parent_data ccap_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "vpll", }, + { .fw_name = "apll", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data sdh_sel_clks[] = { + { .fw_name = "syspll", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data dcu_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data gfx_sel_clks[] = { + { .fw_name = "epll", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data dbg_sel_clks[] = { + { .fw_name = "hirc", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data timer0_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer2_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer3_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer4_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer5_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer6_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer7_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer8_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer9_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer10_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer11_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data uart_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data wdt0_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wdt1_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wdt2_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt0_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt1_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt2_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data spi0_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi1_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi2_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi3_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data qspi0_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data qspi1_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data i2s0_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data i2s1_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data can_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "vpll", }, +}; + +static const struct clk_parent_data cko_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "hirc", }, + { .fw_name = "lirc", }, + { .fw_name = "capll_div4", }, + { .fw_name = "syspll", }, + { .fw_name = "ddrpll", }, + { .fw_name = "epll_div2", }, + { .fw_name = "apll", }, + { .fw_name = "vpll", }, +}; + +static const struct clk_parent_data smc_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "pclk4", }, +}; + +static const struct clk_parent_data kpi_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, +}; + +static const struct clk_div_table ip_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {0, 0}, +}; + +static const struct clk_div_table eadc_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {8, 18}, + {9, 20}, {10, 22}, {11, 24}, {12, 26}, + {13, 28}, {14, 30}, {15, 32}, {0, 0}, +}; + +static struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const struct clk_parent_data *pdata, + int num_pdata) +{ + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const struct clk_parent_data *pdata, + int num_pdata) +{ + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) +{ + return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider_pow2(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) +{ + return devm_clk_hw_register_divider(dev, name, parent, + CLK_DIVIDER_POWER_OF_TWO, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider_table(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width, + const struct clk_div_table *table) +{ + return devm_clk_hw_register_divider_table(dev, name, parent, 0, + reg, shift, width, 0, + table, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_fixed_factor(struct device *dev, const char *name, + const char *parent, unsigned int mult, + unsigned int div) +{ + return devm_clk_hw_register_fixed_factor(dev, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static struct clk_hw *ma35d1_clk_gate(struct device *dev, const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return devm_clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, + reg, shift, 0, &ma35d1_lock); +} + +static int ma35d1_get_pll_setting(struct device_node *clk_node, u32 *pllmode) +{ + const char *of_str; + int i; + + for (i = 0; i < PLL_MAX_NUM; i++) { + if (of_property_read_string_index(clk_node, "nuvoton,pll-mode", i, &of_str)) + return -EINVAL; + if (!strcmp(of_str, "integer")) + pllmode[i] = PLL_MODE_INT; + else if (!strcmp(of_str, "fractional")) + pllmode[i] = PLL_MODE_FRAC; + else if (!strcmp(of_str, "spread-spectrum")) + pllmode[i] = PLL_MODE_SS; + else + return -EINVAL; + } + return 0; +} + +static int ma35d1_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *clk_node = pdev->dev.of_node; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + void __iomem *clk_base; + static struct clk_hw **hws; + static struct clk_hw_onecell_data *ma35d1_hw_data; + u32 pllmode[PLL_MAX_NUM]; + int ret; + + ma35d1_hw_data = devm_kzalloc(dev, + struct_size(ma35d1_hw_data, hws, CLK_MAX_IDX), + GFP_KERNEL); + if (!ma35d1_hw_data) + return -ENOMEM; + + ma35d1_hw_data->num = CLK_MAX_IDX; + hws = ma35d1_hw_data->hws; + + clk_base = devm_ioremap_resource(dev, res); + if (IS_ERR(clk_base)) + return PTR_ERR(clk_base); + + ret = ma35d1_get_pll_setting(clk_node, pllmode); + if (ret < 0) { + dev_err(dev, "Invalid PLL setting!\n"); + return -EINVAL; + } + + hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); + hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt", + clk_base + REG_CLK_PWRCTL, 0); + hws[LXT] = ma35d1_clk_fixed("lxt", 32768); + hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt", + clk_base + REG_CLK_PWRCTL, 1); + hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); + hws[HIRC_GATE] = ma35d1_clk_gate(dev, "hirc_gate", "hirc", + clk_base + REG_CLK_PWRCTL, 2); + hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); + hws[LIRC_GATE] = ma35d1_clk_gate(dev, "lirc_gate", "lirc", + clk_base + REG_CLK_PWRCTL, 3); + + hws[CAPLL] = ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", + hws[HXT], clk_base + REG_CLK_PLL0CTL0); + hws[SYSPLL] = ma35d1_clk_fixed("syspll", 180000000); + hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", + hws[HXT], clk_base + REG_CLK_PLL2CTL0); + hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", + hws[HXT], clk_base + REG_CLK_PLL3CTL0); + hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", + hws[HXT], clk_base + REG_CLK_PLL4CTL0); + hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", + hws[HXT], clk_base + REG_CLK_PLL5CTL0); + + hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); + hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); + hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); + + hws[CA35CLK_MUX] = ma35d1_clk_mux_parent(dev, "ca35clk_mux", + clk_base + REG_CLK_CLKSEL0, 0, 2, + ca35clk_sel_clks, + ARRAY_SIZE(ca35clk_sel_clks)); + hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor(dev, "capll_div2", "ca35clk_mux", 1, 2); + hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor(dev, "capll_div4", "ca35clk_mux", 1, 4); + + hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, + 26, 1, axiclk_sel_clks, + ARRAY_SIZE(axiclk_sel_clks)); + hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0, + 2, 1, sysclk0_sel_clks, + ARRAY_SIZE(sysclk0_sel_clks)); + hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0, + 4, 1, sysclk1_sel_clks, + ARRAY_SIZE(sysclk1_sel_clks)); + hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor(dev, "sysclk1_div2", "sysclk1_mux", 1, 2); + + /* HCLK0~3 & PCLK0~4 */ + hws[HCLK0] = ma35d1_clk_fixed_factor(dev, "hclk0", "sysclk1_mux", 1, 1); + hws[HCLK1] = ma35d1_clk_fixed_factor(dev, "hclk1", "sysclk1_mux", 1, 1); + hws[HCLK2] = ma35d1_clk_fixed_factor(dev, "hclk2", "sysclk1_mux", 1, 1); + hws[PCLK0] = ma35d1_clk_fixed_factor(dev, "pclk0", "sysclk1_mux", 1, 1); + hws[PCLK1] = ma35d1_clk_fixed_factor(dev, "pclk1", "sysclk1_mux", 1, 1); + hws[PCLK2] = ma35d1_clk_fixed_factor(dev, "pclk2", "sysclk1_mux", 1, 1); + + hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); + hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); + hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); + + hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); + hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); + + /* DDR */ + hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 4); + hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 5); + + hws[CAN0_MUX] = ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKSEL4, + 16, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN0_DIV] = ma35d1_clk_divider_table(dev, "can0_div", "can0_mux", + clk_base + REG_CLK_CLKDIV0, + 0, 3, ip_div_table); + hws[CAN0_GATE] = ma35d1_clk_gate(dev, "can0_gate", "can0_div", + clk_base + REG_CLK_SYSCLK0, 8); + hws[CAN1_MUX] = ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKSEL4, + 17, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN1_DIV] = ma35d1_clk_divider_table(dev, "can1_div", "can1_mux", + clk_base + REG_CLK_CLKDIV0, + 4, 3, ip_div_table); + hws[CAN1_GATE] = ma35d1_clk_gate(dev, "can1_gate", "can1_div", + clk_base + REG_CLK_SYSCLK0, 9); + hws[CAN2_MUX] = ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKSEL4, + 18, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN2_DIV] = ma35d1_clk_divider_table(dev, "can2_div", "can2_mux", + clk_base + REG_CLK_CLKDIV0, + 8, 3, ip_div_table); + hws[CAN2_GATE] = ma35d1_clk_gate(dev, "can2_gate", "can2_div", + clk_base + REG_CLK_SYSCLK0, 10); + hws[CAN3_MUX] = ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKSEL4, + 19, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN3_DIV] = ma35d1_clk_divider_table(dev, "can3_div", "can3_mux", + clk_base + REG_CLK_CLKDIV0, + 12, 3, ip_div_table); + hws[CAN3_GATE] = ma35d1_clk_gate(dev, "can3_gate", "can3_div", + clk_base + REG_CLK_SYSCLK0, 11); + + hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0, + 16, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH0_GATE] = ma35d1_clk_gate(dev, "sdh0_gate", "sdh0_mux", + clk_base + REG_CLK_SYSCLK0, 16); + hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0, + 18, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH1_GATE] = ma35d1_clk_gate(dev, "sdh1_gate", "sdh1_mux", + clk_base + REG_CLK_SYSCLK0, 17); + + hws[NAND_GATE] = ma35d1_clk_gate(dev, "nand_gate", "hclk1", + clk_base + REG_CLK_SYSCLK0, 18); + + hws[USBD_GATE] = ma35d1_clk_gate(dev, "usbd_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 19); + hws[USBH_GATE] = ma35d1_clk_gate(dev, "usbh_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 20); + hws[HUSBH0_GATE] = ma35d1_clk_gate(dev, "husbh0_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 21); + hws[HUSBH1_GATE] = ma35d1_clk_gate(dev, "husbh1_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 22); + + hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0, + 26, 1, gfx_sel_clks, ARRAY_SIZE(gfx_sel_clks)); + hws[GFX_GATE] = ma35d1_clk_gate(dev, "gfx_gate", "gfx_mux", + clk_base + REG_CLK_SYSCLK0, 24); + hws[VC8K_GATE] = ma35d1_clk_gate(dev, "vc8k_gate", "sysclk0_mux", + clk_base + REG_CLK_SYSCLK0, 25); + hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0, + 24, 1, dcu_sel_clks, ARRAY_SIZE(dcu_sel_clks)); + hws[DCU_GATE] = ma35d1_clk_gate(dev, "dcu_gate", "dcu_mux", + clk_base + REG_CLK_SYSCLK0, 26); + hws[DCUP_DIV] = ma35d1_clk_divider_table(dev, "dcup_div", "vpll", + clk_base + REG_CLK_CLKDIV0, + 16, 3, ip_div_table); + + hws[EMAC0_GATE] = ma35d1_clk_gate(dev, "emac0_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 27); + hws[EMAC1_GATE] = ma35d1_clk_gate(dev, "emac1_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 28); + + hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, + 12, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP0_DIV] = ma35d1_clk_divider(dev, "ccap0_div", "ccap0_mux", + clk_base + REG_CLK_CLKDIV1, 8, 4); + hws[CCAP0_GATE] = ma35d1_clk_gate(dev, "ccap0_gate", "ccap0_div", + clk_base + REG_CLK_SYSCLK0, 29); + hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0, + 14, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP1_DIV] = ma35d1_clk_divider(dev, "ccap1_div", "ccap1_mux", + clk_base + REG_CLK_CLKDIV1, + 12, 4); + hws[CCAP1_GATE] = ma35d1_clk_gate(dev, "ccap1_gate", "ccap1_div", + clk_base + REG_CLK_SYSCLK0, 30); + + hws[PDMA0_GATE] = ma35d1_clk_gate(dev, "pdma0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 0); + hws[PDMA1_GATE] = ma35d1_clk_gate(dev, "pdma1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 1); + hws[PDMA2_GATE] = ma35d1_clk_gate(dev, "pdma2_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 2); + hws[PDMA3_GATE] = ma35d1_clk_gate(dev, "pdma3_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 3); + + hws[WH0_GATE] = ma35d1_clk_gate(dev, "wh0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 4); + hws[WH1_GATE] = ma35d1_clk_gate(dev, "wh1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 5); + + hws[HWS_GATE] = ma35d1_clk_gate(dev, "hws_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 6); + + hws[EBI_GATE] = ma35d1_clk_gate(dev, "ebi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 7); + + hws[SRAM0_GATE] = ma35d1_clk_gate(dev, "sram0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 8); + hws[SRAM1_GATE] = ma35d1_clk_gate(dev, "sram1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 9); + + hws[ROM_GATE] = ma35d1_clk_gate(dev, "rom_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 10); + + hws[TRA_GATE] = ma35d1_clk_gate(dev, "tra_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 11); + + hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0, + 27, 1, dbg_sel_clks, ARRAY_SIZE(dbg_sel_clks)); + hws[DBG_GATE] = ma35d1_clk_gate(dev, "dbg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 12); + + hws[CKO_MUX] = ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL4, + 24, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); + hws[CKO_DIV] = ma35d1_clk_divider_pow2(dev, "cko_div", "cko_mux", + clk_base + REG_CLK_CLKOCTL, 0, 4); + hws[CKO_GATE] = ma35d1_clk_gate(dev, "cko_gate", "cko_div", + clk_base + REG_CLK_SYSCLK1, 13); + + hws[GTMR_GATE] = ma35d1_clk_gate(dev, "gtmr_gate", "hirc", + clk_base + REG_CLK_SYSCLK1, 14); + + hws[GPA_GATE] = ma35d1_clk_gate(dev, "gpa_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 16); + hws[GPB_GATE] = ma35d1_clk_gate(dev, "gpb_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 17); + hws[GPC_GATE] = ma35d1_clk_gate(dev, "gpc_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 18); + hws[GPD_GATE] = ma35d1_clk_gate(dev, "gpd_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 19); + hws[GPE_GATE] = ma35d1_clk_gate(dev, "gpe_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 20); + hws[GPF_GATE] = ma35d1_clk_gate(dev, "gpf_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 21); + hws[GPG_GATE] = ma35d1_clk_gate(dev, "gpg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 22); + hws[GPH_GATE] = ma35d1_clk_gate(dev, "gph_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 23); + hws[GPI_GATE] = ma35d1_clk_gate(dev, "gpi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 24); + hws[GPJ_GATE] = ma35d1_clk_gate(dev, "gpj_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 25); + hws[GPK_GATE] = ma35d1_clk_gate(dev, "gpk_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 26); + hws[GPL_GATE] = ma35d1_clk_gate(dev, "gpl_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 27); + hws[GPM_GATE] = ma35d1_clk_gate(dev, "gpm_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 28); + hws[GPN_GATE] = ma35d1_clk_gate(dev, "gpn_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 29); + + hws[TMR0_MUX] = ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKSEL1, + 0, 3, timer0_sel_clks, + ARRAY_SIZE(timer0_sel_clks)); + hws[TMR0_GATE] = ma35d1_clk_gate(dev, "tmr0_gate", "tmr0_mux", + clk_base + REG_CLK_APBCLK0, 0); + hws[TMR1_MUX] = ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKSEL1, + 4, 3, timer1_sel_clks, + ARRAY_SIZE(timer1_sel_clks)); + hws[TMR1_GATE] = ma35d1_clk_gate(dev, "tmr1_gate", "tmr1_mux", + clk_base + REG_CLK_APBCLK0, 1); + hws[TMR2_MUX] = ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKSEL1, + 8, 3, timer2_sel_clks, + ARRAY_SIZE(timer2_sel_clks)); + hws[TMR2_GATE] = ma35d1_clk_gate(dev, "tmr2_gate", "tmr2_mux", + clk_base + REG_CLK_APBCLK0, 2); + hws[TMR3_MUX] = ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKSEL1, + 12, 3, timer3_sel_clks, + ARRAY_SIZE(timer3_sel_clks)); + hws[TMR3_GATE] = ma35d1_clk_gate(dev, "tmr3_gate", "tmr3_mux", + clk_base + REG_CLK_APBCLK0, 3); + hws[TMR4_MUX] = ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKSEL1, + 16, 3, timer4_sel_clks, + ARRAY_SIZE(timer4_sel_clks)); + hws[TMR4_GATE] = ma35d1_clk_gate(dev, "tmr4_gate", "tmr4_mux", + clk_base + REG_CLK_APBCLK0, 4); + hws[TMR5_MUX] = ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKSEL1, + 20, 3, timer5_sel_clks, + ARRAY_SIZE(timer5_sel_clks)); + hws[TMR5_GATE] = ma35d1_clk_gate(dev, "tmr5_gate", "tmr5_mux", + clk_base + REG_CLK_APBCLK0, 5); + hws[TMR6_MUX] = ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKSEL1, + 24, 3, timer6_sel_clks, + ARRAY_SIZE(timer6_sel_clks)); + hws[TMR6_GATE] = ma35d1_clk_gate(dev, "tmr6_gate", "tmr6_mux", + clk_base + REG_CLK_APBCLK0, 6); + hws[TMR7_MUX] = ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKSEL1, + 28, 3, timer7_sel_clks, + ARRAY_SIZE(timer7_sel_clks)); + hws[TMR7_GATE] = ma35d1_clk_gate(dev, "tmr7_gate", "tmr7_mux", + clk_base + REG_CLK_APBCLK0, 7); + hws[TMR8_MUX] = ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKSEL2, + 0, 3, timer8_sel_clks, + ARRAY_SIZE(timer8_sel_clks)); + hws[TMR8_GATE] = ma35d1_clk_gate(dev, "tmr8_gate", "tmr8_mux", + clk_base + REG_CLK_APBCLK0, 8); + hws[TMR9_MUX] = ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKSEL2, + 4, 3, timer9_sel_clks, + ARRAY_SIZE(timer9_sel_clks)); + hws[TMR9_GATE] = ma35d1_clk_gate(dev, "tmr9_gate", "tmr9_mux", + clk_base + REG_CLK_APBCLK0, 9); + hws[TMR10_MUX] = ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CLKSEL2, + 8, 3, timer10_sel_clks, + ARRAY_SIZE(timer10_sel_clks)); + hws[TMR10_GATE] = ma35d1_clk_gate(dev, "tmr10_gate", "tmr10_mux", + clk_base + REG_CLK_APBCLK0, 10); + hws[TMR11_MUX] = ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CLKSEL2, + 12, 3, timer11_sel_clks, + ARRAY_SIZE(timer11_sel_clks)); + hws[TMR11_GATE] = ma35d1_clk_gate(dev, "tmr11_gate", "tmr11_mux", + clk_base + REG_CLK_APBCLK0, 11); + + hws[UART0_MUX] = ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CLKSEL2, + 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART0_DIV] = ma35d1_clk_divider(dev, "uart0_div", "uart0_mux", + clk_base + REG_CLK_CLKDIV1, + 16, 4); + hws[UART0_GATE] = ma35d1_clk_gate(dev, "uart0_gate", "uart0_div", + clk_base + REG_CLK_APBCLK0, 12); + hws[UART1_MUX] = ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CLKSEL2, + 18, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART1_DIV] = ma35d1_clk_divider(dev, "uart1_div", "uart1_mux", + clk_base + REG_CLK_CLKDIV1, + 20, 4); + hws[UART1_GATE] = ma35d1_clk_gate(dev, "uart1_gate", "uart1_div", + clk_base + REG_CLK_APBCLK0, 13); + hws[UART2_MUX] = ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CLKSEL2, + 20, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART2_DIV] = ma35d1_clk_divider(dev, "uart2_div", "uart2_mux", + clk_base + REG_CLK_CLKDIV1, + 24, 4); + hws[UART2_GATE] = ma35d1_clk_gate(dev, "uart2_gate", "uart2_div", + clk_base + REG_CLK_APBCLK0, 14); + hws[UART3_MUX] = ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CLKSEL2, + 22, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART3_DIV] = ma35d1_clk_divider(dev, "uart3_div", "uart3_mux", + clk_base + REG_CLK_CLKDIV1, + 28, 4); + hws[UART3_GATE] = ma35d1_clk_gate(dev, "uart3_gate", "uart3_div", + clk_base + REG_CLK_APBCLK0, 15); + hws[UART4_MUX] = ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CLKSEL2, + 24, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART4_DIV] = ma35d1_clk_divider(dev, "uart4_div", "uart4_mux", + clk_base + REG_CLK_CLKDIV2, + 0, 4); + hws[UART4_GATE] = ma35d1_clk_gate(dev, "uart4_gate", "uart4_div", + clk_base + REG_CLK_APBCLK0, 16); + hws[UART5_MUX] = ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CLKSEL2, + 26, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART5_DIV] = ma35d1_clk_divider(dev, "uart5_div", "uart5_mux", + clk_base + REG_CLK_CLKDIV2, + 4, 4); + hws[UART5_GATE] = ma35d1_clk_gate(dev, "uart5_gate", "uart5_div", + clk_base + REG_CLK_APBCLK0, 17); + hws[UART6_MUX] = ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CLKSEL2, + 28, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART6_DIV] = ma35d1_clk_divider(dev, "uart6_div", "uart6_mux", + clk_base + REG_CLK_CLKDIV2, + 8, 4); + hws[UART6_GATE] = ma35d1_clk_gate(dev, "uart6_gate", "uart6_div", + clk_base + REG_CLK_APBCLK0, 18); + hws[UART7_MUX] = ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CLKSEL2, + 30, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART7_DIV] = ma35d1_clk_divider(dev, "uart7_div", "uart7_mux", + clk_base + REG_CLK_CLKDIV2, + 12, 4); + hws[UART7_GATE] = ma35d1_clk_gate(dev, "uart7_gate", "uart7_div", + clk_base + REG_CLK_APBCLK0, 19); + hws[UART8_MUX] = ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CLKSEL3, + 0, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART8_DIV] = ma35d1_clk_divider(dev, "uart8_div", "uart8_mux", + clk_base + REG_CLK_CLKDIV2, + 16, 4); + hws[UART8_GATE] = ma35d1_clk_gate(dev, "uart8_gate", "uart8_div", + clk_base + REG_CLK_APBCLK0, 20); + hws[UART9_MUX] = ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CLKSEL3, + 2, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART9_DIV] = ma35d1_clk_divider(dev, "uart9_div", "uart9_mux", + clk_base + REG_CLK_CLKDIV2, + 20, 4); + hws[UART9_GATE] = ma35d1_clk_gate(dev, "uart9_gate", "uart9_div", + clk_base + REG_CLK_APBCLK0, 21); + hws[UART10_MUX] = ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_CLKSEL3, + 4, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART10_DIV] = ma35d1_clk_divider(dev, "uart10_div", "uart10_mux", + clk_base + REG_CLK_CLKDIV2, + 24, 4); + hws[UART10_GATE] = ma35d1_clk_gate(dev, "uart10_gate", "uart10_div", + clk_base + REG_CLK_APBCLK0, 22); + hws[UART11_MUX] = ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_CLKSEL3, + 6, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART11_DIV] = ma35d1_clk_divider(dev, "uart11_div", "uart11_mux", + clk_base + REG_CLK_CLKDIV2, + 28, 4); + hws[UART11_GATE] = ma35d1_clk_gate(dev, "uart11_gate", "uart11_div", + clk_base + REG_CLK_APBCLK0, 23); + hws[UART12_MUX] = ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_CLKSEL3, + 8, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART12_DIV] = ma35d1_clk_divider(dev, "uart12_div", "uart12_mux", + clk_base + REG_CLK_CLKDIV3, + 0, 4); + hws[UART12_GATE] = ma35d1_clk_gate(dev, "uart12_gate", "uart12_div", + clk_base + REG_CLK_APBCLK0, 24); + hws[UART13_MUX] = ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_CLKSEL3, + 10, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART13_DIV] = ma35d1_clk_divider(dev, "uart13_div", "uart13_mux", + clk_base + REG_CLK_CLKDIV3, + 4, 4); + hws[UART13_GATE] = ma35d1_clk_gate(dev, "uart13_gate", "uart13_div", + clk_base + REG_CLK_APBCLK0, 25); + hws[UART14_MUX] = ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_CLKSEL3, + 12, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART14_DIV] = ma35d1_clk_divider(dev, "uart14_div", "uart14_mux", + clk_base + REG_CLK_CLKDIV3, + 8, 4); + hws[UART14_GATE] = ma35d1_clk_gate(dev, "uart14_gate", "uart14_div", + clk_base + REG_CLK_APBCLK0, 26); + hws[UART15_MUX] = ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_CLKSEL3, + 14, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART15_DIV] = ma35d1_clk_divider(dev, "uart15_div", "uart15_mux", + clk_base + REG_CLK_CLKDIV3, + 12, 4); + hws[UART15_GATE] = ma35d1_clk_gate(dev, "uart15_gate", "uart15_div", + clk_base + REG_CLK_APBCLK0, 27); + hws[UART16_MUX] = ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_CLKSEL3, + 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART16_DIV] = ma35d1_clk_divider(dev, "uart16_div", "uart16_mux", + clk_base + REG_CLK_CLKDIV3, + 16, 4); + hws[UART16_GATE] = ma35d1_clk_gate(dev, "uart16_gate", "uart16_div", + clk_base + REG_CLK_APBCLK0, 28); + + hws[RTC_GATE] = ma35d1_clk_gate(dev, "rtc_gate", "lxt", + clk_base + REG_CLK_APBCLK0, 29); + hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", + clk_base + REG_CLK_APBCLK0, 30); + + hws[KPI_MUX] = ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL4, + 30, 1, kpi_sel_clks, ARRAY_SIZE(kpi_sel_clks)); + hws[KPI_DIV] = ma35d1_clk_divider(dev, "kpi_div", "kpi_mux", + clk_base + REG_CLK_CLKDIV4, + 24, 8); + hws[KPI_GATE] = ma35d1_clk_gate(dev, "kpi_gate", "kpi_div", + clk_base + REG_CLK_APBCLK0, 31); + + hws[I2C0_GATE] = ma35d1_clk_gate(dev, "i2c0_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 0); + hws[I2C1_GATE] = ma35d1_clk_gate(dev, "i2c1_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 1); + hws[I2C2_GATE] = ma35d1_clk_gate(dev, "i2c2_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 2); + hws[I2C3_GATE] = ma35d1_clk_gate(dev, "i2c3_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 3); + hws[I2C4_GATE] = ma35d1_clk_gate(dev, "i2c4_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 4); + hws[I2C5_GATE] = ma35d1_clk_gate(dev, "i2c5_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 5); + + hws[QSPI0_MUX] = ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CLKSEL4, + 8, 2, qspi0_sel_clks, ARRAY_SIZE(qspi0_sel_clks)); + hws[QSPI0_GATE] = ma35d1_clk_gate(dev, "qspi0_gate", "qspi0_mux", + clk_base + REG_CLK_APBCLK1, 6); + hws[QSPI1_MUX] = ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CLKSEL4, + 10, 2, qspi1_sel_clks, ARRAY_SIZE(qspi1_sel_clks)); + hws[QSPI1_GATE] = ma35d1_clk_gate(dev, "qspi1_gate", "qspi1_mux", + clk_base + REG_CLK_APBCLK1, 7); + + hws[SMC0_MUX] = ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKSEL4, + 28, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC0_DIV] = ma35d1_clk_divider(dev, "smc0_div", "smc0_mux", + clk_base + REG_CLK_CLKDIV1, + 0, 4); + hws[SMC0_GATE] = ma35d1_clk_gate(dev, "smc0_gate", "smc0_div", + clk_base + REG_CLK_APBCLK1, 12); + hws[SMC1_MUX] = ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKSEL4, + 29, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC1_DIV] = ma35d1_clk_divider(dev, "smc1_div", "smc1_mux", + clk_base + REG_CLK_CLKDIV1, + 4, 4); + hws[SMC1_GATE] = ma35d1_clk_gate(dev, "smc1_gate", "smc1_div", + clk_base + REG_CLK_APBCLK1, 13); + + hws[WDT0_MUX] = ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKSEL3, + 20, 2, wdt0_sel_clks, ARRAY_SIZE(wdt0_sel_clks)); + hws[WDT0_GATE] = ma35d1_clk_gate(dev, "wdt0_gate", "wdt0_mux", + clk_base + REG_CLK_APBCLK1, 16); + hws[WDT1_MUX] = ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKSEL3, + 24, 2, wdt1_sel_clks, ARRAY_SIZE(wdt1_sel_clks)); + hws[WDT1_GATE] = ma35d1_clk_gate(dev, "wdt1_gate", "wdt1_mux", + clk_base + REG_CLK_APBCLK1, 17); + hws[WDT2_MUX] = ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKSEL3, + 28, 2, wdt2_sel_clks, ARRAY_SIZE(wdt2_sel_clks)); + hws[WDT2_GATE] = ma35d1_clk_gate(dev, "wdt2_gate", "wdt2_mux", + clk_base + REG_CLK_APBCLK1, 18); + + hws[WWDT0_MUX] = ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CLKSEL3, + 22, 2, wwdt0_sel_clks, ARRAY_SIZE(wwdt0_sel_clks)); + hws[WWDT1_MUX] = ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CLKSEL3, + 26, 2, wwdt1_sel_clks, ARRAY_SIZE(wwdt1_sel_clks)); + hws[WWDT2_MUX] = ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CLKSEL3, + 30, 2, wwdt2_sel_clks, ARRAY_SIZE(wwdt2_sel_clks)); + + hws[EPWM0_GATE] = ma35d1_clk_gate(dev, "epwm0_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 24); + hws[EPWM1_GATE] = ma35d1_clk_gate(dev, "epwm1_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 25); + hws[EPWM2_GATE] = ma35d1_clk_gate(dev, "epwm2_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 26); + + hws[I2S0_MUX] = ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKSEL4, + 12, 2, i2s0_sel_clks, ARRAY_SIZE(i2s0_sel_clks)); + hws[I2S0_GATE] = ma35d1_clk_gate(dev, "i2s0_gate", "i2s0_mux", + clk_base + REG_CLK_APBCLK2, 0); + hws[I2S1_MUX] = ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKSEL4, + 14, 2, i2s1_sel_clks, ARRAY_SIZE(i2s1_sel_clks)); + hws[I2S1_GATE] = ma35d1_clk_gate(dev, "i2s1_gate", "i2s1_mux", + clk_base + REG_CLK_APBCLK2, 1); + + hws[SSMCC_GATE] = ma35d1_clk_gate(dev, "ssmcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 2); + hws[SSPCC_GATE] = ma35d1_clk_gate(dev, "sspcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 3); + + hws[SPI0_MUX] = ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKSEL4, + 0, 2, spi0_sel_clks, ARRAY_SIZE(spi0_sel_clks)); + hws[SPI0_GATE] = ma35d1_clk_gate(dev, "spi0_gate", "spi0_mux", + clk_base + REG_CLK_APBCLK2, 4); + hws[SPI1_MUX] = ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKSEL4, + 2, 2, spi1_sel_clks, ARRAY_SIZE(spi1_sel_clks)); + hws[SPI1_GATE] = ma35d1_clk_gate(dev, "spi1_gate", "spi1_mux", + clk_base + REG_CLK_APBCLK2, 5); + hws[SPI2_MUX] = ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKSEL4, + 4, 2, spi2_sel_clks, ARRAY_SIZE(spi2_sel_clks)); + hws[SPI2_GATE] = ma35d1_clk_gate(dev, "spi2_gate", "spi2_mux", + clk_base + REG_CLK_APBCLK2, 6); + hws[SPI3_MUX] = ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKSEL4, + 6, 2, spi3_sel_clks, ARRAY_SIZE(spi3_sel_clks)); + hws[SPI3_GATE] = ma35d1_clk_gate(dev, "spi3_gate", "spi3_mux", + clk_base + REG_CLK_APBCLK2, 7); + + hws[ECAP0_GATE] = ma35d1_clk_gate(dev, "ecap0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 8); + hws[ECAP1_GATE] = ma35d1_clk_gate(dev, "ecap1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 9); + hws[ECAP2_GATE] = ma35d1_clk_gate(dev, "ecap2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 10); + + hws[QEI0_GATE] = ma35d1_clk_gate(dev, "qei0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 12); + hws[QEI1_GATE] = ma35d1_clk_gate(dev, "qei1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 13); + hws[QEI2_GATE] = ma35d1_clk_gate(dev, "qei2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 14); + + hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", hws[PCLK0], + &ma35d1_lock, 0, + clk_base + REG_CLK_CLKDIV4, + 4, 17, 0x1ffff); + hws[ADC_GATE] = ma35d1_clk_gate(dev, "adc_gate", "adc_div", + clk_base + REG_CLK_APBCLK2, 24); + + hws[EADC_DIV] = ma35d1_clk_divider_table(dev, "eadc_div", "pclk2", + clk_base + REG_CLK_CLKDIV4, + 0, 4, eadc_div_table); + hws[EADC_GATE] = ma35d1_clk_gate(dev, "eadc_gate", "eadc_div", + clk_base + REG_CLK_APBCLK2, 25); + + return devm_of_clk_add_hw_provider(dev, + of_clk_hw_onecell_get, + ma35d1_hw_data); +} + +static const struct of_device_id ma35d1_clk_of_match[] = { + { .compatible = "nuvoton,ma35d1-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, ma35d1_clk_of_match); + +static struct platform_driver ma35d1_clk_driver = { + .probe = ma35d1_clocks_probe, + .driver = { + .name = "ma35d1-clk", + .of_match_table = ma35d1_clk_of_match, + }, +}; + +static int __init ma35d1_clocks_init(void) +{ + return platform_driver_register(&ma35d1_clk_driver); +} + +postcore_initcall(ma35d1_clocks_init); + +MODULE_AUTHOR("Chi-Fang Li "); +MODULE_DESCRIPTION("NUVOTON MA35D1 Clock Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h new file mode 100644 index 000000000000..3adee440f60a --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#ifndef __DRV_CLK_NUVOTON_MA35D1_H +#define __DRV_CLK_NUVOTON_MA35D1_H + +struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, + struct clk_hw *parent_hw, void __iomem *base); + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + struct clk_hw *parent_hw, spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit); + +#endif /* __DRV_CLK_NUVOTON_MA35D1_H */ diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c index 93d5907b8530..0a4da519d704 100644 --- a/drivers/clk/pxa/clk-pxa25x.c +++ b/drivers/clk/pxa/clk-pxa25x.c @@ -11,10 +11,12 @@ */ #include #include +#include #include #include #include #include +#include #include #include "clk-pxa.h" diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c index 116c6ac666e3..2bea89874ec1 100644 --- a/drivers/clk/pxa/clk-pxa27x.c +++ b/drivers/clk/pxa/clk-pxa27x.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "clk-pxa.h" @@ -99,7 +100,7 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) return (unsigned int)clks[0] / KHz; } -bool pxa27x_is_ppll_disabled(void) +static bool pxa27x_is_ppll_disabled(void) { unsigned long ccsr = readl(clk_regs + CCSR); diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig index 6580d5edc676..7c4f335864a8 100644 --- a/drivers/clk/ralink/Kconfig +++ b/drivers/clk/ralink/Kconfig @@ -9,3 +9,10 @@ config CLK_MT7621 select MFD_SYSCON help This driver supports MediaTek MT7621 basic clocks. + +config CLK_MTMIPS + bool "Clock driver for MTMIPS SoCs" + depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST + select MFD_SYSCON + help + This driver supports MTMIPS basic clocks. diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile index cf6f9216379d..398c1bf8cbc1 100644 --- a/drivers/clk/ralink/Makefile +++ b/drivers/clk/ralink/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o +obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c new file mode 100644 index 000000000000..1e7991439527 --- /dev/null +++ b/drivers/clk/ralink/clk-mtmips.c @@ -0,0 +1,1117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MTMIPS SoCs Clock Driver + * Author: Sergio Paracuellos + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Configuration registers */ +#define SYSC_REG_SYSTEM_CONFIG 0x10 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_RESET_CTRL 0x34 +#define SYSC_REG_CPU_SYS_CLKCFG 0x3c +#define SYSC_REG_CPLL_CONFIG0 0x54 +#define SYSC_REG_CPLL_CONFIG1 0x58 + +/* RT2880 SoC */ +#define RT2880_CONFIG_CPUCLK_SHIFT 20 +#define RT2880_CONFIG_CPUCLK_MASK 0x3 +#define RT2880_CONFIG_CPUCLK_250 0x0 +#define RT2880_CONFIG_CPUCLK_266 0x1 +#define RT2880_CONFIG_CPUCLK_280 0x2 +#define RT2880_CONFIG_CPUCLK_300 0x3 + +/* RT305X SoC */ +#define RT305X_SYSCFG_CPUCLK_SHIFT 18 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 + +/* RT3352 SoC */ +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 + +/* RT3383 SoC */ +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 +#define RT3883_SYSCFG0_CPUCLK_250 0x0 +#define RT3883_SYSCFG0_CPUCLK_384 0x1 +#define RT3883_SYSCFG0_CPUCLK_480 0x2 +#define RT3883_SYSCFG0_CPUCLK_500 0x3 + +/* RT5350 SoC */ +#define RT5350_CLKCFG0_XTAL_SEL BIT(20) +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 +#define RT5350_SYSCFG0_CPUCLK_360 0x0 +#define RT5350_SYSCFG0_CPUCLK_320 0x2 +#define RT5350_SYSCFG0_CPUCLK_300 0x3 + +/* MT7620 and MT76x8 SoCs */ +#define MT7620_XTAL_FREQ_SEL BIT(6) +#define CPLL_CFG0_SW_CFG BIT(31) +#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 +#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 +#define CPLL_CFG0_LC_CURFCK BIT(15) +#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) +#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 +#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 +#define CPLL_CFG1_CPU_AUX1 BIT(25) +#define CPLL_CFG1_CPU_AUX0 BIT(24) +#define CLKCFG0_PERI_CLK_SEL BIT(4) +#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 +#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf +#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ +#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 +#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f +#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 +#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f + +/* clock scaling */ +#define CLKCFG_FDIV_MASK 0x1f00 +#define CLKCFG_FDIV_USB_VAL 0x0300 +#define CLKCFG_FFRAC_MASK 0x001f +#define CLKCFG_FFRAC_USB_VAL 0x0003 + +struct mtmips_clk; +struct mtmips_clk_fixed; +struct mtmips_clk_factor; + +struct mtmips_clk_data { + struct mtmips_clk *clk_base; + size_t num_clk_base; + struct mtmips_clk_fixed *clk_fixed; + size_t num_clk_fixed; + struct mtmips_clk_factor *clk_factor; + size_t num_clk_factor; + struct mtmips_clk *clk_periph; + size_t num_clk_periph; +}; + +struct mtmips_clk_priv { + struct regmap *sysc; + const struct mtmips_clk_data *data; +}; + +struct mtmips_clk { + struct clk_hw hw; + struct mtmips_clk_priv *priv; +}; + +struct mtmips_clk_fixed { + const char *name; + const char *parent; + unsigned long rate; + struct clk_hw *hw; +}; + +struct mtmips_clk_factor { + const char *name; + const char *parent; + int mult; + int div; + unsigned long flags; + struct clk_hw *hw; +}; + +static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate; +} + +static const struct clk_ops mtmips_periph_clk_ops = { + .recalc_rate = mtmips_pherip_clk_rate, +}; + +#define CLK_PERIPH(_name, _parent) { \ + .init = &(const struct clk_init_data) { \ + .name = _name, \ + .ops = &mtmips_periph_clk_ops, \ + .parent_data = &(const struct clk_parent_data) {\ + .name = _parent, \ + .fw_name = _parent \ + }, \ + .num_parents = 1, \ + /* \ + * There are drivers for these SoCs that are \ + * older than clock driver and are not prepared \ + * for the clock. We don't want the kernel to \ + * disable anything so we add CLK_IS_CRITICAL \ + * flag here. \ + */ \ + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \ + }, \ +} + +static struct mtmips_clk rt2880_pherip_clks[] = { + { CLK_PERIPH("300100.timer", "bus") }, + { CLK_PERIPH("300120.watchdog", "bus") }, + { CLK_PERIPH("300500.uart", "bus") }, + { CLK_PERIPH("300900.i2c", "bus") }, + { CLK_PERIPH("300c00.uartlite", "bus") }, + { CLK_PERIPH("400000.ethernet", "bus") }, + { CLK_PERIPH("480000.wmac", "xtal") } +}; + +static struct mtmips_clk rt305x_pherip_clks[] = { + { CLK_PERIPH("10000100.timer", "bus") }, + { CLK_PERIPH("10000120.watchdog", "bus") }, + { CLK_PERIPH("10000500.uart", "bus") }, + { CLK_PERIPH("10000900.i2c", "bus") }, + { CLK_PERIPH("10000a00.i2s", "bus") }, + { CLK_PERIPH("10000b00.spi", "bus") }, + { CLK_PERIPH("10000b40.spi", "bus") }, + { CLK_PERIPH("10000c00.uartlite", "bus") }, + { CLK_PERIPH("10100000.ethernet", "bus") }, + { CLK_PERIPH("10180000.wmac", "xtal") } +}; + +static struct mtmips_clk rt5350_pherip_clks[] = { + { CLK_PERIPH("10000100.timer", "bus") }, + { CLK_PERIPH("10000120.watchdog", "bus") }, + { CLK_PERIPH("10000500.uart", "periph") }, + { CLK_PERIPH("10000900.i2c", "periph") }, + { CLK_PERIPH("10000a00.i2s", "periph") }, + { CLK_PERIPH("10000b00.spi", "bus") }, + { CLK_PERIPH("10000b40.spi", "bus") }, + { CLK_PERIPH("10000c00.uartlite", "periph") }, + { CLK_PERIPH("10100000.ethernet", "bus") }, + { CLK_PERIPH("10180000.wmac", "xtal") } +}; + +static struct mtmips_clk mt7620_pherip_clks[] = { + { CLK_PERIPH("10000100.timer", "periph") }, + { CLK_PERIPH("10000120.watchdog", "periph") }, + { CLK_PERIPH("10000500.uart", "periph") }, + { CLK_PERIPH("10000900.i2c", "periph") }, + { CLK_PERIPH("10000a00.i2s", "periph") }, + { CLK_PERIPH("10000b00.spi", "bus") }, + { CLK_PERIPH("10000b40.spi", "bus") }, + { CLK_PERIPH("10000c00.uartlite", "periph") }, + { CLK_PERIPH("10180000.wmac", "xtal") } +}; + +static struct mtmips_clk mt76x8_pherip_clks[] = { + { CLK_PERIPH("10000100.timer", "periph") }, + { CLK_PERIPH("10000120.watchdog", "periph") }, + { CLK_PERIPH("10000900.i2c", "periph") }, + { CLK_PERIPH("10000a00.i2s", "pcmi2s") }, + { CLK_PERIPH("10000b00.spi", "bus") }, + { CLK_PERIPH("10000b40.spi", "bus") }, + { CLK_PERIPH("10000c00.uart0", "periph") }, + { CLK_PERIPH("10000d00.uart1", "periph") }, + { CLK_PERIPH("10000e00.uart2", "periph") }, + { CLK_PERIPH("10300000.wmac", "xtal") } +}; + +static int mtmips_register_pherip_clocks(struct device_node *np, + struct clk_hw_onecell_data *clk_data, + struct mtmips_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + struct mtmips_clk *sclk; + size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + + priv->data->num_clk_factor; + int ret, i; + + for (i = 0; i < priv->data->num_clk_periph; i++) { + int idx = idx_start + i; + + sclk = &priv->data->clk_periph[i]; + ret = of_clk_hw_register(np, &sclk->hw); + if (ret) { + pr_err("Couldn't register peripheral clock %d\n", idx); + goto err_clk_unreg; + } + + hws[idx] = &sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + sclk = &priv->data->clk_periph[i]; + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +#define CLK_FIXED(_name, _parent, _rate) \ + { \ + .name = _name, \ + .parent = _parent, \ + .rate = _rate \ + } + +static struct mtmips_clk_fixed rt305x_fixed_clocks[] = { + CLK_FIXED("xtal", NULL, 40000000) +}; + +static struct mtmips_clk_fixed rt3352_fixed_clocks[] = { + CLK_FIXED("periph", "xtal", 40000000) +}; + +static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = { + CLK_FIXED("pcmi2s", "xtal", 480000000), + CLK_FIXED("periph", "xtal", 40000000) +}; + +static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, + struct mtmips_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + struct mtmips_clk_fixed *sclk; + size_t idx_start = priv->data->num_clk_base; + int ret, i; + + for (i = 0; i < priv->data->num_clk_fixed; i++) { + int idx = idx_start + i; + + sclk = &priv->data->clk_fixed[i]; + sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, + sclk->parent, 0, + sclk->rate); + if (IS_ERR(sclk->hw)) { + ret = PTR_ERR(sclk->hw); + pr_err("Couldn't register fixed clock %d\n", idx); + goto err_clk_unreg; + } + + hws[idx] = sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + sclk = &priv->data->clk_fixed[i]; + clk_hw_unregister_fixed_rate(sclk->hw); + } + return ret; +} + +#define CLK_FACTOR(_name, _parent, _mult, _div) \ + { \ + .name = _name, \ + .parent = _parent, \ + .mult = _mult, \ + .div = _div, \ + .flags = CLK_SET_RATE_PARENT \ + } + +static struct mtmips_clk_factor rt2880_factor_clocks[] = { + CLK_FACTOR("bus", "cpu", 1, 2) +}; + +static struct mtmips_clk_factor rt305x_factor_clocks[] = { + CLK_FACTOR("bus", "cpu", 1, 3) +}; + +static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, + struct mtmips_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + struct mtmips_clk_factor *sclk; + size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; + int ret, i; + + for (i = 0; i < priv->data->num_clk_factor; i++) { + int idx = idx_start + i; + + sclk = &priv->data->clk_factor[i]; + sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, + sclk->parent, sclk->flags, + sclk->mult, sclk->div); + if (IS_ERR(sclk->hw)) { + ret = PTR_ERR(sclk->hw); + pr_err("Couldn't register factor clock %d\n", idx); + goto err_clk_unreg; + } + + hws[idx] = sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + sclk = &priv->data->clk_factor[i]; + clk_hw_unregister_fixed_factor(sclk->hw); + } + return ret; +} + +static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) +{ + return container_of(hw, struct mtmips_clk, hw); +} + +static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 val; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val); + if (!(val & RT5350_CLKCFG0_XTAL_SEL)) + return 20000000; + + return 40000000; +} + +static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK; + + switch (t) { + case RT5350_SYSCFG0_CPUCLK_360: + return 360000000; + case RT5350_SYSCFG0_CPUCLK_320: + return 320000000; + case RT5350_SYSCFG0_CPUCLK_300: + return 300000000; + default: + BUG(); + } +} + +static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (parent_rate == 320000000) + return parent_rate / 4; + + return parent_rate / 3; +} + +static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK; + + switch (t) { + case RT3352_SYSCFG0_CPUCLK_LOW: + return 384000000; + case RT3352_SYSCFG0_CPUCLK_HIGH: + return 400000000; + default: + BUG(); + } +} + +static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; + + switch (t) { + case RT305X_SYSCFG_CPUCLK_LOW: + return 320000000; + case RT305X_SYSCFG_CPUCLK_HIGH: + return 384000000; + default: + BUG(); + } +} + +static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK; + + switch (t) { + case RT3883_SYSCFG0_CPUCLK_250: + return 250000000; + case RT3883_SYSCFG0_CPUCLK_384: + return 384000000; + case RT3883_SYSCFG0_CPUCLK_480: + return 480000000; + case RT3883_SYSCFG0_CPUCLK_500: + return 500000000; + default: + BUG(); + } +} + +static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 ddr2; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2; + + switch (parent_rate) { + case 250000000: + return (ddr2) ? 125000000 : 83000000; + case 384000000: + return (ddr2) ? 128000000 : 96000000; + case 480000000: + return (ddr2) ? 160000000 : 120000000; + case 500000000: + return (ddr2) ? 166000000 : 125000000; + default: + WARN_ON_ONCE(parent_rate == 0); + return parent_rate / 4; + } +} + +static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK; + + switch (t) { + case RT2880_CONFIG_CPUCLK_250: + return 250000000; + case RT2880_CONFIG_CPUCLK_266: + return 266000000; + case RT2880_CONFIG_CPUCLK_280: + return 280000000; + case RT2880_CONFIG_CPUCLK_300: + return 300000000; + default: + BUG(); + } +} + +static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) +{ + u64 t; + + t = ref_rate; + t *= mul; + t = div_u64(t, div); + + return t; +} + +static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + static const u32 clk_divider[] = { 2, 3, 4, 8 }; + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + unsigned long cpu_pll; + u32 t; + u32 mul; + u32 div; + + regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t); + if (t & CPLL_CFG0_BYPASS_REF_CLK) { + cpu_pll = parent_rate; + } else if ((t & CPLL_CFG0_SW_CFG) == 0) { + cpu_pll = 600000000; + } else { + mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & + CPLL_CFG0_PLL_MULT_RATIO_MASK; + mul += 24; + if (t & CPLL_CFG0_LC_CURFCK) + mul *= 2; + + div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & + CPLL_CFG0_PLL_DIV_RATIO_MASK; + + WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider)); + + cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); + } + + regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t); + if (t & CPLL_CFG1_CPU_AUX1) + return parent_rate; + + if (t & CPLL_CFG1_CPU_AUX0) + return 480000000; + + return cpu_pll; +} + +static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + u32 mul; + u32 div; + + regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); + mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; + div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & + CPU_SYS_CLKCFG_CPU_FDIV_MASK; + + return mt7620_calc_rate(parent_rate, mul, div); +} + +static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + static const u32 ocp_dividers[16] = { + [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, + [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, + [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, + [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, + [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, + }; + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + u32 ocp_ratio; + u32 div; + + regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); + ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & + CPU_SYS_CLKCFG_OCP_RATIO_MASK; + + if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers))) + return parent_rate; + + div = ocp_dividers[ocp_ratio]; + + if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) + return parent_rate; + + return parent_rate / div; +} + +static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_CLKCFG0, &t); + if (t & CLKCFG0_PERI_CLK_SEL) + return parent_rate; + + return 40000000; +} + +static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtmips_clk *clk = to_mtmips_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 t; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); + if (t & MT7620_XTAL_FREQ_SEL) + return 40000000; + + return 20000000; +} + +static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + if (xtal_clk == 40000000) + return 580000000; + + return 575000000; +} + +#define CLK_BASE(_name, _parent, _recalc) { \ + .init = &(const struct clk_init_data) { \ + .name = _name, \ + .ops = &(const struct clk_ops) { \ + .recalc_rate = _recalc, \ + }, \ + .parent_data = &(const struct clk_parent_data) { \ + .name = _parent, \ + .fw_name = _parent \ + }, \ + .num_parents = _parent ? 1 : 0 \ + }, \ +} + +static struct mtmips_clk rt2880_clks_base[] = { + { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } +}; + +static struct mtmips_clk rt305x_clks_base[] = { + { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } +}; + +static struct mtmips_clk rt3352_clks_base[] = { + { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, + { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) } +}; + +static struct mtmips_clk rt3883_clks_base[] = { + { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, + { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } +}; + +static struct mtmips_clk rt5350_clks_base[] = { + { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, + { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) }, + { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) } +}; + +static struct mtmips_clk mt7620_clks_base[] = { + { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, + { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) }, + { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) }, + { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) }, + { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) } +}; + +static struct mtmips_clk mt76x8_clks_base[] = { + { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, + { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) } +}; + +static int mtmips_register_clocks(struct device_node *np, + struct clk_hw_onecell_data *clk_data, + struct mtmips_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + struct mtmips_clk *sclk; + int ret, i; + + for (i = 0; i < priv->data->num_clk_base; i++) { + sclk = &priv->data->clk_base[i]; + sclk->priv = priv; + ret = of_clk_hw_register(np, &sclk->hw); + if (ret) { + pr_err("Couldn't register top clock %i\n", i); + goto err_clk_unreg; + } + + hws[i] = &sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + sclk = &priv->data->clk_base[i]; + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +static const struct mtmips_clk_data rt2880_clk_data = { + .clk_base = rt2880_clks_base, + .num_clk_base = ARRAY_SIZE(rt2880_clks_base), + .clk_fixed = rt305x_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), + .clk_factor = rt2880_factor_clocks, + .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks), + .clk_periph = rt2880_pherip_clks, + .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks), +}; + +static const struct mtmips_clk_data rt305x_clk_data = { + .clk_base = rt305x_clks_base, + .num_clk_base = ARRAY_SIZE(rt305x_clks_base), + .clk_fixed = rt305x_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), + .clk_factor = rt305x_factor_clocks, + .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), + .clk_periph = rt305x_pherip_clks, + .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks), +}; + +static const struct mtmips_clk_data rt3352_clk_data = { + .clk_base = rt3352_clks_base, + .num_clk_base = ARRAY_SIZE(rt3352_clks_base), + .clk_fixed = rt3352_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), + .clk_factor = rt305x_factor_clocks, + .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), + .clk_periph = rt5350_pherip_clks, + .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), +}; + +static const struct mtmips_clk_data rt3883_clk_data = { + .clk_base = rt3883_clks_base, + .num_clk_base = ARRAY_SIZE(rt3883_clks_base), + .clk_fixed = rt305x_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), + .clk_factor = NULL, + .num_clk_factor = 0, + .clk_periph = rt5350_pherip_clks, + .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), +}; + +static const struct mtmips_clk_data rt5350_clk_data = { + .clk_base = rt5350_clks_base, + .num_clk_base = ARRAY_SIZE(rt5350_clks_base), + .clk_fixed = rt3352_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), + .clk_factor = NULL, + .num_clk_factor = 0, + .clk_periph = rt5350_pherip_clks, + .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), +}; + +static const struct mtmips_clk_data mt7620_clk_data = { + .clk_base = mt7620_clks_base, + .num_clk_base = ARRAY_SIZE(mt7620_clks_base), + .clk_fixed = NULL, + .num_clk_fixed = 0, + .clk_factor = NULL, + .num_clk_factor = 0, + .clk_periph = mt7620_pherip_clks, + .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks), +}; + +static const struct mtmips_clk_data mt76x8_clk_data = { + .clk_base = mt76x8_clks_base, + .num_clk_base = ARRAY_SIZE(mt76x8_clks_base), + .clk_fixed = mt76x8_fixed_clocks, + .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks), + .clk_factor = rt305x_factor_clocks, + .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), + .clk_periph = mt76x8_pherip_clks, + .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks), +}; + +static const struct of_device_id mtmips_of_match[] = { + { + .compatible = "ralink,rt2880-sysc", + .data = &rt2880_clk_data, + }, + { + .compatible = "ralink,rt3050-sysc", + .data = &rt305x_clk_data, + }, + { + .compatible = "ralink,rt3052-sysc", + .data = &rt305x_clk_data, + }, + { + .compatible = "ralink,rt3352-sysc", + .data = &rt3352_clk_data, + }, + { + .compatible = "ralink,rt3883-sysc", + .data = &rt3883_clk_data, + }, + { + .compatible = "ralink,rt5350-sysc", + .data = &rt5350_clk_data, + }, + { + .compatible = "ralink,mt7620-sysc", + .data = &mt7620_clk_data, + }, + { + .compatible = "ralink,mt7628-sysc", + .data = &mt76x8_clk_data, + }, + { + .compatible = "ralink,mt7688-sysc", + .data = &mt76x8_clk_data, + }, + {} +}; + +static void __init mtmips_clk_regs_init(struct device_node *node, + struct mtmips_clk_priv *priv) +{ + u32 t; + + if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) + return; + + /* + * When the CPU goes into sleep mode, the BUS + * clock will be too low for USB to function properly. + * Adjust the busses fractional divider to fix this + */ + regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); + t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); + t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; + regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); +} + +static void __init mtmips_clk_init(struct device_node *node) +{ + const struct of_device_id *match; + const struct mtmips_clk_data *data; + struct mtmips_clk_priv *priv; + struct clk_hw_onecell_data *clk_data; + int ret, i, count; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return; + + priv->sysc = syscon_node_to_regmap(node); + if (IS_ERR(priv->sysc)) { + pr_err("Could not get sysc syscon regmap\n"); + goto free_clk_priv; + } + + mtmips_clk_regs_init(node, priv); + + match = of_match_node(mtmips_of_match, node); + if (WARN_ON(!match)) + return; + + data = match->data; + priv->data = data; + count = priv->data->num_clk_base + priv->data->num_clk_fixed + + priv->data->num_clk_factor + priv->data->num_clk_periph; + clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); + if (!clk_data) + goto free_clk_priv; + + ret = mtmips_register_clocks(node, clk_data, priv); + if (ret) { + pr_err("Couldn't register top clocks\n"); + goto free_clk_data; + } + + ret = mtmips_register_fixed_clocks(clk_data, priv); + if (ret) { + pr_err("Couldn't register fixed clocks\n"); + goto unreg_clk_top; + } + + ret = mtmips_register_factor_clocks(clk_data, priv); + if (ret) { + pr_err("Couldn't register factor clocks\n"); + goto unreg_clk_fixed; + } + + ret = mtmips_register_pherip_clocks(node, clk_data, priv); + if (ret) { + pr_err("Couldn't register peripheral clocks\n"); + goto unreg_clk_factor; + } + + clk_data->num = count; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) { + pr_err("Couldn't add clk hw provider\n"); + goto unreg_clk_periph; + } + + return; + +unreg_clk_periph: + for (i = 0; i < priv->data->num_clk_periph; i++) { + struct mtmips_clk *sclk = &priv->data->clk_periph[i]; + + clk_hw_unregister(&sclk->hw); + } + +unreg_clk_factor: + for (i = 0; i < priv->data->num_clk_factor; i++) { + struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; + + clk_hw_unregister_fixed_factor(sclk->hw); + } + +unreg_clk_fixed: + for (i = 0; i < priv->data->num_clk_fixed; i++) { + struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; + + clk_hw_unregister_fixed_rate(sclk->hw); + } + +unreg_clk_top: + for (i = 0; i < priv->data->num_clk_base; i++) { + struct mtmips_clk *sclk = &priv->data->clk_base[i]; + + clk_hw_unregister(&sclk->hw); + } + +free_clk_data: + kfree(clk_data); + +free_clk_priv: + kfree(priv); +} +CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); +CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); + +struct mtmips_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mtmips_rst, rcdev); +} + +static int mtmips_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mtmips_rst *data = to_mtmips_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mtmips_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mtmips_rst *data = to_mtmips_rst(rcdev); + struct regmap *sysc = data->sysc; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mtmips_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mtmips_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mtmips_deassert_device(rcdev, id); +} + +static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned long id = reset_spec->args[0]; + + if (id == 0 || id >= rcdev->nr_resets) + return -EINVAL; + + return id; +} + +static const struct reset_control_ops reset_ops = { + .reset = mtmips_reset_device, + .assert = mtmips_assert_device, + .deassert = mtmips_deassert_device +}; + +static int mtmips_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mtmips_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_xlate = mtmips_rst_xlate; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + +static int mtmips_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct mtmips_clk_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->sysc = syscon_node_to_regmap(np); + if (IS_ERR(priv->sysc)) + return dev_err_probe(dev, PTR_ERR(priv->sysc), + "Could not get sysc syscon regmap\n"); + + ret = mtmips_reset_init(dev, priv->sysc); + if (ret) + return dev_err_probe(dev, ret, "Could not init reset controller\n"); + + return 0; +} + +static const struct of_device_id mtmips_clk_of_match[] = { + { .compatible = "ralink,rt2880-reset" }, + { .compatible = "ralink,rt2880-sysc" }, + { .compatible = "ralink,rt3050-sysc" }, + { .compatible = "ralink,rt3052-sysc" }, + { .compatible = "ralink,rt3352-sysc" }, + { .compatible = "ralink,rt3883-sysc" }, + { .compatible = "ralink,rt5350-sysc" }, + { .compatible = "ralink,mt7620-sysc" }, + { .compatible = "ralink,mt7628-sysc" }, + { .compatible = "ralink,mt7688-sysc" }, + {} +}; + +static struct platform_driver mtmips_clk_driver = { + .probe = mtmips_clk_probe, + .driver = { + .name = "mtmips-clk", + .of_match_table = mtmips_clk_of_match, + }, +}; + +static int __init mtmips_clk_reset_init(void) +{ + return platform_driver_register(&mtmips_clk_driver); +} +arch_initcall(mtmips_clk_reset_init); diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a577586b23be..a88b6fe5db50 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -29,20 +29,7 @@ #include #include -#define MSM_ID_SMEM 137 - -enum _msm_id { - MSM8996V3 = 0xF6ul, - APQ8096V3 = 0x123ul, - MSM8996SG = 0x131ul, - APQ8096SG = 0x138ul, -}; - -enum _msm8996_version { - MSM8996_V3, - MSM8996_SG, - NUM_OF_MSM8996_VERSIONS, -}; +#include struct qcom_cpufreq_drv; @@ -140,60 +127,32 @@ static void get_krait_bin_format_b(struct device *cpu_dev, dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } -static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -{ - size_t len; - u32 *msm_id; - enum _msm8996_version version; - - msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); - if (IS_ERR(msm_id)) - return NUM_OF_MSM8996_VERSIONS; - - /* The first 4 bytes are format, next to them is the actual msm-id */ - msm_id++; - - switch ((enum _msm_id)*msm_id) { - case MSM8996V3: - case APQ8096V3: - version = MSM8996_V3; - break; - case MSM8996SG: - case APQ8096SG: - version = MSM8996_SG; - break; - default: - version = NUM_OF_MSM8996_VERSIONS; - } - - return version; -} - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, struct qcom_cpufreq_drv *drv) { size_t len; + u32 msm_id; u8 *speedbin; - enum _msm8996_version msm8996_version; + int ret; *pvs_name = NULL; - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); - return -ENODEV; - } + ret = qcom_smem_get_soc_id(&msm_id); + if (ret) + return ret; speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - switch (msm8996_version) { - case MSM8996_V3: + switch (msm_id) { + case QCOM_ID_MSM8996: + case QCOM_ID_APQ8096: drv->versions = 1 << (unsigned int)(*speedbin); break; - case MSM8996_SG: + case QCOM_ID_MSM8996SG: + case QCOM_ID_APQ8096SG: drv->versions = 1 << ((unsigned int)(*speedbin) + 4); break; default: diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c index 5c8d35edaa1c..9156bbe038b7 100644 --- a/drivers/crypto/caam/caamalg_qi2.c +++ b/drivers/crypto/caam/caamalg_qi2.c @@ -5402,7 +5402,7 @@ err_dma_mask: return err; } -static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) +static void __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) { struct device *dev; struct dpaa2_caam_priv *priv; @@ -5443,8 +5443,6 @@ static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) free_percpu(priv->ppriv); fsl_mc_portal_free(priv->mc_io); kmem_cache_destroy(qi_cache); - - return 0; } int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req) diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c index 8dd40d00a672..a42a37634881 100644 --- a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c @@ -765,7 +765,7 @@ err_mcportal: return err; } -static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) +static void dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) { struct dpaa2_qdma_engine *dpaa2_qdma; struct dpaa2_qdma_priv *priv; @@ -787,8 +787,6 @@ static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) dma_async_device_unregister(&dpaa2_qdma->dma_dev); kfree(priv); kfree(dpaa2_qdma); - - return 0; } static void dpaa2_qdma_shutdown(struct fsl_mc_device *ls_dev) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index e7d97b59963b..b5957cc12fee 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -2914,6 +2914,7 @@ static const struct of_device_id scmi_of_match[] = { #endif #ifdef CONFIG_ARM_SCMI_TRANSPORT_SMC { .compatible = "arm,scmi-smc", .data = &scmi_smc_desc}, + { .compatible = "arm,scmi-smc-param", .data = &scmi_smc_desc}, #endif #ifdef CONFIG_ARM_SCMI_TRANSPORT_VIRTIO { .compatible = "arm,scmi-virtio", .data = &scmi_virtio_desc}, diff --git a/drivers/firmware/arm_scmi/powercap.c b/drivers/firmware/arm_scmi/powercap.c index 83b90bde755c..244929cb4f3e 100644 --- a/drivers/firmware/arm_scmi/powercap.c +++ b/drivers/firmware/arm_scmi/powercap.c @@ -108,6 +108,8 @@ struct scmi_powercap_meas_changed_notify_payld { }; struct scmi_powercap_state { + bool enabled; + u32 last_pcap; bool meas_notif_enabled; u64 thresholds; #define THRESH_LOW(p, id) \ @@ -313,24 +315,33 @@ static int scmi_powercap_xfer_cap_get(const struct scmi_protocol_handle *ph, return ret; } -static int scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, - u32 domain_id, u32 *power_cap) +static int __scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, + const struct scmi_powercap_info *dom, + u32 *power_cap) { - struct scmi_powercap_info *dom; - struct powercap_info *pi = ph->get_priv(ph); - - if (!power_cap || domain_id >= pi->num_domains) - return -EINVAL; - - dom = pi->powercaps + domain_id; if (dom->fc_info && dom->fc_info[POWERCAP_FC_CAP].get_addr) { *power_cap = ioread32(dom->fc_info[POWERCAP_FC_CAP].get_addr); trace_scmi_fc_call(SCMI_PROTOCOL_POWERCAP, POWERCAP_CAP_GET, - domain_id, *power_cap, 0); + dom->id, *power_cap, 0); return 0; } - return scmi_powercap_xfer_cap_get(ph, domain_id, power_cap); + return scmi_powercap_xfer_cap_get(ph, dom->id, power_cap); +} + +static int scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, + u32 domain_id, u32 *power_cap) +{ + const struct scmi_powercap_info *dom; + + if (!power_cap) + return -EINVAL; + + dom = scmi_powercap_dom_info_get(ph, domain_id); + if (!dom) + return -EINVAL; + + return __scmi_powercap_cap_get(ph, dom, power_cap); } static int scmi_powercap_xfer_cap_set(const struct scmi_protocol_handle *ph, @@ -375,17 +386,20 @@ static int scmi_powercap_xfer_cap_set(const struct scmi_protocol_handle *ph, return ret; } -static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, - u32 domain_id, u32 power_cap, - bool ignore_dresp) +static int __scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, + struct powercap_info *pi, u32 domain_id, + u32 power_cap, bool ignore_dresp) { + int ret = -EINVAL; const struct scmi_powercap_info *pc; pc = scmi_powercap_dom_info_get(ph, domain_id); - if (!pc || !pc->powercap_cap_config || !power_cap || - power_cap < pc->min_power_cap || - power_cap > pc->max_power_cap) - return -EINVAL; + if (!pc || !pc->powercap_cap_config) + return ret; + + if (power_cap && + (power_cap < pc->min_power_cap || power_cap > pc->max_power_cap)) + return ret; if (pc->fc_info && pc->fc_info[POWERCAP_FC_CAP].set_addr) { struct scmi_fc_info *fci = &pc->fc_info[POWERCAP_FC_CAP]; @@ -394,10 +408,41 @@ static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, ph->hops->fastchannel_db_ring(fci->set_db); trace_scmi_fc_call(SCMI_PROTOCOL_POWERCAP, POWERCAP_CAP_SET, domain_id, power_cap, 0); + ret = 0; + } else { + ret = scmi_powercap_xfer_cap_set(ph, pc, power_cap, + ignore_dresp); + } + + /* Save the last explicitly set non-zero powercap value */ + if (PROTOCOL_REV_MAJOR(pi->version) >= 0x2 && !ret && power_cap) + pi->states[domain_id].last_pcap = power_cap; + + return ret; +} + +static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, + u32 domain_id, u32 power_cap, + bool ignore_dresp) +{ + struct powercap_info *pi = ph->get_priv(ph); + + /* + * Disallow zero as a possible explicitly requested powercap: + * there are enable/disable operations for this. + */ + if (!power_cap) + return -EINVAL; + + /* Just log the last set request if acting on a disabled domain */ + if (PROTOCOL_REV_MAJOR(pi->version) >= 0x2 && + !pi->states[domain_id].enabled) { + pi->states[domain_id].last_pcap = power_cap; return 0; } - return scmi_powercap_xfer_cap_set(ph, pc, power_cap, ignore_dresp); + return __scmi_powercap_cap_set(ph, pi, domain_id, + power_cap, ignore_dresp); } static int scmi_powercap_xfer_pai_get(const struct scmi_protocol_handle *ph, @@ -564,11 +609,78 @@ scmi_powercap_measurements_threshold_set(const struct scmi_protocol_handle *ph, return ret; } +static int scmi_powercap_cap_enable_set(const struct scmi_protocol_handle *ph, + u32 domain_id, bool enable) +{ + int ret; + u32 power_cap; + struct powercap_info *pi = ph->get_priv(ph); + + if (PROTOCOL_REV_MAJOR(pi->version) < 0x2) + return -EINVAL; + + if (enable == pi->states[domain_id].enabled) + return 0; + + if (enable) { + /* Cannot enable with a zero powercap. */ + if (!pi->states[domain_id].last_pcap) + return -EINVAL; + + ret = __scmi_powercap_cap_set(ph, pi, domain_id, + pi->states[domain_id].last_pcap, + true); + } else { + ret = __scmi_powercap_cap_set(ph, pi, domain_id, 0, true); + } + + if (ret) + return ret; + + /* + * Update our internal state to reflect final platform state: the SCMI + * server could have ignored a disable request and kept enforcing some + * powercap limit requested by other agents. + */ + ret = scmi_powercap_cap_get(ph, domain_id, &power_cap); + if (!ret) + pi->states[domain_id].enabled = !!power_cap; + + return ret; +} + +static int scmi_powercap_cap_enable_get(const struct scmi_protocol_handle *ph, + u32 domain_id, bool *enable) +{ + int ret; + u32 power_cap; + struct powercap_info *pi = ph->get_priv(ph); + + *enable = true; + if (PROTOCOL_REV_MAJOR(pi->version) < 0x2) + return 0; + + /* + * Report always real platform state; platform could have ignored + * a previous disable request. Default true on any error. + */ + ret = scmi_powercap_cap_get(ph, domain_id, &power_cap); + if (!ret) + *enable = !!power_cap; + + /* Update internal state with current real platform state */ + pi->states[domain_id].enabled = *enable; + + return 0; +} + static const struct scmi_powercap_proto_ops powercap_proto_ops = { .num_domains_get = scmi_powercap_num_domains_get, .info_get = scmi_powercap_dom_info_get, .cap_get = scmi_powercap_cap_get, .cap_set = scmi_powercap_cap_set, + .cap_enable_set = scmi_powercap_cap_enable_set, + .cap_enable_get = scmi_powercap_cap_enable_get, .pai_get = scmi_powercap_pai_get, .pai_set = scmi_powercap_pai_set, .measurements_get = scmi_powercap_measurements_get, @@ -829,6 +941,11 @@ scmi_powercap_protocol_init(const struct scmi_protocol_handle *ph) if (!pinfo->powercaps) return -ENOMEM; + pinfo->states = devm_kcalloc(ph->dev, pinfo->num_domains, + sizeof(*pinfo->states), GFP_KERNEL); + if (!pinfo->states) + return -ENOMEM; + /* * Note that any failure in retrieving any domain attribute leads to * the whole Powercap protocol initialization failure: this way the @@ -843,15 +960,21 @@ scmi_powercap_protocol_init(const struct scmi_protocol_handle *ph) if (pinfo->powercaps[domain].fastchannels) scmi_powercap_domain_init_fc(ph, domain, &pinfo->powercaps[domain].fc_info); + + /* Grab initial state when disable is supported. */ + if (PROTOCOL_REV_MAJOR(version) >= 0x2) { + ret = __scmi_powercap_cap_get(ph, + &pinfo->powercaps[domain], + &pinfo->states[domain].last_pcap); + if (ret) + return ret; + + pinfo->states[domain].enabled = + !!pinfo->states[domain].last_pcap; + } } - pinfo->states = devm_kcalloc(ph->dev, pinfo->num_domains, - sizeof(*pinfo->states), GFP_KERNEL); - if (!pinfo->states) - return -ENOMEM; - pinfo->version = version; - return ph->set_priv(ph, pinfo); } diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c index 93272e4bbd12..621c37efe3ec 100644 --- a/drivers/firmware/arm_scmi/smc.c +++ b/drivers/firmware/arm_scmi/smc.c @@ -20,6 +20,23 @@ #include "common.h" +/* + * The shmem address is split into 4K page and offset. + * This is to make sure the parameters fit in 32bit arguments of the + * smc/hvc call to keep it uniform across smc32/smc64 conventions. + * This however limits the shmem address to 44 bit. + * + * These optional parameters can be used to distinguish among multiple + * scmi instances that are using the same smc-id. + * The page parameter is passed in r1/x1/w1 register and the offset parameter + * is passed in r2/x2/w2 register. + */ + +#define SHMEM_SIZE (SZ_4K) +#define SHMEM_SHIFT 12 +#define SHMEM_PAGE(x) (_UL((x) >> SHMEM_SHIFT)) +#define SHMEM_OFFSET(x) ((x) & (SHMEM_SIZE - 1)) + /** * struct scmi_smc - Structure representing a SCMI smc transport * @@ -30,6 +47,8 @@ * @inflight: Atomic flag to protect access to Tx/Rx shared memory area. * Used when operating in atomic mode. * @func_id: smc/hvc call function id + * @param_page: 4K page number of the shmem channel + * @param_offset: Offset within the 4K page of the shmem channel */ struct scmi_smc { @@ -40,6 +59,8 @@ struct scmi_smc { #define INFLIGHT_NONE MSG_TOKEN_MAX atomic_t inflight; u32 func_id; + u32 param_page; + u32 param_offset; }; static irqreturn_t smc_msg_done_isr(int irq, void *data) @@ -137,6 +158,10 @@ static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, if (ret < 0) return ret; + if (of_device_is_compatible(dev->of_node, "arm,scmi-smc-param")) { + scmi_info->param_page = SHMEM_PAGE(res.start); + scmi_info->param_offset = SHMEM_OFFSET(res.start); + } /* * If there is an interrupt named "a2p", then the service and * completion of a message is signaled by an interrupt rather than by @@ -179,6 +204,8 @@ static int smc_send_message(struct scmi_chan_info *cinfo, { struct scmi_smc *scmi_info = cinfo->transport_info; struct arm_smccc_res res; + unsigned long page = scmi_info->param_page; + unsigned long offset = scmi_info->param_offset; /* * Channel will be released only once response has been @@ -188,7 +215,8 @@ static int smc_send_message(struct scmi_chan_info *cinfo, shmem_tx_prepare(scmi_info->shmem, xfer, cinfo); - arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_1_1_invoke(scmi_info->func_id, page, offset, 0, 0, 0, 0, 0, + &res); /* Only SMCCC_RET_NOT_SUPPORTED is valid error code */ if (res.a0) { diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegra/bpmp-tegra186.c index 2e26199041cd..6f0d0511b486 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include @@ -18,7 +20,10 @@ struct tegra186_bpmp { struct { struct gen_pool *pool; - void __iomem *virt; + union { + void __iomem *sram; + void *dram; + }; dma_addr_t phys; } tx, rx; @@ -118,8 +123,13 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp_channel *channel, queue_size = tegra_ivc_total_queue_size(message_size); offset = queue_size * index; - iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); - iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + if (priv->rx.pool) { + iosys_map_set_vaddr_iomem(&rx, priv->rx.sram + offset); + iosys_map_set_vaddr_iomem(&tx, priv->tx.sram + offset); + } else { + iosys_map_set_vaddr(&rx, priv->rx.dram + offset); + iosys_map_set_vaddr(&tx, priv->tx.dram + offset); + } err = tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &tx, priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, @@ -158,18 +168,72 @@ static void mbox_handle_rx(struct mbox_client *client, void *data) tegra_bpmp_handle_rx(bpmp); } -static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +static void tegra186_bpmp_teardown_channels(struct tegra_bpmp *bpmp) { - struct tegra186_bpmp *priv; + struct tegra186_bpmp *priv = bpmp->priv; unsigned int i; + + for (i = 0; i < bpmp->threaded.count; i++) { + if (!bpmp->threaded_channels[i].bpmp) + continue; + + tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); + } + + tegra186_bpmp_channel_cleanup(bpmp->rx_channel); + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + + if (priv->tx.pool) { + gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096); + gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.sram, 4096); + } +} + +static int tegra186_bpmp_dram_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv = bpmp->priv; + struct device_node *np; + struct resource res; + size_t size; int err; - priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + np = of_parse_phandle(bpmp->dev->of_node, "memory-region", 0); + if (!np) + return -ENODEV; - bpmp->priv = priv; - priv->parent = bpmp; + err = of_address_to_resource(np, 0, &res); + if (err < 0) { + dev_warn(bpmp->dev, "failed to parse memory region: %d\n", err); + return err; + } + + size = resource_size(&res); + + if (size < SZ_8K) { + dev_warn(bpmp->dev, "DRAM region must be larger than 8 KiB\n"); + return -EINVAL; + } + + priv->tx.phys = res.start; + priv->rx.phys = res.start + SZ_4K; + + priv->tx.dram = devm_memremap(bpmp->dev, priv->tx.phys, size, + MEMREMAP_WC); + if (IS_ERR(priv->tx.dram)) { + err = PTR_ERR(priv->tx.dram); + dev_warn(bpmp->dev, "failed to map DRAM region: %d\n", err); + return err; + } + + priv->rx.dram = priv->tx.dram + SZ_4K; + + return 0; +} + +static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv = bpmp->priv; + int err; priv->tx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); if (!priv->tx.pool) { @@ -177,8 +241,9 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) return -EPROBE_DEFER; } - priv->tx.virt = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys); - if (!priv->tx.virt) { + priv->tx.sram = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, + &priv->tx.phys); + if (!priv->tx.sram) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; } @@ -190,22 +255,45 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) goto free_tx; } - priv->rx.virt = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, &priv->rx.phys); - if (!priv->rx.virt) { + priv->rx.sram = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, + &priv->rx.phys); + if (!priv->rx.sram) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err = -ENOMEM; goto free_tx; } + return 0; + +free_tx: + gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096); + + return err; +} + +static int tegra186_bpmp_setup_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + int err; + + err = tegra186_bpmp_dram_init(bpmp); + if (err == -ENODEV) { + err = tegra186_bpmp_sram_init(bpmp); + if (err < 0) + return err; + } + err = tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, bpmp->soc->channels.cpu_tx.offset); if (err < 0) - goto free_rx; + return err; err = tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, bpmp->soc->channels.cpu_rx.offset); - if (err < 0) - goto cleanup_tx_channel; + if (err < 0) { + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + return err; + } for (i = 0; i < bpmp->threaded.count; i++) { unsigned int index = bpmp->soc->channels.thread.offset + i; @@ -213,9 +301,43 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) err = tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], bpmp, index); if (err < 0) - goto cleanup_channels; + break; } + if (err < 0) + tegra186_bpmp_teardown_channels(bpmp); + + return err; +} + +static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + + /* reset message channels */ + tegra186_bpmp_channel_reset(bpmp->tx_channel); + tegra186_bpmp_channel_reset(bpmp->rx_channel); + + for (i = 0; i < bpmp->threaded.count; i++) + tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); +} + +static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv; + int err; + + priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->parent = bpmp; + bpmp->priv = priv; + + err = tegra186_bpmp_setup_channels(bpmp); + if (err < 0) + return err; + /* mbox registration */ priv->mbox.client.dev = bpmp->dev; priv->mbox.client.rx_callback = mbox_handle_rx; @@ -226,63 +348,27 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) if (IS_ERR(priv->mbox.channel)) { err = PTR_ERR(priv->mbox.channel); dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err); - goto cleanup_channels; + tegra186_bpmp_teardown_channels(bpmp); + return err; } - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); return 0; - -cleanup_channels: - for (i = 0; i < bpmp->threaded.count; i++) { - if (!bpmp->threaded_channels[i].bpmp) - continue; - - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - } - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); -cleanup_tx_channel: - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); -free_rx: - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); -free_tx: - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); - - return err; } static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp) { struct tegra186_bpmp *priv = bpmp->priv; - unsigned int i; mbox_free_channel(priv->mbox.channel); - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); - - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); + tegra186_bpmp_teardown_channels(bpmp); } static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) { - unsigned int i; - - /* reset message channels */ - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); return 0; } diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 8b5e5daa9fae..17bd3590aaa2 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pdev) if (!bpmp->threaded_channels) return -ENOMEM; + platform_set_drvdata(pdev, bpmp); + err = bpmp->soc->ops->init(bpmp); if (err < 0) return err; @@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pdev) dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag); - platform_set_drvdata(pdev, bpmp); - err = of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev); if (err < 0) goto free_mrq; diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index a736db4a5825..9e585b5646df 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -942,8 +942,16 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_reset_get_status); */ int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { - return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), - upper_32_bits(address), size, flags, NULL); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), + upper_32_bits(address), size, flags, + ret_payload); + if (ret_payload[0]) + return -ret_payload[0]; + + return ret; } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_load); diff --git a/drivers/hwmon/max1111.c b/drivers/hwmon/max1111.c index 4c5487aeb3cf..5cc08c720b52 100644 --- a/drivers/hwmon/max1111.c +++ b/drivers/hwmon/max1111.c @@ -80,6 +80,7 @@ static int max1111_read(struct device *dev, int channel) #ifdef CONFIG_SHARPSL_PM static struct max1111_data *the_max1111; +int max1111_read_channel(int channel); int max1111_read_channel(int channel) { if (!the_max1111 || !the_max1111->spi) diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index 40eb27f1b23f..faea40dd66d0 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -1117,20 +1117,13 @@ MODULE_DEVICE_TABLE(of, ads7846_dt_ids); static const struct ads7846_platform_data *ads7846_get_props(struct device *dev) { struct ads7846_platform_data *pdata; - const struct platform_device_id *pdev_id; u32 value; - pdev_id = device_get_match_data(dev); - if (!pdev_id) { - dev_err(dev, "Unknown device model\n"); - return ERR_PTR(-EINVAL); - } - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return ERR_PTR(-ENOMEM); - pdata->model = (unsigned long)pdev_id->driver_data; + pdata->model = (uintptr_t)device_get_match_data(dev); device_property_read_u16(dev, "ti,vref-delay-usecs", &pdata->vref_delay_usecs); diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 91774e6ee624..8efdd1f97139 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -30,17 +30,6 @@ config ARM_PL172_MPMC If you have an embedded system with an AMBA bus and a PL172 controller, say Y or M here. -config ATMEL_SDRAMC - bool "Atmel (Multi-port DDR-)SDRAM Controller" - default y if ARCH_AT91 - depends on ARCH_AT91 || COMPILE_TEST - depends on OF - help - This driver is for Atmel SDRAM Controller or Atmel Multi-port - DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. - Starting with the at91sam9g45, this controller supports SDR, DDR and - LP-DDR memories. - config ATMEL_EBI bool "Atmel EBI driver" default y if ARCH_AT91 diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index ae14ded464a8..d2e6ca9abbe0 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -8,7 +8,6 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o -obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o obj-$(CONFIG_BRCMSTB_DPFE) += brcmstb_dpfe.o obj-$(CONFIG_BRCMSTB_MEMC) += brcmstb_memc.o diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c deleted file mode 100644 index ea6e9e1eaf04..000000000000 --- a/drivers/memory/atmel-sdramc.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Atmel (Multi-port DDR-)SDRAM Controller driver - * - * Author: Alexandre Belloni - * - * Copyright (C) 2014 Atmel - */ - -#include -#include -#include -#include -#include -#include - -struct at91_ramc_caps { - bool has_ddrck; - bool has_mpddr_clk; -}; - -static const struct at91_ramc_caps at91rm9200_caps = { }; - -static const struct at91_ramc_caps at91sam9g45_caps = { - .has_ddrck = 1, - .has_mpddr_clk = 0, -}; - -static const struct at91_ramc_caps sama5d3_caps = { - .has_ddrck = 1, - .has_mpddr_clk = 1, -}; - -static const struct of_device_id atmel_ramc_of_match[] = { - { .compatible = "atmel,at91rm9200-sdramc", .data = &at91rm9200_caps, }, - { .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, }, - { .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, }, - { .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, }, - {}, -}; - -static int atmel_ramc_probe(struct platform_device *pdev) -{ - const struct at91_ramc_caps *caps; - struct clk *clk; - - caps = of_device_get_match_data(&pdev->dev); - - if (caps->has_ddrck) { - clk = devm_clk_get_enabled(&pdev->dev, "ddrck"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - } - - if (caps->has_mpddr_clk) { - clk = devm_clk_get_enabled(&pdev->dev, "mpddr"); - if (IS_ERR(clk)) { - pr_err("AT91 RAMC: couldn't get mpddr clock\n"); - return PTR_ERR(clk); - } - } - - return 0; -} - -static struct platform_driver atmel_ramc_driver = { - .probe = atmel_ramc_probe, - .driver = { - .name = "atmel-ramc", - .of_match_table = atmel_ramc_of_match, - }, -}; - -builtin_platform_driver(atmel_ramc_driver); diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c index 76c82e9c8fce..9339f80b21c5 100644 --- a/drivers/memory/brcmstb_dpfe.c +++ b/drivers/memory/brcmstb_dpfe.c @@ -434,15 +434,17 @@ static void __finalize_command(struct brcmstb_dpfe_priv *priv) static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd, u32 result[]) { - const u32 *msg = priv->dpfe_api->command[cmd]; void __iomem *regs = priv->regs; unsigned int i, chksum, chksum_idx; + const u32 *msg; int ret = 0; u32 resp; if (cmd >= DPFE_CMD_MAX) return -1; + msg = priv->dpfe_api->command[cmd]; + mutex_lock(&priv->lock); /* Wait for DCPU to become ready */ diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 025bb628aaf3..75fcba45ec1b 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -7,6 +7,7 @@ * Copyright (C) 2019-2020 Cogent Embedded, Inc. */ +#include #include #include #include @@ -163,6 +164,11 @@ static const struct regmap_access_table rpcif_volatile_table = { .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), }; +struct rpcif_info { + enum rpcif_type type; + u8 strtim; +}; + struct rpcif_priv { struct device *dev; void __iomem *base; @@ -171,7 +177,7 @@ struct rpcif_priv { struct reset_control *rstc; struct platform_device *vdev; size_t size; - enum rpcif_type type; + const struct rpcif_info *info; enum rpcif_data_dir dir; u8 bus_size; u8 xfer_size; @@ -186,6 +192,26 @@ struct rpcif_priv { u32 ddr; /* DRDRENR or SMDRENR */ }; +static const struct rpcif_info rpcif_info_r8a7796 = { + .type = RPCIF_RCAR_GEN3, + .strtim = 6, +}; + +static const struct rpcif_info rpcif_info_gen3 = { + .type = RPCIF_RCAR_GEN3, + .strtim = 7, +}; + +static const struct rpcif_info rpcif_info_rz_g2l = { + .type = RPCIF_RZ_G2L, + .strtim = 7, +}; + +static const struct rpcif_info rpcif_info_gen4 = { + .type = RPCIF_RCAR_GEN4, + .strtim = 15, +}; + /* * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with * proper width. Requires rpcif_priv.xfer_size to be correctly set before! @@ -310,7 +336,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) if (ret) return ret; - if (rpc->type == RPCIF_RZ_G2L) { + if (rpc->info->type == RPCIF_RZ_G2L) { ret = reset_control_reset(rpc->rstc); if (ret) return ret; @@ -324,12 +350,10 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) /* DMA Transfer is not supported */ regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); - if (rpc->type == RPCIF_RCAR_GEN3) - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, - RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); - else if (rpc->type == RPCIF_RCAR_GEN4) - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, - RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15)); + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, + /* create mask with all affected bits set */ + RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1), + RPCIF_PHYCNT_STRTIM(rpc->info->strtim)); regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), RPCIF_PHYOFFSET1_DDRTMG(3)); @@ -340,7 +364,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYINT, RPCIF_PHYINT_WPVAL, 0); - if (rpc->type == RPCIF_RZ_G2L) + if (rpc->info->type == RPCIF_RZ_G2L) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(3), @@ -729,9 +753,9 @@ static int rpcif_probe(struct platform_device *pdev) rpc->dirmap = devm_ioremap_resource(dev, res); if (IS_ERR(rpc->dirmap)) return PTR_ERR(rpc->dirmap); - rpc->size = resource_size(res); - rpc->type = (uintptr_t)of_device_get_match_data(dev); + rpc->size = resource_size(res); + rpc->info = of_device_get_match_data(dev); rpc->rstc = devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(rpc->rstc)) return PTR_ERR(rpc->rstc); @@ -764,9 +788,10 @@ static int rpcif_remove(struct platform_device *pdev) } static const struct of_device_id rpcif_of_match[] = { - { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, - { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 }, - { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, + { .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 }, + { .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 }, + { .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 }, + { .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l }, {}, }; MODULE_DEVICE_TABLE(of, rpcif_of_match); diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 9082b6c3763d..4a750da1c12a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -792,6 +793,8 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) mc->provider.data = &mc->provider; mc->provider.set = mc->soc->icc_ops->set; mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.get_bw = mc->soc->icc_ops->get_bw; + mc->provider.xlate = mc->soc->icc_ops->xlate; mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; icc_provider_init(&mc->provider); @@ -824,6 +827,8 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) err = icc_link_create(node, TEGRA_ICC_MC); if (err) goto remove_nodes; + + node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); } err = icc_provider_register(&mc->provider); @@ -838,6 +843,23 @@ remove_nodes: return err; } +static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) +{ + unsigned int i; + u32 value; + + value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE); + if (value <= 0) { + mc->num_channels = mc->soc->num_channels; + return; + } + + for (i = 0; i < 32; i++) { + if (value & BIT(i)) + mc->num_channels++; + } +} + static int tegra_mc_probe(struct platform_device *pdev) { struct tegra_mc *mc; @@ -876,6 +898,8 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } + tegra_mc_num_channel_enabled(mc); + if (mc->soc->ops && mc->soc->ops->handle_irq) { mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index bc01586b6560..c3f6655bec60 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -53,6 +53,7 @@ #define MC_ERR_ROUTE_SANITY_ADR 0x9c4 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 #define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 #define MC_GLOBAL_INTSTATUS 0xf24 #define MC_ERR_ADR_HI 0x11fc diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index e935ad4e95b6..6ad8a4023dd7 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -7,9 +7,11 @@ #include #include #include +#include #include #include +#include "mc.h" struct tegra186_emc_dvfs { unsigned long latency; @@ -29,8 +31,15 @@ struct tegra186_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + struct icc_provider provider; }; +static inline struct tegra186_emc *to_tegra186_emc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra186_emc, provider); +} + /* * debugfs interface * @@ -146,8 +155,102 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); +/* + * tegra_emc_icc_set_bw() - Set BW api for EMC provider + * @src: ICC node for External Memory Controller (EMC) + * @dst: ICC node for External Memory (DRAM) + * + * Do nothing here as info to BPMP-FW is now passed in the BW set function + * of the MC driver. BPMP-FW sets the final Freq based on the passed values. + */ +static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +static struct icc_node * +tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + return node; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg = 0; + *peak = 0; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra186_emc *emc) +{ + struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent); + const struct tegra_mc_soc *soc = mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = tegra_emc_icc_set_bw; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate = tegra_emc_of_icc_xlate; + emc->provider.get_bw = tegra_emc_icc_get_init_bw; + + icc_provider_init(&emc->provider); + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto err_msg; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + err = icc_provider_register(&emc->provider); + if (err) + goto remove_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + static int tegra186_emc_probe(struct platform_device *pdev) { + struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); struct mrq_emc_dvfs_latency_response response; struct tegra_bpmp_message msg; struct tegra186_emc *emc; @@ -236,6 +339,32 @@ static int tegra186_emc_probe(struct platform_device *pdev) debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, emc, &tegra186_emc_debug_max_rate_fops); + if (mc && mc->soc->icc_ops) { + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { + mc->bwmgr_mrq_supported = true; + + /* + * MC driver probe can't get BPMP reference as it gets probed + * earlier than BPMP. So, save the BPMP ref got from the EMC + * DT node in the mc->bpmp and use it in MC's icc_set hook. + */ + mc->bpmp = emc->bpmp; + barrier(); + } + + /* + * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'. + * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return + * EINVAL instead of passing the request to BPMP-FW later when the BW + * request is made by client with 'icc_set_bw()' call. + */ + err = tegra_emc_interconnect_init(emc); + if (err) { + mc->bpmp = NULL; + goto put_bpmp; + } + } + return 0; put_bpmp: @@ -245,9 +374,12 @@ put_bpmp: static int tegra186_emc_remove(struct platform_device *pdev) { + struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); struct tegra186_emc *emc = platform_get_drvdata(pdev); debugfs_remove_recursive(emc->debugfs.root); + + mc->bpmp = NULL; tegra_bpmp_put(emc->bpmp); return 0; @@ -272,6 +404,7 @@ static struct platform_driver tegra186_emc_driver = { .name = "tegra186-emc", .of_match_table = tegra186_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, .probe = tegra186_emc_probe, .remove = tegra186_emc_remove, diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 02dcc5748bba..8e873a7bc34f 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1,18 +1,47 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved. */ #include #include +#include +#include +#include #include "mc.h" static const struct tegra_mc_client tegra234_mc_clients[] = { { + .id = TEGRA234_MEMORY_CLIENT_HDAR, + .name = "hdar", + .bpmp_id = TEGRA_ICC_BPMP_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_HDA, + .regs = { + .sid = { + .override = 0xa8, + .security = 0xac, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_HDAW, + .name = "hdaw", + .bpmp_id = TEGRA_ICC_BPMP_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_HDA, + .regs = { + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, + }, + }, { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE, .regs = { .sid = { @@ -23,6 +52,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, .name = "mgbebrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF1, .regs = { .sid = { @@ -33,6 +64,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBECRD, .name = "mgbecrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF2, .regs = { .sid = { @@ -43,6 +76,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, .name = "mgbedrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF3, .regs = { .sid = { @@ -52,6 +87,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, }, { .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .name = "mgbeawr", .sid = TEGRA234_SID_MGBE, .regs = { @@ -63,6 +100,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, .name = "mgbebwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF1, .regs = { .sid = { @@ -73,6 +112,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBECWR, .name = "mgbecwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF2, .regs = { .sid = { @@ -83,6 +124,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", + .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_SDMMC4, .regs = { .sid = { @@ -93,6 +136,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, .name = "mgbedwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF3, .regs = { .sid = { @@ -103,6 +148,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", + .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_SDMMC4, .regs = { .sid = { @@ -110,6 +157,90 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2W, + .name = "vi2w", + .bpmp_id = TEGRA_ICC_BPMP_VI2, + .type = TEGRA_ICC_ISO_VI, + .sid = TEGRA234_SID_ISO_VI2, + .regs = { + .sid = { + .override = 0x380, + .security = 0x384, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALR, + .name = "vi2falr", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x388, + .security = 0x38c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALW, + .name = "vi2falw", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x3e0, + .security = 0x3e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_APER, + .name = "aper", + .bpmp_id = TEGRA_ICC_BPMP_APE, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_APE, + .regs = { + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_APEW, + .name = "apew", + .bpmp_id = TEGRA_ICC_BPMP_APE, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_APE, + .regs = { + .sid = { + .override = 0x3d8, + .security = 0x3dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name = "nvdisplayr", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x490, + .security = 0x494, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_BPMPR, .name = "bpmpr", @@ -153,6 +284,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_APEDMAR, .name = "apedmar", + .bpmp_id = TEGRA_ICC_BPMP_APEDMA, + .type = TEGRA_ICC_ISO_AUDIO, .sid = TEGRA234_SID_APE, .regs = { .sid = { @@ -163,6 +296,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_APEDMAW, .name = "apedmaw", + .bpmp_id = TEGRA_ICC_BPMP_APEDMA, + .type = TEGRA_ICC_ISO_AUDIO, .sid = TEGRA234_SID_APE, .regs = { .sid = { @@ -330,9 +465,466 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x37c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE0R, + .name = "pcie0r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c0, + .security = 0x6c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE0W, + .name = "pcie0w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c8, + .security = 0x6cc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE1R, + .name = "pcie1r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d0, + .security = 0x6d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE1W, + .name = "pcie1w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d8, + .security = 0x6dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE2AR, + .name = "pcie2ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_2, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e0, + .security = 0x6e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE2AW, + .name = "pcie2aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_2, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e8, + .security = 0x6ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE3R, + .name = "pcie3r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_3, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f0, + .security = 0x6f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE3W, + .name = "pcie3w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_3, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f8, + .security = 0x6fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE4R, + .name = "pcie4r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_4, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE4, + .regs = { + .sid = { + .override = 0x700, + .security = 0x704, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE4W, + .name = "pcie4w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_4, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE4, + .regs = { + .sid = { + .override = 0x708, + .security = 0x70c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5R, + .name = "pcie5r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x710, + .security = 0x714, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5W, + .name = "pcie5w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x718, + .security = 0x71c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, + .name = "pcie5r1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x778, + .security = 0x77c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name = "pcie6ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x140, + .security = 0x144, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name = "pcie6aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x148, + .security = 0x14c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name = "pcie6ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name = "pcie7ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x150, + .security = 0x154, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name = "pcie7aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x180, + .security = 0x184, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name = "pcie7ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x248, + .security = 0x24c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name = "pcie8ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x190, + .security = 0x194, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name = "pcie8aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x1d8, + .security = 0x1dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name = "pcie9ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1e0, + .security = 0x1e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name = "pcie9aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1f0, + .security = 0x1f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name = "pcie10ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x1f8, + .security = 0x1fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name = "pcie10aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x200, + .security = 0x204, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name = "pcie10ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x240, + .security = 0x244, + }, + }, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER0, + .name = "sw_cluster0", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER1, + .name = "sw_cluster1", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER2, + .name = "sw_cluster2", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2, + .type = TEGRA_ICC_NISO, }, }; +/* + * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW + * @src: ICC node for Memory Controller's (MC) Client + * @dst: ICC node for Memory Controller (MC) + * + * Passing the current request info from the MC to the BPMP-FW where + * LA and PTSA registers are accessed and the final EMC freq is set + * based on client_id, type, latency and bandwidth. + * icc_set_bw() makes set_bw calls for both MC and EMC providers in + * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'. + * So, the data passed won't be updated by concurrent set calls from + * other clients. + */ +static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); + struct mrq_bwmgr_int_request bwmgr_req = { 0 }; + struct mrq_bwmgr_int_response bwmgr_resp = { 0 }; + const struct tegra_mc_client *pclient = src->data; + struct tegra_bpmp_message msg; + int ret; + + /* + * Same Src and Dst node will happen during boot from icc_node_add(). + * This can be used to pre-initialize and set bandwidth for all clients + * before their drivers are loaded. We are skipping this case as for us, + * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. + */ + if (src->id == dst->id) + return 0; + + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + + if (!mc->bpmp) { + dev_err(mc->dev, "BPMP reference NULL\n"); + return -ENOENT; + } + + if (pclient->type == TEGRA_ICC_NISO) + bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; + else + bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; + + bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; + + bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET; + bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; + bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_BWMGR_INT; + msg.tx.data = &bwmgr_req; + msg.tx.size = sizeof(bwmgr_req); + msg.rx.data = &bwmgr_resp; + msg.rx.size = sizeof(bwmgr_resp); + + ret = tegra_bpmp_transfer(mc->bpmp, &msg); + if (ret < 0) { + dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); + goto error; + } + if (msg.rx.ret < 0) { + pr_err("failed to set bandwidth for %u: %d\n", + bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret); + ret = -EINVAL; + } + +error: + return ret; +} + +static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct icc_provider *p = node->provider; + struct tegra_mc *mc = icc_provider_to_tegra_mc(p); + + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + + if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { + if (mc) + peak_bw = peak_bw * mc->num_channels; + } + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node* +tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + unsigned int cl_id = spec->args[0]; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != cl_id) + continue; + + return node; + } + + /* + * If a client driver calls devm_of_icc_get() before the MC driver + * is probed, then return EPROBE_DEFER to the client driver. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg = 0; + *peak = 0; + + return 0; +} + +static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { + .xlate = tegra234_mc_of_icc_xlate, + .aggregate = tegra234_mc_icc_aggregate, + .get_bw = tegra234_mc_icc_get_init_bw, + .set = tegra234_mc_icc_set, +}; + const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, @@ -345,6 +937,7 @@ const struct tegra_mc_soc tegra234_mc_soc = { MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .icc_ops = &tegra234_mc_icc_ops, .ch_intmask = 0x0000ff00, .global_intstatus_channel_shift = 8, /* diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c index 99413310956b..5757adf418b1 100644 --- a/drivers/misc/sram.c +++ b/drivers/misc/sram.c @@ -235,10 +235,11 @@ static int sram_reserve_regions(struct sram_dev *sram, struct resource *res) goto err_chunks; } if (!label) - label = child->name; - - block->label = devm_kstrdup(sram->dev, - label, GFP_KERNEL); + block->label = devm_kasprintf(sram->dev, GFP_KERNEL, + "%s", dev_name(sram->dev)); + else + block->label = devm_kstrdup(sram->dev, + label, GFP_KERNEL); if (!block->label) { ret = -ENOMEM; goto err_chunks; diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c index a62cffaf6ff1..a9676d0dece8 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c @@ -5025,7 +5025,7 @@ err_wq_alloc: return err; } -static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) +static void dpaa2_eth_remove(struct fsl_mc_device *ls_dev) { struct device *dev; struct net_device *net_dev; @@ -5073,8 +5073,6 @@ static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name); free_netdev(net_dev); - - return 0; } static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = { diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c index 90d23ab1ce9d..4497e3c0456d 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c @@ -219,7 +219,7 @@ err_exit: return err; } -static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) +static void dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; struct ptp_qoriq *ptp_qoriq; @@ -232,8 +232,6 @@ static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) fsl_mc_free_irqs(mc_dev); dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); fsl_mc_portal_free(mc_dev->mc_io); - - return 0; } static const struct fsl_mc_device_id dpaa2_ptp_match_id_table[] = { diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c index f4ae4289c41a..21cc4e52425a 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c @@ -3221,7 +3221,7 @@ static void dpaa2_switch_teardown(struct fsl_mc_device *sw_dev) dev_warn(dev, "dpsw_close err %d\n", err); } -static int dpaa2_switch_remove(struct fsl_mc_device *sw_dev) +static void dpaa2_switch_remove(struct fsl_mc_device *sw_dev) { struct ethsw_port_priv *port_priv; struct ethsw_core *ethsw; @@ -3252,8 +3252,6 @@ static int dpaa2_switch_remove(struct fsl_mc_device *sw_dev) kfree(ethsw); dev_set_drvdata(dev, NULL); - - return 0; } static int dpaa2_switch_probe_port(struct ethsw_core *ethsw, diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c index 948efa9f99e3..7ec94cfcbddb 100644 --- a/drivers/of/of_reserved_mem.c +++ b/drivers/of/of_reserved_mem.c @@ -77,6 +77,57 @@ void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname, return; } +/* + * __reserved_mem_alloc_in_range() - allocate reserved memory described with + * 'alloc-ranges'. Choose bottom-up/top-down depending on nearby existing + * reserved regions to keep the reserved memory contiguous if possible. + */ +static int __init __reserved_mem_alloc_in_range(phys_addr_t size, + phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap, + phys_addr_t *res_base) +{ + bool prev_bottom_up = memblock_bottom_up(); + bool bottom_up = false, top_down = false; + int ret, i; + + for (i = 0; i < reserved_mem_count; i++) { + struct reserved_mem *rmem = &reserved_mem[i]; + + /* Skip regions that were not reserved yet */ + if (rmem->size == 0) + continue; + + /* + * If range starts next to an existing reservation, use bottom-up: + * |....RRRR................RRRRRRRR..............| + * --RRRR------ + */ + if (start >= rmem->base && start <= (rmem->base + rmem->size)) + bottom_up = true; + + /* + * If range ends next to an existing reservation, use top-down: + * |....RRRR................RRRRRRRR..............| + * -------RRRR----- + */ + if (end >= rmem->base && end <= (rmem->base + rmem->size)) + top_down = true; + } + + /* Change setting only if either bottom-up or top-down was selected */ + if (bottom_up != top_down) + memblock_set_bottom_up(bottom_up); + + ret = early_init_dt_alloc_reserved_memory_arch(size, align, + start, end, nomap, res_base); + + /* Restore old setting if needed */ + if (bottom_up != top_down) + memblock_set_bottom_up(prev_bottom_up); + + return ret; +} + /* * __reserved_mem_alloc_size() - allocate reserved memory described by * 'size', 'alignment' and 'alloc-ranges' properties. @@ -137,8 +188,8 @@ static int __init __reserved_mem_alloc_size(unsigned long node, end = start + dt_mem_next_cell(dt_root_size_cells, &prop); - ret = early_init_dt_alloc_reserved_memory_arch(size, - align, start, end, nomap, &base); + ret = __reserved_mem_alloc_in_range(size, align, + start, end, nomap, &base); if (ret == 0) { pr_debug("allocated memory for '%s' node: base %pa, size %lu MiB\n", uname, &base, @@ -217,6 +268,11 @@ static int __init __rmem_cmp(const void *a, const void *b) if (ra->size > rb->size) return 1; + if (ra->fdt_node < rb->fdt_node) + return -1; + if (ra->fdt_node > rb->fdt_node) + return 1; + return 0; } diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 78ae84187449..051e29b7ad2b 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -140,8 +140,8 @@ struct platform_device *of_device_alloc(struct device_node *np, } } - dev->dev.of_node = of_node_get(np); - dev->dev.fwnode = &np->fwnode; + /* setup generic device info */ + device_set_node(&dev->dev, of_fwnode_handle(np)); dev->dev.parent = parent ? : &platform_bus; if (bus_id) @@ -239,8 +239,7 @@ static struct amba_device *of_amba_device_create(struct device_node *node, dev->dev.dma_mask = &dev->dev.coherent_dma_mask; /* setup generic device info */ - dev->dev.of_node = of_node_get(node); - dev->dev.fwnode = &node->fwnode; + device_set_node(&dev->dev, of_fwnode_handle(node)); dev->dev.parent = parent ? : &platform_bus; dev->dev.platform_data = platform_data; if (bus_id) diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 5386efeaf710..a406a12eb208 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -2658,7 +2658,7 @@ static struct i2c_driver unittest_i2c_dev_driver = { .driver = { .name = "unittest-i2c-dev", }, - .probe_new = unittest_i2c_dev_probe, + .probe = unittest_i2c_dev_probe, .remove = unittest_i2c_dev_remove, .id_table = unittest_i2c_dev_id, }; @@ -2735,7 +2735,7 @@ static struct i2c_driver unittest_i2c_mux_driver = { .driver = { .name = "unittest-i2c-mux", }, - .probe_new = unittest_i2c_mux_probe, + .probe = unittest_i2c_mux_probe, .remove = unittest_i2c_mux_remove, .id_table = unittest_i2c_mux_id, }; diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 09825b4a075e..4fdadc7b045f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -223,6 +224,7 @@ #define EP_STATE_ENABLED 1 static const unsigned int pcie_gen_freq[] = { + GEN1_CORE_CLK_FREQ, /* PCI_EXP_LNKSTA_CLS == 0; undefined */ GEN1_CORE_CLK_FREQ, GEN2_CORE_CLK_FREQ, GEN3_CORE_CLK_FREQ, @@ -287,6 +289,7 @@ struct tegra_pcie_dw { unsigned int pex_rst_irq; int ep_state; long link_status; + struct icc_path *icc_path; }; static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) @@ -309,6 +312,27 @@ struct tegra_pcie_soc { enum dw_pcie_device_mode mode; }; +static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) +{ + struct dw_pcie *pci = &pcie->pci; + u32 val, speed, width; + + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); + + val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE); + + if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) + dev_err(pcie->dev, "can't set bw[%u]\n", val); + + if (speed >= ARRAY_SIZE(pcie_gen_freq)) + speed = 0; + + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); +} + static void apply_bad_link_workaround(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -452,14 +476,12 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) struct tegra_pcie_dw *pcie = arg; struct dw_pcie_ep *ep = &pcie->pci.ep; struct dw_pcie *pci = &pcie->pci; - u32 val, speed; + u32 val; if (test_and_clear_bit(0, &pcie->link_status)) dw_pcie_ep_linkup(ep); - speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & - PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + tegra_pcie_icc_set(pcie); if (pcie->of_data->has_ltr_req_fix) return IRQ_HANDLED; @@ -945,9 +967,9 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) static int tegra_pcie_dw_start_link(struct dw_pcie *pci) { - u32 val, offset, speed, tmp; struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); struct dw_pcie_rp *pp = &pci->pp; + u32 val, offset, tmp; bool retry = true; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { @@ -1018,9 +1040,7 @@ retry_link: goto retry_link; } - speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & - PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + tegra_pcie_icc_set(pcie); tegra_pcie_enable_interrupts(pp); @@ -2224,6 +2244,14 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + pcie->icc_path = devm_of_icc_get(&pdev->dev, "write"); + ret = PTR_ERR_OR_ZERO(pcie->icc_path); + if (ret) { + tegra_bpmp_put(pcie->bpmp); + dev_err_probe(&pdev->dev, ret, "failed to get write interconnect\n"); + return ret; + } + switch (pcie->of_data->mode) { case DW_PCIE_RC_TYPE: ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index d532f3c6f670..2656d3d3ae40 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -51,4 +51,10 @@ config PINCTRL_STM32MP157 depends on OF && HAS_IOMEM default MACH_STM32MP157 select PINCTRL_STM32 + +config PINCTRL_STM32MP257 + bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25 + depends on OF && HAS_IOMEM + default MACH_STM32MP25 + select PINCTRL_STM32 endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 619629ee9944..7b17464d8de1 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o +obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index e0c31c4c8bca..5e5de92ddd58 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -24,6 +24,9 @@ #define STM32MP_PKG_AB BIT(1) #define STM32MP_PKG_AC BIT(2) #define STM32MP_PKG_AD BIT(3) +#define STM32MP_PKG_AI BIT(8) +#define STM32MP_PKG_AK BIT(10) +#define STM32MP_PKG_AL BIT(11) struct stm32_desc_function { const char *name; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c new file mode 100644 index 000000000000..73f091cd827e --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c @@ -0,0 +1,2581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32mp257_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(0, "PA0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "UART8_CTS"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM3_ETR"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(1, "PA1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(3, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(6, "USART1_RTS"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM4_CH2"), + STM32_FUNCTION(9, "I2C4_SDA"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(12, "LCD_R3"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(15, "ETH3_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(2, "PA2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "I3C1_SDA"), + STM32_FUNCTION(11, "I2C1_SDA"), + STM32_FUNCTION(12, "LCD_B0"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CTL ETH3_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(3, "PA3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "I3C1_SCL"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "I2C1_SCL"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(15, "ETH3_RGMII_TX_CTL ETH3_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(4, "PA4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM2_CH1"), + STM32_FUNCTION(11, "LCD_R1"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(5, "PA5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(4, "SPI4_MOSI"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM2_CH4"), + STM32_FUNCTION(11, "LCD_G0"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CLK ETH3_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(6, "PA6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(4, "SPI4_SCK"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM2_ETR"), + STM32_FUNCTION(11, "LCD_G4"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD0 ETH3_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(7, "PA7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM4_ETR"), + STM32_FUNCTION(9, "I2C2_SMBA"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(11, "LCD_B5"), + STM32_FUNCTION(12, "I2C3_SMBA"), + STM32_FUNCTION(13, "I2C4_SMBA"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD1 ETH3_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(8, "PA8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "USART2_RX"), + STM32_FUNCTION(10, "I2C5_SCL"), + STM32_FUNCTION(13, "LCD_B2"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(9, "PA9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(4, "SPI4_NSS"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(13, "LCD_G7"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD0 ETH3_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(10, "PA10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(4, "SPI4_MISO"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(9, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(13, "LCD_R6"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD1 ETH3_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(11, "PA11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "SPI8_SCK"), + STM32_FUNCTION(3, "LPTIM2_CH1"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(12, "PA12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(3, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM4_CH1"), + STM32_FUNCTION(9, "I2C4_SCL"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(11, "ETH1_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(13, "PA13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(2, "SPI8_RDY"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "LPTIM2_ETR"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(14, "PA14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(2, "SPI8_NSS"), + STM32_FUNCTION(3, "LPTIM2_CH2"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(15, "PA15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(10, "I2C7_SDA"), + STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(16, "PB0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "TIM20_CH4N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(17, "PB1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "TIM20_CH3N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"), + STM32_FUNCTION(13, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(18, "PB2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "TIM17_BKIN"), + STM32_FUNCTION(8, "TIM16_BKIN"), + STM32_FUNCTION(9, "TIM20_CH2N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(19, "PB3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(9, "TIM20_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(20, "PB4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "UART4_CTS"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(7, "TIM14_CH1"), + STM32_FUNCTION(9, "TIM20_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(21, "PB5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RTS"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(9, "TIM20_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(15, "SDMMC3_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(22, "PB6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(9, "TIM20_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(15, "SDMMC3_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(23, "PB7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(9, "TIM20_ETR"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(15, "SDMMC3_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(24, "PB8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(9, "TIM20_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(25, "PB9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(2, "SPI3_RDY"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM20_BKIN"), + STM32_FUNCTION(10, "TIM10_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(26, "PB10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"), + STM32_FUNCTION(13, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(27, "PB11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "I2S3_MCK"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM20_BKIN2"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(28, "PB12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(6, "UART8_CTS"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(10, "DSI_TE"), + STM32_FUNCTION(11, "SDMMC3_D2"), + STM32_FUNCTION(12, "FMC_NWAIT"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(29, "PB13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(6, "UART8_RX"), + STM32_FUNCTION(11, "SDMMC3_CK"), + STM32_FUNCTION(12, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(13, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(30, "PB14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "SDMMC3_D0"), + STM32_FUNCTION(12, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(13, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(31, "PB15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "UART8_RTS"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(8, "TIM3_CH2"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(11, "ETH1_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(32, "PC0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_B"), + STM32_FUNCTION(6, "USART6_TX"), + STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(12, "ETH1_MII_TX_CLK"), + STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(33, "PC1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(10, "I2C7_SCL"), + STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(34, "PC2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(2, "SPI8_MOSI"), + STM32_FUNCTION(3, "LPTIM2_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(35, "PC3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(36, "PC4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_B"), + STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"), + STM32_FUNCTION(13, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(37, "PC5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C4_SDA"), + STM32_FUNCTION(11, "ETH2_MDIO"), + STM32_FUNCTION(12, "ETH1_MII_COL"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(14, "ETH1_PPS_OUT"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(38, "PC6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(10, "I2C4_SCL"), + STM32_FUNCTION(11, "ETH2_MDC"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(14, "ETH1_PHY_INTN"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(39, "PC7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SD_B"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"), + STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(40, "PC8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"), + STM32_FUNCTION(12, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(41, "PC9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(42, "PC10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(43, "PC11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "TIM3_CH1"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(44, "PC12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"), + STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(45, "PC13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(48, "PD0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SAI1_D2"), + STM32_FUNCTION(6, "SAI4_FS_A"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"), + STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(49, "PD1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SAI1_CK2"), + STM32_FUNCTION(6, "SAI4_SD_A"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "FDCAN3_RX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(50, "PD2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SAI1_CK1"), + STM32_FUNCTION(6, "SAI4_SCK_A"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(10, "FDCAN3_TX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(51, "PD3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(2, "SAI1_MCLK_A"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(4, "SAI1_D1"), + STM32_FUNCTION(6, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(52, "PD4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(3, "HDP3"), + STM32_FUNCTION(4, "SAI1_D3"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(10, "TIM4_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(53, "PD5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(3, "HDP4"), + STM32_FUNCTION(4, "SAI1_D4"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(54, "PD6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(3, "HDP5"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(55, "PD7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(56, "PD8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "SAI1_FS_A"), + STM32_FUNCTION(5, "UART4_CTS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"), + STM32_FUNCTION(12, "SDMMC1_D7"), + STM32_FUNCTION(13, "SDMMC1_D123DIR"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(57, "PD9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SAI1_SD_A"), + STM32_FUNCTION(5, "UART4_RTS"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"), + STM32_FUNCTION(12, "SDMMC1_D6"), + STM32_FUNCTION(13, "SDMMC1_D0DIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(58, "PD10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(4, "SAI1_SCK_A"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "I2C4_SDA"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"), + STM32_FUNCTION(12, "SDMMC1_D5"), + STM32_FUNCTION(13, "SDMMC1_CDIR"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(59, "PD11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SAI1_MCLK_A"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"), + STM32_FUNCTION(12, "SDMMC1_D4"), + STM32_FUNCTION(13, "SDMMC1_CKIN"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(60, "PD12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(2, "SPI7_MISO"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "UART8_RTS"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "SDMMC3_CMD"), + STM32_FUNCTION(12, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(13, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(61, "PD13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "SDMMC3_D1"), + STM32_FUNCTION(12, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(62, "PD14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(12, "FMC_AD4 FMC_D4"), + STM32_FUNCTION(13, "SDMMC3_D3"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(63, "PD15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(2, "SPI1_RDY"), + STM32_FUNCTION(6, "DSI_TE"), + STM32_FUNCTION(7, "I2C5_SDA"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "TIM5_ETR"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(12, "FMC_AD3 FMC_D3"), + STM32_FUNCTION(13, "SDMMC3_CKIN"), + STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(64, "PE0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI3_RDY"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(11, "SDMMC1_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(65, "PE1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "I2S3_MCK"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(11, "SDMMC1_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(66, "PE2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "SDMMC1_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(67, "PE3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "SDMMC1_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(68, "PE4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(11, "SDMMC1_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(69, "PE5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(11, "SDMMC1_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(70, "PE6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(5, "SPDIFRX1_IN2"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(12, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(13, "SDMMC2_D6"), + STM32_FUNCTION(14, "SDMMC2_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(71, "PE7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(4, "SAI4_D4"), + STM32_FUNCTION(5, "SPDIFRX1_IN3"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "TIM14_CH1"), + STM32_FUNCTION(12, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(13, "SDMMC2_D7"), + STM32_FUNCTION(14, "SDMMC2_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(72, "PE8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(4, "SAI4_CK1"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(12, "FMC_A17 FMC_ALE"), + STM32_FUNCTION(13, "SDMMC2_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(73, "PE9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(4, "SAI4_D2"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(12, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(13, "SDMMC2_D5"), + STM32_FUNCTION(14, "SDMMC2_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(74, "PE10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(4, "SAI4_D1"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "FMC_NE3"), + STM32_FUNCTION(12, "FMC_NCE2"), + STM32_FUNCTION(13, "SDMMC2_D4"), + STM32_FUNCTION(14, "SDMMC2_CKIN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(75, "PE11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(4, "SAI4_D3"), + STM32_FUNCTION(5, "SAI1_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(12, "FMC_A16 FMC_CLE"), + STM32_FUNCTION(13, "SDMMC2_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(76, "PE12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(4, "SAI4_CK2"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(11, "FMC_NE2"), + STM32_FUNCTION(12, "FMC_NCE1"), + STM32_FUNCTION(13, "SDMMC2_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(77, "PE13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(5, "SAI1_SD_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(12, "FMC_RNB"), + STM32_FUNCTION(13, "SDMMC2_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(78, "PE14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(12, "FMC_NWE"), + STM32_FUNCTION(13, "SDMMC2_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(79, "PE15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI1_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(12, "FMC_NOE"), + STM32_FUNCTION(13, "SDMMC2_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(80, "PF0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM12_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(12, "ETH2_MII_CRS"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(81, "PF1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(2, "SPI8_MISO"), + STM32_FUNCTION(3, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(82, "PF2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(7, "I2C4_SMBA"), + STM32_FUNCTION(9, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(12, "ETH2_MII_COL"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(83, "PF3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(4, "UART8_RX"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM3_CH4"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(84, "PF4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(3, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM4_CH4"), + STM32_FUNCTION(9, "ETH1_MDC"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH1_PPS_OUT"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(85, "PF5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(3, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(8, "TIM4_CH3"), + STM32_FUNCTION(9, "ETH1_MDIO"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(12, "ETH1_PHY_INTN"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(86, "PF6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(4, "SAI3_MCLK_B"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C3_SMBA"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(87, "PF7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"), + STM32_FUNCTION(12, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(88, "PF8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(4, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH2_MII_RX_ER"), + STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(89, "PF9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(4, "SAI3_SD_B"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "UART8_RTS"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(12, "ETH2_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(90, "PF10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(7, "UART8_TX"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(91, "PF11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "UART8_RX"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(92, "PF12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(93, "PF13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "USART6_TX"), + STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(9, "TIM3_CH3"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(94, "PF14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(4, "USART6_RX"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM3_CH4"), + STM32_FUNCTION(14, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(95, "PF15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "USART6_CTS"), + STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(9, "TIM3_ETR"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(96, "PG0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"), + STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(97, "PG1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RX_ER"), + STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(98, "PG2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(12, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(99, "PG3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "UART8_TX"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(8, "TIM3_CH3"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(100, "PG4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI3_FS_B"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH2_MDC"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(101, "PG5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(4, "USART6_RTS"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(102, "PG6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(103, "PG7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(104, "PG8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SPI1_RDY"), + STM32_FUNCTION(5, "USART6_CK"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(105, "PG9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(106, "PG10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(1, "TRACED8"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(14, "LCD_G4"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(107, "PG11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(1, "TRACED9"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(108, "PG12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(1, "TRACED10"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(109, "PG13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(1, "TRACED11"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(110, "PG14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(1, "TRACED12"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI5"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(14, "LCD_B1"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(111, "PG15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(1, "TRACED13"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(4, "LPTIM1_CH2"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(14, "LCD_B2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(114, "PH2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "I3C3_SDA"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "I2C5_SDA"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_GTX_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(115, "PH3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(10, "TIM5_CH3"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(116, "PH4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM17_BKIN"), + STM32_FUNCTION(10, "TIM5_CH2"), + STM32_FUNCTION(11, "LCD_R0"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "USBH_HS_OVRCUR"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(117, "PH5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "UART8_CTS"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(11, "LCD_G1"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "USBH_HS_VBUSEN"), + STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(118, "PH6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "I3C3_SCL"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "I2C5_SCL"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "I2C1_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(119, "PH7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(10, "TIM5_CH4"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(120, "PH8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(10, "TIM5_CH1"), + STM32_FUNCTION(11, "I2C3_SMBA"), + STM32_FUNCTION(12, "I2C5_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(121, "PH9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(11, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(122, "PH10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(10, "ETH2_MDC"), + STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(123, "PH11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "ETH2_MDIO"), + STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(124, "PH12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(125, "PH13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(128, "PI0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(1, "TRACED14"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(4, "LPTIM1_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(129, "PI1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(1, "TRACED15"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(130, "PI2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "LPTIM1_ETR"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(14, "LCD_B5"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(131, "PI3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "LPTIM1_IN2"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(132, "PI4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "LPTIM1_CH1"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(133, "PI5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(14, "LCD_DE"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(134, "PI6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(9, "TIM3_CH1"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(135, "PI7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "TIM3_CH2"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(136, "PI8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(137, "PI9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(2, "SPI7_MOSI"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM16_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "DSI_TE"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(138, "PI10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(2, "SAI1_SCK_A"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPDIFRX1_IN0"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(9, "TIM4_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(14, "DSI_TE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(139, "PI11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(6, "UART8_TX"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "SDMMC3_D3"), + STM32_FUNCTION(12, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(140, "PI12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(3, "SPI4_NSS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(141, "PI13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(3, "SPI4_MOSI"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(142, "PI14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(8, "TIM20_CH3"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(143, "PI15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(8, "TIM20_BKIN2"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "SDMMC3_CDIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(144, "PJ0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "SAI4_D2"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(12, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(14, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(145, "PJ1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(146, "PJ2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(13, "FMC_A14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(147, "PJ3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SAI2_FS_A"), + STM32_FUNCTION(6, "SAI4_D1"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(148, "PJ4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(4, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "I2C2_SMBA"), + STM32_FUNCTION(11, "I2C5_SMBA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(149, "PJ5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI2_SCK_B"), + STM32_FUNCTION(6, "SAI4_CK1"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(150, "PJ6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM20_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(151, "PJ7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI4_D3"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SMBA"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(152, "PJ8"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(6, "SAI4_CK2"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(153, "PJ9"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(3, "SPI4_RDY"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(154, "PJ10"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(155, "PJ11"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SAI2_SCK_A"), + STM32_FUNCTION(6, "SAI4_D4"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(156, "PJ12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(4, "SAI2_SD_A"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "I3C2_SCL"), + STM32_FUNCTION(13, "FMC_A15"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(157, "PJ13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(4, "SAI2_MCLK_A"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "I3C2_SDA"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(158, "PJ14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(3, "SPI4_SCK"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(159, "PJ15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI4_MISO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(160, "PK0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM20_ETR"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(11, "SDMMC3_D123DIR"), + STM32_FUNCTION(13, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(161, "PK1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(8, "TIM20_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "SDMMC3_D0DIR"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(162, "PK2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "TIM20_CH2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(163, "PK3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(8, "TIM20_CH3N"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(164, "PK4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(8, "TIM20_CH1"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(11, "SDMMC3_CKIN"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(165, "PK5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM20_CH4N"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(11, "I2C5_SCL"), + STM32_FUNCTION(13, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(166, "PK6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM20_CH2N"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(12, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(13, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(167, "PK7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM20_CH4"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "I2C5_SDA"), + STM32_FUNCTION(12, "FMC_NCE4"), + STM32_FUNCTION(13, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static const struct stm32_desc_pin stm32mp257_z_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(400, "PZ0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ0"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "TIM8_CH1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(401, "PZ1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ1"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "TIM8_CH2"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(10, "I2C8_SMBA"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(402, "PZ2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ2"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(403, "PZ3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ3"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(404, "PZ4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ4"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(405, "PZ5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ5"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(406, "PZ6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ6"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "TIM8_CH3"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(407, "PZ7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ7"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(408, "PZ8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ8"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SMBA"), + STM32_FUNCTION(10, "LPTIM5_ETR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(409, "PZ9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ9"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CKI5"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32mp257_match_data = { + .pins = stm32mp257_pins, + .npins = ARRAY_SIZE(stm32mp257_pins), +}; + +static struct stm32_pinctrl_match_data stm32mp257_z_match_data = { + .pins = stm32mp257_z_pins, + .npins = ARRAY_SIZE(stm32mp257_z_pins), +}; + +static const struct of_device_id stm32mp257_pctrl_match[] = { + { + .compatible = "st,stm32mp257-pinctrl", + .data = &stm32mp257_match_data, + }, + { + .compatible = "st,stm32mp257-z-pinctrl", + .data = &stm32mp257_z_match_data, + }, + { } +}; + +static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume) +}; + +static struct platform_driver stm32mp257_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32mp257-pinctrl", + .of_match_table = stm32mp257_pctrl_match, + .pm = &stm32_pinctrl_dev_pm_ops, + }, +}; + +static int __init stm32mp257_pinctrl_init(void) +{ + return platform_driver_register(&stm32mp257_pinctrl_driver); +} +arch_initcall(stm32mp257_pinctrl_init); diff --git a/drivers/powercap/arm_scmi_powercap.c b/drivers/powercap/arm_scmi_powercap.c index 05d0e516176a..5231f6d52ae3 100644 --- a/drivers/powercap/arm_scmi_powercap.c +++ b/drivers/powercap/arm_scmi_powercap.c @@ -70,10 +70,26 @@ static int scmi_powercap_get_power_uw(struct powercap_zone *pz, return 0; } +static int scmi_powercap_zone_enable_set(struct powercap_zone *pz, bool mode) +{ + struct scmi_powercap_zone *spz = to_scmi_powercap_zone(pz); + + return powercap_ops->cap_enable_set(spz->ph, spz->info->id, mode); +} + +static int scmi_powercap_zone_enable_get(struct powercap_zone *pz, bool *mode) +{ + struct scmi_powercap_zone *spz = to_scmi_powercap_zone(pz); + + return powercap_ops->cap_enable_get(spz->ph, spz->info->id, mode); +} + static const struct powercap_zone_ops zone_ops = { .get_max_power_range_uw = scmi_powercap_get_max_power_range_uw, .get_power_uw = scmi_powercap_get_power_uw, .release = scmi_powercap_zone_release, + .set_enable = scmi_powercap_zone_enable_set, + .get_enable = scmi_powercap_zone_enable_get, }; static void scmi_powercap_normalize_cap(const struct scmi_powercap_zone *spz, diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a850e9f486dd..48845dc8fa85 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -313,7 +313,7 @@ config ST_SLIM_REMOTEPROC config STM32_RPROC tristate "STM32 remoteproc support" - depends on ARCH_STM32 + depends on ARCH_STM32 || COMPILE_TEST depends on REMOTEPROC select MAILBOX help diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 095f66130f48..54f5ce302e7a 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -81,21 +81,6 @@ enum pru_iomem { PRU_IOMEM_MAX, }; -/** - * enum pru_type - PRU core type identifier - * - * @PRU_TYPE_PRU: Programmable Real-time Unit - * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit - * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit - * @PRU_TYPE_MAX: just keep this one at the end - */ -enum pru_type { - PRU_TYPE_PRU = 0, - PRU_TYPE_RTU, - PRU_TYPE_TX_PRU, - PRU_TYPE_MAX, -}; - /** * struct pru_private_data - device data for a PRU core * @type: type of the PRU core (PRU, RTU, Tx_PRU) diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c index 8746cbb1f168..e432febf4337 100644 --- a/drivers/remoteproc/stm32_rproc.c +++ b/drivers/remoteproc/stm32_rproc.c @@ -118,10 +118,10 @@ static int stm32_rproc_mem_alloc(struct rproc *rproc, struct device *dev = rproc->dev.parent; void *va; - dev_dbg(dev, "map memory: %pa+%x\n", &mem->dma, mem->len); + dev_dbg(dev, "map memory: %pad+%zx\n", &mem->dma, mem->len); va = ioremap_wc(mem->dma, mem->len); if (IS_ERR_OR_NULL(va)) { - dev_err(dev, "Unable to map memory region: %pa+%x\n", + dev_err(dev, "Unable to map memory region: %pad+0x%zx\n", &mem->dma, mem->len); return -ENOMEM; } @@ -627,7 +627,7 @@ stm32_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz) ddata->rsc_va = devm_ioremap_wc(dev, rsc_pa, RSC_TBL_SIZE); if (IS_ERR_OR_NULL(ddata->rsc_va)) { - dev_err(dev, "Unable to map memory region: %pa+%zx\n", + dev_err(dev, "Unable to map memory region: %pa+%x\n", &rsc_pa, RSC_TBL_SIZE); ddata->rsc_va = NULL; return ERR_PTR(-ENOMEM); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6aa8f243b30c..ccd59ddd7610 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,8 +143,12 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. -config RESET_OXNAS - bool +config RESET_NUVOTON_MA35D1 + bool "Nuvoton MA35D1 Reset Driver" + depends on ARCH_MA35 || COMPILE_TEST + default ARCH_MA35 + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. config RESET_PISTACHIO bool "Pistachio Reset Driver" @@ -154,7 +158,8 @@ config RESET_PISTACHIO config RESET_POLARFIRE_SOC bool "Microchip PolarFire SoC (MPFS) Reset Driver" - depends on AUXILIARY_BUS && MCHP_CLK_MPFS + depends on MCHP_CLK_MPFS + select AUXILIARY_BUS default MCHP_CLK_MPFS help This driver supports peripheral reset for the Microchip PolarFire SoC diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7fec5af6c964..8270da8a4baa 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -21,7 +21,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o -obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c index e48d8fcb3133..a8b8f5ea77ec 100644 --- a/drivers/reset/reset-ath79.c +++ b/drivers/reset/reset-ath79.c @@ -86,7 +86,6 @@ static int ath79_reset_restart_handler(struct notifier_block *nb, static int ath79_reset_probe(struct platform_device *pdev) { struct ath79_reset *ath79_reset; - struct resource *res; int err; ath79_reset = devm_kzalloc(&pdev->dev, @@ -96,8 +95,7 @@ static int ath79_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ath79_reset); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ath79_reset->base = devm_ioremap_resource(&pdev->dev, res); + ath79_reset->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ath79_reset->base)) return PTR_ERR(ath79_reset->base); diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c index a854ef41364d..115f69e0db33 100644 --- a/drivers/reset/reset-axs10x.c +++ b/drivers/reset/reset-axs10x.c @@ -44,14 +44,12 @@ static const struct reset_control_ops axs10x_reset_ops = { static int axs10x_reset_probe(struct platform_device *pdev) { struct axs10x_rst *rst; - struct resource *mem; rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); if (!rst) return -ENOMEM; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_rst = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rst->regs_rst)) return PTR_ERR(rst->regs_rst); diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c index 433fa0c40e47..823317772bac 100644 --- a/drivers/reset/reset-brcmstb-rescal.c +++ b/drivers/reset/reset-brcmstb-rescal.c @@ -66,14 +66,12 @@ static const struct reset_control_ops brcm_rescal_reset_ops = { static int brcm_rescal_reset_probe(struct platform_device *pdev) { struct brcm_rescal_reset *data; - struct resource *res; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->base = devm_ioremap_resource(&pdev->dev, res); + data->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->base)) return PTR_ERR(data->base); diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c index 4c7b8647b49c..98460e08752c 100644 --- a/drivers/reset/reset-hsdk.c +++ b/drivers/reset/reset-hsdk.c @@ -92,19 +92,16 @@ static const struct reset_control_ops hsdk_reset_ops = { static int hsdk_reset_probe(struct platform_device *pdev) { struct hsdk_rst *rst; - struct resource *mem; rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); if (!rst) return -ENOMEM; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rst->regs_ctl)) return PTR_ERR(rst->regs_ctl); - mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); - rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_rst = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(rst->regs_rst)) return PTR_ERR(rst->regs_rst); diff --git a/drivers/reset/reset-lpc18xx.c b/drivers/reset/reset-lpc18xx.c index 35d8dd4cccfc..36ec95518905 100644 --- a/drivers/reset/reset-lpc18xx.c +++ b/drivers/reset/reset-lpc18xx.c @@ -139,7 +139,6 @@ static const struct reset_control_ops lpc18xx_rgu_ops = { static int lpc18xx_rgu_probe(struct platform_device *pdev) { struct lpc18xx_rgu_data *rc; - struct resource *res; u32 fcclk, firc; int ret; @@ -147,8 +146,7 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev) if (!rc) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rc->base = devm_ioremap_resource(&pdev->dev, res); + rc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rc->base)) return PTR_ERR(rc->base); diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..54e53863c98a --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct notifier_block restart_handler; + void __iomem *base; + /* protect registers against concurrent read-modify-write */ + spinlock_t lock; +}; + +static const struct { + u32 reg_ofs; + u32 bit; +} ma35d1_reset_map[] = { + [MA35D1_RESET_CHIP] = {0x20, 0}, + [MA35D1_RESET_CA35CR0] = {0x20, 1}, + [MA35D1_RESET_CA35CR1] = {0x20, 2}, + [MA35D1_RESET_CM4] = {0x20, 3}, + [MA35D1_RESET_PDMA0] = {0x20, 4}, + [MA35D1_RESET_PDMA1] = {0x20, 5}, + [MA35D1_RESET_PDMA2] = {0x20, 6}, + [MA35D1_RESET_PDMA3] = {0x20, 7}, + [MA35D1_RESET_DISP] = {0x20, 9}, + [MA35D1_RESET_VCAP0] = {0x20, 10}, + [MA35D1_RESET_VCAP1] = {0x20, 11}, + [MA35D1_RESET_GFX] = {0x20, 12}, + [MA35D1_RESET_VDEC] = {0x20, 13}, + [MA35D1_RESET_WHC0] = {0x20, 14}, + [MA35D1_RESET_WHC1] = {0x20, 15}, + [MA35D1_RESET_GMAC0] = {0x20, 16}, + [MA35D1_RESET_GMAC1] = {0x20, 17}, + [MA35D1_RESET_HWSEM] = {0x20, 18}, + [MA35D1_RESET_EBI] = {0x20, 19}, + [MA35D1_RESET_HSUSBH0] = {0x20, 20}, + [MA35D1_RESET_HSUSBH1] = {0x20, 21}, + [MA35D1_RESET_HSUSBD] = {0x20, 22}, + [MA35D1_RESET_USBHL] = {0x20, 23}, + [MA35D1_RESET_SDH0] = {0x20, 24}, + [MA35D1_RESET_SDH1] = {0x20, 25}, + [MA35D1_RESET_NAND] = {0x20, 26}, + [MA35D1_RESET_GPIO] = {0x20, 27}, + [MA35D1_RESET_MCTLP] = {0x20, 28}, + [MA35D1_RESET_MCTLC] = {0x20, 29}, + [MA35D1_RESET_DDRPUB] = {0x20, 30}, + [MA35D1_RESET_TMR0] = {0x24, 2}, + [MA35D1_RESET_TMR1] = {0x24, 3}, + [MA35D1_RESET_TMR2] = {0x24, 4}, + [MA35D1_RESET_TMR3] = {0x24, 5}, + [MA35D1_RESET_I2C0] = {0x24, 8}, + [MA35D1_RESET_I2C1] = {0x24, 9}, + [MA35D1_RESET_I2C2] = {0x24, 10}, + [MA35D1_RESET_I2C3] = {0x24, 11}, + [MA35D1_RESET_QSPI0] = {0x24, 12}, + [MA35D1_RESET_SPI0] = {0x24, 13}, + [MA35D1_RESET_SPI1] = {0x24, 14}, + [MA35D1_RESET_SPI2] = {0x24, 15}, + [MA35D1_RESET_UART0] = {0x24, 16}, + [MA35D1_RESET_UART1] = {0x24, 17}, + [MA35D1_RESET_UART2] = {0x24, 18}, + [MA35D1_RESET_UART3] = {0x24, 19}, + [MA35D1_RESET_UART4] = {0x24, 20}, + [MA35D1_RESET_UART5] = {0x24, 21}, + [MA35D1_RESET_UART6] = {0x24, 22}, + [MA35D1_RESET_UART7] = {0x24, 23}, + [MA35D1_RESET_CANFD0] = {0x24, 24}, + [MA35D1_RESET_CANFD1] = {0x24, 25}, + [MA35D1_RESET_EADC0] = {0x24, 28}, + [MA35D1_RESET_I2S0] = {0x24, 29}, + [MA35D1_RESET_SC0] = {0x28, 0}, + [MA35D1_RESET_SC1] = {0x28, 1}, + [MA35D1_RESET_QSPI1] = {0x28, 4}, + [MA35D1_RESET_SPI3] = {0x28, 6}, + [MA35D1_RESET_EPWM0] = {0x28, 16}, + [MA35D1_RESET_EPWM1] = {0x28, 17}, + [MA35D1_RESET_QEI0] = {0x28, 22}, + [MA35D1_RESET_QEI1] = {0x28, 23}, + [MA35D1_RESET_ECAP0] = {0x28, 26}, + [MA35D1_RESET_ECAP1] = {0x28, 27}, + [MA35D1_RESET_CANFD2] = {0x28, 28}, + [MA35D1_RESET_ADC0] = {0x28, 31}, + [MA35D1_RESET_TMR4] = {0x2C, 0}, + [MA35D1_RESET_TMR5] = {0x2C, 1}, + [MA35D1_RESET_TMR6] = {0x2C, 2}, + [MA35D1_RESET_TMR7] = {0x2C, 3}, + [MA35D1_RESET_TMR8] = {0x2C, 4}, + [MA35D1_RESET_TMR9] = {0x2C, 5}, + [MA35D1_RESET_TMR10] = {0x2C, 6}, + [MA35D1_RESET_TMR11] = {0x2C, 7}, + [MA35D1_RESET_UART8] = {0x2C, 8}, + [MA35D1_RESET_UART9] = {0x2C, 9}, + [MA35D1_RESET_UART10] = {0x2C, 10}, + [MA35D1_RESET_UART11] = {0x2C, 11}, + [MA35D1_RESET_UART12] = {0x2C, 12}, + [MA35D1_RESET_UART13] = {0x2C, 13}, + [MA35D1_RESET_UART14] = {0x2C, 14}, + [MA35D1_RESET_UART15] = {0x2C, 15}, + [MA35D1_RESET_UART16] = {0x2C, 16}, + [MA35D1_RESET_I2S1] = {0x2C, 17}, + [MA35D1_RESET_I2C4] = {0x2C, 18}, + [MA35D1_RESET_I2C5] = {0x2C, 19}, + [MA35D1_RESET_EPWM2] = {0x2C, 20}, + [MA35D1_RESET_ECAP2] = {0x2C, 21}, + [MA35D1_RESET_QEI2] = {0x2C, 22}, + [MA35D1_RESET_CANFD3] = {0x2C, 23}, + [MA35D1_RESET_KPI] = {0x2C, 24}, + [MA35D1_RESET_GIC] = {0x2C, 28}, + [MA35D1_RESET_SSMCC] = {0x2C, 30}, + [MA35D1_RESET_SSPCC] = {0x2C, 31} +}; + +static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd) +{ + struct ma35d1_reset_data *data = + container_of(this, struct ma35d1_reset_data, restart_handler); + u32 id = MA35D1_RESET_CHIP; + + writel_relaxed(BIT(ma35d1_reset_map[id].bit), + data->base + ma35d1_reset_map[id].reg_ofs); + return 0; +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) +{ + struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); + unsigned long flags; + u32 reg; + + if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) + return -EINVAL; + + spin_lock_irqsave(&data->lock, flags); + reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + if (assert) + reg |= BIT(ma35d1_reset_map[id].bit); + else + reg &= ~(BIT(ma35d1_reset_map[id].bit)); + writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); + u32 reg; + + if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) + return -EINVAL; + + reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + return !!(reg & BIT(ma35d1_reset_map[id].bit)); +} + +static const struct reset_control_ops ma35d1_reset_ops = { + .assert = ma35d1_reset_assert, + .deassert = ma35d1_reset_deassert, + .status = ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] = { + { .compatible = "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + struct ma35d1_reset_data *reset_data; + struct device *dev = &pdev->dev; + int err; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reset_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reset_data->base)) + return PTR_ERR(reset_data->base); + + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; + reset_data->rcdev.ops = &ma35d1_reset_ops; + reset_data->rcdev.of_node = dev->of_node; + reset_data->restart_handler.notifier_call = ma35d1_restart_handler; + reset_data->restart_handler.priority = 192; + spin_lock_init(&reset_data->lock); + + err = register_restart_handler(&reset_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); +} + +static struct platform_driver ma35d1_reset_driver = { + .probe = ma35d1_reset_probe, + .driver = { + .name = "ma35d1-reset", + .of_match_table = ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); diff --git a/drivers/reset/reset-meson-audio-arb.c b/drivers/reset/reset-meson-audio-arb.c index 1dc06e08a8da..6a3f6a6a3bbf 100644 --- a/drivers/reset/reset-meson-audio-arb.c +++ b/drivers/reset/reset-meson-audio-arb.c @@ -151,11 +151,8 @@ static int meson_audio_arb_probe(struct platform_device *pdev) platform_set_drvdata(pdev, arb); arb->clk = devm_clk_get(dev, NULL); - if (IS_ERR(arb->clk)) { - if (PTR_ERR(arb->clk) != -EPROBE_DEFER) - dev_err(dev, "failed to get clock\n"); - return PTR_ERR(arb->clk); - } + if (IS_ERR(arb->clk)) + return dev_err_probe(dev, PTR_ERR(arb->clk), "failed to get clock\n"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); arb->regs = devm_ioremap_resource(dev, res); diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 26dc54778615..13878ca2779d 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -116,14 +116,12 @@ MODULE_DEVICE_TABLE(of, meson_reset_dt_ids); static int meson_reset_probe(struct platform_device *pdev) { struct meson_reset *data; - struct resource *res; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->reg_base = devm_ioremap_resource(&pdev->dev, res); + data->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->reg_base)) return PTR_ERR(data->reg_base); diff --git a/drivers/reset/reset-oxnas.c b/drivers/reset/reset-oxnas.c deleted file mode 100644 index 8209f922dc16..000000000000 --- a/drivers/reset/reset-oxnas.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor Reset Controller driver - * - * Copyright (C) 2016 Neil Armstrong - * Copyright (C) 2014 Ma Haijun - * Copyright (C) 2009 Oxford Semiconductor Ltd - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Regmap offsets */ -#define RST_SET_REGOFFSET 0x34 -#define RST_CLR_REGOFFSET 0x38 - -struct oxnas_reset { - struct regmap *regmap; - struct reset_controller_dev rcdev; -}; - -static int oxnas_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); - msleep(50); - regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); - - return 0; -} - -static int oxnas_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); - - return 0; -} - -static int oxnas_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); - - return 0; -} - -static const struct reset_control_ops oxnas_reset_ops = { - .reset = oxnas_reset_reset, - .assert = oxnas_reset_assert, - .deassert = oxnas_reset_deassert, -}; - -static const struct of_device_id oxnas_reset_dt_ids[] = { - { .compatible = "oxsemi,ox810se-reset", }, - { .compatible = "oxsemi,ox820-reset", }, - { /* sentinel */ }, -}; - -static int oxnas_reset_probe(struct platform_device *pdev) -{ - struct oxnas_reset *data; - struct device *parent; - - parent = pdev->dev.parent; - if (!parent) { - dev_err(&pdev->dev, "no parent\n"); - return -ENODEV; - } - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - data->regmap = syscon_node_to_regmap(parent->of_node); - if (IS_ERR(data->regmap)) { - dev_err(&pdev->dev, "failed to get parent regmap\n"); - return PTR_ERR(data->regmap); - } - - platform_set_drvdata(pdev, data); - - data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = 32; - data->rcdev.ops = &oxnas_reset_ops; - data->rcdev.of_node = pdev->dev.of_node; - - return devm_reset_controller_register(&pdev->dev, &data->rcdev); -} - -static struct platform_driver oxnas_reset_driver = { - .probe = oxnas_reset_probe, - .driver = { - .name = "oxnas-reset", - .of_match_table = oxnas_reset_dt_ids, - }, -}; -builtin_platform_driver(oxnas_reset_driver); diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig index 1fa706a2c3dc..d832339f61bc 100644 --- a/drivers/reset/starfive/Kconfig +++ b/drivers/reset/starfive/Kconfig @@ -13,7 +13,8 @@ config RESET_STARFIVE_JH7100 config RESET_STARFIVE_JH7110 bool "StarFive JH7110 Reset Driver" - depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS + depends on CLK_STARFIVE_JH7110_SYS + select AUXILIARY_BUS select RESET_STARFIVE_JH71X0 default ARCH_STARFIVE help diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig index 9455e1c7a5aa..a2622e146b8b 100644 --- a/drivers/reset/sti/Kconfig +++ b/drivers/reset/sti/Kconfig @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only if ARCH_STI -config STI_RESET_SYSCFG - bool - config STIH407_RESET bool - select STI_RESET_SYSCFG endif diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile index 3eb30f7e8e3d..5e833496cee3 100644 --- a/drivers/reset/sti/Makefile +++ b/drivers/reset/sti/Makefile @@ -1,4 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o - -obj-$(CONFIG_STIH407_RESET) += reset-stih407.o +obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c index b4b46e0f207e..c1ba04f6f155 100644 --- a/drivers/reset/sti/reset-syscfg.c +++ b/drivers/reset/sti/reset-syscfg.c @@ -64,22 +64,12 @@ static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev, return err; if (ch->ack) { - unsigned long timeout = jiffies + msecs_to_jiffies(1000); u32 ack_val; - while (true) { - err = regmap_field_read(ch->ack, &ack_val); - if (err) - return err; - - if (ack_val == ctrl_val) - break; - - if (time_after(jiffies, timeout)) - return -ETIME; - - cpu_relax(); - } + err = regmap_field_read_poll_timeout(ch->ack, ack_val, (ack_val == ctrl_val), + 100, USEC_PER_SEC); + if (err) + return err; } return 0; diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index e93518763526..25b4b71df9b8 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -105,7 +105,7 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(ACODEC, 0), SEC_PD(AUDIO, 0), SEC_PD(OTP, 0), - SEC_PD(DMA, 0), + SEC_PD(DMA, GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE), SEC_PD(SD_EMMC, 0), SEC_PD(RAMA, 0), /* SRAMB is used as ATF runtime memory, and should be always on */ diff --git a/drivers/soc/fsl/dpio/dpio-driver.c b/drivers/soc/fsl/dpio/dpio-driver.c index 74eace3109a1..9e3fddd8f5a9 100644 --- a/drivers/soc/fsl/dpio/dpio-driver.c +++ b/drivers/soc/fsl/dpio/dpio-driver.c @@ -270,7 +270,7 @@ static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev) fsl_mc_free_irqs(dpio_dev); } -static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) +static void dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) { struct device *dev; struct dpio_priv *priv; @@ -297,14 +297,8 @@ static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle); - fsl_mc_portal_free(dpio_dev->mc_io); - - return 0; - err_open: fsl_mc_portal_free(dpio_dev->mc_io); - - return err; } static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = { diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index e0d096607fef..fa9ffbed0e92 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -62,6 +62,7 @@ config QE_TDM config QE_USB bool + depends on QUICC_ENGINE default y if USB_FSL_QE help QE USB Controller support diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 26f3d9a41496..4aa0913817ae 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -1051,7 +1051,6 @@ static struct platform_driver mtk_mutex_driver = { .probe = mtk_mutex_probe, .driver = { .name = "mediatek-mutex", - .owner = THIS_MODULE, .of_match_table = mutex_driver_dt_match, }, }; diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 15789a03e6c6..11095b8de71a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -47,6 +47,7 @@ /* macro for device wrapper default value */ #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 +#define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a /* macro for manual command */ @@ -169,6 +170,40 @@ static const u32 mt6323_regs[] = { [PWRAP_DEW_RDDMY_NO] = 0x01a4, }; +static const u32 mt6331_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x018c, + [PWRAP_DEW_READ_TEST] = 0x018e, + [PWRAP_DEW_WRITE_TEST] = 0x0190, + [PWRAP_DEW_CRC_SWRST] = 0x0192, + [PWRAP_DEW_CRC_EN] = 0x0194, + [PWRAP_DEW_CRC_VAL] = 0x0196, + [PWRAP_DEW_MON_GRP_SEL] = 0x0198, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c, + [PWRAP_DEW_CIPHER_EN] = 0x019e, + [PWRAP_DEW_CIPHER_RDY] = 0x01a0, + [PWRAP_DEW_CIPHER_MODE] = 0x01a2, + [PWRAP_DEW_CIPHER_SWRST] = 0x01a4, + [PWRAP_DEW_RDDMY_NO] = 0x01a6, +}; + +static const u32 mt6332_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x80f6, + [PWRAP_DEW_READ_TEST] = 0x80f8, + [PWRAP_DEW_WRITE_TEST] = 0x80fa, + [PWRAP_DEW_CRC_SWRST] = 0x80fc, + [PWRAP_DEW_CRC_EN] = 0x80fe, + [PWRAP_DEW_CRC_VAL] = 0x8100, + [PWRAP_DEW_MON_GRP_SEL] = 0x8102, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106, + [PWRAP_DEW_CIPHER_EN] = 0x8108, + [PWRAP_DEW_CIPHER_RDY] = 0x810a, + [PWRAP_DEW_CIPHER_MODE] = 0x810c, + [PWRAP_DEW_CIPHER_SWRST] = 0x810e, + [PWRAP_DEW_RDDMY_NO] = 0x8110, +}; + static const u32 mt6351_regs[] = { [PWRAP_DEW_DIO_EN] = 0x02F2, [PWRAP_DEW_READ_TEST] = 0x02F4, @@ -604,6 +639,91 @@ static int mt6779_regs[] = { [PWRAP_WACS2_VLDCLR] = 0xC28, }; +static int mt6795_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_RDDMY] = 0x10, + [PWRAP_SI_CK_CON] = 0x14, + [PWRAP_CSHEXT_WRITE] = 0x18, + [PWRAP_CSHEXT_READ] = 0x1c, + [PWRAP_CSLEXT_START] = 0x20, + [PWRAP_CSLEXT_END] = 0x24, + [PWRAP_STAUPD_PRD] = 0x28, + [PWRAP_STAUPD_GRPEN] = 0x2c, + [PWRAP_EINT_STA0_ADR] = 0x30, + [PWRAP_EINT_STA1_ADR] = 0x34, + [PWRAP_STAUPD_MAN_TRIG] = 0x40, + [PWRAP_STAUPD_STA] = 0x44, + [PWRAP_WRAP_STA] = 0x48, + [PWRAP_HARB_INIT] = 0x4c, + [PWRAP_HARB_HPRIO] = 0x50, + [PWRAP_HIPRIO_ARB_EN] = 0x54, + [PWRAP_HARB_STA0] = 0x58, + [PWRAP_HARB_STA1] = 0x5c, + [PWRAP_MAN_EN] = 0x60, + [PWRAP_MAN_CMD] = 0x64, + [PWRAP_MAN_RDATA] = 0x68, + [PWRAP_MAN_VLDCLR] = 0x6c, + [PWRAP_WACS0_EN] = 0x70, + [PWRAP_INIT_DONE0] = 0x74, + [PWRAP_WACS0_CMD] = 0x78, + [PWRAP_WACS0_RDATA] = 0x7c, + [PWRAP_WACS0_VLDCLR] = 0x80, + [PWRAP_WACS1_EN] = 0x84, + [PWRAP_INIT_DONE1] = 0x88, + [PWRAP_WACS1_CMD] = 0x8c, + [PWRAP_WACS1_RDATA] = 0x90, + [PWRAP_WACS1_VLDCLR] = 0x94, + [PWRAP_WACS2_EN] = 0x98, + [PWRAP_INIT_DONE2] = 0x9c, + [PWRAP_WACS2_CMD] = 0xa0, + [PWRAP_WACS2_RDATA] = 0xa4, + [PWRAP_WACS2_VLDCLR] = 0xa8, + [PWRAP_INT_EN] = 0xac, + [PWRAP_INT_FLG_RAW] = 0xb0, + [PWRAP_INT_FLG] = 0xb4, + [PWRAP_INT_CLR] = 0xb8, + [PWRAP_SIG_ADR] = 0xbc, + [PWRAP_SIG_MODE] = 0xc0, + [PWRAP_SIG_VALUE] = 0xc4, + [PWRAP_SIG_ERRVAL] = 0xc8, + [PWRAP_CRC_EN] = 0xcc, + [PWRAP_TIMER_EN] = 0xd0, + [PWRAP_TIMER_STA] = 0xd4, + [PWRAP_WDT_UNIT] = 0xd8, + [PWRAP_WDT_SRC_EN] = 0xdc, + [PWRAP_WDT_FLG] = 0xe0, + [PWRAP_DEBUG_INT_SEL] = 0xe4, + [PWRAP_DVFS_ADR0] = 0xe8, + [PWRAP_DVFS_WDATA0] = 0xec, + [PWRAP_DVFS_ADR1] = 0xf0, + [PWRAP_DVFS_WDATA1] = 0xf4, + [PWRAP_DVFS_ADR2] = 0xf8, + [PWRAP_DVFS_WDATA2] = 0xfc, + [PWRAP_DVFS_ADR3] = 0x100, + [PWRAP_DVFS_WDATA3] = 0x104, + [PWRAP_DVFS_ADR4] = 0x108, + [PWRAP_DVFS_WDATA4] = 0x10c, + [PWRAP_DVFS_ADR5] = 0x110, + [PWRAP_DVFS_WDATA5] = 0x114, + [PWRAP_DVFS_ADR6] = 0x118, + [PWRAP_DVFS_WDATA6] = 0x11c, + [PWRAP_DVFS_ADR7] = 0x120, + [PWRAP_DVFS_WDATA7] = 0x124, + [PWRAP_SPMINF_STA] = 0x128, + [PWRAP_CIPHER_KEY_SEL] = 0x12c, + [PWRAP_CIPHER_IV_SEL] = 0x130, + [PWRAP_CIPHER_EN] = 0x134, + [PWRAP_CIPHER_RDY] = 0x138, + [PWRAP_CIPHER_MODE] = 0x13c, + [PWRAP_CIPHER_SWRST] = 0x140, + [PWRAP_DCM_EN] = 0x144, + [PWRAP_DCM_DBC_PRD] = 0x148, + [PWRAP_EXT_CK] = 0x14c, +}; + static int mt6797_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1181,6 +1301,8 @@ static int mt8186_regs[] = { enum pmic_type { PMIC_MT6323, + PMIC_MT6331, + PMIC_MT6332, PMIC_MT6351, PMIC_MT6357, PMIC_MT6358, @@ -1193,6 +1315,7 @@ enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, PWRAP_MT6779, + PWRAP_MT6795, PWRAP_MT6797, PWRAP_MT6873, PWRAP_MT7622, @@ -1218,11 +1341,21 @@ struct pwrap_slv_regops { int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); }; +/** + * struct pwrap_slv_type - PMIC device wrapper definitions + * @dew_regs: Device Wrapper (DeW) register offsets + * @type: PMIC Type (model) + * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device + * @comp_type: Companion PMIC Type (model) + * @regops: Register R/W ops + * @caps: Capability flags for the target device + */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; + const u32 *comp_dew_regs; + enum pmic_type comp_type; const struct pwrap_slv_regops *regops; - /* Flags indicating the capability for the target slave */ u32 caps; }; @@ -1455,6 +1588,18 @@ static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) return pwrap_write(context, adr, wdata); } +static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs, + u16 read_test_val) +{ + bool is_success; + u32 rdata; + + pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); + is_success = ((rdata & U16_MAX) == read_test_val); + + return is_success; +} + static int pwrap_reset_spislave(struct pmic_wrapper *wrp) { bool tmp; @@ -1498,18 +1643,18 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp) */ static int pwrap_init_sidly(struct pmic_wrapper *wrp) { - u32 rdata; u32 i; u32 pass = 0; + bool read_ok; signed char dly[16] = { -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 }; for (i = 0; i < 4; i++) { pwrap_writel(wrp, i, PWRAP_SIDLY); - pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], - &rdata); - if (rdata == PWRAP_DEW_READ_TEST_VAL) { + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, + PWRAP_DEW_READ_TEST_VAL); + if (read_ok) { dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); pass |= 1 << i; } @@ -1529,11 +1674,13 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp) static int pwrap_init_dual_io(struct pmic_wrapper *wrp) { int ret; - bool tmp; - u32 rdata; + bool read_ok, tmp; + bool comp_read_ok = true; /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); + if (wrp->slave->comp_dew_regs) + pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); /* Check IDLE & INIT_DONE in advance */ ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, @@ -1546,12 +1693,15 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_DIO_EN); /* Read Test */ - pwrap_read(wrp, - wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); - if (rdata != PWRAP_DEW_READ_TEST_VAL) { - dev_err(wrp->dev, - "Read failed on DIO mode: 0x%04x!=0x%04x\n", - PWRAP_DEW_READ_TEST_VAL, rdata); + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); + if (wrp->slave->comp_dew_regs) + comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, + PWRAP_DEW_COMP_READ_TEST_VAL); + if (!read_ok || !comp_read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", + !read_ok ? "fail" : "success", + wrp->slave->comp_dew_regs && !comp_read_ok ? + ", Companion PMIC fail" : ""); return -EFAULT; } @@ -1586,6 +1736,20 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6795: + if (wrp->slave->type == PMIC_MT6331) { + const u32 *dew_regs = wrp->slave->dew_regs; + + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + + if (wrp->slave->comp_type == PMIC_MT6332) { + dew_regs = wrp->slave->comp_dew_regs; + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + } + } + pwrap_writel(wrp, 0x88, PWRAP_RDDMY); + pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); + break; case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; @@ -1626,19 +1790,41 @@ static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; } -static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs) { u32 rdata; int ret; - ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], - &rdata); + ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata); if (ret) return false; return rdata == 1; } + +static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +{ + bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); + + if (!ret) + return ret; + + /* If there's any companion, wait for it to be ready too */ + if (wrp->slave->comp_dew_regs) + ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); + + return ret; +} + +static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs) +{ + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); +} + static int pwrap_init_cipher(struct pmic_wrapper *wrp) { int ret; @@ -1658,6 +1844,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT2701: case PWRAP_MT6765: case PWRAP_MT6779: + case PWRAP_MT6795: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: @@ -1675,10 +1862,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) } /* Config cipher mode @PMIC */ - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); + pwrap_config_cipher(wrp, wrp->slave->dew_regs); + + /* If there is any companion PMIC, configure cipher mode there too */ + if (wrp->slave->comp_type > 0) + pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); switch (wrp->slave->type) { case PMIC_MT6397: @@ -1740,6 +1928,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) static int pwrap_init_security(struct pmic_wrapper *wrp) { + u32 crc_val; int ret; /* Enable encryption */ @@ -1748,14 +1937,21 @@ static int pwrap_init_security(struct pmic_wrapper *wrp) return ret; /* Signature checking - using CRC */ - if (pwrap_write(wrp, - wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) - return -EFAULT; + ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); + if (ret == 0 && wrp->slave->comp_dew_regs) + ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1); pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); - pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], - PWRAP_SIG_ADR); + + /* CRC value */ + crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; + if (wrp->slave->comp_dew_regs) + crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; + + pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR); + + /* PMIC Wrapper Arbiter priority */ pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); @@ -1819,6 +2015,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) return 0; } +static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) +{ + pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); + + if (wrp->slave->type == PMIC_MT6331) + pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); + + if (wrp->slave->comp_type == PMIC_MT6332) + pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); + + return 0; +} + static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); @@ -1854,10 +2063,16 @@ static int pwrap_init(struct pmic_wrapper *wrp) if (wrp->rstc_bridge) reset_control_reset(wrp->rstc_bridge); - if (wrp->master->type == PWRAP_MT8173) { + switch (wrp->master->type) { + case PWRAP_MT6795: + fallthrough; + case PWRAP_MT8173: /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); + break; + default: + break; } if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { @@ -1982,6 +2197,16 @@ static const struct pwrap_slv_type pmic_mt6323 = { PWRAP_SLV_CAP_SECURITY, }; +static const struct pwrap_slv_type pmic_mt6331 = { + .dew_regs = mt6331_regs, + .type = PMIC_MT6331, + .comp_dew_regs = mt6332_regs, + .comp_type = PMIC_MT6332, + .regops = &pwrap_regops16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6351 = { .dew_regs = mt6351_regs, .type = PMIC_MT6351, @@ -2027,6 +2252,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { static const struct of_device_id of_slave_match_tbl[] = { { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, + { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, @@ -2079,6 +2305,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = { .init_soc_specific = NULL, }; +static const struct pmic_wrapper_type pwrap_mt6795 = { + .regs = mt6795_regs, + .type = PWRAP_MT6795, + .arb_en_all = 0x3f, + .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)), + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, + .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt6795_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6797 = { .regs = mt6797_regs, .type = PWRAP_MT6797, @@ -2212,6 +2451,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, + { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 81585733c8a9..3a2f97cd5272 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2061,9 +2061,9 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; if (svsb->type == SVSB_HIGH) - svsb->opp_dev = svs_add_device_link(svsp, "mali"); + svsb->opp_dev = svs_add_device_link(svsp, "gpu"); else if (svsb->type == SVSB_LOW) - svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); + svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); if (IS_ERR(svsb->opp_dev)) return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a491718f8064..e597799e8121 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -135,6 +135,17 @@ config QCOM_RMTFS_MEM Say y here if you intend to boot the modem remoteproc. +config QCOM_RPM_MASTER_STATS + tristate "Qualcomm RPM Master stats" + depends on ARCH_QCOM || COMPILE_TEST + help + The RPM Master sleep stats driver provides detailed per-subsystem + sleep/wake data, read from the RPM message RAM. It can be used to + assess whether all the low-power modes available are entered as + expected or to check which part of the SoC prevents it from sleeping. + + Say y here if you intend to debug or monitor platform sleep. + config QCOM_RPMH tristate "Qualcomm RPM-Hardened (RPMH) Communication" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 89b775512bef..99114c71092b 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o +obj-$(CONFIG_QCOM_RPM_MASTER_STATS) += rpm_master_stats.o obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o qcom_rpmh-y += rpmh.o diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index f65bfeca7ed6..40068a285913 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -806,7 +806,7 @@ static int bwmon_remove(struct platform_device *pdev) static const struct icc_bwmon_data msm8998_bwmon_data = { .sample_ms = 4, - .count_unit_kb = 64, + .count_unit_kb = 1024, .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ .default_medbw_kbps = 512 * 1024, /* 512 MBps */ .default_lowbw_kbps = 0, diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 33dd8c315eb7..6f177e46fa0f 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -210,6 +210,7 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, const struct elf32_hdr *ehdr; phys_addr_t min_addr = PHYS_ADDR_MAX; phys_addr_t max_addr = 0; + bool relocate = false; size_t metadata_len; void *metadata; int ret; @@ -224,6 +225,9 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, if (!mdt_phdr_valid(phdr)) continue; + if (phdr->p_flags & QCOM_MDT_RELOCATABLE) + relocate = true; + if (phdr->p_paddr < min_addr) min_addr = phdr->p_paddr; @@ -246,11 +250,13 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, goto out; } - ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); - if (ret) { - /* Unable to set up relocation */ - dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); - goto out; + if (relocate) { + ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + if (ret) { + /* Unable to set up relocation */ + dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); + goto out; + } } out: @@ -258,6 +264,34 @@ out: } EXPORT_SYMBOL_GPL(qcom_mdt_pas_init); +static bool qcom_mdt_bins_are_split(const struct firmware *fw, const char *fw_name) +{ + const struct elf32_phdr *phdrs; + const struct elf32_hdr *ehdr; + uint64_t seg_start, seg_end; + int i; + + ehdr = (struct elf32_hdr *)fw->data; + phdrs = (struct elf32_phdr *)(ehdr + 1); + + for (i = 0; i < ehdr->e_phnum; i++) { + /* + * The size of the MDT file is not padded to include any + * zero-sized segments at the end. Ignore these, as they should + * not affect the decision about image being split or not. + */ + if (!phdrs[i].p_filesz) + continue; + + seg_start = phdrs[i].p_offset; + seg_end = phdrs[i].p_offset + phdrs[i].p_filesz; + if (seg_start > fw->size || seg_end > fw->size) + return true; + } + + return false; +} + static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, @@ -270,6 +304,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, phys_addr_t min_addr = PHYS_ADDR_MAX; ssize_t offset; bool relocate = false; + bool is_split; void *ptr; int ret = 0; int i; @@ -277,6 +312,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, if (!fw || !mem_region || !mem_phys || !mem_size) return -EINVAL; + is_split = qcom_mdt_bins_are_split(fw, fw_name); ehdr = (struct elf32_hdr *)fw->data; phdrs = (struct elf32_phdr *)(ehdr + 1); @@ -330,8 +366,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ptr = mem_region + offset; - if (phdr->p_filesz && phdr->p_offset < fw->size && - phdr->p_offset + phdr->p_filesz <= fw->size) { + if (phdr->p_filesz && !is_split) { /* Firmware is large enough to be non-split */ if (phdr->p_offset + phdr->p_filesz > fw->size) { dev_err(dev, "file %s segment %d would be truncated\n", diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index 199fe9872035..aaddc3cc53b7 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -76,6 +76,10 @@ struct ocmem { #define OCMEM_REG_GFX_MPU_START 0x00001004 #define OCMEM_REG_GFX_MPU_END 0x00001008 +#define OCMEM_HW_VERSION_MAJOR(val) FIELD_GET(GENMASK(31, 28), val) +#define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val) +#define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val) + #define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val)) #define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val)) @@ -355,6 +359,12 @@ static int ocmem_dev_probe(struct platform_device *pdev) } } + reg = ocmem_read(ocmem, OCMEM_REG_HW_VERSION); + dev_dbg(dev, "OCMEM hardware version: %lu.%lu.%lu\n", + OCMEM_HW_VERSION_MAJOR(reg), + OCMEM_HW_VERSION_MINOR(reg), + OCMEM_HW_VERSION_STEP(reg)); + reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE); ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg); ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg); diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 8bf95df0a56a..c87056769ebd 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -338,13 +338,17 @@ static int pmic_glink_remove(struct platform_device *pdev) return 0; } -/* Do not handle altmode for now on those platforms */ static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_ALTMODE) | + BIT(PMIC_GLINK_CLIENT_UCSI); + +/* Do not handle altmode for now on those platforms */ +static const unsigned long pmic_glink_sm8550_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | BIT(PMIC_GLINK_CLIENT_UCSI); static const struct of_device_id pmic_glink_of_match[] = { { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, - { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8550_client_mask }, { .compatible = "qcom,pmic-glink" }, {} }; diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index dd50a255fa6c..ba788762835f 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -281,27 +281,14 @@ static void geni_se_select_fifo_mode(struct geni_se *se) geni_se_irq_clear(se); - /* - * The RX path for the UART is asynchronous and so needs more - * complex logic for enabling / disabling its interrupts. - * - * Specific notes: - * - The done and TX-related interrupts are managed manually. - * - We don't RX from the main sequencer (we use the secondary) so - * we don't need the RX-related interrupts enabled in the main - * sequencer for UART. - */ + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val |= S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); @@ -317,17 +304,14 @@ static void geni_se_select_dma_mode(struct geni_se *se) geni_se_irq_clear(se); + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val &= ~S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); @@ -344,10 +328,6 @@ static void geni_se_select_gpi_mode(struct geni_se *se) writel(0, se->base + SE_IRQ_EN); - val = readl(se->base + SE_GENI_S_IRQ_EN); - val &= ~S_CMD_DONE_EN; - writel(val, se->base + SE_GENI_S_IRQ_EN); - val = readl(se->base + SE_GENI_M_IRQ_EN); val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 820bdd9f8e46..78d7361fdcf2 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -650,7 +650,7 @@ int qmi_handle_init(struct qmi_handle *qmi, size_t recv_buf_size, if (!qmi->recv_buf) return -ENOMEM; - qmi->wq = alloc_workqueue("qmi_msg_handler", WQ_UNBOUND, 1); + qmi->wq = alloc_ordered_workqueue("qmi_msg_handler", 0); if (!qmi->wq) { ret = -ENOMEM; goto err_free_recv_buf; diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c index 5e3ba0be0903..e9a0cca07189 100644 --- a/drivers/soc/qcom/ramp_controller.c +++ b/drivers/soc/qcom/ramp_controller.c @@ -308,12 +308,15 @@ static int qcom_ramp_controller_probe(struct platform_device *pdev) return qcom_ramp_controller_start(qrc); } -static int qcom_ramp_controller_remove(struct platform_device *pdev) +static void qcom_ramp_controller_remove(struct platform_device *pdev) { struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev); + int ret; - return rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, - RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis); + ret = rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, + RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis); + if (ret) + dev_err(&pdev->dev, "Failed to send disable sequence\n"); } static const struct of_device_id qcom_ramp_controller_match_table[] = { @@ -329,7 +332,7 @@ static struct platform_driver qcom_ramp_controller_driver = { .suppress_bind_attrs = true, }, .probe = qcom_ramp_controller_probe, - .remove = qcom_ramp_controller_remove, + .remove_new = qcom_ramp_controller_remove, }; static int __init qcom_ramp_controller_init(void) diff --git a/drivers/soc/qcom/rpm_master_stats.c b/drivers/soc/qcom/rpm_master_stats.c new file mode 100644 index 000000000000..9ca13bcf67d3 --- /dev/null +++ b/drivers/soc/qcom/rpm_master_stats.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + * + * This driver supports what is known as "Master Stats v2" in Qualcomm + * downstream kernel terms, which seems to be the only version which has + * ever shipped, all the way from 2013 to 2023. + */ + +#include +#include +#include +#include +#include +#include + +struct master_stats_data { + void __iomem *base; + const char *label; +}; + +struct rpm_master_stats { + u32 active_cores; + u32 num_shutdowns; + u64 shutdown_req; + u64 wakeup_idx; + u64 bringup_req; + u64 bringup_ack; + u32 wakeup_reason; /* 0 = "rude wakeup", 1 = scheduled wakeup */ + u32 last_sleep_trans_dur; + u32 last_wake_trans_dur; + + /* Per-subsystem (*not necessarily* SoC-wide) XO shutdown stats */ + u32 xo_count; + u64 xo_last_enter; + u64 last_exit; + u64 xo_total_dur; +} __packed; + +static int master_stats_show(struct seq_file *s, void *unused) +{ + struct master_stats_data *data = s->private; + struct rpm_master_stats stat; + + memcpy_fromio(&stat, data->base, sizeof(stat)); + + seq_printf(s, "%s:\n", data->label); + + seq_printf(s, "\tLast shutdown @ %llu\n", stat.shutdown_req); + seq_printf(s, "\tLast bringup req @ %llu\n", stat.bringup_req); + seq_printf(s, "\tLast bringup ack @ %llu\n", stat.bringup_ack); + seq_printf(s, "\tLast wakeup idx: %llu\n", stat.wakeup_idx); + seq_printf(s, "\tLast XO shutdown enter @ %llu\n", stat.xo_last_enter); + seq_printf(s, "\tLast XO shutdown exit @ %llu\n", stat.last_exit); + seq_printf(s, "\tXO total duration: %llu\n", stat.xo_total_dur); + seq_printf(s, "\tLast sleep transition duration: %u\n", stat.last_sleep_trans_dur); + seq_printf(s, "\tLast wake transition duration: %u\n", stat.last_wake_trans_dur); + seq_printf(s, "\tXO shutdown count: %u\n", stat.xo_count); + seq_printf(s, "\tWakeup reason: 0x%x\n", stat.wakeup_reason); + seq_printf(s, "\tShutdown count: %u\n", stat.num_shutdowns); + seq_printf(s, "\tActive cores bitmask: 0x%x\n", stat.active_cores); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(master_stats); + +static int master_stats_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct master_stats_data *data; + struct device_node *msgram_np; + struct dentry *dent, *root; + struct resource res; + int count, i, ret; + + count = of_property_count_strings(dev->of_node, "qcom,master-names"); + if (count < 0) + return count; + + data = devm_kzalloc(dev, count * sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + root = debugfs_create_dir("qcom_rpm_master_stats", NULL); + platform_set_drvdata(pdev, root); + + for (i = 0; i < count; i++) { + msgram_np = of_parse_phandle(dev->of_node, "qcom,rpm-msg-ram", i); + if (!msgram_np) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, -ENODEV, + "Couldn't parse MSG RAM phandle idx %d", i); + } + + /* + * Purposefully skip devm_platform helpers as we're using a + * shared resource. + */ + ret = of_address_to_resource(msgram_np, 0, &res); + of_node_put(msgram_np); + if (ret < 0) { + debugfs_remove_recursive(root); + return ret; + } + + data[i].base = devm_ioremap(dev, res.start, resource_size(&res)); + if (!data[i].base) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, -EINVAL, + "Could not map the MSG RAM slice idx %d!\n", i); + } + + ret = of_property_read_string_index(dev->of_node, "qcom,master-names", i, + &data[i].label); + if (ret < 0) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, ret, + "Could not read name idx %d!\n", i); + } + + /* + * Generally it's not advised to fail on debugfs errors, but this + * driver's only job is exposing data therein. + */ + dent = debugfs_create_file(data[i].label, 0444, root, + &data[i], &master_stats_fops); + if (IS_ERR(dent)) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, PTR_ERR(dent), + "Failed to create debugfs file %s!\n", data[i].label); + } + } + + device_set_pm_not_required(dev); + + return 0; +} + +static void master_stats_remove(struct platform_device *pdev) +{ + struct dentry *root = platform_get_drvdata(pdev); + + debugfs_remove_recursive(root); +} + +static const struct of_device_id rpm_master_table[] = { + { .compatible = "qcom,rpm-master-stats" }, + { }, +}; + +static struct platform_driver master_stats_driver = { + .probe = master_stats_probe, + .remove_new = master_stats_remove, + .driver = { + .name = "qcom_rpm_master_stats", + .of_match_table = rpm_master_table, + }, +}; +module_platform_driver(master_stats_driver); + +MODULE_DESCRIPTION("Qualcomm RPM Master Statistics driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index f8397dcb146c..99b017fd76b7 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -892,8 +892,8 @@ static int rpmpd_set_performance(struct generic_pm_domain *domain, pd->corner = state; /* Always send updates for vfc and vfl */ - if (!pd->enabled && pd->key != KEY_FLOOR_CORNER && - pd->key != KEY_FLOOR_LEVEL) + if (!pd->enabled && pd->key != cpu_to_le32(KEY_FLOOR_CORNER) && + pd->key != cpu_to_le32(KEY_FLOOR_LEVEL)) goto out; ret = rpmpd_aggregate_corner(pd); diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 6be7ea93c78c..b0d59e815c3b 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -14,6 +14,7 @@ #include #include #include +#include /* * The Qualcomm shared memory system is a allocate only heap structure that @@ -500,7 +501,7 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) return ret; } -EXPORT_SYMBOL(qcom_smem_alloc); +EXPORT_SYMBOL_GPL(qcom_smem_alloc); static void *qcom_smem_get_global(struct qcom_smem *smem, unsigned item, @@ -674,7 +675,7 @@ void *qcom_smem_get(unsigned host, unsigned item, size_t *size) return ptr; } -EXPORT_SYMBOL(qcom_smem_get); +EXPORT_SYMBOL_GPL(qcom_smem_get); /** * qcom_smem_get_free_space() - retrieve amount of free space in a partition @@ -719,7 +720,7 @@ int qcom_smem_get_free_space(unsigned host) return ret; } -EXPORT_SYMBOL(qcom_smem_get_free_space); +EXPORT_SYMBOL_GPL(qcom_smem_get_free_space); static bool addr_in_range(void __iomem *base, size_t size, void *addr) { @@ -770,7 +771,29 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) return 0; } -EXPORT_SYMBOL(qcom_smem_virt_to_phys); +EXPORT_SYMBOL_GPL(qcom_smem_virt_to_phys); + +/** + * qcom_smem_get_soc_id() - return the SoC ID + * @id: On success, we return the SoC ID here. + * + * Look up SoC ID from HW/SW build ID and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_soc_id(u32 *id) +{ + struct socinfo *info; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + *id = __le32_to_cpu(info->id); + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c2e4a57dd666..4d49945b3a35 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -32,15 +33,6 @@ #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) -#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 -#define SMEM_SOCINFO_CHIP_ID_LENGTH 32 - -/* - * SMEM item id, used to acquire handles to respective - * SMEM region. - */ -#define SMEM_HW_SW_BUILD_ID 137 - #ifdef CONFIG_DEBUG_FS #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 #define SMEM_IMAGE_VERSION_SIZE 4096 @@ -126,64 +118,7 @@ static const char *const pmic_models[] = { [58] = "PM8450", [65] = "PM8010", }; -#endif /* CONFIG_DEBUG_FS */ -/* Socinfo SMEM item structure */ -struct socinfo { - __le32 fmt; - __le32 id; - __le32 ver; - char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; - /* Version 2 */ - __le32 raw_id; - __le32 raw_ver; - /* Version 3 */ - __le32 hw_plat; - /* Version 4 */ - __le32 plat_ver; - /* Version 5 */ - __le32 accessory_chip; - /* Version 6 */ - __le32 hw_plat_subtype; - /* Version 7 */ - __le32 pmic_model; - __le32 pmic_die_rev; - /* Version 8 */ - __le32 pmic_model_1; - __le32 pmic_die_rev_1; - __le32 pmic_model_2; - __le32 pmic_die_rev_2; - /* Version 9 */ - __le32 foundry_id; - /* Version 10 */ - __le32 serial_num; - /* Version 11 */ - __le32 num_pmics; - __le32 pmic_array_offset; - /* Version 12 */ - __le32 chip_family; - __le32 raw_device_family; - __le32 raw_device_num; - /* Version 13 */ - __le32 nproduct_id; - char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; - /* Version 14 */ - __le32 num_clusters; - __le32 ncluster_array_offset; - __le32 num_defective_parts; - __le32 ndefective_parts_array_offset; - /* Version 15 */ - __le32 nmodem_supported; - /* Version 16 */ - __le32 feature_code; - __le32 pcode; - __le32 npartnamemap_offset; - __le32 nnum_partname_mapping; - /* Version 17 */ - __le32 oem_variant; -}; - -#ifdef CONFIG_DEBUG_FS struct socinfo_params { u32 raw_device_family; u32 hw_plat_subtype; @@ -198,12 +133,15 @@ struct socinfo_params { u32 nproduct_id; u32 num_clusters; u32 ncluster_array_offset; - u32 num_defective_parts; - u32 ndefective_parts_array_offset; + u32 num_subset_parts; + u32 nsubset_parts_array_offset; u32 nmodem_supported; u32 feature_code; u32 pcode; u32 oem_variant; + u32 num_func_clusters; + u32 boot_cluster; + u32 boot_core; }; struct smem_image_version { @@ -434,6 +372,9 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SM8350) }, { qcom_board_id(QCM2290) }, { qcom_board_id(SM6115) }, + { qcom_board_id(IPQ5010) }, + { qcom_board_id(IPQ5018) }, + { qcom_board_id(IPQ5028) }, { qcom_board_id(SC8280XP) }, { qcom_board_id(IPQ6005) }, { qcom_board_id(QRB5165) }, @@ -447,6 +388,9 @@ static const struct soc_id soc_id[] = { { qcom_board_id_named(SM8450_3, "SM8450") }, { qcom_board_id(SC7280) }, { qcom_board_id(SC7180P) }, + { qcom_board_id(IPQ5000) }, + { qcom_board_id(IPQ0509) }, + { qcom_board_id(IPQ0518) }, { qcom_board_id(SM6375) }, { qcom_board_id(IPQ9514) }, { qcom_board_id(IPQ9550) }, @@ -454,6 +398,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ9570) }, { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, + { qcom_board_id(IPQ5016) }, { qcom_board_id(IPQ9510) }, { qcom_board_id(QRB4210) }, { qcom_board_id(QRB2210) }, @@ -461,11 +406,15 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, { qcom_board_id(QDU1010) }, + { qcom_board_id(IPQ5019) }, { qcom_board_id(QRU1032) }, { qcom_board_id(QRU1052) }, { qcom_board_id(QRU1062) }, { qcom_board_id(IPQ5332) }, { qcom_board_id(IPQ5322) }, + { qcom_board_id(IPQ5312) }, + { qcom_board_id(IPQ5302) }, + { qcom_board_id(IPQ5300) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) @@ -620,6 +569,19 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 19): + qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters); + qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster); + qcom_socinfo->info.boot_core = __le32_to_cpu(info->boot_core); + + debugfs_create_u32("num_func_clusters", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.num_func_clusters); + debugfs_create_u32("boot_cluster", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.boot_cluster); + debugfs_create_u32("boot_core", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.boot_core); + fallthrough; + case SOCINFO_VERSION(0, 18): case SOCINFO_VERSION(0, 17): qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant); debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root, @@ -643,17 +605,18 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, case SOCINFO_VERSION(0, 14): qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); - qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts); - qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset); + qcom_socinfo->info.num_subset_parts = __le32_to_cpu(info->num_subset_parts); + qcom_socinfo->info.nsubset_parts_array_offset = + __le32_to_cpu(info->nsubset_parts_array_offset); debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.num_clusters); debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.ncluster_array_offset); - debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root, - &qcom_socinfo->info.num_defective_parts); - debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root, - &qcom_socinfo->info.ndefective_parts_array_offset); + debugfs_create_u32("num_subset_parts", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.num_subset_parts); + debugfs_create_u32("nsubset_parts_array_offset", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.nsubset_parts_array_offset); fallthrough; case SOCINFO_VERSION(0, 13): qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index e1c7e91f5a86..98fd97da6cd4 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -12,6 +12,7 @@ #define WDTRSTCR_RESET 0xA55A0002 #define WDTRSTCR 0x0054 +#define GEN4_WDTRSTCR 0x0010 #define CR7BAR 0x0070 #define CR7BAREN BIT(4) @@ -27,6 +28,12 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base) return 0; } +static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base) +{ + iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR); + return 0; +} + /* * Most of the R-Car Gen3 SoCs have an ARM Realtime Core. * Firmware boot address has to be set in CR7BAR before @@ -66,6 +73,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = { .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; +/* V3U firmware doesn't enable WDT reset and there won't be updates anymore */ +static const struct rst_config rcar_rst_v3u __initconst = { + .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ + .configure = rcar_rst_v3u_enable_wdt_reset, +}; + static const struct rst_config rcar_rst_gen4 __initconst = { .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ }; @@ -101,7 +114,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, /* R-Car Gen4 */ - { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 }, + { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u }, { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, { .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 }, { /* sentinel */ } diff --git a/drivers/soc/renesas/rmobile-sysc.c b/drivers/soc/renesas/rmobile-sysc.c index 728ebac98e14..912daadaa10d 100644 --- a/drivers/soc/renesas/rmobile-sysc.c +++ b/drivers/soc/renesas/rmobile-sysc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -19,8 +21,6 @@ #include #include -#include - /* SYSC */ #define SPDCR 0x08 /* SYS Power Down Control Register */ #define SWUCR 0x14 /* SYS Wakeup Control Register */ @@ -47,6 +47,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) { struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); unsigned int mask = BIT(rmobile_pd->bit_shift); + u32 val; if (rmobile_pd->suspend) { int ret = rmobile_pd->suspend(); @@ -56,14 +57,10 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) } if (readl(rmobile_pd->base + PSTR) & mask) { - unsigned int retry_count; writel(mask, rmobile_pd->base + SPDCR); - for (retry_count = PSTR_RETRIES; retry_count; retry_count--) { - if (!(readl(rmobile_pd->base + SPDCR) & mask)) - break; - cpu_relax(); - } + readl_poll_timeout_atomic(rmobile_pd->base + SPDCR, val, + !(val & mask), 0, PSTR_RETRIES); } pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask, @@ -74,8 +71,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) { - unsigned int mask = BIT(rmobile_pd->bit_shift); - unsigned int retry_count; + unsigned int val, mask = BIT(rmobile_pd->bit_shift); int ret = 0; if (readl(rmobile_pd->base + PSTR) & mask) @@ -83,16 +79,9 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) writel(mask, rmobile_pd->base + SWUCR); - for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) { - if (!(readl(rmobile_pd->base + SWUCR) & mask)) - break; - if (retry_count > PSTR_RETRIES) - udelay(PSTR_DELAY_US); - else - cpu_relax(); - } - if (!retry_count) - ret = -EIO; + ret = readl_poll_timeout_atomic(rmobile_pd->base + SWUCR, val, + (val & mask), PSTR_DELAY_US, + PSTR_RETRIES * PSTR_DELAY_US); pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n", rmobile_pd->genpd.name, mask, diff --git a/drivers/soc/rockchip/dtpm.c b/drivers/soc/rockchip/dtpm.c index 5a23784b5221..b36d4f752c30 100644 --- a/drivers/soc/rockchip/dtpm.c +++ b/drivers/soc/rockchip/dtpm.c @@ -12,33 +12,33 @@ #include static struct dtpm_node __initdata rk3399_hierarchy[] = { - [0]{ .name = "rk3399", - .type = DTPM_NODE_VIRTUAL }, - [1]{ .name = "package", - .type = DTPM_NODE_VIRTUAL, - .parent = &rk3399_hierarchy[0] }, - [2]{ .name = "/cpus/cpu@0", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [3]{ .name = "/cpus/cpu@1", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [4]{ .name = "/cpus/cpu@2", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [5]{ .name = "/cpus/cpu@3", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [6]{ .name = "/cpus/cpu@100", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [7]{ .name = "/cpus/cpu@101", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [8]{ .name = "/gpu@ff9a0000", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [9]{ /* sentinel */ } + [0] = { .name = "rk3399", + .type = DTPM_NODE_VIRTUAL }, + [1] = { .name = "package", + .type = DTPM_NODE_VIRTUAL, + .parent = &rk3399_hierarchy[0] }, + [2] = { .name = "/cpus/cpu@0", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [3] = { .name = "/cpus/cpu@1", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [4] = { .name = "/cpus/cpu@2", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [5] = { .name = "/cpus/cpu@3", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [6] = { .name = "/cpus/cpu@100", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [7] = { .name = "/cpus/cpu@101", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [8] = { .name = "/gpu@ff9a0000", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [9] = { /* sentinel */ } }; static struct of_device_id __initdata rockchip_dtpm_match_table[] = { diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 84bc022f9e5b..e3de49e671dc 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -43,8 +43,10 @@ struct rockchip_domain_info { bool active_wakeup; int pwr_w_mask; int req_w_mask; + int mem_status_mask; int repair_status_mask; u32 pwr_offset; + u32 mem_offset; u32 req_offset; }; @@ -54,6 +56,9 @@ struct rockchip_pmu_info { u32 req_offset; u32 idle_offset; u32 ack_offset; + u32 mem_pwr_offset; + u32 chain_status_offset; + u32 mem_status_offset; u32 repair_status_offset; u32 core_pwrcnt_offset; @@ -119,13 +124,15 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \ +#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ { \ .name = _name, \ .pwr_offset = p_offset, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ + .mem_offset = m_offset, \ + .mem_status_mask = (m_status), \ .repair_status_mask = (r_status), \ .req_offset = r_offset, \ .req_w_mask = (req) << 16, \ @@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void) } EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); -#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ - DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup) +#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \ + DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) return !(val & pd->info->status_mask); } +static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + unsigned int val; + + regmap_read(pmu->regmap, + pmu->info->mem_status_offset + pd->info->mem_offset, &val); + + /* 1'b0: power on, 1'b1: power off */ + return !(val & pd->info->mem_status_mask); +} + +static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + unsigned int val; + + regmap_read(pmu->regmap, + pmu->info->chain_status_offset + pd->info->mem_offset, &val); + + /* 1'b1: power on, 1'b0: power off */ + return val & pd->info->mem_status_mask; +} + +static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + struct generic_pm_domain *genpd = &pd->genpd; + bool is_on; + int ret = 0; + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on, + is_on == true, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get chain status '%s', target_on=1, val=%d\n", + genpd->name, is_on); + goto error; + } + + udelay(20); + + regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, + (pd->info->pwr_mask | pd->info->pwr_w_mask)); + wmb(); + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, + is_on == false, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get mem status '%s', target_on=0, val=%d\n", + genpd->name, is_on); + goto error; + } + + regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, + pd->info->pwr_w_mask); + wmb(); + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, + is_on == true, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get mem status '%s', target_on=1, val=%d\n", + genpd->name, is_on); + } + +error: + return ret; +} + static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, bool on) { struct rockchip_pmu *pmu = pd->pmu; struct generic_pm_domain *genpd = &pd->genpd; u32 pd_pwr_offset = pd->info->pwr_offset; - bool is_on; + bool is_on, is_mem_on = false; if (pd->info->pwr_mask == 0) return; - else if (pd->info->pwr_w_mask) + + if (on && pd->info->mem_status_mask) + is_mem_on = rockchip_pmu_domain_is_mem_on(pd); + + if (pd->info->pwr_w_mask) regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, on ? pd->info->pwr_w_mask : (pd->info->pwr_mask | pd->info->pwr_w_mask)); @@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, wmb(); + if (is_mem_on && rockchip_pmu_domain_mem_reset(pd)) + return; + if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, is_on == on, 0, 10000)) { dev_err(pmu->dev, @@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, pd->genpd.flags = GENPD_FLAG_PM_CLK; if (pd_info->active_wakeup) pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; - pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd)); + pm_genpd_init(&pd->genpd, NULL, + !rockchip_pmu_domain_is_on(pd) || + (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); pmu->genpd_data.domains[id] = &pd->genpd; return 0; @@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { }; static const struct rockchip_domain_info rk3588_pm_domains[] = { - [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false), - [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false), - [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false), - [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false), - [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false), - [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false), - [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false), - [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false), - [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false), - [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false), - [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false), - [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false), - [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false), - [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false), - [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false), - [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false), - [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false), - [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), - [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false), - [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false), - [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false), - [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false), - [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false), - [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true), - [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false), - [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false), - [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false), - [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true), - [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false), + [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), + [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), + [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false), + [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false), + [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false), + [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false), + [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false), + [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false), + [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false), + [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false), + [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false), + [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false), + [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false), + [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false), + [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false), + [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false), + [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false), + [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), + [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false), + [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false), + [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false), + [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false), + [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false), + [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true), + [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false), + [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false), + [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false), + [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true), + [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false), }; static const struct rockchip_pmu_info px30_pmu = { @@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = { .req_offset = 0x10c, .idle_offset = 0x120, .ack_offset = 0x118, + .mem_pwr_offset = 0x1a0, + .chain_status_offset = 0x1f0, + .mem_status_offset = 0x1f8, .repair_status_offset = 0x290, .num_domains = ARRAY_SIZE(rk3588_pm_domains), diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 732c86ce2be8..5b2664da9853 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -57,6 +57,12 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) if (pmu_data->powerdown_conf_extra) pmu_data->powerdown_conf_extra(mode); + + if (pmu_data->pmu_config_extra) { + for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) + pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], + pmu_data->pmu_config_extra[i].offset); + } } /* @@ -79,6 +85,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos4210-pmu", .data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data), + }, { + .compatible = "samsung,exynos4212-pmu", + .data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data), }, { .compatible = "samsung,exynos4412-pmu", .data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data), diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 5e851f32307e..1c652ffd79b4 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -20,6 +20,7 @@ struct exynos_pmu_conf { struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; + const struct exynos_pmu_conf *pmu_config_extra; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); @@ -32,6 +33,7 @@ extern void __iomem *pmu_base_addr; /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; +extern const struct exynos_pmu_data exynos4212_pmu_data; extern const struct exynos_pmu_data exynos4412_pmu_data; extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; diff --git a/drivers/soc/samsung/exynos4-pmu.c b/drivers/soc/samsung/exynos4-pmu.c index cb35103565a6..f8092190b938 100644 --- a/drivers/soc/samsung/exynos4-pmu.c +++ b/drivers/soc/samsung/exynos4-pmu.c @@ -86,7 +86,7 @@ static const struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -191,6 +191,10 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -204,6 +208,11 @@ const struct exynos_pmu_data exynos4210_pmu_data = { .pmu_config = exynos4210_pmu_config, }; -const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4412_pmu_config, +const struct exynos_pmu_data exynos4212_pmu_data = { + .pmu_config = exynos4x12_pmu_config, +}; + +const struct exynos_pmu_data exynos4412_pmu_data = { + .pmu_config = exynos4x12_pmu_config, + .pmu_config_extra = exynos4412_pmu_config, }; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 932a03c64534..c759fb7c8adc 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -663,7 +663,7 @@ static const struct nvmem_keepout tegra234_fuse_keepouts[] = { static const struct tegra_fuse_info tegra234_fuse_info = { .read = tegra30_fuse_read, - .size = 0x98c, + .size = 0xf90, .spare = 0x280, }; diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 4591c5bcb690..eb0a1d924526 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. */ #include @@ -62,6 +62,7 @@ bool tegra_is_silicon(void) switch (tegra_get_chip_id()) { case TEGRA194: case TEGRA234: + case TEGRA264: if (tegra_get_platform() == 0) return true; diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 5d17799524c9..162f52456f65 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -396,7 +396,6 @@ struct tegra_pmc_soc { * @clk: pointer to pclk clock * @soc: pointer to SoC data structure * @tz_only: flag specifying if the PMC can only be accessed via TrustZone - * @debugfs: pointer to debugfs entry * @rate: currently configured rate of pclk * @suspend_mode: lowest suspend mode available * @cpu_good_time: CPU power good time (in microseconds) @@ -431,7 +430,6 @@ struct tegra_pmc { void __iomem *aotag; void __iomem *scratch; struct clk *clk; - struct dentry *debugfs; const struct tegra_pmc_soc *soc; bool tz_only; @@ -1190,16 +1188,6 @@ static int powergate_show(struct seq_file *s, void *data) DEFINE_SHOW_ATTRIBUTE(powergate); -static int tegra_powergate_debugfs_init(void) -{ - pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, - &powergate_fops); - if (!pmc->debugfs) - return -ENOMEM; - - return 0; -} - static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, struct device_node *np) { @@ -3004,7 +2992,8 @@ static int tegra_pmc_probe(struct platform_device *pdev) */ if (pmc->clk) { pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; - err = clk_notifier_register(pmc->clk, &pmc->clk_nb); + err = devm_clk_notifier_register(&pdev->dev, pmc->clk, + &pmc->clk_nb); if (err) { dev_err(&pdev->dev, "failed to register clk notifier\n"); @@ -3026,19 +3015,13 @@ static int tegra_pmc_probe(struct platform_device *pdev) tegra_pmc_reset_sysfs_init(pmc); - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_powergate_debugfs_init(); - if (err < 0) - goto cleanup_sysfs; - } - err = tegra_pmc_pinctrl_init(pmc); if (err) - goto cleanup_debugfs; + goto cleanup_sysfs; err = tegra_pmc_regmap_init(pmc); if (err < 0) - goto cleanup_debugfs; + goto cleanup_sysfs; err = tegra_powergate_init(pmc, pdev->dev.of_node); if (err < 0) @@ -3061,16 +3044,15 @@ static int tegra_pmc_probe(struct platform_device *pdev) if (pmc->soc->set_wake_filters) pmc->soc->set_wake_filters(pmc); + debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); + return 0; cleanup_powergates: tegra_powergate_remove_all(pdev->dev.of_node); -cleanup_debugfs: - debugfs_remove(pmc->debugfs); cleanup_sysfs: device_remove_file(&pdev->dev, &dev_attr_reset_reason); device_remove_file(&pdev->dev, &dev_attr_reset_level); - clk_notifier_unregister(pmc->clk, &pmc->clk_nb); return err; } @@ -4250,6 +4232,7 @@ static const struct tegra_wake_event tegra234_wake_events[] = { TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), TEGRA_WAKE_IRQ("rtc", 73, 10), + TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), }; static const struct tegra_pmc_soc tegra234_pmc_soc = { diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 8c2a1036bef5..2cae17b65fd9 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -85,7 +85,7 @@ config TI_K3_SOCINFO config TI_PRUSS tristate "TI PRU-ICSS Subsystem Platform drivers" - depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 + depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST select MFD_SYSCON help TI PRU-ICSS Subsystem platform specific support. diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 6882c86b3ce5..7fdefee1ed87 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -6,6 +6,7 @@ * Author(s): * Suman Anna * Andrew F. Davis + * Tero Kristo */ #include @@ -18,7 +19,9 @@ #include #include #include +#include #include +#include "pruss.h" /** * struct pruss_private_data - PRUSS driver private data @@ -30,6 +33,257 @@ struct pruss_private_data { bool has_core_mux_clock; }; +/** + * pruss_get() - get the pruss for a given PRU remoteproc + * @rproc: remoteproc handle of a PRU instance + * + * Finds the parent pruss device for a PRU given the @rproc handle of the + * PRU remote processor. This function increments the pruss device's refcount, + * so always use pruss_put() to decrement it back once pruss isn't needed + * anymore. + * + * This API doesn't check if @rproc is valid or not. It is expected the caller + * will have done a pru_rproc_get() on @rproc, before calling this API to make + * sure that @rproc is valid. + * + * Return: pruss handle on success, and an ERR_PTR on failure using one + * of the following error values + * -EINVAL if invalid parameter + * -ENODEV if PRU device or PRUSS device is not found + */ +struct pruss *pruss_get(struct rproc *rproc) +{ + struct pruss *pruss; + struct device *dev; + struct platform_device *ppdev; + + if (IS_ERR_OR_NULL(rproc)) + return ERR_PTR(-EINVAL); + + dev = &rproc->dev; + + /* make sure it is PRU rproc */ + if (!dev->parent || !is_pru_rproc(dev->parent)) + return ERR_PTR(-ENODEV); + + ppdev = to_platform_device(dev->parent->parent); + pruss = platform_get_drvdata(ppdev); + if (!pruss) + return ERR_PTR(-ENODEV); + + get_device(pruss->dev); + + return pruss; +} +EXPORT_SYMBOL_GPL(pruss_get); + +/** + * pruss_put() - decrement pruss device's usecount + * @pruss: pruss handle + * + * Complimentary function for pruss_get(). Needs to be called + * after the PRUSS is used, and only if the pruss_get() succeeds. + */ +void pruss_put(struct pruss *pruss) +{ + if (IS_ERR_OR_NULL(pruss)) + return; + + put_device(pruss->dev); +} +EXPORT_SYMBOL_GPL(pruss_put); + +/** + * pruss_request_mem_region() - request a memory resource + * @pruss: the pruss instance + * @mem_id: the memory resource id + * @region: pointer to memory region structure to be filled in + * + * This function allows a client driver to request a memory resource, + * and if successful, will let the client driver own the particular + * memory region until released using the pruss_release_mem_region() + * API. + * + * Return: 0 if requested memory region is available (in such case pointer to + * memory region is returned via @region), an error otherwise + */ +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + if (!pruss || !region || mem_id >= PRUSS_MEM_MAX) + return -EINVAL; + + mutex_lock(&pruss->lock); + + if (pruss->mem_in_use[mem_id]) { + mutex_unlock(&pruss->lock); + return -EBUSY; + } + + *region = pruss->mem_regions[mem_id]; + pruss->mem_in_use[mem_id] = region; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_request_mem_region); + +/** + * pruss_release_mem_region() - release a memory resource + * @pruss: the pruss instance + * @region: the memory region to release + * + * This function is the complimentary function to + * pruss_request_mem_region(), and allows the client drivers to + * release back a memory resource. + * + * Return: 0 on success, an error code otherwise + */ +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + int id; + + if (!pruss || !region) + return -EINVAL; + + mutex_lock(&pruss->lock); + + /* find out the memory region being released */ + for (id = 0; id < PRUSS_MEM_MAX; id++) { + if (pruss->mem_in_use[id] == region) + break; + } + + if (id == PRUSS_MEM_MAX) { + mutex_unlock(&pruss->lock); + return -EINVAL; + } + + pruss->mem_in_use[id] = NULL; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_release_mem_region); + +/** + * pruss_cfg_get_gpmux() - get the current GPMUX value for a PRU device + * @pruss: pruss instance + * @pru_id: PRU identifier (0-1) + * @mux: pointer to store the current mux value into + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux) +{ + int ret; + u32 val; + + if (pru_id >= PRUSS_NUM_PRUS || !mux) + return -EINVAL; + + ret = pruss_cfg_read(pruss, PRUSS_CFG_GPCFG(pru_id), &val); + if (!ret) + *mux = (u8)((val & PRUSS_GPCFG_PRU_MUX_SEL_MASK) >> + PRUSS_GPCFG_PRU_MUX_SEL_SHIFT); + return ret; +} +EXPORT_SYMBOL_GPL(pruss_cfg_get_gpmux); + +/** + * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device + * @pruss: pruss instance + * @pru_id: PRU identifier (0-1) + * @mux: new mux value for PRU + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux) +{ + if (mux >= PRUSS_GP_MUX_SEL_MAX || + pru_id >= PRUSS_NUM_PRUS) + return -EINVAL; + + return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id), + PRUSS_GPCFG_PRU_MUX_SEL_MASK, + (u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT); +} +EXPORT_SYMBOL_GPL(pruss_cfg_set_gpmux); + +/** + * pruss_cfg_gpimode() - set the GPI mode of the PRU + * @pruss: the pruss instance handle + * @pru_id: id of the PRU core within the PRUSS + * @mode: GPI mode to set + * + * Sets the GPI mode for a given PRU by programming the + * corresponding PRUSS_CFG_GPCFGx register + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_gpimode(struct pruss *pruss, enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode) +{ + if (pru_id >= PRUSS_NUM_PRUS || mode >= PRUSS_GPI_MODE_MAX) + return -EINVAL; + + return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id), + PRUSS_GPCFG_PRU_GPI_MODE_MASK, + mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT); +} +EXPORT_SYMBOL_GPL(pruss_cfg_gpimode); + +/** + * pruss_cfg_miirt_enable() - Enable/disable MII RT Events + * @pruss: the pruss instance + * @enable: enable/disable + * + * Enable/disable the MII RT Events for the PRUSS. + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable) +{ + u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0; + + return pruss_cfg_update(pruss, PRUSS_CFG_MII_RT, + PRUSS_MII_RT_EVENT_EN, set); +} +EXPORT_SYMBOL_GPL(pruss_cfg_miirt_enable); + +/** + * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality + * @pruss: the pruss instance + * @pru_type: PRU core type identifier + * @enable: enable/disable + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_xfr_enable(struct pruss *pruss, enum pru_type pru_type, + bool enable) +{ + u32 mask, set; + + switch (pru_type) { + case PRU_TYPE_PRU: + mask = PRUSS_SPP_XFER_SHIFT_EN; + break; + case PRU_TYPE_RTU: + mask = PRUSS_SPP_RTU_XFR_SHIFT_EN; + break; + default: + return -EINVAL; + } + + set = enable ? mask : 0; + + return pruss_cfg_update(pruss, PRUSS_CFG_SPP, mask, set); +} +EXPORT_SYMBOL_GPL(pruss_cfg_xfr_enable); + static void pruss_of_free_clk_provider(void *data) { struct device_node *clk_mux_np = data; @@ -38,6 +292,11 @@ static void pruss_of_free_clk_provider(void *data) of_node_put(clk_mux_np); } +static void pruss_clk_unregister_mux(void *data) +{ + clk_unregister_mux(data); +} + static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux, char *mux_name, struct device_node *clks_np) { @@ -93,8 +352,7 @@ static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux, goto put_clk_mux_np; } - ret = devm_add_action_or_reset(dev, (void(*)(void *))clk_unregister_mux, - clk_mux); + ret = devm_add_action_or_reset(dev, pruss_clk_unregister_mux, clk_mux); if (ret) { dev_err(dev, "failed to add clkmux unregister action %d", ret); goto put_clk_mux_np; @@ -232,6 +490,7 @@ static int pruss_probe(struct platform_device *pdev) return -ENOMEM; pruss->dev = dev; + mutex_init(&pruss->lock); child = of_get_child_by_name(np, "memories"); if (!child) { diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h new file mode 100644 index 000000000000..6c55987e0e55 --- /dev/null +++ b/drivers/soc/ti/pruss.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PRU-ICSS Subsystem user interfaces + * + * Copyright (C) 2015-2023 Texas Instruments Incorporated - http://www.ti.com + * MD Danish Anwar + */ + +#ifndef _SOC_TI_PRUSS_H_ +#define _SOC_TI_PRUSS_H_ + +#include +#include + +/* + * PRU_ICSS_CFG registers + * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only + */ +#define PRUSS_CFG_REVID 0x00 +#define PRUSS_CFG_SYSCFG 0x04 +#define PRUSS_CFG_GPCFG(x) (0x08 + (x) * 4) +#define PRUSS_CFG_CGR 0x10 +#define PRUSS_CFG_ISRP 0x14 +#define PRUSS_CFG_ISP 0x18 +#define PRUSS_CFG_IESP 0x1C +#define PRUSS_CFG_IECP 0x20 +#define PRUSS_CFG_SCRP 0x24 +#define PRUSS_CFG_PMAO 0x28 +#define PRUSS_CFG_MII_RT 0x2C +#define PRUSS_CFG_IEPCLK 0x30 +#define PRUSS_CFG_SPP 0x34 +#define PRUSS_CFG_PIN_MX 0x40 + +/* PRUSS_GPCFG register bits */ +#define PRUSS_GPCFG_PRU_GPI_MODE_MASK GENMASK(1, 0) +#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT 0 + +#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT 26 +#define PRUSS_GPCFG_PRU_MUX_SEL_MASK GENMASK(29, 26) + +/* PRUSS_MII_RT register bits */ +#define PRUSS_MII_RT_EVENT_EN BIT(0) + +/* PRUSS_SPP register bits */ +#define PRUSS_SPP_XFER_SHIFT_EN BIT(1) +#define PRUSS_SPP_PRU1_PAD_HP_EN BIT(0) +#define PRUSS_SPP_RTU_XFR_SHIFT_EN BIT(3) + +/** + * pruss_cfg_read() - read a PRUSS CFG sub-module register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @val: pointer to return the value in + * + * Reads a given register within the PRUSS CFG sub-module and + * returns it through the passed-in @val pointer + * + * Return: 0 on success, or an error code otherwise + */ +static int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_read(pruss->cfg_regmap, reg, val); +} + +/** + * pruss_cfg_update() - configure a PRUSS CFG sub-module register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @mask: bit mask to use for programming the @val + * @val: value to write + * + * Programs a given register within the PRUSS CFG sub-module + * + * Return: 0 on success, or an error code otherwise + */ +static int pruss_cfg_update(struct pruss *pruss, unsigned int reg, + unsigned int mask, unsigned int val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_update_bits(pruss->cfg_regmap, reg, mask, val); +} + +#endif /* _SOC_TI_PRUSS_H_ */ diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index da7898239a46..62b2f1464e46 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -815,7 +815,6 @@ static int omap_sr_probe(struct platform_device *pdev) { struct omap_sr *sr_info; struct omap_sr_data *pdata = pdev->dev.platform_data; - struct resource *mem; struct dentry *nvalue_dir; int i, ret = 0; @@ -835,8 +834,7 @@ static int omap_sr_probe(struct platform_device *pdev) return -EINVAL; } - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sr_info->base = devm_ioremap_resource(&pdev->dev, mem); + sr_info->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sr_info->base)) return PTR_ERR(sr_info->base); diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index c9197912ec24..3aff106fc11a 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -202,7 +202,7 @@ static int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc) { m3_ipc->dbg_path = debugfs_create_dir("wkup_m3_ipc", NULL); - if (!m3_ipc->dbg_path) + if (IS_ERR(m3_ipc->dbg_path)) return -EINVAL; (void)debugfs_create_file("enable_late_halt", 0644, diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c index c76381899ef4..f9d9b82b562d 100644 --- a/drivers/soc/xilinx/xlnx_event_manager.c +++ b/drivers/soc/xilinx/xlnx_event_manager.c @@ -192,11 +192,12 @@ static int xlnx_remove_cb_for_suspend(event_cb_func_t cb_fun) struct registered_event_data *eve_data; struct agent_cb *cb_pos; struct agent_cb *cb_next; + struct hlist_node *tmp; is_need_to_unregister = false; /* Check for existing entry in hash table for given cb_type */ - hash_for_each_possible(reg_driver_map, eve_data, hentry, PM_INIT_SUSPEND_CB) { + hash_for_each_possible_safe(reg_driver_map, eve_data, tmp, hentry, PM_INIT_SUSPEND_CB) { if (eve_data->cb_type == PM_INIT_SUSPEND_CB) { /* Delete the list of callback */ list_for_each_entry_safe(cb_pos, cb_next, &eve_data->cb_list_head, list) { @@ -228,11 +229,12 @@ static int xlnx_remove_cb_for_notify_event(const u32 node_id, const u32 event, u64 key = ((u64)node_id << 32U) | (u64)event; struct agent_cb *cb_pos; struct agent_cb *cb_next; + struct hlist_node *tmp; is_need_to_unregister = false; /* Check for existing entry in hash table for given key id */ - hash_for_each_possible(reg_driver_map, eve_data, hentry, key) { + hash_for_each_possible_safe(reg_driver_map, eve_data, tmp, hentry, key) { if (eve_data->key == key) { /* Delete the list of callback */ list_for_each_entry_safe(cb_pos, cb_next, &eve_data->cb_list_head, list) { diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 78a8a7545d1e..641dcc958911 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -218,7 +218,7 @@ static int zynqmp_pm_probe(struct platform_device *pdev) } else if (ret != -EACCES && ret != -ENODEV) { dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret); return ret; - } else if (of_find_property(pdev->dev.of_node, "mboxes", NULL)) { + } else if (of_property_present(pdev->dev.of_node, "mboxes")) { zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev, sizeof(struct zynqmp_pm_work_struct), @@ -240,7 +240,7 @@ static int zynqmp_pm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Failed to request rx channel\n"); return PTR_ERR(rx_chan); } - } else if (of_find_property(pdev->dev.of_node, "interrupts", NULL)) { + } else if (of_property_present(pdev->dev.of_node, "interrupts")) { irq = platform_get_irq(pdev, 0); if (irq <= 0) return -ENXIO; diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 3861ae06d902..d5b28fd35d66 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -1541,12 +1541,11 @@ static int optee_load_fw(struct platform_device *pdev, * This uses the GFP_DMA flag to ensure we are allocated memory in the * 32-bit space since TF-A cannot map memory beyond the 32-bit boundary. */ - data_buf = kmalloc(fw->size, GFP_KERNEL | GFP_DMA); + data_buf = kmemdup(fw->data, fw->size, GFP_KERNEL | GFP_DMA); if (!data_buf) { rc = -ENOMEM; goto fw_err; } - memcpy(data_buf, fw->data, fw->size); data_pa = virt_to_phys(data_buf); reg_pair_from_64(&data_pa_high, &data_pa_low, data_pa); reg_pair_from_64(&data_size_high, &data_size_low, data_size); diff --git a/drivers/usb/gadget/udc/pxa27x_udc.c b/drivers/usb/gadget/udc/pxa27x_udc.c index 0ecdfd2ba9e9..fdf9cd4506b0 100644 --- a/drivers/usb/gadget/udc/pxa27x_udc.c +++ b/drivers/usb/gadget/udc/pxa27x_udc.c @@ -2472,12 +2472,6 @@ static void pxa_udc_shutdown(struct platform_device *_dev) udc_disable(udc); } -#ifdef CONFIG_PXA27x -extern void pxa27x_clear_otgph(void); -#else -#define pxa27x_clear_otgph() do {} while (0) -#endif - #ifdef CONFIG_PM /** * pxa_udc_suspend - Suspend udc device diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index 0bc7e96bcc93..dcac2938789a 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -263,12 +264,6 @@ static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci) __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); } -#ifdef CONFIG_PXA27x -extern void pxa27x_clear_otgph(void); -#else -#define pxa27x_clear_otgph() do {} while (0) -#endif - static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) { int retval; diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c b/drivers/vfio/fsl-mc/vfio_fsl_mc.c index c89a047a4cd8..f2140e94d41e 100644 --- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c @@ -570,7 +570,7 @@ static void vfio_fsl_mc_release_dev(struct vfio_device *core_vdev) mutex_destroy(&vdev->igate); } -static int vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) +static void vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; struct vfio_fsl_mc_device *vdev = dev_get_drvdata(dev); @@ -578,7 +578,6 @@ static int vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) vfio_unregister_group_dev(&vdev->vdev); dprc_remove_devices(mc_dev, NULL, 0); vfio_put_device(&vdev->vdev); - return 0; } static const struct vfio_device_ops vfio_fsl_mc_ops = { diff --git a/fs/buffer.c b/fs/buffer.c index cdd100273450..bd091329026c 100644 --- a/fs/buffer.c +++ b/fs/buffer.c @@ -591,6 +591,76 @@ int sync_mapping_buffers(struct address_space *mapping) } EXPORT_SYMBOL(sync_mapping_buffers); +/** + * generic_buffers_fsync_noflush - generic buffer fsync implementation + * for simple filesystems with no inode lock + * + * @file: file to synchronize + * @start: start offset in bytes + * @end: end offset in bytes (inclusive) + * @datasync: only synchronize essential metadata if true + * + * This is a generic implementation of the fsync method for simple + * filesystems which track all non-inode metadata in the buffers list + * hanging off the address_space structure. + */ +int generic_buffers_fsync_noflush(struct file *file, loff_t start, loff_t end, + bool datasync) +{ + struct inode *inode = file->f_mapping->host; + int err; + int ret; + + err = file_write_and_wait_range(file, start, end); + if (err) + return err; + + ret = sync_mapping_buffers(inode->i_mapping); + if (!(inode->i_state & I_DIRTY_ALL)) + goto out; + if (datasync && !(inode->i_state & I_DIRTY_DATASYNC)) + goto out; + + err = sync_inode_metadata(inode, 1); + if (ret == 0) + ret = err; + +out: + /* check and advance again to catch errors after syncing out buffers */ + err = file_check_and_advance_wb_err(file); + if (ret == 0) + ret = err; + return ret; +} +EXPORT_SYMBOL(generic_buffers_fsync_noflush); + +/** + * generic_buffers_fsync - generic buffer fsync implementation + * for simple filesystems with no inode lock + * + * @file: file to synchronize + * @start: start offset in bytes + * @end: end offset in bytes (inclusive) + * @datasync: only synchronize essential metadata if true + * + * This is a generic implementation of the fsync method for simple + * filesystems which track all non-inode metadata in the buffers list + * hanging off the address_space structure. This also makes sure that + * a device cache flush operation is called at the end. + */ +int generic_buffers_fsync(struct file *file, loff_t start, loff_t end, + bool datasync) +{ + struct inode *inode = file->f_mapping->host; + int ret; + + ret = generic_buffers_fsync_noflush(file, start, end, datasync); + if (!ret) + ret = blkdev_issue_flush(inode->i_sb->s_bdev); + return ret; +} +EXPORT_SYMBOL(generic_buffers_fsync); + /* * Called when we've recently written block `bblock', and it is known that * `bblock' was for a buffer_boundary() buffer. This means that the block at diff --git a/fs/dlm/ast.c b/fs/dlm/ast.c index 700ff2e0515a..1f2f70a1b824 100644 --- a/fs/dlm/ast.c +++ b/fs/dlm/ast.c @@ -36,23 +36,6 @@ void dlm_callback_set_last_ptr(struct dlm_callback **from, *from = to; } -void dlm_purge_lkb_callbacks(struct dlm_lkb *lkb) -{ - struct dlm_callback *cb, *safe; - - list_for_each_entry_safe(cb, safe, &lkb->lkb_callbacks, list) { - list_del(&cb->list); - kref_put(&cb->ref, dlm_release_callback); - } - - clear_bit(DLM_IFL_CB_PENDING_BIT, &lkb->lkb_iflags); - - /* invalidate */ - dlm_callback_set_last_ptr(&lkb->lkb_last_cast, NULL); - dlm_callback_set_last_ptr(&lkb->lkb_last_cb, NULL); - lkb->lkb_last_bast_mode = -1; -} - int dlm_enqueue_lkb_callback(struct dlm_lkb *lkb, uint32_t flags, int mode, int status, uint32_t sbflags) { @@ -181,10 +164,12 @@ void dlm_callback_work(struct work_struct *work) spin_lock(&lkb->lkb_cb_lock); rv = dlm_dequeue_lkb_callback(lkb, &cb); - spin_unlock(&lkb->lkb_cb_lock); - - if (WARN_ON_ONCE(rv == DLM_DEQUEUE_CALLBACK_EMPTY)) + if (WARN_ON_ONCE(rv == DLM_DEQUEUE_CALLBACK_EMPTY)) { + clear_bit(DLM_IFL_CB_PENDING_BIT, &lkb->lkb_iflags); + spin_unlock(&lkb->lkb_cb_lock); goto out; + } + spin_unlock(&lkb->lkb_cb_lock); for (;;) { castfn = lkb->lkb_astfn; diff --git a/fs/dlm/ast.h b/fs/dlm/ast.h index 880b11882495..ce007892dc2d 100644 --- a/fs/dlm/ast.h +++ b/fs/dlm/ast.h @@ -26,7 +26,6 @@ void dlm_callback_set_last_ptr(struct dlm_callback **from, struct dlm_callback *to); void dlm_release_callback(struct kref *ref); -void dlm_purge_lkb_callbacks(struct dlm_lkb *lkb); void dlm_callback_work(struct work_struct *work); int dlm_callback_start(struct dlm_ls *ls); void dlm_callback_stop(struct dlm_ls *ls); diff --git a/fs/dlm/dlm_internal.h b/fs/dlm/dlm_internal.h index 986a9d7b1f33..c8156770205e 100644 --- a/fs/dlm/dlm_internal.h +++ b/fs/dlm/dlm_internal.h @@ -246,7 +246,7 @@ struct dlm_lkb { int8_t lkb_highbast; /* highest mode bast sent for */ int8_t lkb_wait_type; /* type of reply waiting for */ - int8_t lkb_wait_count; + atomic_t lkb_wait_count; int lkb_wait_nodeid; /* for debugging */ struct list_head lkb_statequeue; /* rsb g/c/w list */ diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c index debf8a55ad7d..f511a9d7d416 100644 --- a/fs/dlm/lock.c +++ b/fs/dlm/lock.c @@ -1407,6 +1407,7 @@ static int add_to_waiters(struct dlm_lkb *lkb, int mstype, int to_nodeid) { struct dlm_ls *ls = lkb->lkb_resource->res_ls; int error = 0; + int wc; mutex_lock(&ls->ls_waiters_mutex); @@ -1428,20 +1429,17 @@ static int add_to_waiters(struct dlm_lkb *lkb, int mstype, int to_nodeid) error = -EBUSY; goto out; } - lkb->lkb_wait_count++; + wc = atomic_inc_return(&lkb->lkb_wait_count); hold_lkb(lkb); log_debug(ls, "addwait %x cur %d overlap %d count %d f %x", - lkb->lkb_id, lkb->lkb_wait_type, mstype, - lkb->lkb_wait_count, dlm_iflags_val(lkb)); + lkb->lkb_id, lkb->lkb_wait_type, mstype, wc, + dlm_iflags_val(lkb)); goto out; } - DLM_ASSERT(!lkb->lkb_wait_count, - dlm_print_lkb(lkb); - printk("wait_count %d\n", lkb->lkb_wait_count);); - - lkb->lkb_wait_count++; + wc = atomic_fetch_inc(&lkb->lkb_wait_count); + DLM_ASSERT(!wc, dlm_print_lkb(lkb); printk("wait_count %d\n", wc);); lkb->lkb_wait_type = mstype; lkb->lkb_wait_nodeid = to_nodeid; /* for debugging */ hold_lkb(lkb); @@ -1504,7 +1502,7 @@ static int _remove_from_waiters(struct dlm_lkb *lkb, int mstype, log_debug(ls, "remwait %x convert_reply zap overlap_cancel", lkb->lkb_id); lkb->lkb_wait_type = 0; - lkb->lkb_wait_count--; + atomic_dec(&lkb->lkb_wait_count); unhold_lkb(lkb); goto out_del; } @@ -1531,16 +1529,15 @@ static int _remove_from_waiters(struct dlm_lkb *lkb, int mstype, if (overlap_done && lkb->lkb_wait_type) { log_error(ls, "remwait error %x reply %d wait_type %d overlap", lkb->lkb_id, mstype, lkb->lkb_wait_type); - lkb->lkb_wait_count--; + atomic_dec(&lkb->lkb_wait_count); unhold_lkb(lkb); lkb->lkb_wait_type = 0; } - DLM_ASSERT(lkb->lkb_wait_count, dlm_print_lkb(lkb);); + DLM_ASSERT(atomic_read(&lkb->lkb_wait_count), dlm_print_lkb(lkb);); clear_bit(DLM_IFL_RESEND_BIT, &lkb->lkb_iflags); - lkb->lkb_wait_count--; - if (!lkb->lkb_wait_count) + if (atomic_dec_and_test(&lkb->lkb_wait_count)) list_del_init(&lkb->lkb_wait_reply); unhold_lkb(lkb); return 0; @@ -2669,7 +2666,7 @@ static int validate_lock_args(struct dlm_ls *ls, struct dlm_lkb *lkb, goto out; /* lock not allowed if there's any op in progress */ - if (lkb->lkb_wait_type || lkb->lkb_wait_count) + if (lkb->lkb_wait_type || atomic_read(&lkb->lkb_wait_count)) goto out; if (is_overlap(lkb)) @@ -2731,7 +2728,7 @@ static int validate_unlock_args(struct dlm_lkb *lkb, struct dlm_args *args) /* normal unlock not allowed if there's any op in progress */ if (!(args->flags & (DLM_LKF_CANCEL | DLM_LKF_FORCEUNLOCK)) && - (lkb->lkb_wait_type || lkb->lkb_wait_count)) + (lkb->lkb_wait_type || atomic_read(&lkb->lkb_wait_count))) goto out; /* an lkb may be waiting for an rsb lookup to complete where the @@ -4616,7 +4613,7 @@ static void _receive_message(struct dlm_ls *ls, struct dlm_message *ms, { int error = 0, noent = 0; - if (!dlm_is_member(ls, le32_to_cpu(ms->m_header.h_nodeid))) { + if (WARN_ON_ONCE(!dlm_is_member(ls, le32_to_cpu(ms->m_header.h_nodeid)))) { log_limit(ls, "receive %d from non-member %d %x %x %d", le32_to_cpu(ms->m_type), le32_to_cpu(ms->m_header.h_nodeid), @@ -4754,7 +4751,7 @@ static void dlm_receive_message(struct dlm_ls *ls, struct dlm_message *ms, /* If we were a member of this lockspace, left, and rejoined, other nodes may still be sending us messages from the lockspace generation before we left. */ - if (!ls->ls_generation) { + if (WARN_ON_ONCE(!ls->ls_generation)) { log_limit(ls, "receive %d from %d ignore old gen", le32_to_cpu(ms->m_type), nodeid); return; @@ -5066,10 +5063,9 @@ int dlm_recover_waiters_post(struct dlm_ls *ls) /* drop all wait_count references we still * hold a reference for this iteration. */ - while (lkb->lkb_wait_count) { - lkb->lkb_wait_count--; + while (!atomic_dec_and_test(&lkb->lkb_wait_count)) unhold_lkb(lkb); - } + mutex_lock(&ls->ls_waiters_mutex); list_del_init(&lkb->lkb_wait_reply); mutex_unlock(&ls->ls_waiters_mutex); diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c index 67261b7b1f0e..0455dddb0797 100644 --- a/fs/dlm/lockspace.c +++ b/fs/dlm/lockspace.c @@ -935,15 +935,3 @@ void dlm_stop_lockspaces(void) log_print("dlm user daemon left %d lockspaces", count); } -void dlm_stop_lockspaces_check(void) -{ - struct dlm_ls *ls; - - spin_lock(&lslist_lock); - list_for_each_entry(ls, &lslist, ls_list) { - if (WARN_ON(!rwsem_is_locked(&ls->ls_in_recovery) || - !dlm_locking_stopped(ls))) - break; - } - spin_unlock(&lslist_lock); -} diff --git a/fs/dlm/lockspace.h b/fs/dlm/lockspace.h index 03f4a4a3a871..47ebd4411926 100644 --- a/fs/dlm/lockspace.h +++ b/fs/dlm/lockspace.h @@ -27,7 +27,6 @@ struct dlm_ls *dlm_find_lockspace_local(void *id); struct dlm_ls *dlm_find_lockspace_device(int minor); void dlm_put_lockspace(struct dlm_ls *ls); void dlm_stop_lockspaces(void); -void dlm_stop_lockspaces_check(void); int dlm_new_user_lockspace(const char *name, const char *cluster, uint32_t flags, int lvblen, const struct dlm_lockspace_ops *ops, diff --git a/fs/dlm/lowcomms.c b/fs/dlm/lowcomms.c index 5c12d8cdfc16..9f14ea9f6322 100644 --- a/fs/dlm/lowcomms.c +++ b/fs/dlm/lowcomms.c @@ -546,9 +546,6 @@ int dlm_lowcomms_connect_node(int nodeid) struct connection *con; int idx; - if (nodeid == dlm_our_nodeid()) - return 0; - idx = srcu_read_lock(&connections_srcu); con = nodeid2con(nodeid, 0); if (WARN_ON_ONCE(!con)) { @@ -735,19 +732,15 @@ static void stop_connection_io(struct connection *con) if (con->othercon) stop_connection_io(con->othercon); + spin_lock_bh(&con->writequeue_lock); + set_bit(CF_IO_STOP, &con->flags); + spin_unlock_bh(&con->writequeue_lock); + down_write(&con->sock_lock); if (con->sock) { lock_sock(con->sock->sk); restore_callbacks(con->sock->sk); - - spin_lock_bh(&con->writequeue_lock); - set_bit(CF_IO_STOP, &con->flags); - spin_unlock_bh(&con->writequeue_lock); release_sock(con->sock->sk); - } else { - spin_lock_bh(&con->writequeue_lock); - set_bit(CF_IO_STOP, &con->flags); - spin_unlock_bh(&con->writequeue_lock); } up_write(&con->sock_lock); @@ -867,30 +860,8 @@ struct dlm_processed_nodes { struct list_head list; }; -static void add_processed_node(int nodeid, struct list_head *processed_nodes) -{ - struct dlm_processed_nodes *n; - - list_for_each_entry(n, processed_nodes, list) { - /* we already remembered this node */ - if (n->nodeid == nodeid) - return; - } - - /* if it's fails in worst case we simple don't send an ack back. - * We try it next time. - */ - n = kmalloc(sizeof(*n), GFP_NOFS); - if (!n) - return; - - n->nodeid = nodeid; - list_add(&n->list, processed_nodes); -} - static void process_dlm_messages(struct work_struct *work) { - struct dlm_processed_nodes *n, *n_tmp; struct processqueue_entry *pentry; LIST_HEAD(processed_nodes); @@ -898,6 +869,7 @@ static void process_dlm_messages(struct work_struct *work) pentry = list_first_entry_or_null(&processqueue, struct processqueue_entry, list); if (WARN_ON_ONCE(!pentry)) { + process_dlm_messages_pending = false; spin_unlock(&processqueue_lock); return; } @@ -908,7 +880,6 @@ static void process_dlm_messages(struct work_struct *work) for (;;) { dlm_process_incoming_buffer(pentry->nodeid, pentry->buf, pentry->buflen); - add_processed_node(pentry->nodeid, &processed_nodes); free_processqueue_entry(pentry); spin_lock(&processqueue_lock); @@ -923,13 +894,6 @@ static void process_dlm_messages(struct work_struct *work) list_del(&pentry->list); spin_unlock(&processqueue_lock); } - - /* send ack back after we processed couple of messages */ - list_for_each_entry_safe(n, n_tmp, &processed_nodes, list) { - list_del(&n->list); - dlm_midcomms_receive_done(n->nodeid); - kfree(n); - } } /* Data received from remote end */ @@ -1500,8 +1464,7 @@ int dlm_lowcomms_close(int nodeid) call_srcu(&connections_srcu, &con->rcu, connection_release); if (con->othercon) { clean_one_writequeue(con->othercon); - if (con->othercon) - call_srcu(&connections_srcu, &con->othercon->rcu, connection_release); + call_srcu(&connections_srcu, &con->othercon->rcu, connection_release); } srcu_read_unlock(&connections_srcu, idx); diff --git a/fs/dlm/main.c b/fs/dlm/main.c index 93755f83a30d..6ca28299c9db 100644 --- a/fs/dlm/main.c +++ b/fs/dlm/main.c @@ -73,10 +73,10 @@ static void __exit exit_dlm(void) dlm_plock_exit(); dlm_user_exit(); dlm_config_exit(); - dlm_memory_exit(); dlm_lockspace_exit(); dlm_midcomms_exit(); dlm_unregister_debugfs(); + dlm_memory_exit(); } module_init(init_dlm); diff --git a/fs/dlm/member.c b/fs/dlm/member.c index 923c01a8a0aa..77d202e4a02a 100644 --- a/fs/dlm/member.c +++ b/fs/dlm/member.c @@ -307,6 +307,21 @@ static void add_ordered_member(struct dlm_ls *ls, struct dlm_member *new) } } +static int add_remote_member(int nodeid) +{ + int error; + + if (nodeid == dlm_our_nodeid()) + return 0; + + error = dlm_lowcomms_connect_node(nodeid); + if (error < 0) + return error; + + dlm_midcomms_add_member(nodeid); + return 0; +} + static int dlm_add_member(struct dlm_ls *ls, struct dlm_config_node *node) { struct dlm_member *memb; @@ -316,16 +331,16 @@ static int dlm_add_member(struct dlm_ls *ls, struct dlm_config_node *node) if (!memb) return -ENOMEM; - error = dlm_lowcomms_connect_node(node->nodeid); + memb->nodeid = node->nodeid; + memb->weight = node->weight; + memb->comm_seq = node->comm_seq; + + error = add_remote_member(node->nodeid); if (error < 0) { kfree(memb); return error; } - memb->nodeid = node->nodeid; - memb->weight = node->weight; - memb->comm_seq = node->comm_seq; - dlm_midcomms_add_member(node->nodeid); add_ordered_member(ls, memb); ls->ls_num_nodes++; return 0; @@ -370,9 +385,17 @@ static void clear_memb_list(struct list_head *head, } } +static void remove_remote_member(int nodeid) +{ + if (nodeid == dlm_our_nodeid()) + return; + + dlm_midcomms_remove_member(nodeid); +} + static void clear_members_cb(int nodeid) { - dlm_midcomms_remove_member(nodeid); + remove_remote_member(nodeid); } void dlm_clear_members(struct dlm_ls *ls) @@ -562,7 +585,7 @@ int dlm_recover_members(struct dlm_ls *ls, struct dlm_recover *rv, int *neg_out) neg++; list_move(&memb->list, &ls->ls_nodes_gone); - dlm_midcomms_remove_member(memb->nodeid); + remove_remote_member(memb->nodeid); ls->ls_num_nodes--; dlm_lsop_recover_slot(ls, memb); } diff --git a/fs/dlm/midcomms.c b/fs/dlm/midcomms.c index c02c43e4980a..e1a0df67b566 100644 --- a/fs/dlm/midcomms.c +++ b/fs/dlm/midcomms.c @@ -136,7 +136,6 @@ #include #include "dlm_internal.h" -#include "lockspace.h" #include "lowcomms.h" #include "config.h" #include "memory.h" @@ -149,12 +148,14 @@ /* 5 seconds wait to sync ending of dlm */ #define DLM_SHUTDOWN_TIMEOUT msecs_to_jiffies(5000) #define DLM_VERSION_NOT_SET 0 +#define DLM_SEND_ACK_BACK_MSG_THRESHOLD 32 +#define DLM_RECV_ACK_BACK_MSG_THRESHOLD (DLM_SEND_ACK_BACK_MSG_THRESHOLD * 8) struct midcomms_node { int nodeid; uint32_t version; - uint32_t seq_send; - uint32_t seq_next; + atomic_t seq_send; + atomic_t seq_next; /* These queues are unbound because we cannot drop any message in dlm. * We could send a fence signal for a specific node to the cluster * manager if queues hits some maximum value, however this handling @@ -166,7 +167,7 @@ struct midcomms_node { #define DLM_NODE_FLAG_CLOSE 1 #define DLM_NODE_FLAG_STOP_TX 2 #define DLM_NODE_FLAG_STOP_RX 3 -#define DLM_NODE_ULP_DELIVERED 4 + atomic_t ulp_delivered; unsigned long flags; wait_queue_head_t shutdown_wait; @@ -318,8 +319,9 @@ static void midcomms_node_reset(struct midcomms_node *node) { pr_debug("reset node %d\n", node->nodeid); - node->seq_next = DLM_SEQ_INIT; - node->seq_send = DLM_SEQ_INIT; + atomic_set(&node->seq_next, DLM_SEQ_INIT); + atomic_set(&node->seq_send, DLM_SEQ_INIT); + atomic_set(&node->ulp_delivered, 0); node->version = DLM_VERSION_NOT_SET; node->flags = 0; @@ -394,6 +396,28 @@ static int dlm_send_ack(int nodeid, uint32_t seq) return 0; } +static void dlm_send_ack_threshold(struct midcomms_node *node, + uint32_t threshold) +{ + uint32_t oval, nval; + bool send_ack; + + /* let only send one user trigger threshold to send ack back */ + do { + oval = atomic_read(&node->ulp_delivered); + send_ack = (oval > threshold); + /* abort if threshold is not reached */ + if (!send_ack) + break; + + nval = 0; + /* try to reset ulp_delivered counter */ + } while (atomic_cmpxchg(&node->ulp_delivered, oval, nval) != oval); + + if (send_ack) + dlm_send_ack(node->nodeid, atomic_read(&node->seq_next)); +} + static int dlm_send_fin(struct midcomms_node *node, void (*ack_rcv)(struct midcomms_node *node)) { @@ -493,9 +517,19 @@ static void dlm_midcomms_receive_buffer(union dlm_packet *p, struct midcomms_node *node, uint32_t seq) { - if (seq == node->seq_next) { - node->seq_next++; + bool is_expected_seq; + uint32_t oval, nval; + do { + oval = atomic_read(&node->seq_next); + is_expected_seq = (oval == seq); + if (!is_expected_seq) + break; + + nval = oval + 1; + } while (atomic_cmpxchg(&node->seq_next, oval, nval) != oval); + + if (is_expected_seq) { switch (p->header.h_cmd) { case DLM_FIN: spin_lock(&node->state_lock); @@ -504,7 +538,7 @@ static void dlm_midcomms_receive_buffer(union dlm_packet *p, switch (node->state) { case DLM_ESTABLISHED: - dlm_send_ack(node->nodeid, node->seq_next); + dlm_send_ack(node->nodeid, nval); /* passive shutdown DLM_LAST_ACK case 1 * additional we check if the node is used by @@ -523,14 +557,14 @@ static void dlm_midcomms_receive_buffer(union dlm_packet *p, } break; case DLM_FIN_WAIT1: - dlm_send_ack(node->nodeid, node->seq_next); + dlm_send_ack(node->nodeid, nval); node->state = DLM_CLOSING; set_bit(DLM_NODE_FLAG_STOP_RX, &node->flags); pr_debug("switch node %d to state %s\n", node->nodeid, dlm_state_str(node->state)); break; case DLM_FIN_WAIT2: - dlm_send_ack(node->nodeid, node->seq_next); + dlm_send_ack(node->nodeid, nval); midcomms_node_reset(node); pr_debug("switch node %d to state %s\n", node->nodeid, dlm_state_str(node->state)); @@ -551,18 +585,20 @@ static void dlm_midcomms_receive_buffer(union dlm_packet *p, WARN_ON_ONCE(test_bit(DLM_NODE_FLAG_STOP_RX, &node->flags)); dlm_receive_buffer_3_2_trace(seq, p); dlm_receive_buffer(p, node->nodeid); - set_bit(DLM_NODE_ULP_DELIVERED, &node->flags); + atomic_inc(&node->ulp_delivered); + /* unlikely case to send ack back when we don't transmit */ + dlm_send_ack_threshold(node, DLM_RECV_ACK_BACK_MSG_THRESHOLD); break; } } else { /* retry to ack message which we already have by sending back * current node->seq_next number as ack. */ - if (seq < node->seq_next) - dlm_send_ack(node->nodeid, node->seq_next); + if (seq < oval) + dlm_send_ack(node->nodeid, oval); log_print_ratelimited("ignore dlm msg because seq mismatch, seq: %u, expected: %u, nodeid: %d", - seq, node->seq_next, node->nodeid); + seq, oval, node->nodeid); } } @@ -960,49 +996,6 @@ int dlm_process_incoming_buffer(int nodeid, unsigned char *buf, int len) return ret; } -void dlm_midcomms_receive_done(int nodeid) -{ - struct midcomms_node *node; - int idx; - - idx = srcu_read_lock(&nodes_srcu); - node = nodeid2node(nodeid, 0); - if (!node) { - srcu_read_unlock(&nodes_srcu, idx); - return; - } - - /* old protocol, we do nothing */ - switch (node->version) { - case DLM_VERSION_3_2: - break; - default: - srcu_read_unlock(&nodes_srcu, idx); - return; - } - - /* do nothing if we didn't delivered stateful to ulp */ - if (!test_and_clear_bit(DLM_NODE_ULP_DELIVERED, - &node->flags)) { - srcu_read_unlock(&nodes_srcu, idx); - return; - } - - spin_lock(&node->state_lock); - /* we only ack if state is ESTABLISHED */ - switch (node->state) { - case DLM_ESTABLISHED: - spin_unlock(&node->state_lock); - dlm_send_ack(node->nodeid, node->seq_next); - break; - default: - spin_unlock(&node->state_lock); - /* do nothing FIN has it's own ack send */ - break; - } - srcu_read_unlock(&nodes_srcu, idx); -} - void dlm_midcomms_unack_msg_resend(int nodeid) { struct midcomms_node *node; @@ -1059,7 +1052,7 @@ static void midcomms_new_msg_cb(void *data) list_add_tail_rcu(&mh->list, &mh->node->send_queue); spin_unlock_bh(&mh->node->send_queue_lock); - mh->seq = mh->node->seq_send++; + mh->seq = atomic_fetch_inc(&mh->node->seq_send); } static struct dlm_msg *dlm_midcomms_get_msg_3_2(struct dlm_mhandle *mh, int nodeid, @@ -1133,6 +1126,8 @@ struct dlm_mhandle *dlm_midcomms_get_mhandle(int nodeid, int len, goto err; } + /* send ack back if necessary */ + dlm_send_ack_threshold(node, DLM_SEND_ACK_BACK_MSG_THRESHOLD); break; default: dlm_free_mhandle(mh); @@ -1281,9 +1276,6 @@ void dlm_midcomms_add_member(int nodeid) struct midcomms_node *node; int idx; - if (nodeid == dlm_our_nodeid()) - return; - idx = srcu_read_lock(&nodes_srcu); node = nodeid2node(nodeid, GFP_NOFS); if (!node) { @@ -1329,9 +1321,6 @@ void dlm_midcomms_remove_member(int nodeid) struct midcomms_node *node; int idx; - if (nodeid == dlm_our_nodeid()) - return; - idx = srcu_read_lock(&nodes_srcu); node = nodeid2node(nodeid, 0); if (!node) { @@ -1488,11 +1477,6 @@ int dlm_midcomms_close(int nodeid) struct midcomms_node *node; int idx, ret; - if (nodeid == dlm_our_nodeid()) - return 0; - - dlm_stop_lockspaces_check(); - idx = srcu_read_lock(&nodes_srcu); /* Abort pending close/remove operation */ node = nodeid2node(nodeid, 0); @@ -1542,7 +1526,7 @@ static void midcomms_new_rawmsg_cb(void *data) switch (h->h_cmd) { case DLM_OPTS: if (!h->u.h_seq) - h->u.h_seq = cpu_to_le32(rd->node->seq_send++); + h->u.h_seq = cpu_to_le32(atomic_fetch_inc(&rd->node->seq_send)); break; default: break; diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index ed4357e62f35..70a4752ed913 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -30,8 +30,6 @@ struct plock_async_data { struct plock_op { struct list_head list; int done; - /* if lock op got interrupted while waiting dlm_controld reply */ - bool sigint; struct dlm_plock_info info; /* if set indicates async handling */ struct plock_async_data *data; @@ -157,23 +155,29 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, send_op(op); - rv = wait_event_interruptible(recv_wq, (op->done != 0)); - if (rv == -ERESTARTSYS) { - spin_lock(&ops_lock); - /* recheck under ops_lock if we got a done != 0, - * if so this interrupt case should be ignored - */ - if (op->done != 0) { + if (op->info.wait) { + rv = wait_event_killable(recv_wq, (op->done != 0)); + if (rv == -ERESTARTSYS) { + spin_lock(&ops_lock); + /* recheck under ops_lock if we got a done != 0, + * if so this interrupt case should be ignored + */ + if (op->done != 0) { + spin_unlock(&ops_lock); + goto do_lock_wait; + } + list_del(&op->list); spin_unlock(&ops_lock); - goto do_lock_wait; - } - op->sigint = true; - spin_unlock(&ops_lock); - log_debug(ls, "%s: wait interrupted %x %llx pid %d", - __func__, ls->ls_global_id, - (unsigned long long)number, op->info.pid); - goto out; + log_debug(ls, "%s: wait interrupted %x %llx pid %d", + __func__, ls->ls_global_id, + (unsigned long long)number, op->info.pid); + do_unlock_close(&op->info); + dlm_release_plock_op(op); + goto out; + } + } else { + wait_event(recv_wq, (op->done != 0)); } do_lock_wait: @@ -360,7 +364,9 @@ int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file, locks_init_lock(fl); fl->fl_type = (op->info.ex) ? F_WRLCK : F_RDLCK; fl->fl_flags = FL_POSIX; - fl->fl_pid = -op->info.pid; + fl->fl_pid = op->info.pid; + if (op->info.nodeid != dlm_our_nodeid()) + fl->fl_pid = -fl->fl_pid; fl->fl_start = op->info.start; fl->fl_end = op->info.end; rv = 0; @@ -389,7 +395,7 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, if (op->info.flags & DLM_PLOCK_FL_CLOSE) list_del(&op->list); else - list_move(&op->list, &recv_list); + list_move_tail(&op->list, &recv_list); memcpy(&info, &op->info, sizeof(info)); } spin_unlock(&ops_lock); @@ -427,33 +433,52 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, if (check_version(&info)) return -EINVAL; + /* + * The results for waiting ops (SETLKW) can be returned in any + * order, so match all fields to find the op. The results for + * non-waiting ops are returned in the order that they were sent + * to userspace, so match the result with the first non-waiting op. + */ spin_lock(&ops_lock); - list_for_each_entry(iter, &recv_list, list) { - if (iter->info.fsid == info.fsid && - iter->info.number == info.number && - iter->info.owner == info.owner) { - if (iter->sigint) { - list_del(&iter->list); - spin_unlock(&ops_lock); - - pr_debug("%s: sigint cleanup %x %llx pid %d", - __func__, iter->info.fsid, - (unsigned long long)iter->info.number, - iter->info.pid); - do_unlock_close(&iter->info); - memcpy(&iter->info, &info, sizeof(info)); - dlm_release_plock_op(iter); - return count; + if (info.wait) { + list_for_each_entry(iter, &recv_list, list) { + if (iter->info.fsid == info.fsid && + iter->info.number == info.number && + iter->info.owner == info.owner && + iter->info.pid == info.pid && + iter->info.start == info.start && + iter->info.end == info.end && + iter->info.ex == info.ex && + iter->info.wait) { + op = iter; + break; } - list_del_init(&iter->list); - memcpy(&iter->info, &info, sizeof(info)); - if (iter->data) - do_callback = 1; - else - iter->done = 1; - op = iter; - break; } + } else { + list_for_each_entry(iter, &recv_list, list) { + if (!iter->info.wait) { + op = iter; + break; + } + } + } + + if (op) { + /* Sanity check that op and info match. */ + if (info.wait) + WARN_ON(op->info.optype != DLM_PLOCK_OP_LOCK); + else + WARN_ON(op->info.fsid != info.fsid || + op->info.number != info.number || + op->info.owner != info.owner || + op->info.optype != info.optype); + + list_del_init(&op->list); + memcpy(&op->info, &info, sizeof(info)); + if (op->data) + do_callback = 1; + else + op->done = 1; } spin_unlock(&ops_lock); @@ -463,8 +488,8 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, else wake_up(&recv_wq); } else - log_print("%s: no op %x %llx", __func__, - info.fsid, (unsigned long long)info.number); + pr_debug("%s: no op %x %llx", __func__, + info.fsid, (unsigned long long)info.number); return count; } diff --git a/fs/dlm/user.c b/fs/dlm/user.c index d9c09fc0aba1..695e691b38b3 100644 --- a/fs/dlm/user.c +++ b/fs/dlm/user.c @@ -145,6 +145,24 @@ static void compat_output(struct dlm_lock_result *res, } #endif +/* should held proc->asts_spin lock */ +void dlm_purge_lkb_callbacks(struct dlm_lkb *lkb) +{ + struct dlm_callback *cb, *safe; + + list_for_each_entry_safe(cb, safe, &lkb->lkb_callbacks, list) { + list_del(&cb->list); + kref_put(&cb->ref, dlm_release_callback); + } + + clear_bit(DLM_IFL_CB_PENDING_BIT, &lkb->lkb_iflags); + + /* invalidate */ + dlm_callback_set_last_ptr(&lkb->lkb_last_cast, NULL); + dlm_callback_set_last_ptr(&lkb->lkb_last_cb, NULL); + lkb->lkb_last_bast_mode = -1; +} + /* Figure out if this lock is at the end of its life and no longer available for the application to use. The lkb still exists until the final ast is read. A lock becomes EOL in three situations: diff --git a/fs/dlm/user.h b/fs/dlm/user.h index 33059452d79e..2caf8e6e24d5 100644 --- a/fs/dlm/user.h +++ b/fs/dlm/user.h @@ -6,6 +6,7 @@ #ifndef __USER_DOT_H__ #define __USER_DOT_H__ +void dlm_purge_lkb_callbacks(struct dlm_lkb *lkb); void dlm_user_add_ast(struct dlm_lkb *lkb, uint32_t flags, int mode, int status, uint32_t sbflags); int dlm_user_init(void); diff --git a/fs/exec.c b/fs/exec.c index 80b8611c416d..1a827d55ba94 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -152,8 +152,6 @@ SYSCALL_DEFINE1(uselib, const char __user *, library) path_noexec(&file->f_path))) goto exit; - fsnotify_open(file); - error = -ENOEXEC; read_lock(&binfmt_lock); @@ -940,9 +938,6 @@ static struct file *do_open_execat(int fd, struct filename *name, int flags) if (err) goto exit; - if (name->name[0] != '\0') - fsnotify_open(file); - out: return file; diff --git a/fs/exportfs/expfs.c b/fs/exportfs/expfs.c index ab88d33d106c..40e624cf7e92 100644 --- a/fs/exportfs/expfs.c +++ b/fs/exportfs/expfs.c @@ -381,11 +381,27 @@ static int export_encode_fh(struct inode *inode, struct fid *fid, return type; } +/** + * exportfs_encode_inode_fh - encode a file handle from inode + * @inode: the object to encode + * @fid: where to store the file handle fragment + * @max_len: maximum length to store there + * @flags: properties of the requested file handle + * + * Returns an enum fid_type or a negative errno. + */ int exportfs_encode_inode_fh(struct inode *inode, struct fid *fid, - int *max_len, struct inode *parent) + int *max_len, struct inode *parent, int flags) { const struct export_operations *nop = inode->i_sb->s_export_op; + /* + * If a decodeable file handle was requested, we need to make sure that + * filesystem can decode file handles. + */ + if (nop && !(flags & EXPORT_FH_FID) && !nop->fh_to_dentry) + return -EOPNOTSUPP; + if (nop && nop->encode_fh) return nop->encode_fh(inode, fid->raw, max_len, parent); @@ -393,14 +409,23 @@ int exportfs_encode_inode_fh(struct inode *inode, struct fid *fid, } EXPORT_SYMBOL_GPL(exportfs_encode_inode_fh); +/** + * exportfs_encode_fh - encode a file handle from dentry + * @dentry: the object to encode + * @fid: where to store the file handle fragment + * @max_len: maximum length to store there + * @flags: properties of the requested file handle + * + * Returns an enum fid_type or a negative errno. + */ int exportfs_encode_fh(struct dentry *dentry, struct fid *fid, int *max_len, - int connectable) + int flags) { int error; struct dentry *p = NULL; struct inode *inode = dentry->d_inode, *parent = NULL; - if (connectable && !S_ISDIR(inode->i_mode)) { + if ((flags & EXPORT_FH_CONNECTABLE) && !S_ISDIR(inode->i_mode)) { p = dget_parent(dentry); /* * note that while p might've ceased to be our parent already, @@ -409,7 +434,7 @@ int exportfs_encode_fh(struct dentry *dentry, struct fid *fid, int *max_len, parent = p->d_inode; } - error = exportfs_encode_inode_fh(inode, fid, max_len, parent); + error = exportfs_encode_inode_fh(inode, fid, max_len, parent, flags); dput(p); return error; diff --git a/fs/ext2/Makefile b/fs/ext2/Makefile index 311479d864a7..8860948ef9ca 100644 --- a/fs/ext2/Makefile +++ b/fs/ext2/Makefile @@ -6,7 +6,10 @@ obj-$(CONFIG_EXT2_FS) += ext2.o ext2-y := balloc.o dir.o file.o ialloc.o inode.o \ - ioctl.o namei.o super.o symlink.o + ioctl.o namei.o super.o symlink.o trace.o + +# For tracepoints to include our trace.h from tracepoint infrastructure +CFLAGS_trace.o := -I$(src) ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o xattr_user.o xattr_trusted.o ext2-$(CONFIG_EXT2_FS_POSIX_ACL) += acl.o diff --git a/fs/ext2/dir.c b/fs/ext2/dir.c index 4a6955a0a116..42db804794bd 100644 --- a/fs/ext2/dir.c +++ b/fs/ext2/dir.c @@ -186,23 +186,25 @@ fail: * NOTE: ext2_find_entry() and ext2_dotdot() act as a call to ext2_get_page() * and should be treated as a call to ext2_get_page() for nesting purposes. */ -static struct page * ext2_get_page(struct inode *dir, unsigned long n, - int quiet, void **page_addr) +static void *ext2_get_page(struct inode *dir, unsigned long n, + int quiet, struct page **page) { struct address_space *mapping = dir->i_mapping; struct folio *folio = read_mapping_folio(mapping, n, NULL); + void *page_addr; if (IS_ERR(folio)) - return &folio->page; - *page_addr = kmap_local_folio(folio, n & (folio_nr_pages(folio) - 1)); + return ERR_CAST(folio); + page_addr = kmap_local_folio(folio, n & (folio_nr_pages(folio) - 1)); if (unlikely(!folio_test_checked(folio))) { - if (!ext2_check_page(&folio->page, quiet, *page_addr)) + if (!ext2_check_page(&folio->page, quiet, page_addr)) goto fail; } - return &folio->page; + *page = &folio->page; + return page_addr; fail: - ext2_put_page(&folio->page, *page_addr); + ext2_put_page(&folio->page, page_addr); return ERR_PTR(-EIO); } @@ -240,7 +242,7 @@ ext2_validate_entry(char *base, unsigned offset, unsigned mask) break; p = ext2_next_entry(p); } - return (char *)p - base; + return offset_in_page(p); } static inline void ext2_set_de_type(ext2_dirent *de, struct inode *inode) @@ -271,16 +273,17 @@ ext2_readdir(struct file *file, struct dir_context *ctx) EXT2_HAS_INCOMPAT_FEATURE(sb, EXT2_FEATURE_INCOMPAT_FILETYPE); for ( ; n < npages; n++, offset = 0) { - char *kaddr, *limit; ext2_dirent *de; - struct page *page = ext2_get_page(inode, n, 0, (void **)&kaddr); + struct page *page; + char *kaddr = ext2_get_page(inode, n, 0, &page); + char *limit; - if (IS_ERR(page)) { + if (IS_ERR(kaddr)) { ext2_error(sb, __func__, "bad page in #%lu", inode->i_ino); ctx->pos += PAGE_SIZE - offset; - return PTR_ERR(page); + return PTR_ERR(kaddr); } if (unlikely(need_revalidate)) { if (offset) { @@ -296,7 +299,7 @@ ext2_readdir(struct file *file, struct dir_context *ctx) if (de->rec_len == 0) { ext2_error(sb, __func__, "zero-length directory entry"); - ext2_put_page(page, kaddr); + ext2_put_page(page, de); return -EIO; } if (de->inode) { @@ -308,7 +311,7 @@ ext2_readdir(struct file *file, struct dir_context *ctx) if (!dir_emit(ctx, de->name, de->name_len, le32_to_cpu(de->inode), d_type)) { - ext2_put_page(page, kaddr); + ext2_put_page(page, de); return 0; } } @@ -336,8 +339,7 @@ ext2_readdir(struct file *file, struct dir_context *ctx) * should be treated as a call to ext2_get_page() for nesting purposes. */ struct ext2_dir_entry_2 *ext2_find_entry (struct inode *dir, - const struct qstr *child, struct page **res_page, - void **res_page_addr) + const struct qstr *child, struct page **res_page) { const char *name = child->name; int namelen = child->len; @@ -347,40 +349,36 @@ struct ext2_dir_entry_2 *ext2_find_entry (struct inode *dir, struct page *page = NULL; struct ext2_inode_info *ei = EXT2_I(dir); ext2_dirent * de; - void *page_addr; if (npages == 0) goto out; /* OFFSET_CACHE */ *res_page = NULL; - *res_page_addr = NULL; start = ei->i_dir_start_lookup; if (start >= npages) start = 0; n = start; do { - char *kaddr; - page = ext2_get_page(dir, n, 0, &page_addr); - if (IS_ERR(page)) - return ERR_CAST(page); + char *kaddr = ext2_get_page(dir, n, 0, &page); + if (IS_ERR(kaddr)) + return ERR_CAST(kaddr); - kaddr = page_addr; de = (ext2_dirent *) kaddr; kaddr += ext2_last_byte(dir, n) - reclen; while ((char *) de <= kaddr) { if (de->rec_len == 0) { ext2_error(dir->i_sb, __func__, "zero-length directory entry"); - ext2_put_page(page, page_addr); + ext2_put_page(page, de); goto out; } if (ext2_match(namelen, name, de)) goto found; de = ext2_next_entry(de); } - ext2_put_page(page, page_addr); + ext2_put_page(page, kaddr); if (++n >= npages) n = 0; @@ -398,7 +396,6 @@ out: found: *res_page = page; - *res_page_addr = page_addr; ei->i_dir_start_lookup = n; return de; } @@ -415,33 +412,26 @@ found: * ext2_find_entry() and ext2_dotdot() act as a call to ext2_get_page() and * should be treated as a call to ext2_get_page() for nesting purposes. */ -struct ext2_dir_entry_2 *ext2_dotdot(struct inode *dir, struct page **p, - void **pa) +struct ext2_dir_entry_2 *ext2_dotdot(struct inode *dir, struct page **p) { - void *page_addr; - struct page *page = ext2_get_page(dir, 0, 0, &page_addr); - ext2_dirent *de = NULL; + ext2_dirent *de = ext2_get_page(dir, 0, 0, p); - if (!IS_ERR(page)) { - de = ext2_next_entry((ext2_dirent *) page_addr); - *p = page; - *pa = page_addr; - } - return de; + if (!IS_ERR(de)) + return ext2_next_entry(de); + return NULL; } int ext2_inode_by_name(struct inode *dir, const struct qstr *child, ino_t *ino) { struct ext2_dir_entry_2 *de; struct page *page; - void *page_addr; - de = ext2_find_entry(dir, child, &page, &page_addr); + de = ext2_find_entry(dir, child, &page); if (IS_ERR(de)) return PTR_ERR(de); *ino = le32_to_cpu(de->inode); - ext2_put_page(page, page_addr); + ext2_put_page(page, de); return 0; } @@ -462,11 +452,9 @@ static int ext2_handle_dirsync(struct inode *dir) } int ext2_set_link(struct inode *dir, struct ext2_dir_entry_2 *de, - struct page *page, void *page_addr, struct inode *inode, - bool update_times) + struct page *page, struct inode *inode, bool update_times) { - loff_t pos = page_offset(page) + - (char *) de - (char *) page_addr; + loff_t pos = page_offset(page) + offset_in_page(de); unsigned len = ext2_rec_len_from_disk(de->rec_len); int err; @@ -498,7 +486,6 @@ int ext2_add_link (struct dentry *dentry, struct inode *inode) unsigned reclen = EXT2_DIR_REC_LEN(namelen); unsigned short rec_len, name_len; struct page *page = NULL; - void *page_addr = NULL; ext2_dirent * de; unsigned long npages = dir_pages(dir); unsigned long n; @@ -511,15 +498,12 @@ int ext2_add_link (struct dentry *dentry, struct inode *inode) * to protect that region. */ for (n = 0; n <= npages; n++) { - char *kaddr; + char *kaddr = ext2_get_page(dir, n, 0, &page); char *dir_end; - page = ext2_get_page(dir, n, 0, &page_addr); - err = PTR_ERR(page); - if (IS_ERR(page)) - goto out; + if (IS_ERR(kaddr)) + return PTR_ERR(kaddr); lock_page(page); - kaddr = page_addr; dir_end = kaddr + ext2_last_byte(dir, n); de = (ext2_dirent *)kaddr; kaddr += PAGE_SIZE - reclen; @@ -550,14 +534,13 @@ int ext2_add_link (struct dentry *dentry, struct inode *inode) de = (ext2_dirent *) ((char *) de + rec_len); } unlock_page(page); - ext2_put_page(page, page_addr); + ext2_put_page(page, kaddr); } BUG(); return -EINVAL; got_it: - pos = page_offset(page) + - (char *)de - (char *)page_addr; + pos = page_offset(page) + offset_in_page(de); err = ext2_prepare_chunk(page, pos, rec_len); if (err) goto out_unlock; @@ -578,8 +561,7 @@ got_it: err = ext2_handle_dirsync(dir); /* OFFSET_CACHE */ out_put: - ext2_put_page(page, page_addr); -out: + ext2_put_page(page, de); return err; out_unlock: unlock_page(page); @@ -590,34 +572,36 @@ out_unlock: * ext2_delete_entry deletes a directory entry by merging it with the * previous entry. Page is up-to-date. */ -int ext2_delete_entry (struct ext2_dir_entry_2 *dir, struct page *page, - char *kaddr) +int ext2_delete_entry(struct ext2_dir_entry_2 *dir, struct page *page) { struct inode *inode = page->mapping->host; - unsigned from = ((char*)dir - kaddr) & ~(ext2_chunk_size(inode)-1); - unsigned to = ((char *)dir - kaddr) + + char *kaddr = (char *)((unsigned long)dir & PAGE_MASK); + unsigned from = offset_in_page(dir) & ~(ext2_chunk_size(inode)-1); + unsigned to = offset_in_page(dir) + ext2_rec_len_from_disk(dir->rec_len); loff_t pos; - ext2_dirent * pde = NULL; - ext2_dirent * de = (ext2_dirent *) (kaddr + from); + ext2_dirent *pde = NULL; + ext2_dirent *de = (ext2_dirent *)(kaddr + from); int err; while ((char*)de < (char*)dir) { if (de->rec_len == 0) { ext2_error(inode->i_sb, __func__, "zero-length directory entry"); - err = -EIO; - goto out; + return -EIO; } pde = de; de = ext2_next_entry(de); } if (pde) - from = (char *)pde - kaddr; + from = offset_in_page(pde); pos = page_offset(page) + from; lock_page(page); err = ext2_prepare_chunk(page, pos, to - from); - BUG_ON(err); + if (err) { + unlock_page(page); + return err; + } if (pde) pde->rec_len = ext2_rec_len_to_disk(to - from); dir->inode = 0; @@ -625,9 +609,7 @@ int ext2_delete_entry (struct ext2_dir_entry_2 *dir, struct page *page, inode->i_ctime = inode->i_mtime = current_time(inode); EXT2_I(inode)->i_flags &= ~EXT2_BTREE_FL; mark_inode_dirty(inode); - err = ext2_handle_dirsync(inode); -out: - return err; + return ext2_handle_dirsync(inode); } /* @@ -677,19 +659,17 @@ fail: */ int ext2_empty_dir (struct inode * inode) { - void *page_addr = NULL; - struct page *page = NULL; + struct page *page; + char *kaddr; unsigned long i, npages = dir_pages(inode); for (i = 0; i < npages; i++) { - char *kaddr; - ext2_dirent * de; - page = ext2_get_page(inode, i, 0, &page_addr); + ext2_dirent *de; - if (IS_ERR(page)) + kaddr = ext2_get_page(inode, i, 0, &page); + if (IS_ERR(kaddr)) return 0; - kaddr = page_addr; de = (ext2_dirent *)kaddr; kaddr += ext2_last_byte(inode, i) - EXT2_DIR_REC_LEN(1); @@ -715,12 +695,12 @@ int ext2_empty_dir (struct inode * inode) } de = ext2_next_entry(de); } - ext2_put_page(page, page_addr); + ext2_put_page(page, kaddr); } return 1; not_empty: - ext2_put_page(page, page_addr); + ext2_put_page(page, kaddr); return 0; } diff --git a/fs/ext2/ext2.h b/fs/ext2/ext2.h index 8244366862e4..35a041c47c38 100644 --- a/fs/ext2/ext2.h +++ b/fs/ext2/ext2.h @@ -70,10 +70,7 @@ struct mb_cache; * second extended-fs super-block data in memory */ struct ext2_sb_info { - unsigned long s_frag_size; /* Size of a fragment in bytes */ - unsigned long s_frags_per_block;/* Number of fragments per block */ unsigned long s_inodes_per_block;/* Number of inodes per block */ - unsigned long s_frags_per_group;/* Number of fragments in a group */ unsigned long s_blocks_per_group;/* Number of blocks in a group */ unsigned long s_inodes_per_group;/* Number of inodes in a group */ unsigned long s_itb_per_group; /* Number of inode table blocks per group */ @@ -188,15 +185,6 @@ static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb) #define EXT2_INODE_SIZE(s) (EXT2_SB(s)->s_inode_size) #define EXT2_FIRST_INO(s) (EXT2_SB(s)->s_first_ino) -/* - * Macro-instructions used to manage fragments - */ -#define EXT2_MIN_FRAG_SIZE 1024 -#define EXT2_MAX_FRAG_SIZE 4096 -#define EXT2_MIN_FRAG_LOG_SIZE 10 -#define EXT2_FRAG_SIZE(s) (EXT2_SB(s)->s_frag_size) -#define EXT2_FRAGS_PER_BLOCK(s) (EXT2_SB(s)->s_frags_per_block) - /* * Structure of a blocks group descriptor */ @@ -730,14 +718,12 @@ extern int ext2_inode_by_name(struct inode *dir, const struct qstr *child, ino_t *ino); extern int ext2_make_empty(struct inode *, struct inode *); extern struct ext2_dir_entry_2 *ext2_find_entry(struct inode *, const struct qstr *, - struct page **, void **res_page_addr); -extern int ext2_delete_entry(struct ext2_dir_entry_2 *dir, struct page *page, - char *kaddr); + struct page **); +extern int ext2_delete_entry(struct ext2_dir_entry_2 *dir, struct page *page); extern int ext2_empty_dir (struct inode *); -extern struct ext2_dir_entry_2 *ext2_dotdot(struct inode *dir, struct page **p, void **pa); +extern struct ext2_dir_entry_2 *ext2_dotdot(struct inode *dir, struct page **p); int ext2_set_link(struct inode *dir, struct ext2_dir_entry_2 *de, - struct page *page, void *page_addr, struct inode *inode, - bool update_times); + struct page *page, struct inode *inode, bool update_times); static inline void ext2_put_page(struct page *page, void *page_addr) { kunmap_local(page_addr); @@ -754,6 +740,7 @@ extern unsigned long ext2_count_free (struct buffer_head *, unsigned); extern struct inode *ext2_iget (struct super_block *, unsigned long); extern int ext2_write_inode (struct inode *, struct writeback_control *); extern void ext2_evict_inode(struct inode *); +void ext2_write_failed(struct address_space *mapping, loff_t to); extern int ext2_get_block(struct inode *, sector_t, struct buffer_head *, int); extern int ext2_setattr (struct mnt_idmap *, struct dentry *, struct iattr *); extern int ext2_getattr (struct mnt_idmap *, const struct path *, diff --git a/fs/ext2/file.c b/fs/ext2/file.c index d1ae0f0a3726..0b4c91c62e1f 100644 --- a/fs/ext2/file.c +++ b/fs/ext2/file.c @@ -25,9 +25,11 @@ #include #include #include +#include #include "ext2.h" #include "xattr.h" #include "acl.h" +#include "trace.h" #ifdef CONFIG_FS_DAX static ssize_t ext2_dax_read_iter(struct kiocb *iocb, struct iov_iter *to) @@ -153,7 +155,7 @@ int ext2_fsync(struct file *file, loff_t start, loff_t end, int datasync) int ret; struct super_block *sb = file->f_mapping->host->i_sb; - ret = generic_file_fsync(file, start, end, datasync); + ret = generic_buffers_fsync(file, start, end, datasync); if (ret == -EIO) /* We don't really know where the IO error happened... */ ext2_error(sb, __func__, @@ -161,12 +163,131 @@ int ext2_fsync(struct file *file, loff_t start, loff_t end, int datasync) return ret; } +static ssize_t ext2_dio_read_iter(struct kiocb *iocb, struct iov_iter *to) +{ + struct file *file = iocb->ki_filp; + struct inode *inode = file->f_mapping->host; + ssize_t ret; + + trace_ext2_dio_read_begin(iocb, to, 0); + inode_lock_shared(inode); + ret = iomap_dio_rw(iocb, to, &ext2_iomap_ops, NULL, 0, NULL, 0); + inode_unlock_shared(inode); + trace_ext2_dio_read_end(iocb, to, ret); + + return ret; +} + +static int ext2_dio_write_end_io(struct kiocb *iocb, ssize_t size, + int error, unsigned int flags) +{ + loff_t pos = iocb->ki_pos; + struct inode *inode = file_inode(iocb->ki_filp); + + if (error) + goto out; + + /* + * If we are extending the file, we have to update i_size here before + * page cache gets invalidated in iomap_dio_rw(). This prevents racing + * buffered reads from zeroing out too much from page cache pages. + * Note that all extending writes always happens synchronously with + * inode lock held by ext2_dio_write_iter(). So it is safe to update + * inode size here for extending file writes. + */ + pos += size; + if (pos > i_size_read(inode)) { + i_size_write(inode, pos); + mark_inode_dirty(inode); + } +out: + trace_ext2_dio_write_endio(iocb, size, error); + return error; +} + +static const struct iomap_dio_ops ext2_dio_write_ops = { + .end_io = ext2_dio_write_end_io, +}; + +static ssize_t ext2_dio_write_iter(struct kiocb *iocb, struct iov_iter *from) +{ + struct file *file = iocb->ki_filp; + struct inode *inode = file->f_mapping->host; + ssize_t ret; + unsigned int flags = 0; + unsigned long blocksize = inode->i_sb->s_blocksize; + loff_t offset = iocb->ki_pos; + loff_t count = iov_iter_count(from); + ssize_t status = 0; + + trace_ext2_dio_write_begin(iocb, from, 0); + inode_lock(inode); + ret = generic_write_checks(iocb, from); + if (ret <= 0) + goto out_unlock; + + ret = kiocb_modified(iocb); + if (ret) + goto out_unlock; + + /* use IOMAP_DIO_FORCE_WAIT for unaligned or extending writes */ + if (iocb->ki_pos + iov_iter_count(from) > i_size_read(inode) || + (!IS_ALIGNED(iocb->ki_pos | iov_iter_alignment(from), blocksize))) + flags |= IOMAP_DIO_FORCE_WAIT; + + ret = iomap_dio_rw(iocb, from, &ext2_iomap_ops, &ext2_dio_write_ops, + flags, NULL, 0); + + /* ENOTBLK is magic return value for fallback to buffered-io */ + if (ret == -ENOTBLK) + ret = 0; + + if (ret < 0 && ret != -EIOCBQUEUED) + ext2_write_failed(inode->i_mapping, offset + count); + + /* handle case for partial write and for fallback to buffered write */ + if (ret >= 0 && iov_iter_count(from)) { + loff_t pos, endbyte; + int ret2; + + iocb->ki_flags &= ~IOCB_DIRECT; + pos = iocb->ki_pos; + status = generic_perform_write(iocb, from); + if (unlikely(status < 0)) { + ret = status; + goto out_unlock; + } + + iocb->ki_pos += status; + ret += status; + endbyte = pos + status - 1; + ret2 = filemap_write_and_wait_range(inode->i_mapping, pos, + endbyte); + if (!ret2) + invalidate_mapping_pages(inode->i_mapping, + pos >> PAGE_SHIFT, + endbyte >> PAGE_SHIFT); + if (ret > 0) + generic_write_sync(iocb, ret); + } + +out_unlock: + inode_unlock(inode); + if (status) + trace_ext2_dio_write_buff_end(iocb, from, status); + trace_ext2_dio_write_end(iocb, from, ret); + return ret; +} + static ssize_t ext2_file_read_iter(struct kiocb *iocb, struct iov_iter *to) { #ifdef CONFIG_FS_DAX if (IS_DAX(iocb->ki_filp->f_mapping->host)) return ext2_dax_read_iter(iocb, to); #endif + if (iocb->ki_flags & IOCB_DIRECT) + return ext2_dio_read_iter(iocb, to); + return generic_file_read_iter(iocb, to); } @@ -176,6 +297,9 @@ static ssize_t ext2_file_write_iter(struct kiocb *iocb, struct iov_iter *from) if (IS_DAX(iocb->ki_filp->f_mapping->host)) return ext2_dax_write_iter(iocb, from); #endif + if (iocb->ki_flags & IOCB_DIRECT) + return ext2_dio_write_iter(iocb, from); + return generic_file_write_iter(iocb, from); } diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c index 26f135e7ffce..75983215c7a1 100644 --- a/fs/ext2/inode.c +++ b/fs/ext2/inode.c @@ -56,7 +56,7 @@ static inline int ext2_inode_is_fast_symlink(struct inode *inode) static void ext2_truncate_blocks(struct inode *inode, loff_t offset); -static void ext2_write_failed(struct address_space *mapping, loff_t to) +void ext2_write_failed(struct address_space *mapping, loff_t to) { struct inode *inode = mapping->host; @@ -809,9 +809,27 @@ static int ext2_iomap_begin(struct inode *inode, loff_t offset, loff_t length, bool new = false, boundary = false; u32 bno; int ret; + bool create = flags & IOMAP_WRITE; + + /* + * For writes that could fill holes inside i_size on a + * DIO_SKIP_HOLES filesystem we forbid block creations: only + * overwrites are permitted. + */ + if ((flags & IOMAP_DIRECT) && + (first_block << blkbits) < i_size_read(inode)) + create = 0; + + /* + * Writes that span EOF might trigger an IO size update on completion, + * so consider them to be dirty for the purposes of O_DSYNC even if + * there is no other metadata changes pending or have been made here. + */ + if ((flags & IOMAP_WRITE) && offset + length > i_size_read(inode)) + iomap->flags |= IOMAP_F_DIRTY; ret = ext2_get_blocks(inode, first_block, max_blocks, - &bno, &new, &boundary, flags & IOMAP_WRITE); + &bno, &new, &boundary, create); if (ret < 0) return ret; @@ -823,6 +841,12 @@ static int ext2_iomap_begin(struct inode *inode, loff_t offset, loff_t length, iomap->bdev = inode->i_sb->s_bdev; if (ret == 0) { + /* + * Switch to buffered-io for writing to holes in a non-extent + * based filesystem to avoid stale data exposure problem. + */ + if (!create && (flags & IOMAP_WRITE) && (flags & IOMAP_DIRECT)) + return -ENOTBLK; iomap->type = IOMAP_HOLE; iomap->addr = IOMAP_NULL_ADDR; iomap->length = 1 << blkbits; @@ -844,6 +868,13 @@ static int ext2_iomap_end(struct inode *inode, loff_t offset, loff_t length, ssize_t written, unsigned flags, struct iomap *iomap) { + /* + * Switch to buffered-io in case of any error. + * Blocks allocated can be used by the buffered-io path. + */ + if ((flags & IOMAP_DIRECT) && (flags & IOMAP_WRITE) && written == 0) + return -ENOTBLK; + if (iomap->type == IOMAP_MAPPED && written < length && (flags & IOMAP_WRITE)) @@ -908,22 +939,6 @@ static sector_t ext2_bmap(struct address_space *mapping, sector_t block) return generic_block_bmap(mapping,block,ext2_get_block); } -static ssize_t -ext2_direct_IO(struct kiocb *iocb, struct iov_iter *iter) -{ - struct file *file = iocb->ki_filp; - struct address_space *mapping = file->f_mapping; - struct inode *inode = mapping->host; - size_t count = iov_iter_count(iter); - loff_t offset = iocb->ki_pos; - ssize_t ret; - - ret = blockdev_direct_IO(iocb, inode, iter, ext2_get_block); - if (ret < 0 && iov_iter_rw(iter) == WRITE) - ext2_write_failed(mapping, offset + count); - return ret; -} - static int ext2_writepages(struct address_space *mapping, struct writeback_control *wbc) { @@ -946,7 +961,7 @@ const struct address_space_operations ext2_aops = { .write_begin = ext2_write_begin, .write_end = ext2_write_end, .bmap = ext2_bmap, - .direct_IO = ext2_direct_IO, + .direct_IO = noop_direct_IO, .writepages = ext2_writepages, .migrate_folio = buffer_migrate_folio, .is_partially_uptodate = block_is_partially_uptodate, @@ -1259,9 +1274,8 @@ static int ext2_setsize(struct inode *inode, loff_t newsize) inode_dio_wait(inode); if (IS_DAX(inode)) - error = dax_zero_range(inode, newsize, - PAGE_ALIGN(newsize) - newsize, NULL, - &ext2_iomap_ops); + error = dax_truncate_page(inode, newsize, NULL, + &ext2_iomap_ops); else error = block_truncate_page(inode->i_mapping, newsize, ext2_get_block); diff --git a/fs/ext2/namei.c b/fs/ext2/namei.c index 7f5dfa87cc95..937dd8f60f96 100644 --- a/fs/ext2/namei.c +++ b/fs/ext2/namei.c @@ -269,26 +269,25 @@ out_dir: goto out; } -static int ext2_unlink(struct inode * dir, struct dentry *dentry) +static int ext2_unlink(struct inode *dir, struct dentry *dentry) { - struct inode * inode = d_inode(dentry); - struct ext2_dir_entry_2 * de; - struct page * page; - void *page_addr; + struct inode *inode = d_inode(dentry); + struct ext2_dir_entry_2 *de; + struct page *page; int err; err = dquot_initialize(dir); if (err) goto out; - de = ext2_find_entry(dir, &dentry->d_name, &page, &page_addr); + de = ext2_find_entry(dir, &dentry->d_name, &page); if (IS_ERR(de)) { err = PTR_ERR(de); goto out; } - err = ext2_delete_entry (de, page, page_addr); - ext2_put_page(page, page_addr); + err = ext2_delete_entry(de, page); + ext2_put_page(page, de); if (err) goto out; @@ -323,10 +322,8 @@ static int ext2_rename (struct mnt_idmap * idmap, struct inode * old_inode = d_inode(old_dentry); struct inode * new_inode = d_inode(new_dentry); struct page * dir_page = NULL; - void *dir_page_addr; struct ext2_dir_entry_2 * dir_de = NULL; struct page * old_page; - void *old_page_addr; struct ext2_dir_entry_2 * old_de; int err; @@ -335,28 +332,24 @@ static int ext2_rename (struct mnt_idmap * idmap, err = dquot_initialize(old_dir); if (err) - goto out; + return err; err = dquot_initialize(new_dir); if (err) - goto out; + return err; - old_de = ext2_find_entry(old_dir, &old_dentry->d_name, &old_page, - &old_page_addr); - if (IS_ERR(old_de)) { - err = PTR_ERR(old_de); - goto out; - } + old_de = ext2_find_entry(old_dir, &old_dentry->d_name, &old_page); + if (IS_ERR(old_de)) + return PTR_ERR(old_de); if (S_ISDIR(old_inode->i_mode)) { err = -EIO; - dir_de = ext2_dotdot(old_inode, &dir_page, &dir_page_addr); + dir_de = ext2_dotdot(old_inode, &dir_page); if (!dir_de) goto out_old; } if (new_inode) { - void *page_addr; struct page *new_page; struct ext2_dir_entry_2 *new_de; @@ -365,14 +358,13 @@ static int ext2_rename (struct mnt_idmap * idmap, goto out_dir; new_de = ext2_find_entry(new_dir, &new_dentry->d_name, - &new_page, &page_addr); + &new_page); if (IS_ERR(new_de)) { err = PTR_ERR(new_de); goto out_dir; } - err = ext2_set_link(new_dir, new_de, new_page, page_addr, - old_inode, true); - ext2_put_page(new_page, page_addr); + err = ext2_set_link(new_dir, new_de, new_page, old_inode, true); + ext2_put_page(new_page, new_de); if (err) goto out_dir; new_inode->i_ctime = current_time(new_inode); @@ -394,27 +386,20 @@ static int ext2_rename (struct mnt_idmap * idmap, old_inode->i_ctime = current_time(old_inode); mark_inode_dirty(old_inode); - ext2_delete_entry(old_de, old_page, old_page_addr); - - if (dir_de) { - if (old_dir != new_dir) { + err = ext2_delete_entry(old_de, old_page); + if (!err && dir_de) { + if (old_dir != new_dir) err = ext2_set_link(old_inode, dir_de, dir_page, - dir_page_addr, new_dir, false); + new_dir, false); - } - ext2_put_page(dir_page, dir_page_addr); inode_dec_link_count(old_dir); } - -out_old: - ext2_put_page(old_page, old_page_addr); -out: - return err; - out_dir: if (dir_de) - ext2_put_page(dir_page, dir_page_addr); - goto out_old; + ext2_put_page(dir_page, dir_de); +out_old: + ext2_put_page(old_page, old_de); + return err; } const struct inode_operations ext2_dir_inode_operations = { diff --git a/fs/ext2/super.c b/fs/ext2/super.c index f342f347a695..2959afc7541c 100644 --- a/fs/ext2/super.c +++ b/fs/ext2/super.c @@ -668,10 +668,9 @@ static int ext2_setup_super (struct super_block * sb, es->s_max_mnt_count = cpu_to_le16(EXT2_DFL_MAX_MNT_COUNT); le16_add_cpu(&es->s_mnt_count, 1); if (test_opt (sb, DEBUG)) - ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, fs=%lu, gc=%lu, " + ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, gc=%lu, " "bpg=%lu, ipg=%lu, mo=%04lx]", EXT2FS_VERSION, EXT2FS_DATE, sb->s_blocksize, - sbi->s_frag_size, sbi->s_groups_count, EXT2_BLOCKS_PER_GROUP(sb), EXT2_INODES_PER_GROUP(sb), @@ -1012,14 +1011,7 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) } } - sbi->s_frag_size = EXT2_MIN_FRAG_SIZE << - le32_to_cpu(es->s_log_frag_size); - if (sbi->s_frag_size == 0) - goto cantfind_ext2; - sbi->s_frags_per_block = sb->s_blocksize / sbi->s_frag_size; - sbi->s_blocks_per_group = le32_to_cpu(es->s_blocks_per_group); - sbi->s_frags_per_group = le32_to_cpu(es->s_frags_per_group); sbi->s_inodes_per_group = le32_to_cpu(es->s_inodes_per_group); sbi->s_inodes_per_block = sb->s_blocksize / EXT2_INODE_SIZE(sb); @@ -1045,11 +1037,10 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) goto failed_mount; } - if (sb->s_blocksize != sbi->s_frag_size) { + if (es->s_log_frag_size != es->s_log_block_size) { ext2_msg(sb, KERN_ERR, - "error: fragsize %lu != blocksize %lu" - "(not supported yet)", - sbi->s_frag_size, sb->s_blocksize); + "error: fragsize log %u != blocksize log %u", + le32_to_cpu(es->s_log_frag_size), sb->s_blocksize_bits); goto failed_mount; } @@ -1066,12 +1057,6 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) sbi->s_blocks_per_group, sbi->s_inodes_per_group + 3); goto failed_mount; } - if (sbi->s_frags_per_group > sb->s_blocksize * 8) { - ext2_msg(sb, KERN_ERR, - "error: #fragments per group too big: %lu", - sbi->s_frags_per_group); - goto failed_mount; - } if (sbi->s_inodes_per_group < sbi->s_inodes_per_block || sbi->s_inodes_per_group > sb->s_blocksize * 8) { ext2_msg(sb, KERN_ERR, diff --git a/fs/ext2/trace.c b/fs/ext2/trace.c new file mode 100644 index 000000000000..b01cdf6526fd --- /dev/null +++ b/fs/ext2/trace.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "ext2.h" +#include + +#define CREATE_TRACE_POINTS +#include "trace.h" diff --git a/fs/ext2/trace.h b/fs/ext2/trace.h new file mode 100644 index 000000000000..7d230e13576e --- /dev/null +++ b/fs/ext2/trace.h @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM ext2 + +#if !defined(_EXT2_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _EXT2_TRACE_H + +#include + +DECLARE_EVENT_CLASS(ext2_dio_class, + TP_PROTO(struct kiocb *iocb, struct iov_iter *iter, ssize_t ret), + TP_ARGS(iocb, iter, ret), + TP_STRUCT__entry( + __field(dev_t, dev) + __field(ino_t, ino) + __field(loff_t, isize) + __field(loff_t, pos) + __field(size_t, count) + __field(int, ki_flags) + __field(bool, aio) + __field(ssize_t, ret) + ), + TP_fast_assign( + __entry->dev = file_inode(iocb->ki_filp)->i_sb->s_dev; + __entry->ino = file_inode(iocb->ki_filp)->i_ino; + __entry->isize = file_inode(iocb->ki_filp)->i_size; + __entry->pos = iocb->ki_pos; + __entry->count = iov_iter_count(iter); + __entry->ki_flags = iocb->ki_flags; + __entry->aio = !is_sync_kiocb(iocb); + __entry->ret = ret; + ), + TP_printk("dev %d:%d ino 0x%lx isize 0x%llx pos 0x%llx len %zu flags %s aio %d ret %zd", + MAJOR(__entry->dev), MINOR(__entry->dev), + __entry->ino, + __entry->isize, + __entry->pos, + __entry->count, + __print_flags(__entry->ki_flags, "|", TRACE_IOCB_STRINGS), + __entry->aio, + __entry->ret) +); + +#define DEFINE_DIO_RW_EVENT(name) \ +DEFINE_EVENT(ext2_dio_class, name, \ + TP_PROTO(struct kiocb *iocb, struct iov_iter *iter, ssize_t ret), \ + TP_ARGS(iocb, iter, ret)) +DEFINE_DIO_RW_EVENT(ext2_dio_write_begin); +DEFINE_DIO_RW_EVENT(ext2_dio_write_end); +DEFINE_DIO_RW_EVENT(ext2_dio_write_buff_end); +DEFINE_DIO_RW_EVENT(ext2_dio_read_begin); +DEFINE_DIO_RW_EVENT(ext2_dio_read_end); + +TRACE_EVENT(ext2_dio_write_endio, + TP_PROTO(struct kiocb *iocb, ssize_t size, int ret), + TP_ARGS(iocb, size, ret), + TP_STRUCT__entry( + __field(dev_t, dev) + __field(ino_t, ino) + __field(loff_t, isize) + __field(loff_t, pos) + __field(ssize_t, size) + __field(int, ki_flags) + __field(bool, aio) + __field(int, ret) + ), + TP_fast_assign( + __entry->dev = file_inode(iocb->ki_filp)->i_sb->s_dev; + __entry->ino = file_inode(iocb->ki_filp)->i_ino; + __entry->isize = file_inode(iocb->ki_filp)->i_size; + __entry->pos = iocb->ki_pos; + __entry->size = size; + __entry->ki_flags = iocb->ki_flags; + __entry->aio = !is_sync_kiocb(iocb); + __entry->ret = ret; + ), + TP_printk("dev %d:%d ino 0x%lx isize 0x%llx pos 0x%llx len %zd flags %s aio %d ret %d", + MAJOR(__entry->dev), MINOR(__entry->dev), + __entry->ino, + __entry->isize, + __entry->pos, + __entry->size, + __print_flags(__entry->ki_flags, "|", TRACE_IOCB_STRINGS), + __entry->aio, + __entry->ret) +); + +#endif /* _EXT2_TRACE_H */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace +#include diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index 02fa8a64dc3f..0a2d55faa095 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -127,6 +127,58 @@ enum SHIFT_DIRECTION { SHIFT_RIGHT, }; +/* + * For each criteria, mballoc has slightly different way of finding + * the required blocks nad usually, higher the criteria the slower the + * allocation. We start at lower criterias and keep falling back to + * higher ones if we are not able to find any blocks. Lower (earlier) + * criteria are faster. + */ +enum criteria { + /* + * Used when number of blocks needed is a power of 2. This + * doesn't trigger any disk IO except prefetch and is the + * fastest criteria. + */ + CR_POWER2_ALIGNED, + + /* + * Tries to lookup in-memory data structures to find the most + * suitable group that satisfies goal request. No disk IO + * except block prefetch. + */ + CR_GOAL_LEN_FAST, + + /* + * Same as CR_GOAL_LEN_FAST but is allowed to reduce the goal + * length to the best available length for faster allocation. + */ + CR_BEST_AVAIL_LEN, + + /* + * Reads each block group sequentially, performing disk IO if + * necessary, to find find_suitable block group. Tries to + * allocate goal length but might trim the request if nothing + * is found after enough tries. + */ + CR_GOAL_LEN_SLOW, + + /* + * Finds the first free set of blocks and allocates + * those. This is only used in rare cases when + * CR_GOAL_LEN_SLOW also fails to allocate anything. + */ + CR_ANY_FREE, + + /* + * Number of criterias defined. + */ + EXT4_MB_NUM_CRS +}; + +/* criteria below which we use fast block scanning and avoid unnecessary IO */ +#define CR_FAST CR_GOAL_LEN_SLOW + /* * Flags used in mballoc's allocation_context flags field. * @@ -165,9 +217,12 @@ enum SHIFT_DIRECTION { /* Do strict check for free blocks while retrying block allocation */ #define EXT4_MB_STRICT_CHECK 0x4000 /* Large fragment size list lookup succeeded at least once for cr = 0 */ -#define EXT4_MB_CR0_OPTIMIZED 0x8000 +#define EXT4_MB_CR_POWER2_ALIGNED_OPTIMIZED 0x8000 /* Avg fragment size rb tree lookup succeeded at least once for cr = 1 */ -#define EXT4_MB_CR1_OPTIMIZED 0x00010000 +#define EXT4_MB_CR_GOAL_LEN_FAST_OPTIMIZED 0x00010000 +/* Avg fragment size rb tree lookup succeeded at least once for cr = 1.5 */ +#define EXT4_MB_CR_BEST_AVAIL_LEN_OPTIMIZED 0x00020000 + struct ext4_allocation_request { /* target inode for block we're allocating */ struct inode *inode; @@ -1532,21 +1587,25 @@ struct ext4_sb_info { unsigned long s_mb_last_start; unsigned int s_mb_prefetch; unsigned int s_mb_prefetch_limit; + unsigned int s_mb_best_avail_max_trim_order; /* stats for buddy allocator */ atomic_t s_bal_reqs; /* number of reqs with len > 1 */ atomic_t s_bal_success; /* we found long enough chunks */ atomic_t s_bal_allocated; /* in blocks */ atomic_t s_bal_ex_scanned; /* total extents scanned */ + atomic_t s_bal_cX_ex_scanned[EXT4_MB_NUM_CRS]; /* total extents scanned */ atomic_t s_bal_groups_scanned; /* number of groups scanned */ atomic_t s_bal_goals; /* goal hits */ + atomic_t s_bal_len_goals; /* len goal hits */ atomic_t s_bal_breaks; /* too long searches */ atomic_t s_bal_2orders; /* 2^order hits */ - atomic_t s_bal_cr0_bad_suggestions; - atomic_t s_bal_cr1_bad_suggestions; - atomic64_t s_bal_cX_groups_considered[4]; - atomic64_t s_bal_cX_hits[4]; - atomic64_t s_bal_cX_failed[4]; /* cX loop didn't find blocks */ + atomic_t s_bal_p2_aligned_bad_suggestions; + atomic_t s_bal_goal_fast_bad_suggestions; + atomic_t s_bal_best_avail_bad_suggestions; + atomic64_t s_bal_cX_groups_considered[EXT4_MB_NUM_CRS]; + atomic64_t s_bal_cX_hits[EXT4_MB_NUM_CRS]; + atomic64_t s_bal_cX_failed[EXT4_MB_NUM_CRS]; /* cX loop didn't find blocks */ atomic_t s_mb_buddies_generated; /* number of buddies generated */ atomic64_t s_mb_generation_time; atomic_t s_mb_lost_chunks; @@ -2632,10 +2691,6 @@ extern void ext4_get_group_no_and_offset(struct super_block *sb, extern ext4_group_t ext4_get_group_number(struct super_block *sb, ext4_fsblk_t block); -extern unsigned int ext4_block_group(struct super_block *sb, - ext4_fsblk_t blocknr); -extern ext4_grpblk_t ext4_block_group_offset(struct super_block *sb, - ext4_fsblk_t blocknr); extern int ext4_bg_has_super(struct super_block *sb, ext4_group_t group); extern unsigned long ext4_bg_num_gdb(struct super_block *sb, ext4_group_t group); @@ -2841,8 +2896,6 @@ int ext4_fc_record_regions(struct super_block *sb, int ino, /* mballoc.c */ extern const struct seq_operations ext4_mb_seq_groups_ops; extern const struct seq_operations ext4_mb_seq_structs_summary_ops; -extern long ext4_mb_stats; -extern long ext4_mb_max_to_scan; extern int ext4_seq_mb_stats_show(struct seq_file *seq, void *offset); extern int ext4_mb_init(struct super_block *); extern int ext4_mb_release(struct super_block *); @@ -3481,14 +3534,8 @@ extern int ext4_try_to_write_inline_data(struct address_space *mapping, struct inode *inode, loff_t pos, unsigned len, struct page **pagep); -extern int ext4_write_inline_data_end(struct inode *inode, - loff_t pos, unsigned len, - unsigned copied, - struct page *page); -extern struct buffer_head * -ext4_journalled_write_inline_data(struct inode *inode, - unsigned len, - struct page *page); +int ext4_write_inline_data_end(struct inode *inode, loff_t pos, unsigned len, + unsigned copied, struct folio *folio); extern int ext4_da_write_inline_data_begin(struct address_space *mapping, struct inode *inode, loff_t pos, unsigned len, diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index 35703dce23a3..e4115d338f10 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c @@ -3123,7 +3123,7 @@ void ext4_ext_release(struct super_block *sb) #endif } -static int ext4_zeroout_es(struct inode *inode, struct ext4_extent *ex) +static void ext4_zeroout_es(struct inode *inode, struct ext4_extent *ex) { ext4_lblk_t ee_block; ext4_fsblk_t ee_pblock; @@ -3134,10 +3134,10 @@ static int ext4_zeroout_es(struct inode *inode, struct ext4_extent *ex) ee_pblock = ext4_ext_pblock(ex); if (ee_len == 0) - return 0; + return; - return ext4_es_insert_extent(inode, ee_block, ee_len, ee_pblock, - EXTENT_STATUS_WRITTEN); + ext4_es_insert_extent(inode, ee_block, ee_len, ee_pblock, + EXTENT_STATUS_WRITTEN); } /* FIXME!! we need to try to merge to left or right after zero-out */ @@ -3287,7 +3287,7 @@ static int ext4_split_extent_at(handle_t *handle, err = ext4_ext_dirty(handle, inode, path + path->p_depth); if (!err) /* update extent status tree */ - err = ext4_zeroout_es(inode, &zero_ex); + ext4_zeroout_es(inode, &zero_ex); /* If we failed at this point, we don't know in which * state the extent tree exactly is so don't try to fix * length of the original extent as it may do even more @@ -3640,9 +3640,8 @@ fallback: out: /* If we have gotten a failure, don't zero out status tree */ if (!err) { - err = ext4_zeroout_es(inode, &zero_ex1); - if (!err) - err = ext4_zeroout_es(inode, &zero_ex2); + ext4_zeroout_es(inode, &zero_ex1); + ext4_zeroout_es(inode, &zero_ex2); } return err ? err : allocated; } @@ -4403,15 +4402,8 @@ int ext4_ext_truncate(handle_t *handle, struct inode *inode) last_block = (inode->i_size + sb->s_blocksize - 1) >> EXT4_BLOCK_SIZE_BITS(sb); -retry: - err = ext4_es_remove_extent(inode, last_block, - EXT_MAX_BLOCKS - last_block); - if (err == -ENOMEM) { - memalloc_retry_wait(GFP_ATOMIC); - goto retry; - } - if (err) - return err; + ext4_es_remove_extent(inode, last_block, EXT_MAX_BLOCKS - last_block); + retry_remove_space: err = ext4_ext_remove_space(inode, last_block, EXT_MAX_BLOCKS - 1); if (err == -ENOMEM) { @@ -5363,13 +5355,7 @@ static int ext4_collapse_range(struct file *file, loff_t offset, loff_t len) down_write(&EXT4_I(inode)->i_data_sem); ext4_discard_preallocations(inode, 0); - - ret = ext4_es_remove_extent(inode, punch_start, - EXT_MAX_BLOCKS - punch_start); - if (ret) { - up_write(&EXT4_I(inode)->i_data_sem); - goto out_stop; - } + ext4_es_remove_extent(inode, punch_start, EXT_MAX_BLOCKS - punch_start); ret = ext4_ext_remove_space(inode, punch_start, punch_stop - 1); if (ret) { @@ -5547,12 +5533,7 @@ static int ext4_insert_range(struct file *file, loff_t offset, loff_t len) ext4_free_ext_path(path); } - ret = ext4_es_remove_extent(inode, offset_lblk, - EXT_MAX_BLOCKS - offset_lblk); - if (ret) { - up_write(&EXT4_I(inode)->i_data_sem); - goto out_stop; - } + ext4_es_remove_extent(inode, offset_lblk, EXT_MAX_BLOCKS - offset_lblk); /* * if offset_lblk lies in a hole which is at start of file, use @@ -5610,12 +5591,8 @@ ext4_swap_extents(handle_t *handle, struct inode *inode1, BUG_ON(!inode_is_locked(inode1)); BUG_ON(!inode_is_locked(inode2)); - *erp = ext4_es_remove_extent(inode1, lblk1, count); - if (unlikely(*erp)) - return 0; - *erp = ext4_es_remove_extent(inode2, lblk2, count); - if (unlikely(*erp)) - return 0; + ext4_es_remove_extent(inode1, lblk1, count); + ext4_es_remove_extent(inode2, lblk2, count); while (count) { struct ext4_extent *ex1, *ex2, tmp_ex; diff --git a/fs/ext4/extents_status.c b/fs/ext4/extents_status.c index 595abb9e7d74..9b5b8951afb4 100644 --- a/fs/ext4/extents_status.c +++ b/fs/ext4/extents_status.c @@ -144,9 +144,11 @@ static struct kmem_cache *ext4_es_cachep; static struct kmem_cache *ext4_pending_cachep; -static int __es_insert_extent(struct inode *inode, struct extent_status *newes); +static int __es_insert_extent(struct inode *inode, struct extent_status *newes, + struct extent_status *prealloc); static int __es_remove_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t end, int *reserved); + ext4_lblk_t end, int *reserved, + struct extent_status *prealloc); static int es_reclaim_extents(struct ext4_inode_info *ei, int *nr_to_scan); static int __es_shrink(struct ext4_sb_info *sbi, int nr_to_scan, struct ext4_inode_info *locked_ei); @@ -446,22 +448,36 @@ static void ext4_es_list_del(struct inode *inode) spin_unlock(&sbi->s_es_lock); } -static struct extent_status * -ext4_es_alloc_extent(struct inode *inode, ext4_lblk_t lblk, ext4_lblk_t len, - ext4_fsblk_t pblk) +/* + * Returns true if we cannot fail to allocate memory for this extent_status + * entry and cannot reclaim it until its status changes. + */ +static inline bool ext4_es_must_keep(struct extent_status *es) +{ + /* fiemap, bigalloc, and seek_data/hole need to use it. */ + if (ext4_es_is_delayed(es)) + return true; + + return false; +} + +static inline struct extent_status *__es_alloc_extent(bool nofail) +{ + if (!nofail) + return kmem_cache_alloc(ext4_es_cachep, GFP_ATOMIC); + + return kmem_cache_zalloc(ext4_es_cachep, GFP_KERNEL | __GFP_NOFAIL); +} + +static void ext4_es_init_extent(struct inode *inode, struct extent_status *es, + ext4_lblk_t lblk, ext4_lblk_t len, ext4_fsblk_t pblk) { - struct extent_status *es; - es = kmem_cache_alloc(ext4_es_cachep, GFP_ATOMIC); - if (es == NULL) - return NULL; es->es_lblk = lblk; es->es_len = len; es->es_pblk = pblk; - /* - * We don't count delayed extent because we never try to reclaim them - */ - if (!ext4_es_is_delayed(es)) { + /* We never try to reclaim a must kept extent, so we don't count it. */ + if (!ext4_es_must_keep(es)) { if (!EXT4_I(inode)->i_es_shk_nr++) ext4_es_list_add(inode); percpu_counter_inc(&EXT4_SB(inode->i_sb)-> @@ -470,8 +486,11 @@ ext4_es_alloc_extent(struct inode *inode, ext4_lblk_t lblk, ext4_lblk_t len, EXT4_I(inode)->i_es_all_nr++; percpu_counter_inc(&EXT4_SB(inode->i_sb)->s_es_stats.es_stats_all_cnt); +} - return es; +static inline void __es_free_extent(struct extent_status *es) +{ + kmem_cache_free(ext4_es_cachep, es); } static void ext4_es_free_extent(struct inode *inode, struct extent_status *es) @@ -479,8 +498,8 @@ static void ext4_es_free_extent(struct inode *inode, struct extent_status *es) EXT4_I(inode)->i_es_all_nr--; percpu_counter_dec(&EXT4_SB(inode->i_sb)->s_es_stats.es_stats_all_cnt); - /* Decrease the shrink counter when this es is not delayed */ - if (!ext4_es_is_delayed(es)) { + /* Decrease the shrink counter when we can reclaim the extent. */ + if (!ext4_es_must_keep(es)) { BUG_ON(EXT4_I(inode)->i_es_shk_nr == 0); if (!--EXT4_I(inode)->i_es_shk_nr) ext4_es_list_del(inode); @@ -488,7 +507,7 @@ static void ext4_es_free_extent(struct inode *inode, struct extent_status *es) s_es_stats.es_stats_shk_cnt); } - kmem_cache_free(ext4_es_cachep, es); + __es_free_extent(es); } /* @@ -749,7 +768,8 @@ static inline void ext4_es_insert_extent_check(struct inode *inode, } #endif -static int __es_insert_extent(struct inode *inode, struct extent_status *newes) +static int __es_insert_extent(struct inode *inode, struct extent_status *newes, + struct extent_status *prealloc) { struct ext4_es_tree *tree = &EXT4_I(inode)->i_es_tree; struct rb_node **p = &tree->root.rb_node; @@ -789,10 +809,15 @@ static int __es_insert_extent(struct inode *inode, struct extent_status *newes) } } - es = ext4_es_alloc_extent(inode, newes->es_lblk, newes->es_len, - newes->es_pblk); + if (prealloc) + es = prealloc; + else + es = __es_alloc_extent(false); if (!es) return -ENOMEM; + ext4_es_init_extent(inode, es, newes->es_lblk, newes->es_len, + newes->es_pblk); + rb_link_node(&es->rb_node, parent, p); rb_insert_color(&es->rb_node, &tree->root); @@ -804,26 +829,27 @@ out: /* * ext4_es_insert_extent() adds information to an inode's extent * status tree. - * - * Return 0 on success, error code on failure. */ -int ext4_es_insert_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t len, ext4_fsblk_t pblk, - unsigned int status) +void ext4_es_insert_extent(struct inode *inode, ext4_lblk_t lblk, + ext4_lblk_t len, ext4_fsblk_t pblk, + unsigned int status) { struct extent_status newes; ext4_lblk_t end = lblk + len - 1; - int err = 0; + int err1 = 0; + int err2 = 0; struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb); + struct extent_status *es1 = NULL; + struct extent_status *es2 = NULL; if (EXT4_SB(inode->i_sb)->s_mount_state & EXT4_FC_REPLAY) - return 0; + return; es_debug("add [%u/%u) %llu %x to extent status tree of inode %lu\n", lblk, len, pblk, status, inode->i_ino); if (!len) - return 0; + return; BUG_ON(end < lblk); @@ -842,29 +868,40 @@ int ext4_es_insert_extent(struct inode *inode, ext4_lblk_t lblk, ext4_es_insert_extent_check(inode, &newes); - write_lock(&EXT4_I(inode)->i_es_lock); - err = __es_remove_extent(inode, lblk, end, NULL); - if (err != 0) - goto error; retry: - err = __es_insert_extent(inode, &newes); - if (err == -ENOMEM && __es_shrink(EXT4_SB(inode->i_sb), - 128, EXT4_I(inode))) - goto retry; - if (err == -ENOMEM && !ext4_es_is_delayed(&newes)) - err = 0; + if (err1 && !es1) + es1 = __es_alloc_extent(true); + if ((err1 || err2) && !es2) + es2 = __es_alloc_extent(true); + write_lock(&EXT4_I(inode)->i_es_lock); + + err1 = __es_remove_extent(inode, lblk, end, NULL, es1); + if (err1 != 0) + goto error; + + err2 = __es_insert_extent(inode, &newes, es2); + if (err2 == -ENOMEM && !ext4_es_must_keep(&newes)) + err2 = 0; + if (err2 != 0) + goto error; if (sbi->s_cluster_ratio > 1 && test_opt(inode->i_sb, DELALLOC) && (status & EXTENT_STATUS_WRITTEN || status & EXTENT_STATUS_UNWRITTEN)) __revise_pending(inode, lblk, len); + /* es is pre-allocated but not used, free it. */ + if (es1 && !es1->es_len) + __es_free_extent(es1); + if (es2 && !es2->es_len) + __es_free_extent(es2); error: write_unlock(&EXT4_I(inode)->i_es_lock); + if (err1 || err2) + goto retry; ext4_es_print_tree(inode); - - return err; + return; } /* @@ -897,7 +934,7 @@ void ext4_es_cache_extent(struct inode *inode, ext4_lblk_t lblk, es = __es_tree_search(&EXT4_I(inode)->i_es_tree.root, lblk); if (!es || es->es_lblk > end) - __es_insert_extent(inode, &newes); + __es_insert_extent(inode, &newes, NULL); write_unlock(&EXT4_I(inode)->i_es_lock); } @@ -1287,6 +1324,7 @@ static unsigned int get_rsvd(struct inode *inode, ext4_lblk_t end, * @lblk - first block in range * @end - last block in range * @reserved - number of cluster reservations released + * @prealloc - pre-allocated es to avoid memory allocation failures * * If @reserved is not NULL and delayed allocation is enabled, counts * block/cluster reservations freed by removing range and if bigalloc @@ -1294,7 +1332,8 @@ static unsigned int get_rsvd(struct inode *inode, ext4_lblk_t end, * error code on failure. */ static int __es_remove_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t end, int *reserved) + ext4_lblk_t end, int *reserved, + struct extent_status *prealloc) { struct ext4_es_tree *tree = &EXT4_I(inode)->i_es_tree; struct rb_node *node; @@ -1302,14 +1341,12 @@ static int __es_remove_extent(struct inode *inode, ext4_lblk_t lblk, struct extent_status orig_es; ext4_lblk_t len1, len2; ext4_fsblk_t block; - int err; + int err = 0; bool count_reserved = true; struct rsvd_count rc; if (reserved == NULL || !test_opt(inode->i_sb, DELALLOC)) count_reserved = false; -retry: - err = 0; es = __es_tree_search(&tree->root, lblk); if (!es) @@ -1343,14 +1380,13 @@ retry: orig_es.es_len - len2; ext4_es_store_pblock_status(&newes, block, ext4_es_status(&orig_es)); - err = __es_insert_extent(inode, &newes); + err = __es_insert_extent(inode, &newes, prealloc); if (err) { + if (!ext4_es_must_keep(&newes)) + return 0; + es->es_lblk = orig_es.es_lblk; es->es_len = orig_es.es_len; - if ((err == -ENOMEM) && - __es_shrink(EXT4_SB(inode->i_sb), - 128, EXT4_I(inode))) - goto retry; goto out; } } else { @@ -1422,39 +1458,48 @@ out: * @len - number of blocks to remove * * Reduces block/cluster reservation count and for bigalloc cancels pending - * reservations as needed. Returns 0 on success, error code on failure. + * reservations as needed. */ -int ext4_es_remove_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t len) +void ext4_es_remove_extent(struct inode *inode, ext4_lblk_t lblk, + ext4_lblk_t len) { ext4_lblk_t end; int err = 0; int reserved = 0; + struct extent_status *es = NULL; if (EXT4_SB(inode->i_sb)->s_mount_state & EXT4_FC_REPLAY) - return 0; + return; trace_ext4_es_remove_extent(inode, lblk, len); es_debug("remove [%u/%u) from extent status tree of inode %lu\n", lblk, len, inode->i_ino); if (!len) - return err; + return; end = lblk + len - 1; BUG_ON(end < lblk); +retry: + if (err && !es) + es = __es_alloc_extent(true); /* * ext4_clear_inode() depends on us taking i_es_lock unconditionally * so that we are sure __es_shrink() is done with the inode before it * is reclaimed. */ write_lock(&EXT4_I(inode)->i_es_lock); - err = __es_remove_extent(inode, lblk, end, &reserved); + err = __es_remove_extent(inode, lblk, end, &reserved, es); + if (es && !es->es_len) + __es_free_extent(es); write_unlock(&EXT4_I(inode)->i_es_lock); + if (err) + goto retry; + ext4_es_print_tree(inode); ext4_da_release_space(inode, reserved); - return err; + return; } static int __es_shrink(struct ext4_sb_info *sbi, int nr_to_scan, @@ -1702,11 +1747,8 @@ static int es_do_reclaim_extents(struct ext4_inode_info *ei, ext4_lblk_t end, (*nr_to_scan)--; node = rb_next(&es->rb_node); - /* - * We can't reclaim delayed extent from status tree because - * fiemap, bigallic, and seek_data/hole need to use it. - */ - if (ext4_es_is_delayed(es)) + + if (ext4_es_must_keep(es)) goto next; if (ext4_es_is_referenced(es)) { ext4_es_clear_referenced(es); @@ -1770,7 +1812,7 @@ void ext4_clear_inode_es(struct inode *inode) while (node) { es = rb_entry(node, struct extent_status, rb_node); node = rb_next(node); - if (!ext4_es_is_delayed(es)) { + if (!ext4_es_must_keep(es)) { rb_erase(&es->rb_node, &tree->root); ext4_es_free_extent(inode, es); } @@ -1972,17 +2014,18 @@ bool ext4_is_pending(struct inode *inode, ext4_lblk_t lblk) * @lblk - logical block to be added * @allocated - indicates whether a physical cluster has been allocated for * the logical cluster that contains the block - * - * Returns 0 on success, negative error code on failure. */ -int ext4_es_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk, - bool allocated) +void ext4_es_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk, + bool allocated) { struct extent_status newes; - int err = 0; + int err1 = 0; + int err2 = 0; + struct extent_status *es1 = NULL; + struct extent_status *es2 = NULL; if (EXT4_SB(inode->i_sb)->s_mount_state & EXT4_FC_REPLAY) - return 0; + return; es_debug("add [%u/1) delayed to extent status tree of inode %lu\n", lblk, inode->i_ino); @@ -1994,29 +2037,37 @@ int ext4_es_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk, ext4_es_insert_extent_check(inode, &newes); +retry: + if (err1 && !es1) + es1 = __es_alloc_extent(true); + if ((err1 || err2) && !es2) + es2 = __es_alloc_extent(true); write_lock(&EXT4_I(inode)->i_es_lock); - err = __es_remove_extent(inode, lblk, lblk, NULL); - if (err != 0) + err1 = __es_remove_extent(inode, lblk, lblk, NULL, es1); + if (err1 != 0) goto error; -retry: - err = __es_insert_extent(inode, &newes); - if (err == -ENOMEM && __es_shrink(EXT4_SB(inode->i_sb), - 128, EXT4_I(inode))) - goto retry; - if (err != 0) + + err2 = __es_insert_extent(inode, &newes, es2); + if (err2 != 0) goto error; if (allocated) __insert_pending(inode, lblk); + /* es is pre-allocated but not used, free it. */ + if (es1 && !es1->es_len) + __es_free_extent(es1); + if (es2 && !es2->es_len) + __es_free_extent(es2); error: write_unlock(&EXT4_I(inode)->i_es_lock); + if (err1 || err2) + goto retry; ext4_es_print_tree(inode); ext4_print_pending_tree(inode); - - return err; + return; } /* diff --git a/fs/ext4/extents_status.h b/fs/ext4/extents_status.h index 4ec30a798260..d9847a4a25db 100644 --- a/fs/ext4/extents_status.h +++ b/fs/ext4/extents_status.h @@ -127,14 +127,14 @@ extern int __init ext4_init_es(void); extern void ext4_exit_es(void); extern void ext4_es_init_tree(struct ext4_es_tree *tree); -extern int ext4_es_insert_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t len, ext4_fsblk_t pblk, - unsigned int status); +extern void ext4_es_insert_extent(struct inode *inode, ext4_lblk_t lblk, + ext4_lblk_t len, ext4_fsblk_t pblk, + unsigned int status); extern void ext4_es_cache_extent(struct inode *inode, ext4_lblk_t lblk, ext4_lblk_t len, ext4_fsblk_t pblk, unsigned int status); -extern int ext4_es_remove_extent(struct inode *inode, ext4_lblk_t lblk, - ext4_lblk_t len); +extern void ext4_es_remove_extent(struct inode *inode, ext4_lblk_t lblk, + ext4_lblk_t len); extern void ext4_es_find_extent_range(struct inode *inode, int (*match_fn)(struct extent_status *es), ext4_lblk_t lblk, ext4_lblk_t end, @@ -249,8 +249,8 @@ extern void ext4_exit_pending(void); extern void ext4_init_pending_tree(struct ext4_pending_tree *tree); extern void ext4_remove_pending(struct inode *inode, ext4_lblk_t lblk); extern bool ext4_is_pending(struct inode *inode, ext4_lblk_t lblk); -extern int ext4_es_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk, - bool allocated); +extern void ext4_es_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk, + bool allocated); extern unsigned int ext4_es_delayed_clu(struct inode *inode, ext4_lblk_t lblk, ext4_lblk_t len); extern void ext4_clear_inode_es(struct inode *inode); diff --git a/fs/ext4/file.c b/fs/ext4/file.c index 6a16d07965f9..c457c8517f0f 100644 --- a/fs/ext4/file.c +++ b/fs/ext4/file.c @@ -450,13 +450,14 @@ static const struct iomap_dio_ops ext4_dio_write_ops = { */ static ssize_t ext4_dio_write_checks(struct kiocb *iocb, struct iov_iter *from, bool *ilock_shared, bool *extend, - bool *unwritten) + bool *unwritten, int *dio_flags) { struct file *file = iocb->ki_filp; struct inode *inode = file_inode(file); loff_t offset; size_t count; ssize_t ret; + bool overwrite, unaligned_io; restart: ret = ext4_generic_write_checks(iocb, from); @@ -465,16 +466,20 @@ restart: offset = iocb->ki_pos; count = ret; - if (ext4_extending_io(inode, offset, count)) - *extend = true; + + unaligned_io = ext4_unaligned_io(inode, from, offset); + *extend = ext4_extending_io(inode, offset, count); + overwrite = ext4_overwrite_io(inode, offset, count, unwritten); + /* - * Determine whether the IO operation will overwrite allocated - * and initialized blocks. - * We need exclusive i_rwsem for changing security info - * in file_modified(). + * Determine whether we need to upgrade to an exclusive lock. This is + * required to change security info in file_modified(), for extending + * I/O, any form of non-overwrite I/O, and unaligned I/O to unwritten + * extents (as partial block zeroing may be required). */ - if (*ilock_shared && (!IS_NOSEC(inode) || *extend || - !ext4_overwrite_io(inode, offset, count, unwritten))) { + if (*ilock_shared && + ((!IS_NOSEC(inode) || *extend || !overwrite || + (unaligned_io && *unwritten)))) { if (iocb->ki_flags & IOCB_NOWAIT) { ret = -EAGAIN; goto out; @@ -485,6 +490,32 @@ restart: goto restart; } + /* + * Now that locking is settled, determine dio flags and exclusivity + * requirements. Unaligned writes are allowed under shared lock so long + * as they are pure overwrites. Set the iomap overwrite only flag as an + * added precaution in this case. Even though this is unnecessary, we + * can detect and warn on unexpected -EAGAIN if an unsafe unaligned + * write is ever submitted. + * + * Otherwise, concurrent unaligned writes risk data corruption due to + * partial block zeroing in the dio layer, and so the I/O must occur + * exclusively. The inode lock is already held exclusive if the write is + * non-overwrite or extending, so drain all outstanding dio and set the + * force wait dio flag. + */ + if (*ilock_shared && unaligned_io) { + *dio_flags = IOMAP_DIO_OVERWRITE_ONLY; + } else if (!*ilock_shared && (unaligned_io || *extend)) { + if (iocb->ki_flags & IOCB_NOWAIT) { + ret = -EAGAIN; + goto out; + } + if (unaligned_io && (!overwrite || *unwritten)) + inode_dio_wait(inode); + *dio_flags = IOMAP_DIO_FORCE_WAIT; + } + ret = file_modified(file); if (ret < 0) goto out; @@ -506,17 +537,10 @@ static ssize_t ext4_dio_write_iter(struct kiocb *iocb, struct iov_iter *from) loff_t offset = iocb->ki_pos; size_t count = iov_iter_count(from); const struct iomap_ops *iomap_ops = &ext4_iomap_ops; - bool extend = false, unaligned_io = false, unwritten = false; + bool extend = false, unwritten = false; bool ilock_shared = true; + int dio_flags = 0; - /* - * We initially start with shared inode lock unless it is - * unaligned IO which needs exclusive lock anyways. - */ - if (ext4_unaligned_io(inode, from, offset)) { - unaligned_io = true; - ilock_shared = false; - } /* * Quick check here without any i_rwsem lock to see if it is extending * IO. A more reliable check is done in ext4_dio_write_checks() with @@ -549,16 +573,11 @@ static ssize_t ext4_dio_write_iter(struct kiocb *iocb, struct iov_iter *from) return ext4_buffered_write_iter(iocb, from); } - ret = ext4_dio_write_checks(iocb, from, - &ilock_shared, &extend, &unwritten); + ret = ext4_dio_write_checks(iocb, from, &ilock_shared, &extend, + &unwritten, &dio_flags); if (ret <= 0) return ret; - /* if we're going to block and IOCB_NOWAIT is set, return -EAGAIN */ - if ((iocb->ki_flags & IOCB_NOWAIT) && (unaligned_io || extend)) { - ret = -EAGAIN; - goto out; - } /* * Make sure inline data cannot be created anymore since we are going * to allocate blocks for DIO. We know the inode does not have any @@ -569,19 +588,6 @@ static ssize_t ext4_dio_write_iter(struct kiocb *iocb, struct iov_iter *from) offset = iocb->ki_pos; count = ret; - /* - * Unaligned direct IO must be serialized among each other as zeroing - * of partial blocks of two competing unaligned IOs can result in data - * corruption. - * - * So we make sure we don't allow any unaligned IO in flight. - * For IOs where we need not wait (like unaligned non-AIO DIO), - * below inode_dio_wait() may anyway become a no-op, since we start - * with exclusive lock. - */ - if (unaligned_io) - inode_dio_wait(inode); - if (extend) { handle = ext4_journal_start(inode, EXT4_HT_INODE, 2); if (IS_ERR(handle)) { @@ -601,8 +607,8 @@ static ssize_t ext4_dio_write_iter(struct kiocb *iocb, struct iov_iter *from) if (ilock_shared && !unwritten) iomap_ops = &ext4_iomap_overwrite_ops; ret = iomap_dio_rw(iocb, from, iomap_ops, &ext4_dio_write_ops, - (unaligned_io || extend) ? IOMAP_DIO_FORCE_WAIT : 0, - NULL, 0); + dio_flags, NULL, 0); + WARN_ON_ONCE(ret == -EAGAIN && !(iocb->ki_flags & IOCB_NOWAIT)); if (ret == -ENOTBLK) ret = 0; diff --git a/fs/ext4/fsync.c b/fs/ext4/fsync.c index 2a143209aa0c..0c56f3a011a1 100644 --- a/fs/ext4/fsync.c +++ b/fs/ext4/fsync.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "ext4.h" #include "ext4_jbd2.h" @@ -78,21 +79,13 @@ static int ext4_sync_parent(struct inode *inode) return ret; } -static int ext4_fsync_nojournal(struct inode *inode, bool datasync, - bool *needs_barrier) +static int ext4_fsync_nojournal(struct file *file, loff_t start, loff_t end, + int datasync, bool *needs_barrier) { - int ret, err; - - ret = sync_mapping_buffers(inode->i_mapping); - if (!(inode->i_state & I_DIRTY_ALL)) - return ret; - if (datasync && !(inode->i_state & I_DIRTY_DATASYNC)) - return ret; - - err = sync_inode_metadata(inode, 1); - if (!ret) - ret = err; + struct inode *inode = file->f_inode; + int ret; + ret = generic_buffers_fsync_noflush(file, start, end, datasync); if (!ret) ret = ext4_sync_parent(inode); if (test_opt(inode->i_sb, BARRIER)) @@ -155,6 +148,14 @@ int ext4_sync_file(struct file *file, loff_t start, loff_t end, int datasync) goto out; } + if (!sbi->s_journal) { + ret = ext4_fsync_nojournal(file, start, end, datasync, + &needs_barrier); + if (needs_barrier) + goto issue_flush; + goto out; + } + ret = file_write_and_wait_range(file, start, end); if (ret) goto out; @@ -164,11 +165,9 @@ int ext4_sync_file(struct file *file, loff_t start, loff_t end, int datasync) * Metadata is in the journal, we wait for proper transaction to * commit here. */ - if (!sbi->s_journal) - ret = ext4_fsync_nojournal(inode, datasync, &needs_barrier); - else - ret = ext4_fsync_journal(inode, datasync, &needs_barrier); + ret = ext4_fsync_journal(inode, datasync, &needs_barrier); +issue_flush: if (needs_barrier) { err = blkdev_issue_flush(inode->i_sb->s_bdev); if (!ret) diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c index c68bebe7ff4b..a9f3716119d3 100644 --- a/fs/ext4/indirect.c +++ b/fs/ext4/indirect.c @@ -651,6 +651,14 @@ int ext4_ind_map_blocks(handle_t *handle, struct inode *inode, ext4_update_inode_fsync_trans(handle, inode, 1); count = ar.len; + + /* + * Update reserved blocks/metadata blocks after successful block + * allocation which had been deferred till now. + */ + if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) + ext4_da_update_reserve_space(inode, count, 1); + got_it: map->m_flags |= EXT4_MAP_MAPPED; map->m_pblk = le32_to_cpu(chain[depth-1].key); diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index 5854bd5a3352..a4b7e4bc32d4 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -741,9 +741,8 @@ convert: } int ext4_write_inline_data_end(struct inode *inode, loff_t pos, unsigned len, - unsigned copied, struct page *page) + unsigned copied, struct folio *folio) { - struct folio *folio = page_folio(page); handle_t *handle = ext4_journal_current_handle(); int no_expand; void *kaddr; @@ -823,30 +822,6 @@ out: return ret ? ret : copied; } -struct buffer_head * -ext4_journalled_write_inline_data(struct inode *inode, - unsigned len, - struct page *page) -{ - int ret, no_expand; - void *kaddr; - struct ext4_iloc iloc; - - ret = ext4_get_inode_loc(inode, &iloc); - if (ret) { - ext4_std_error(inode->i_sb, ret); - return NULL; - } - - ext4_write_lock_xattr(inode, &no_expand); - kaddr = kmap_atomic(page); - ext4_write_inline_data(inode, &iloc, kaddr, 0, len); - kunmap_atomic(kaddr); - ext4_write_unlock_xattr(inode, &no_expand); - - return iloc.bh; -} - /* * Try to make the page cache and handle ready for the inline data case. * We can call this function in 2 cases: @@ -1964,16 +1939,8 @@ int ext4_inline_data_truncate(struct inode *inode, int *has_inline) * the extent status cache must be cleared to avoid leaving * behind stale delayed allocated extent entries */ - if (!ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) { -retry: - err = ext4_es_remove_extent(inode, 0, EXT_MAX_BLOCKS); - if (err == -ENOMEM) { - memalloc_retry_wait(GFP_ATOMIC); - goto retry; - } - if (err) - goto out_error; - } + if (!ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) + ext4_es_remove_extent(inode, 0, EXT_MAX_BLOCKS); /* Clear the content in the xattr space. */ if (inline_size > EXT4_MIN_INLINE_DATA_SIZE) { diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 9ca583360166..43775a6ca505 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -567,10 +567,8 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode, ext4_es_scan_range(inode, &ext4_es_is_delayed, map->m_lblk, map->m_lblk + map->m_len - 1)) status |= EXTENT_STATUS_DELAYED; - ret = ext4_es_insert_extent(inode, map->m_lblk, - map->m_len, map->m_pblk, status); - if (ret < 0) - retval = ret; + ext4_es_insert_extent(inode, map->m_lblk, map->m_len, + map->m_pblk, status); } up_read((&EXT4_I(inode)->i_data_sem)); @@ -632,16 +630,6 @@ found: */ ext4_clear_inode_state(inode, EXT4_STATE_EXT_MIGRATE); } - - /* - * Update reserved blocks/metadata blocks after successful - * block allocation which had been deferred till now. We don't - * support fallocate for non extent files. So we can update - * reserve space here. - */ - if ((retval > 0) && - (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)) - ext4_da_update_reserve_space(inode, retval, 1); } if (retval > 0) { @@ -689,12 +677,8 @@ found: ext4_es_scan_range(inode, &ext4_es_is_delayed, map->m_lblk, map->m_lblk + map->m_len - 1)) status |= EXTENT_STATUS_DELAYED; - ret = ext4_es_insert_extent(inode, map->m_lblk, map->m_len, - map->m_pblk, status); - if (ret < 0) { - retval = ret; - goto out_sem; - } + ext4_es_insert_extent(inode, map->m_lblk, map->m_len, + map->m_pblk, status); } out_sem: @@ -1287,7 +1271,8 @@ static int ext4_write_end(struct file *file, if (ext4_has_inline_data(inode) && ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) - return ext4_write_inline_data_end(inode, pos, len, copied, page); + return ext4_write_inline_data_end(inode, pos, len, copied, + folio); copied = block_write_end(file, mapping, pos, len, copied, page, fsdata); /* @@ -1395,7 +1380,8 @@ static int ext4_journalled_write_end(struct file *file, BUG_ON(!ext4_handle_valid(handle)); if (ext4_has_inline_data(inode)) - return ext4_write_inline_data_end(inode, pos, len, copied, page); + return ext4_write_inline_data_end(inode, pos, len, copied, + folio); if (unlikely(copied < len) && !folio_test_uptodate(folio)) { copied = 0; @@ -1638,7 +1624,6 @@ static int ext4_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk) struct ext4_sb_info *sbi = EXT4_SB(inode->i_sb); int ret; bool allocated = false; - bool reserved = false; /* * If the cluster containing lblk is shared with a delayed, @@ -1654,8 +1639,7 @@ static int ext4_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk) if (sbi->s_cluster_ratio == 1) { ret = ext4_da_reserve_space(inode); if (ret != 0) /* ENOSPC */ - goto errout; - reserved = true; + return ret; } else { /* bigalloc */ if (!ext4_es_scan_clu(inode, &ext4_es_is_delonly, lblk)) { if (!ext4_es_scan_clu(inode, @@ -1663,12 +1647,11 @@ static int ext4_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk) ret = ext4_clu_mapped(inode, EXT4_B2C(sbi, lblk)); if (ret < 0) - goto errout; + return ret; if (ret == 0) { ret = ext4_da_reserve_space(inode); if (ret != 0) /* ENOSPC */ - goto errout; - reserved = true; + return ret; } else { allocated = true; } @@ -1678,12 +1661,8 @@ static int ext4_insert_delayed_block(struct inode *inode, ext4_lblk_t lblk) } } - ret = ext4_es_insert_delayed_block(inode, lblk, allocated); - if (ret && reserved) - ext4_da_release_space(inode, 1); - -errout: - return ret; + ext4_es_insert_delayed_block(inode, lblk, allocated); + return 0; } /* @@ -1780,7 +1759,6 @@ add_delayed: set_buffer_new(bh); set_buffer_delay(bh); } else if (retval > 0) { - int ret; unsigned int status; if (unlikely(retval != map->m_len)) { @@ -1793,10 +1771,8 @@ add_delayed: status = map->m_flags & EXT4_MAP_UNWRITTEN ? EXTENT_STATUS_UNWRITTEN : EXTENT_STATUS_WRITTEN; - ret = ext4_es_insert_extent(inode, map->m_lblk, map->m_len, - map->m_pblk, status); - if (ret != 0) - retval = ret; + ext4_es_insert_extent(inode, map->m_lblk, map->m_len, + map->m_pblk, status); } out_unlock: @@ -2321,11 +2297,11 @@ static int ext4_da_writepages_trans_blocks(struct inode *inode) MAX_WRITEPAGES_EXTENT_LEN + bpp - 1, bpp); } -static int ext4_journal_page_buffers(handle_t *handle, struct page *page, - int len) +static int ext4_journal_folio_buffers(handle_t *handle, struct folio *folio, + size_t len) { - struct buffer_head *page_bufs = page_buffers(page); - struct inode *inode = page->mapping->host; + struct buffer_head *page_bufs = folio_buffers(folio); + struct inode *inode = folio->mapping->host; int ret, err; ret = ext4_walk_page_buffers(handle, inode, page_bufs, 0, len, @@ -2334,7 +2310,7 @@ static int ext4_journal_page_buffers(handle_t *handle, struct page *page, NULL, write_end_fn); if (ret == 0) ret = err; - err = ext4_jbd2_inode_add_write(handle, inode, page_offset(page), len); + err = ext4_jbd2_inode_add_write(handle, inode, folio_pos(folio), len); if (ret == 0) ret = err; EXT4_I(inode)->i_datasync_tid = handle->h_transaction->t_tid; @@ -2344,22 +2320,20 @@ static int ext4_journal_page_buffers(handle_t *handle, struct page *page, static int mpage_journal_page_buffers(handle_t *handle, struct mpage_da_data *mpd, - struct page *page) + struct folio *folio) { struct inode *inode = mpd->inode; loff_t size = i_size_read(inode); - int len; + size_t len = folio_size(folio); - ClearPageChecked(page); + folio_clear_checked(folio); mpd->wbc->nr_to_write--; - if (page->index == size >> PAGE_SHIFT && + if (folio_pos(folio) + len > size && !ext4_verity_in_progress(inode)) - len = size & ~PAGE_MASK; - else - len = PAGE_SIZE; + len = size - folio_pos(folio); - return ext4_journal_page_buffers(handle, page, len); + return ext4_journal_folio_buffers(handle, folio, len); } /* @@ -2499,7 +2473,7 @@ static int mpage_prepare_extent_to_map(struct mpage_da_data *mpd) /* Pending dirtying of journalled data? */ if (folio_test_checked(folio)) { err = mpage_journal_page_buffers(handle, - mpd, &folio->page); + mpd, folio); if (err < 0) goto out; mpd->journalled_more_data = 1; @@ -2944,15 +2918,15 @@ retry: * Check if we should update i_disksize * when write to the end of file but not require block allocation */ -static int ext4_da_should_update_i_disksize(struct page *page, +static int ext4_da_should_update_i_disksize(struct folio *folio, unsigned long offset) { struct buffer_head *bh; - struct inode *inode = page->mapping->host; + struct inode *inode = folio->mapping->host; unsigned int idx; int i; - bh = page_buffers(page); + bh = folio_buffers(folio); idx = offset >> inode->i_blkbits; for (i = 0; i < idx; i++) @@ -2972,17 +2946,19 @@ static int ext4_da_write_end(struct file *file, loff_t new_i_size; unsigned long start, end; int write_mode = (int)(unsigned long)fsdata; + struct folio *folio = page_folio(page); if (write_mode == FALL_BACK_TO_NONDELALLOC) return ext4_write_end(file, mapping, pos, - len, copied, page, fsdata); + len, copied, &folio->page, fsdata); trace_ext4_da_write_end(inode, pos, len, copied); if (write_mode != CONVERT_INLINE_DATA && ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA) && ext4_has_inline_data(inode)) - return ext4_write_inline_data_end(inode, pos, len, copied, page); + return ext4_write_inline_data_end(inode, pos, len, copied, + folio); if (unlikely(copied < len) && !PageUptodate(page)) copied = 0; @@ -3006,10 +2982,11 @@ static int ext4_da_write_end(struct file *file, */ new_i_size = pos + copied; if (copied && new_i_size > inode->i_size && - ext4_da_should_update_i_disksize(page, end)) + ext4_da_should_update_i_disksize(folio, end)) ext4_update_i_disksize(inode, new_i_size); - return generic_write_end(file, mapping, pos, len, copied, page, fsdata); + return generic_write_end(file, mapping, pos, len, copied, &folio->page, + fsdata); } /* @@ -3105,7 +3082,7 @@ static int ext4_read_folio(struct file *file, struct folio *folio) int ret = -EAGAIN; struct inode *inode = folio->mapping->host; - trace_ext4_readpage(&folio->page); + trace_ext4_read_folio(inode, folio); if (ext4_has_inline_data(inode)) ret = ext4_readpage_inline(inode, folio); @@ -3164,9 +3141,10 @@ static void ext4_journalled_invalidate_folio(struct folio *folio, static bool ext4_release_folio(struct folio *folio, gfp_t wait) { - journal_t *journal = EXT4_JOURNAL(folio->mapping->host); + struct inode *inode = folio->mapping->host; + journal_t *journal = EXT4_JOURNAL(inode); - trace_ext4_releasepage(&folio->page); + trace_ext4_release_folio(inode, folio); /* Page has dirty journalled data -> cannot release */ if (folio_test_checked(folio)) @@ -3992,12 +3970,8 @@ int ext4_punch_hole(struct file *file, loff_t offset, loff_t length) down_write(&EXT4_I(inode)->i_data_sem); ext4_discard_preallocations(inode, 0); - ret = ext4_es_remove_extent(inode, first_block, - stop_block - first_block); - if (ret) { - up_write(&EXT4_I(inode)->i_data_sem); - goto out_stop; - } + ext4_es_remove_extent(inode, first_block, + stop_block - first_block); if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)) ret = ext4_ext_remove_space(inode, first_block, @@ -6156,7 +6130,7 @@ retry_alloc: err = __block_write_begin(&folio->page, 0, len, ext4_get_block); if (!err) { ret = VM_FAULT_SIGBUS; - if (ext4_journal_page_buffers(handle, &folio->page, len)) + if (ext4_journal_folio_buffers(handle, folio, len)) goto out_error; } else { folio_unlock(folio); diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c index 961284cc9b65..331859511f80 100644 --- a/fs/ext4/ioctl.c +++ b/fs/ext4/ioctl.c @@ -796,6 +796,7 @@ static int ext4_ioctl_setproject(struct inode *inode, __u32 projid) int ext4_force_shutdown(struct super_block *sb, u32 flags) { struct ext4_sb_info *sbi = EXT4_SB(sb); + int ret; if (flags > EXT4_GOING_FLAGS_NOLOGFLUSH) return -EINVAL; @@ -808,7 +809,9 @@ int ext4_force_shutdown(struct super_block *sb, u32 flags) switch (flags) { case EXT4_GOING_FLAGS_DEFAULT: - freeze_bdev(sb->s_bdev); + ret = freeze_bdev(sb->s_bdev); + if (ret) + return ret; set_bit(EXT4_FLAGS_SHUTDOWN, &sbi->s_ext4_flags); thaw_bdev(sb->s_bdev); break; diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 20f67a260df5..a2475b8c9fb5 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -154,19 +154,31 @@ * structures to decide the order in which groups are to be traversed for * fulfilling an allocation request. * - * At CR = 0, we look for groups which have the largest_free_order >= the order - * of the request. We directly look at the largest free order list in the data - * structure (1) above where largest_free_order = order of the request. If that - * list is empty, we look at remaining list in the increasing order of - * largest_free_order. This allows us to perform CR = 0 lookup in O(1) time. + * At CR_POWER2_ALIGNED , we look for groups which have the largest_free_order + * >= the order of the request. We directly look at the largest free order list + * in the data structure (1) above where largest_free_order = order of the + * request. If that list is empty, we look at remaining list in the increasing + * order of largest_free_order. This allows us to perform CR_POWER2_ALIGNED + * lookup in O(1) time. * - * At CR = 1, we only consider groups where average fragment size > request - * size. So, we lookup a group which has average fragment size just above or - * equal to request size using our average fragment size group lists (data - * structure 2) in O(1) time. + * At CR_GOAL_LEN_FAST, we only consider groups where + * average fragment size > request size. So, we lookup a group which has average + * fragment size just above or equal to request size using our average fragment + * size group lists (data structure 2) in O(1) time. + * + * At CR_BEST_AVAIL_LEN, we aim to optimize allocations which can't be satisfied + * in CR_GOAL_LEN_FAST. The fact that we couldn't find a group in + * CR_GOAL_LEN_FAST suggests that there is no BG that has avg + * fragment size > goal length. So before falling to the slower + * CR_GOAL_LEN_SLOW, in CR_BEST_AVAIL_LEN we proactively trim goal length and + * then use the same fragment lists as CR_GOAL_LEN_FAST to find a BG with a big + * enough average fragment size. This increases the chances of finding a + * suitable block group in O(1) time and results in faster allocation at the + * cost of reduced size of allocation. * * If "mb_optimize_scan" mount option is not set, mballoc traverses groups in - * linear order which requires O(N) search time for each CR 0 and CR 1 phase. + * linear order which requires O(N) search time for each CR_POWER2_ALIGNED and + * CR_GOAL_LEN_FAST phase. * * The regular allocator (using the buddy cache) supports a few tunables. * @@ -351,8 +363,8 @@ * - bitlock on a group (group) * - object (inode/locality) (object) * - per-pa lock (pa) - * - cr0 lists lock (cr0) - * - cr1 tree lock (cr1) + * - cr_power2_aligned lists lock (cr_power2_aligned) + * - cr_goal_len_fast lists lock (cr_goal_len_fast) * * Paths: * - new pa @@ -384,7 +396,7 @@ * * - allocation path (ext4_mb_regular_allocator) * group - * cr0/cr1 + * cr_power2_aligned/cr_goal_len_fast */ static struct kmem_cache *ext4_pspace_cachep; static struct kmem_cache *ext4_ac_cachep; @@ -409,7 +421,7 @@ static void ext4_mb_generate_from_freelist(struct super_block *sb, void *bitmap, static void ext4_mb_new_preallocation(struct ext4_allocation_context *ac); static bool ext4_mb_good_group(struct ext4_allocation_context *ac, - ext4_group_t group, int cr); + ext4_group_t group, enum criteria cr); static int ext4_try_to_trim_range(struct super_block *sb, struct ext4_buddy *e4b, ext4_grpblk_t start, @@ -858,8 +870,8 @@ mb_update_avg_fragment_size(struct super_block *sb, struct ext4_group_info *grp) * Choose next group by traversing largest_free_order lists. Updates *new_cr if * cr level needs an update. */ -static void ext4_mb_choose_next_group_cr0(struct ext4_allocation_context *ac, - int *new_cr, ext4_group_t *group, ext4_group_t ngroups) +static void ext4_mb_choose_next_group_p2_aligned(struct ext4_allocation_context *ac, + enum criteria *new_cr, ext4_group_t *group, ext4_group_t ngroups) { struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); struct ext4_group_info *iter, *grp; @@ -868,8 +880,8 @@ static void ext4_mb_choose_next_group_cr0(struct ext4_allocation_context *ac, if (ac->ac_status == AC_STATUS_FOUND) return; - if (unlikely(sbi->s_mb_stats && ac->ac_flags & EXT4_MB_CR0_OPTIMIZED)) - atomic_inc(&sbi->s_bal_cr0_bad_suggestions); + if (unlikely(sbi->s_mb_stats && ac->ac_flags & EXT4_MB_CR_POWER2_ALIGNED_OPTIMIZED)) + atomic_inc(&sbi->s_bal_p2_aligned_bad_suggestions); grp = NULL; for (i = ac->ac_2order; i < MB_NUM_ORDERS(ac->ac_sb); i++) { @@ -884,8 +896,8 @@ static void ext4_mb_choose_next_group_cr0(struct ext4_allocation_context *ac, list_for_each_entry(iter, &sbi->s_mb_largest_free_orders[i], bb_largest_free_order_node) { if (sbi->s_mb_stats) - atomic64_inc(&sbi->s_bal_cX_groups_considered[0]); - if (likely(ext4_mb_good_group(ac, iter->bb_group, 0))) { + atomic64_inc(&sbi->s_bal_cX_groups_considered[CR_POWER2_ALIGNED]); + if (likely(ext4_mb_good_group(ac, iter->bb_group, CR_POWER2_ALIGNED))) { grp = iter; break; } @@ -897,57 +909,155 @@ static void ext4_mb_choose_next_group_cr0(struct ext4_allocation_context *ac, if (!grp) { /* Increment cr and search again */ - *new_cr = 1; + *new_cr = CR_GOAL_LEN_FAST; } else { *group = grp->bb_group; - ac->ac_flags |= EXT4_MB_CR0_OPTIMIZED; + ac->ac_flags |= EXT4_MB_CR_POWER2_ALIGNED_OPTIMIZED; } } +/* + * Find a suitable group of given order from the average fragments list. + */ +static struct ext4_group_info * +ext4_mb_find_good_group_avg_frag_lists(struct ext4_allocation_context *ac, int order) +{ + struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); + struct list_head *frag_list = &sbi->s_mb_avg_fragment_size[order]; + rwlock_t *frag_list_lock = &sbi->s_mb_avg_fragment_size_locks[order]; + struct ext4_group_info *grp = NULL, *iter; + enum criteria cr = ac->ac_criteria; + + if (list_empty(frag_list)) + return NULL; + read_lock(frag_list_lock); + if (list_empty(frag_list)) { + read_unlock(frag_list_lock); + return NULL; + } + list_for_each_entry(iter, frag_list, bb_avg_fragment_size_node) { + if (sbi->s_mb_stats) + atomic64_inc(&sbi->s_bal_cX_groups_considered[cr]); + if (likely(ext4_mb_good_group(ac, iter->bb_group, cr))) { + grp = iter; + break; + } + } + read_unlock(frag_list_lock); + return grp; +} + /* * Choose next group by traversing average fragment size list of suitable * order. Updates *new_cr if cr level needs an update. */ -static void ext4_mb_choose_next_group_cr1(struct ext4_allocation_context *ac, - int *new_cr, ext4_group_t *group, ext4_group_t ngroups) +static void ext4_mb_choose_next_group_goal_fast(struct ext4_allocation_context *ac, + enum criteria *new_cr, ext4_group_t *group, ext4_group_t ngroups) { struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); - struct ext4_group_info *grp = NULL, *iter; + struct ext4_group_info *grp = NULL; int i; - if (unlikely(ac->ac_flags & EXT4_MB_CR1_OPTIMIZED)) { + if (unlikely(ac->ac_flags & EXT4_MB_CR_GOAL_LEN_FAST_OPTIMIZED)) { if (sbi->s_mb_stats) - atomic_inc(&sbi->s_bal_cr1_bad_suggestions); + atomic_inc(&sbi->s_bal_goal_fast_bad_suggestions); } for (i = mb_avg_fragment_size_order(ac->ac_sb, ac->ac_g_ex.fe_len); i < MB_NUM_ORDERS(ac->ac_sb); i++) { - if (list_empty(&sbi->s_mb_avg_fragment_size[i])) - continue; - read_lock(&sbi->s_mb_avg_fragment_size_locks[i]); - if (list_empty(&sbi->s_mb_avg_fragment_size[i])) { - read_unlock(&sbi->s_mb_avg_fragment_size_locks[i]); - continue; - } - list_for_each_entry(iter, &sbi->s_mb_avg_fragment_size[i], - bb_avg_fragment_size_node) { - if (sbi->s_mb_stats) - atomic64_inc(&sbi->s_bal_cX_groups_considered[1]); - if (likely(ext4_mb_good_group(ac, iter->bb_group, 1))) { - grp = iter; - break; - } - } - read_unlock(&sbi->s_mb_avg_fragment_size_locks[i]); + grp = ext4_mb_find_good_group_avg_frag_lists(ac, i); if (grp) break; } if (grp) { *group = grp->bb_group; - ac->ac_flags |= EXT4_MB_CR1_OPTIMIZED; + ac->ac_flags |= EXT4_MB_CR_GOAL_LEN_FAST_OPTIMIZED; } else { - *new_cr = 2; + *new_cr = CR_BEST_AVAIL_LEN; + } +} + +/* + * We couldn't find a group in CR_GOAL_LEN_FAST so try to find the highest free fragment + * order we have and proactively trim the goal request length to that order to + * find a suitable group faster. + * + * This optimizes allocation speed at the cost of slightly reduced + * preallocations. However, we make sure that we don't trim the request too + * much and fall to CR_GOAL_LEN_SLOW in that case. + */ +static void ext4_mb_choose_next_group_best_avail(struct ext4_allocation_context *ac, + enum criteria *new_cr, ext4_group_t *group, ext4_group_t ngroups) +{ + struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); + struct ext4_group_info *grp = NULL; + int i, order, min_order; + unsigned long num_stripe_clusters = 0; + + if (unlikely(ac->ac_flags & EXT4_MB_CR_BEST_AVAIL_LEN_OPTIMIZED)) { + if (sbi->s_mb_stats) + atomic_inc(&sbi->s_bal_best_avail_bad_suggestions); + } + + /* + * mb_avg_fragment_size_order() returns order in a way that makes + * retrieving back the length using (1 << order) inaccurate. Hence, use + * fls() instead since we need to know the actual length while modifying + * goal length. + */ + order = fls(ac->ac_g_ex.fe_len); + min_order = order - sbi->s_mb_best_avail_max_trim_order; + if (min_order < 0) + min_order = 0; + + if (1 << min_order < ac->ac_o_ex.fe_len) + min_order = fls(ac->ac_o_ex.fe_len) + 1; + + if (sbi->s_stripe > 0) { + /* + * We are assuming that stripe size is always a multiple of + * cluster ratio otherwise __ext4_fill_super exists early. + */ + num_stripe_clusters = EXT4_NUM_B2C(sbi, sbi->s_stripe); + if (1 << min_order < num_stripe_clusters) + min_order = fls(num_stripe_clusters); + } + + for (i = order; i >= min_order; i--) { + int frag_order; + /* + * Scale down goal len to make sure we find something + * in the free fragments list. Basically, reduce + * preallocations. + */ + ac->ac_g_ex.fe_len = 1 << i; + + if (num_stripe_clusters > 0) { + /* + * Try to round up the adjusted goal length to + * stripe size (in cluster units) multiple for + * efficiency. + */ + ac->ac_g_ex.fe_len = roundup(ac->ac_g_ex.fe_len, + num_stripe_clusters); + } + + frag_order = mb_avg_fragment_size_order(ac->ac_sb, + ac->ac_g_ex.fe_len); + + grp = ext4_mb_find_good_group_avg_frag_lists(ac, frag_order); + if (grp) + break; + } + + if (grp) { + *group = grp->bb_group; + ac->ac_flags |= EXT4_MB_CR_BEST_AVAIL_LEN_OPTIMIZED; + } else { + /* Reset goal length to original goal length before falling into CR_GOAL_LEN_SLOW */ + ac->ac_g_ex.fe_len = ac->ac_orig_goal_len; + *new_cr = CR_GOAL_LEN_SLOW; } } @@ -955,7 +1065,7 @@ static inline int should_optimize_scan(struct ext4_allocation_context *ac) { if (unlikely(!test_opt2(ac->ac_sb, MB_OPTIMIZE_SCAN))) return 0; - if (ac->ac_criteria >= 2) + if (ac->ac_criteria >= CR_GOAL_LEN_SLOW) return 0; if (!ext4_test_inode_flag(ac->ac_inode, EXT4_INODE_EXTENTS)) return 0; @@ -1000,7 +1110,7 @@ inc_and_return: * @ngroups Total number of groups */ static void ext4_mb_choose_next_group(struct ext4_allocation_context *ac, - int *new_cr, ext4_group_t *group, ext4_group_t ngroups) + enum criteria *new_cr, ext4_group_t *group, ext4_group_t ngroups) { *new_cr = ac->ac_criteria; @@ -1009,10 +1119,12 @@ static void ext4_mb_choose_next_group(struct ext4_allocation_context *ac, return; } - if (*new_cr == 0) { - ext4_mb_choose_next_group_cr0(ac, new_cr, group, ngroups); - } else if (*new_cr == 1) { - ext4_mb_choose_next_group_cr1(ac, new_cr, group, ngroups); + if (*new_cr == CR_POWER2_ALIGNED) { + ext4_mb_choose_next_group_p2_aligned(ac, new_cr, group, ngroups); + } else if (*new_cr == CR_GOAL_LEN_FAST) { + ext4_mb_choose_next_group_goal_fast(ac, new_cr, group, ngroups); + } else if (*new_cr == CR_BEST_AVAIL_LEN) { + ext4_mb_choose_next_group_best_avail(ac, new_cr, group, ngroups); } else { /* * TODO: For CR=2, we can arrange groups in an rb tree sorted by @@ -2103,6 +2215,7 @@ static void ext4_mb_measure_extent(struct ext4_allocation_context *ac, BUG_ON(ac->ac_status != AC_STATUS_CONTINUE); ac->ac_found++; + ac->ac_cX_found[ac->ac_criteria]++; /* * The special case - take what you catch first @@ -2207,11 +2320,11 @@ int ext4_mb_find_by_goal(struct ext4_allocation_context *ac, ac->ac_g_ex.fe_len, &ex); ex.fe_logical = 0xDEADFA11; /* debug value */ - if (max >= ac->ac_g_ex.fe_len && ac->ac_g_ex.fe_len == sbi->s_stripe) { + if (max >= ac->ac_g_ex.fe_len && + ac->ac_g_ex.fe_len == EXT4_B2C(sbi, sbi->s_stripe)) { ext4_fsblk_t start; - start = ext4_group_first_block_no(ac->ac_sb, e4b->bd_group) + - ex.fe_start; + start = ext4_grp_offs_to_block(ac->ac_sb, &ex); /* use do_div to get remainder (would be 64-bit modulo) */ if (do_div(start, sbi->s_stripe) == 0) { ac->ac_found++; @@ -2277,6 +2390,7 @@ void ext4_mb_simple_scan_group(struct ext4_allocation_context *ac, break; } ac->ac_found++; + ac->ac_cX_found[ac->ac_criteria]++; ac->ac_b_ex.fe_len = 1 << i; ac->ac_b_ex.fe_start = k << i; @@ -2305,7 +2419,7 @@ void ext4_mb_complex_scan_group(struct ext4_allocation_context *ac, struct super_block *sb = ac->ac_sb; void *bitmap = e4b->bd_bitmap; struct ext4_free_extent ex; - int i; + int i, j, freelen; int free; free = e4b->bd_info->bb_free; @@ -2332,6 +2446,24 @@ void ext4_mb_complex_scan_group(struct ext4_allocation_context *ac, break; } + if (ac->ac_criteria < CR_FAST) { + /* + * In CR_GOAL_LEN_FAST and CR_BEST_AVAIL_LEN, we are + * sure that this group will have a large enough + * continuous free extent, so skip over the smaller free + * extents + */ + j = mb_find_next_bit(bitmap, + EXT4_CLUSTERS_PER_GROUP(sb), i); + freelen = j - i; + + if (freelen < ac->ac_g_ex.fe_len) { + i = j; + free -= freelen; + continue; + } + } + mb_find_extent(e4b, i, ac->ac_g_ex.fe_len, &ex); if (WARN_ON(ex.fe_len <= 0)) break; @@ -2373,7 +2505,7 @@ void ext4_mb_scan_aligned(struct ext4_allocation_context *ac, struct ext4_free_extent ex; ext4_fsblk_t first_group_block; ext4_fsblk_t a; - ext4_grpblk_t i; + ext4_grpblk_t i, stripe; int max; BUG_ON(sbi->s_stripe == 0); @@ -2385,18 +2517,21 @@ void ext4_mb_scan_aligned(struct ext4_allocation_context *ac, do_div(a, sbi->s_stripe); i = (a * sbi->s_stripe) - first_group_block; + stripe = EXT4_B2C(sbi, sbi->s_stripe); + i = EXT4_B2C(sbi, i); while (i < EXT4_CLUSTERS_PER_GROUP(sb)) { if (!mb_test_bit(i, bitmap)) { - max = mb_find_extent(e4b, i, sbi->s_stripe, &ex); - if (max >= sbi->s_stripe) { + max = mb_find_extent(e4b, i, stripe, &ex); + if (max >= stripe) { ac->ac_found++; + ac->ac_cX_found[ac->ac_criteria]++; ex.fe_logical = 0xDEADF00D; /* debug value */ ac->ac_b_ex = ex; ext4_mb_use_best_found(ac, e4b); break; } } - i += sbi->s_stripe; + i += stripe; } } @@ -2406,13 +2541,13 @@ void ext4_mb_scan_aligned(struct ext4_allocation_context *ac, * for the allocation or not. */ static bool ext4_mb_good_group(struct ext4_allocation_context *ac, - ext4_group_t group, int cr) + ext4_group_t group, enum criteria cr) { ext4_grpblk_t free, fragments; int flex_size = ext4_flex_bg_size(EXT4_SB(ac->ac_sb)); struct ext4_group_info *grp = ext4_get_group_info(ac->ac_sb, group); - BUG_ON(cr < 0 || cr >= 4); + BUG_ON(cr < CR_POWER2_ALIGNED || cr >= EXT4_MB_NUM_CRS); if (unlikely(EXT4_MB_GRP_BBITMAP_CORRUPT(grp) || !grp)) return false; @@ -2426,7 +2561,7 @@ static bool ext4_mb_good_group(struct ext4_allocation_context *ac, return false; switch (cr) { - case 0: + case CR_POWER2_ALIGNED: BUG_ON(ac->ac_2order == 0); /* Avoid using the first bg of a flexgroup for data files */ @@ -2445,15 +2580,16 @@ static bool ext4_mb_good_group(struct ext4_allocation_context *ac, return false; return true; - case 1: + case CR_GOAL_LEN_FAST: + case CR_BEST_AVAIL_LEN: if ((free / fragments) >= ac->ac_g_ex.fe_len) return true; break; - case 2: + case CR_GOAL_LEN_SLOW: if (free >= ac->ac_g_ex.fe_len) return true; break; - case 3: + case CR_ANY_FREE: return true; default: BUG(); @@ -2474,7 +2610,7 @@ static bool ext4_mb_good_group(struct ext4_allocation_context *ac, * out"! */ static int ext4_mb_good_group_nolock(struct ext4_allocation_context *ac, - ext4_group_t group, int cr) + ext4_group_t group, enum criteria cr) { struct ext4_group_info *grp = ext4_get_group_info(ac->ac_sb, group); struct super_block *sb = ac->ac_sb; @@ -2494,7 +2630,7 @@ static int ext4_mb_good_group_nolock(struct ext4_allocation_context *ac, free = grp->bb_free; if (free == 0) goto out; - if (cr <= 2 && free < ac->ac_g_ex.fe_len) + if (cr <= CR_FAST && free < ac->ac_g_ex.fe_len) goto out; if (unlikely(EXT4_MB_GRP_BBITMAP_CORRUPT(grp))) goto out; @@ -2509,15 +2645,16 @@ static int ext4_mb_good_group_nolock(struct ext4_allocation_context *ac, ext4_get_group_desc(sb, group, NULL); int ret; - /* cr=0/1 is a very optimistic search to find large - * good chunks almost for free. If buddy data is not - * ready, then this optimization makes no sense. But - * we never skip the first block group in a flex_bg, - * since this gets used for metadata block allocation, - * and we want to make sure we locate metadata blocks - * in the first block group in the flex_bg if possible. + /* + * cr=CR_POWER2_ALIGNED/CR_GOAL_LEN_FAST is a very optimistic + * search to find large good chunks almost for free. If buddy + * data is not ready, then this optimization makes no sense. But + * we never skip the first block group in a flex_bg, since this + * gets used for metadata block allocation, and we want to make + * sure we locate metadata blocks in the first block group in + * the flex_bg if possible. */ - if (cr < 2 && + if (cr < CR_FAST && (!sbi->s_log_groups_per_flex || ((group & ((1 << sbi->s_log_groups_per_flex) - 1)) != 0)) && !(ext4_has_group_desc_csum(sb) && @@ -2567,9 +2704,7 @@ ext4_group_t ext4_mb_prefetch(struct super_block *sb, ext4_group_t group, */ if (gdp && grp && !EXT4_MB_GRP_TEST_AND_SET_READ(grp) && EXT4_MB_GRP_NEED_INIT(grp) && - ext4_free_group_clusters(sb, gdp) > 0 && - !(ext4_has_group_desc_csum(sb) && - (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)))) { + ext4_free_group_clusters(sb, gdp) > 0 ) { bh = ext4_read_block_bitmap_nowait(sb, group, true); if (bh && !IS_ERR(bh)) { if (!buffer_uptodate(bh) && cnt) @@ -2610,9 +2745,7 @@ void ext4_mb_prefetch_fini(struct super_block *sb, ext4_group_t group, grp = ext4_get_group_info(sb, group); if (grp && gdp && EXT4_MB_GRP_NEED_INIT(grp) && - ext4_free_group_clusters(sb, gdp) > 0 && - !(ext4_has_group_desc_csum(sb) && - (gdp->bg_flags & cpu_to_le16(EXT4_BG_BLOCK_UNINIT)))) { + ext4_free_group_clusters(sb, gdp) > 0) { if (ext4_mb_init_group(sb, group, GFP_NOFS)) break; } @@ -2623,7 +2756,7 @@ static noinline_for_stack int ext4_mb_regular_allocator(struct ext4_allocation_context *ac) { ext4_group_t prefetch_grp = 0, ngroups, group, i; - int cr = -1, new_cr; + enum criteria new_cr, cr = CR_GOAL_LEN_FAST; int err = 0, first_err = 0; unsigned int nr = 0, prefetch_ios = 0; struct ext4_sb_info *sbi; @@ -2680,14 +2813,15 @@ ext4_mb_regular_allocator(struct ext4_allocation_context *ac) spin_unlock(&sbi->s_md_lock); } - /* Let's just scan groups to find more-less suitable blocks */ - cr = ac->ac_2order ? 0 : 1; /* - * cr == 0 try to get exact allocation, - * cr == 3 try to get anything + * Let's just scan groups to find more-less suitable blocks We + * start with CR_GOAL_LEN_FAST, unless it is power of 2 + * aligned, in which case let's do that faster approach first. */ + if (ac->ac_2order) + cr = CR_POWER2_ALIGNED; repeat: - for (; cr < 4 && ac->ac_status == AC_STATUS_CONTINUE; cr++) { + for (; cr < EXT4_MB_NUM_CRS && ac->ac_status == AC_STATUS_CONTINUE; cr++) { ac->ac_criteria = cr; /* * searching for the right group start @@ -2714,10 +2848,8 @@ repeat: * spend a lot of time loading imperfect groups */ if ((prefetch_grp == group) && - (cr > 1 || + (cr >= CR_FAST || prefetch_ios < sbi->s_mb_prefetch_limit)) { - unsigned int curr_ios = prefetch_ios; - nr = sbi->s_mb_prefetch; if (ext4_has_feature_flex_bg(sb)) { nr = 1 << sbi->s_log_groups_per_flex; @@ -2726,8 +2858,6 @@ repeat: } prefetch_grp = ext4_mb_prefetch(sb, group, nr, &prefetch_ios); - if (prefetch_ios == curr_ios) - nr = 0; } /* This now checks without needing the buddy page */ @@ -2756,10 +2886,13 @@ repeat: } ac->ac_groups_scanned++; - if (cr == 0) + if (cr == CR_POWER2_ALIGNED) ext4_mb_simple_scan_group(ac, &e4b); - else if (cr == 1 && sbi->s_stripe && - !(ac->ac_g_ex.fe_len % sbi->s_stripe)) + else if ((cr == CR_GOAL_LEN_FAST || + cr == CR_BEST_AVAIL_LEN) && + sbi->s_stripe && + !(ac->ac_g_ex.fe_len % + EXT4_B2C(sbi, sbi->s_stripe))) ext4_mb_scan_aligned(ac, &e4b); else ext4_mb_complex_scan_group(ac, &e4b); @@ -2773,6 +2906,11 @@ repeat: /* Processed all groups and haven't found blocks */ if (sbi->s_mb_stats && i == ngroups) atomic64_inc(&sbi->s_bal_cX_failed[cr]); + + if (i == ngroups && ac->ac_criteria == CR_BEST_AVAIL_LEN) + /* Reset goal length to original goal length before + * falling into CR_GOAL_LEN_SLOW */ + ac->ac_g_ex.fe_len = ac->ac_orig_goal_len; } if (ac->ac_b_ex.fe_len > 0 && ac->ac_status != AC_STATUS_FOUND && @@ -2798,7 +2936,7 @@ repeat: ac->ac_b_ex.fe_len = 0; ac->ac_status = AC_STATUS_CONTINUE; ac->ac_flags |= EXT4_MB_HINT_FIRST; - cr = 3; + cr = CR_ANY_FREE; goto repeat; } } @@ -2914,51 +3052,94 @@ int ext4_seq_mb_stats_show(struct seq_file *seq, void *offset) seq_puts(seq, "mballoc:\n"); if (!sbi->s_mb_stats) { seq_puts(seq, "\tmb stats collection turned off.\n"); - seq_puts(seq, "\tTo enable, please write \"1\" to sysfs file mb_stats.\n"); + seq_puts( + seq, + "\tTo enable, please write \"1\" to sysfs file mb_stats.\n"); return 0; } seq_printf(seq, "\treqs: %u\n", atomic_read(&sbi->s_bal_reqs)); seq_printf(seq, "\tsuccess: %u\n", atomic_read(&sbi->s_bal_success)); - seq_printf(seq, "\tgroups_scanned: %u\n", atomic_read(&sbi->s_bal_groups_scanned)); + seq_printf(seq, "\tgroups_scanned: %u\n", + atomic_read(&sbi->s_bal_groups_scanned)); - seq_puts(seq, "\tcr0_stats:\n"); - seq_printf(seq, "\t\thits: %llu\n", atomic64_read(&sbi->s_bal_cX_hits[0])); - seq_printf(seq, "\t\tgroups_considered: %llu\n", - atomic64_read(&sbi->s_bal_cX_groups_considered[0])); + /* CR_POWER2_ALIGNED stats */ + seq_puts(seq, "\tcr_p2_aligned_stats:\n"); + seq_printf(seq, "\t\thits: %llu\n", + atomic64_read(&sbi->s_bal_cX_hits[CR_POWER2_ALIGNED])); + seq_printf( + seq, "\t\tgroups_considered: %llu\n", + atomic64_read( + &sbi->s_bal_cX_groups_considered[CR_POWER2_ALIGNED])); + seq_printf(seq, "\t\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_cX_ex_scanned[CR_POWER2_ALIGNED])); seq_printf(seq, "\t\tuseless_loops: %llu\n", - atomic64_read(&sbi->s_bal_cX_failed[0])); + atomic64_read(&sbi->s_bal_cX_failed[CR_POWER2_ALIGNED])); seq_printf(seq, "\t\tbad_suggestions: %u\n", - atomic_read(&sbi->s_bal_cr0_bad_suggestions)); + atomic_read(&sbi->s_bal_p2_aligned_bad_suggestions)); - seq_puts(seq, "\tcr1_stats:\n"); - seq_printf(seq, "\t\thits: %llu\n", atomic64_read(&sbi->s_bal_cX_hits[1])); + /* CR_GOAL_LEN_FAST stats */ + seq_puts(seq, "\tcr_goal_fast_stats:\n"); + seq_printf(seq, "\t\thits: %llu\n", + atomic64_read(&sbi->s_bal_cX_hits[CR_GOAL_LEN_FAST])); seq_printf(seq, "\t\tgroups_considered: %llu\n", - atomic64_read(&sbi->s_bal_cX_groups_considered[1])); + atomic64_read( + &sbi->s_bal_cX_groups_considered[CR_GOAL_LEN_FAST])); + seq_printf(seq, "\t\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_cX_ex_scanned[CR_GOAL_LEN_FAST])); seq_printf(seq, "\t\tuseless_loops: %llu\n", - atomic64_read(&sbi->s_bal_cX_failed[1])); + atomic64_read(&sbi->s_bal_cX_failed[CR_GOAL_LEN_FAST])); seq_printf(seq, "\t\tbad_suggestions: %u\n", - atomic_read(&sbi->s_bal_cr1_bad_suggestions)); + atomic_read(&sbi->s_bal_goal_fast_bad_suggestions)); - seq_puts(seq, "\tcr2_stats:\n"); - seq_printf(seq, "\t\thits: %llu\n", atomic64_read(&sbi->s_bal_cX_hits[2])); - seq_printf(seq, "\t\tgroups_considered: %llu\n", - atomic64_read(&sbi->s_bal_cX_groups_considered[2])); + /* CR_BEST_AVAIL_LEN stats */ + seq_puts(seq, "\tcr_best_avail_stats:\n"); + seq_printf(seq, "\t\thits: %llu\n", + atomic64_read(&sbi->s_bal_cX_hits[CR_BEST_AVAIL_LEN])); + seq_printf( + seq, "\t\tgroups_considered: %llu\n", + atomic64_read( + &sbi->s_bal_cX_groups_considered[CR_BEST_AVAIL_LEN])); + seq_printf(seq, "\t\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_cX_ex_scanned[CR_BEST_AVAIL_LEN])); seq_printf(seq, "\t\tuseless_loops: %llu\n", - atomic64_read(&sbi->s_bal_cX_failed[2])); + atomic64_read(&sbi->s_bal_cX_failed[CR_BEST_AVAIL_LEN])); + seq_printf(seq, "\t\tbad_suggestions: %u\n", + atomic_read(&sbi->s_bal_best_avail_bad_suggestions)); - seq_puts(seq, "\tcr3_stats:\n"); - seq_printf(seq, "\t\thits: %llu\n", atomic64_read(&sbi->s_bal_cX_hits[3])); + /* CR_GOAL_LEN_SLOW stats */ + seq_puts(seq, "\tcr_goal_slow_stats:\n"); + seq_printf(seq, "\t\thits: %llu\n", + atomic64_read(&sbi->s_bal_cX_hits[CR_GOAL_LEN_SLOW])); seq_printf(seq, "\t\tgroups_considered: %llu\n", - atomic64_read(&sbi->s_bal_cX_groups_considered[3])); + atomic64_read( + &sbi->s_bal_cX_groups_considered[CR_GOAL_LEN_SLOW])); + seq_printf(seq, "\t\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_cX_ex_scanned[CR_GOAL_LEN_SLOW])); seq_printf(seq, "\t\tuseless_loops: %llu\n", - atomic64_read(&sbi->s_bal_cX_failed[3])); - seq_printf(seq, "\textents_scanned: %u\n", atomic_read(&sbi->s_bal_ex_scanned)); + atomic64_read(&sbi->s_bal_cX_failed[CR_GOAL_LEN_SLOW])); + + /* CR_ANY_FREE stats */ + seq_puts(seq, "\tcr_any_free_stats:\n"); + seq_printf(seq, "\t\thits: %llu\n", + atomic64_read(&sbi->s_bal_cX_hits[CR_ANY_FREE])); + seq_printf( + seq, "\t\tgroups_considered: %llu\n", + atomic64_read(&sbi->s_bal_cX_groups_considered[CR_ANY_FREE])); + seq_printf(seq, "\t\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_cX_ex_scanned[CR_ANY_FREE])); + seq_printf(seq, "\t\tuseless_loops: %llu\n", + atomic64_read(&sbi->s_bal_cX_failed[CR_ANY_FREE])); + + /* Aggregates */ + seq_printf(seq, "\textents_scanned: %u\n", + atomic_read(&sbi->s_bal_ex_scanned)); seq_printf(seq, "\t\tgoal_hits: %u\n", atomic_read(&sbi->s_bal_goals)); + seq_printf(seq, "\t\tlen_goal_hits: %u\n", + atomic_read(&sbi->s_bal_len_goals)); seq_printf(seq, "\t\t2^n_hits: %u\n", atomic_read(&sbi->s_bal_2orders)); seq_printf(seq, "\t\tbreaks: %u\n", atomic_read(&sbi->s_bal_breaks)); seq_printf(seq, "\t\tlost: %u\n", atomic_read(&sbi->s_mb_lost_chunks)); - seq_printf(seq, "\tbuddies_generated: %u/%u\n", atomic_read(&sbi->s_mb_buddies_generated), ext4_get_groups_count(sb)); @@ -2966,8 +3147,7 @@ int ext4_seq_mb_stats_show(struct seq_file *seq, void *offset) atomic64_read(&sbi->s_mb_generation_time)); seq_printf(seq, "\tpreallocated: %u\n", atomic_read(&sbi->s_mb_preallocated)); - seq_printf(seq, "\tdiscarded: %u\n", - atomic_read(&sbi->s_mb_discarded)); + seq_printf(seq, "\tdiscarded: %u\n", atomic_read(&sbi->s_mb_discarded)); return 0; } @@ -3454,6 +3634,8 @@ int ext4_mb_init(struct super_block *sb) sbi->s_mb_stats = MB_DEFAULT_STATS; sbi->s_mb_stream_request = MB_DEFAULT_STREAM_THRESHOLD; sbi->s_mb_order2_reqs = MB_DEFAULT_ORDER2_REQS; + sbi->s_mb_best_avail_max_trim_order = MB_DEFAULT_BEST_AVAIL_TRIM_ORDER; + /* * The default group preallocation is 512, which for 4k block * sizes translates to 2 megabytes. However for bigalloc file @@ -3478,7 +3660,7 @@ int ext4_mb_init(struct super_block *sb) */ if (sbi->s_stripe > 1) { sbi->s_mb_group_prealloc = roundup( - sbi->s_mb_group_prealloc, sbi->s_stripe); + sbi->s_mb_group_prealloc, EXT4_B2C(sbi, sbi->s_stripe)); } sbi->s_locality_groups = alloc_percpu(struct ext4_locality_group); @@ -4283,7 +4465,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, start_off = ((loff_t)ac->ac_o_ex.fe_logical >> (22 - bsbits)) << 22; size = 4 * 1024 * 1024; - } else if (NRL_CHECK_SIZE(ac->ac_o_ex.fe_len, + } else if (NRL_CHECK_SIZE(EXT4_C2B(sbi, ac->ac_o_ex.fe_len), (8<<20)>>bsbits, max, 8 * 1024)) { start_off = ((loff_t)ac->ac_o_ex.fe_logical >> (23 - bsbits)) << 23; @@ -4357,6 +4539,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, * placement or satisfy big request as is */ ac->ac_g_ex.fe_logical = start; ac->ac_g_ex.fe_len = EXT4_NUM_B2C(sbi, size); + ac->ac_orig_goal_len = ac->ac_g_ex.fe_len; /* define goal start in order to merge */ if (ar->pright && (ar->lright == (start + size)) && @@ -4390,11 +4573,20 @@ static void ext4_mb_collect_stats(struct ext4_allocation_context *ac) atomic_add(ac->ac_b_ex.fe_len, &sbi->s_bal_allocated); if (ac->ac_b_ex.fe_len >= ac->ac_o_ex.fe_len) atomic_inc(&sbi->s_bal_success); + atomic_add(ac->ac_found, &sbi->s_bal_ex_scanned); + for (int i=0; iac_cX_found[i], &sbi->s_bal_cX_ex_scanned[i]); + } + atomic_add(ac->ac_groups_scanned, &sbi->s_bal_groups_scanned); if (ac->ac_g_ex.fe_start == ac->ac_b_ex.fe_start && ac->ac_g_ex.fe_group == ac->ac_b_ex.fe_group) atomic_inc(&sbi->s_bal_goals); + /* did we allocate as much as normalizer originally wanted? */ + if (ac->ac_f_ex.fe_len == ac->ac_orig_goal_len) + atomic_inc(&sbi->s_bal_len_goals); + if (ac->ac_found > sbi->s_mb_max_to_scan) atomic_inc(&sbi->s_bal_breaks); } @@ -4528,6 +4720,37 @@ ext4_mb_check_group_pa(ext4_fsblk_t goal_block, return pa; } +/* + * check if found pa meets EXT4_MB_HINT_GOAL_ONLY + */ +static bool +ext4_mb_pa_goal_check(struct ext4_allocation_context *ac, + struct ext4_prealloc_space *pa) +{ + struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); + ext4_fsblk_t start; + + if (likely(!(ac->ac_flags & EXT4_MB_HINT_GOAL_ONLY))) + return true; + + /* + * If EXT4_MB_HINT_GOAL_ONLY is set, ac_g_ex will not be adjusted + * in ext4_mb_normalize_request and will keep same with ac_o_ex + * from ext4_mb_initialize_context. Choose ac_g_ex here to keep + * consistent with ext4_mb_find_by_goal. + */ + start = pa->pa_pstart + + (ac->ac_g_ex.fe_logical - pa->pa_lstart); + if (ext4_grp_offs_to_block(ac->ac_sb, &ac->ac_g_ex) != start) + return false; + + if (ac->ac_g_ex.fe_len > pa->pa_len - + EXT4_B2C(sbi, ac->ac_g_ex.fe_logical - pa->pa_lstart)) + return false; + + return true; +} + /* * search goal blocks in preallocated space */ @@ -4578,11 +4801,11 @@ ext4_mb_use_preallocated(struct ext4_allocation_context *ac) /* found preallocated blocks, use them */ spin_lock(&tmp_pa->pa_lock); - if (tmp_pa->pa_deleted == 0 && tmp_pa->pa_free) { + if (tmp_pa->pa_deleted == 0 && tmp_pa->pa_free && + likely(ext4_mb_pa_goal_check(ac, tmp_pa))) { atomic_inc(&tmp_pa->pa_count); ext4_mb_use_inode_pa(ac, tmp_pa); spin_unlock(&tmp_pa->pa_lock); - ac->ac_criteria = 10; read_unlock(&ei->i_prealloc_lock); return true; } @@ -4625,7 +4848,6 @@ ext4_mb_use_preallocated(struct ext4_allocation_context *ac) } if (cpa) { ext4_mb_use_group_pa(ac, cpa); - ac->ac_criteria = 20; return true; } return false; @@ -4849,7 +5071,7 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) pa = ac->ac_pa; - if (ac->ac_b_ex.fe_len < ac->ac_g_ex.fe_len) { + if (ac->ac_b_ex.fe_len < ac->ac_orig_goal_len) { int new_bex_start; int new_bex_end; @@ -4864,14 +5086,14 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) * fragmentation in check while ensuring logical range of best * extent doesn't overflow out of goal extent: * - * 1. Check if best ex can be kept at end of goal and still - * cover original start + * 1. Check if best ex can be kept at end of goal (before + * cr_best_avail trimmed it) and still cover original start * 2. Else, check if best ex can be kept at start of goal and * still cover original start * 3. Else, keep the best ex at start of original request. */ new_bex_end = ac->ac_g_ex.fe_logical + - EXT4_C2B(sbi, ac->ac_g_ex.fe_len); + EXT4_C2B(sbi, ac->ac_orig_goal_len); new_bex_start = new_bex_end - EXT4_C2B(sbi, ac->ac_b_ex.fe_len); if (ac->ac_o_ex.fe_logical >= new_bex_start) goto adjust_bex; @@ -4892,7 +5114,7 @@ adjust_bex: BUG_ON(ac->ac_o_ex.fe_logical < ac->ac_b_ex.fe_logical); BUG_ON(ac->ac_o_ex.fe_len > ac->ac_b_ex.fe_len); BUG_ON(new_bex_end > (ac->ac_g_ex.fe_logical + - EXT4_C2B(sbi, ac->ac_g_ex.fe_len))); + EXT4_C2B(sbi, ac->ac_orig_goal_len))); } pa->pa_lstart = ac->ac_b_ex.fe_logical; @@ -5399,6 +5621,10 @@ static void ext4_mb_show_ac(struct ext4_allocation_context *ac) (unsigned long)ac->ac_b_ex.fe_logical, (int)ac->ac_criteria); mb_debug(sb, "%u found", ac->ac_found); + mb_debug(sb, "used pa: %s, ", ac->ac_pa ? "yes" : "no"); + if (ac->ac_pa) + mb_debug(sb, "pa_type %s\n", ac->ac_pa->pa_type == MB_GROUP_PA ? + "group pa" : "inode pa"); ext4_mb_show_pa(sb); } #else @@ -5508,6 +5734,7 @@ ext4_mb_initialize_context(struct ext4_allocation_context *ac, ac->ac_o_ex.fe_start = block; ac->ac_o_ex.fe_len = len; ac->ac_g_ex = ac->ac_o_ex; + ac->ac_orig_goal_len = ac->ac_g_ex.fe_len; ac->ac_flags = ar->flags; /* we have to define context: we'll work with a file or @@ -5751,8 +5978,72 @@ out_dbg: return ret; } -static ext4_fsblk_t ext4_mb_new_blocks_simple(handle_t *handle, - struct ext4_allocation_request *ar, int *errp); +/* + * Simple allocator for Ext4 fast commit replay path. It searches for blocks + * linearly starting at the goal block and also excludes the blocks which + * are going to be in use after fast commit replay. + */ +static ext4_fsblk_t +ext4_mb_new_blocks_simple(struct ext4_allocation_request *ar, int *errp) +{ + struct buffer_head *bitmap_bh; + struct super_block *sb = ar->inode->i_sb; + struct ext4_sb_info *sbi = EXT4_SB(sb); + ext4_group_t group, nr; + ext4_grpblk_t blkoff; + ext4_grpblk_t max = EXT4_CLUSTERS_PER_GROUP(sb); + ext4_grpblk_t i = 0; + ext4_fsblk_t goal, block; + struct ext4_super_block *es = EXT4_SB(sb)->s_es; + + goal = ar->goal; + if (goal < le32_to_cpu(es->s_first_data_block) || + goal >= ext4_blocks_count(es)) + goal = le32_to_cpu(es->s_first_data_block); + + ar->len = 0; + ext4_get_group_no_and_offset(sb, goal, &group, &blkoff); + for (nr = ext4_get_groups_count(sb); nr > 0; nr--) { + bitmap_bh = ext4_read_block_bitmap(sb, group); + if (IS_ERR(bitmap_bh)) { + *errp = PTR_ERR(bitmap_bh); + pr_warn("Failed to read block bitmap\n"); + return 0; + } + + while (1) { + i = mb_find_next_zero_bit(bitmap_bh->b_data, max, + blkoff); + if (i >= max) + break; + if (ext4_fc_replay_check_excluded(sb, + ext4_group_first_block_no(sb, group) + + EXT4_C2B(sbi, i))) { + blkoff = i + 1; + } else + break; + } + brelse(bitmap_bh); + if (i < max) + break; + + if (++group >= ext4_get_groups_count(sb)) + group = 0; + + blkoff = 0; + } + + if (i >= max) { + *errp = -ENOSPC; + return 0; + } + + block = ext4_group_first_block_no(sb, group) + EXT4_C2B(sbi, i); + ext4_mb_mark_bb(sb, block, 1, 1); + ar->len = 1; + + return block; +} /* * Main entry point into mballoc to allocate blocks @@ -5777,7 +6068,7 @@ ext4_fsblk_t ext4_mb_new_blocks(handle_t *handle, trace_ext4_request_blocks(ar); if (sbi->s_mount_state & EXT4_FC_REPLAY) - return ext4_mb_new_blocks_simple(handle, ar, errp); + return ext4_mb_new_blocks_simple(ar, errp); /* Allow to use superuser reservation for quota file */ if (ext4_is_quota_file(ar->inode)) @@ -6001,68 +6292,6 @@ ext4_mb_free_metadata(handle_t *handle, struct ext4_buddy *e4b, spin_unlock(&sbi->s_md_lock); } -/* - * Simple allocator for Ext4 fast commit replay path. It searches for blocks - * linearly starting at the goal block and also excludes the blocks which - * are going to be in use after fast commit replay. - */ -static ext4_fsblk_t ext4_mb_new_blocks_simple(handle_t *handle, - struct ext4_allocation_request *ar, int *errp) -{ - struct buffer_head *bitmap_bh; - struct super_block *sb = ar->inode->i_sb; - ext4_group_t group; - ext4_grpblk_t blkoff; - ext4_grpblk_t max = EXT4_CLUSTERS_PER_GROUP(sb); - ext4_grpblk_t i = 0; - ext4_fsblk_t goal, block; - struct ext4_super_block *es = EXT4_SB(sb)->s_es; - - goal = ar->goal; - if (goal < le32_to_cpu(es->s_first_data_block) || - goal >= ext4_blocks_count(es)) - goal = le32_to_cpu(es->s_first_data_block); - - ar->len = 0; - ext4_get_group_no_and_offset(sb, goal, &group, &blkoff); - for (; group < ext4_get_groups_count(sb); group++) { - bitmap_bh = ext4_read_block_bitmap(sb, group); - if (IS_ERR(bitmap_bh)) { - *errp = PTR_ERR(bitmap_bh); - pr_warn("Failed to read block bitmap\n"); - return 0; - } - - while (1) { - i = mb_find_next_zero_bit(bitmap_bh->b_data, max, - blkoff); - if (i >= max) - break; - if (ext4_fc_replay_check_excluded(sb, - ext4_group_first_block_no(sb, group) + i)) { - blkoff = i + 1; - } else - break; - } - brelse(bitmap_bh); - if (i < max) - break; - - blkoff = 0; - } - - if (group >= ext4_get_groups_count(sb) || i >= max) { - *errp = -ENOSPC; - return 0; - } - - block = ext4_group_first_block_no(sb, group) + i; - ext4_mb_mark_bb(sb, block, 1, 1); - ar->len = 1; - - return block; -} - static void ext4_free_blocks_simple(struct inode *inode, ext4_fsblk_t block, unsigned long count) { @@ -6243,8 +6472,8 @@ do_more: * them with group lock_held */ if (test_opt(sb, DISCARD)) { - err = ext4_issue_discard(sb, block_group, bit, count, - NULL); + err = ext4_issue_discard(sb, block_group, bit, + count_clusters, NULL); if (err && err != -EOPNOTSUPP) ext4_msg(sb, KERN_WARNING, "discard request in" " group:%u block:%d count:%lu failed" @@ -6328,12 +6557,6 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode, sbi = EXT4_SB(sb); - if (sbi->s_mount_state & EXT4_FC_REPLAY) { - ext4_free_blocks_simple(inode, block, count); - return; - } - - might_sleep(); if (bh) { if (block) BUG_ON(block != bh->b_blocknr); @@ -6341,6 +6564,13 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode, block = bh->b_blocknr; } + if (sbi->s_mount_state & EXT4_FC_REPLAY) { + ext4_free_blocks_simple(inode, block, EXT4_NUM_B2C(sbi, count)); + return; + } + + might_sleep(); + if (!(flags & EXT4_FREE_BLOCKS_VALIDATED) && !ext4_inode_block_valid(inode, block, count)) { ext4_error(sb, "Freeing blocks not in datazone - " diff --git a/fs/ext4/mballoc.h b/fs/ext4/mballoc.h index 6d85ee8674a6..df6b5e7c2274 100644 --- a/fs/ext4/mballoc.h +++ b/fs/ext4/mballoc.h @@ -49,7 +49,7 @@ #define MB_DEFAULT_MIN_TO_SCAN 10 /* - * with 'ext4_mb_stats' allocator will collect stats that will be + * with 's_mb_stats' allocator will collect stats that will be * shown at umount. The collecting costs though! */ #define MB_DEFAULT_STATS 0 @@ -85,6 +85,13 @@ */ #define MB_DEFAULT_LINEAR_SCAN_THRESHOLD 16 +/* + * The maximum order upto which CR_BEST_AVAIL_LEN can trim a particular + * allocation request. Example, if we have an order 7 request and max trim order + * of 3, we can trim this request upto order 4. + */ +#define MB_DEFAULT_BEST_AVAIL_TRIM_ORDER 3 + /* * Number of valid buddy orders */ @@ -179,11 +186,18 @@ struct ext4_allocation_context { /* copy of the best found extent taken before preallocation efforts */ struct ext4_free_extent ac_f_ex; + /* + * goal len can change in CR1.5, so save the original len. This is + * used while adjusting the PA window and for accounting. + */ + ext4_grpblk_t ac_orig_goal_len; + __u32 ac_groups_considered; __u32 ac_flags; /* allocation hints */ __u16 ac_groups_scanned; __u16 ac_groups_linear_remaining; __u16 ac_found; + __u16 ac_cX_found[EXT4_MB_NUM_CRS]; __u16 ac_tail; __u16 ac_buddy; __u8 ac_status; diff --git a/fs/ext4/readpage.c b/fs/ext4/readpage.c index 6f46823fba61..3e7d160f543f 100644 --- a/fs/ext4/readpage.c +++ b/fs/ext4/readpage.c @@ -334,7 +334,7 @@ int ext4_mpage_readpages(struct inode *inode, folio_size(folio)); if (first_hole == 0) { if (ext4_need_verity(inode, folio->index) && - !fsverity_verify_page(&folio->page)) + !fsverity_verify_folio(folio)) goto set_error_page; folio_mark_uptodate(folio); folio_unlock(folio); diff --git a/fs/ext4/super.c b/fs/ext4/super.c index eaa5858d5285..c94ebf704616 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -1133,6 +1133,12 @@ static void ext4_blkdev_remove(struct ext4_sb_info *sbi) struct block_device *bdev; bdev = sbi->s_journal_bdev; if (bdev) { + /* + * Invalidate the journal device's buffers. We don't want them + * floating about in memory - the physical journal device may + * hotswapped, and it breaks the `ro-after' testing code. + */ + invalidate_bdev(bdev); blkdev_put(bdev, sbi->s_sb); sbi->s_journal_bdev = NULL; } @@ -1164,12 +1170,12 @@ static void dump_orphan_list(struct super_block *sb, struct ext4_sb_info *sbi) #ifdef CONFIG_QUOTA static int ext4_quota_off(struct super_block *sb, int type); -static inline void ext4_quota_off_umount(struct super_block *sb) +static inline void ext4_quotas_off(struct super_block *sb, int type) { - int type; + BUG_ON(type > EXT4_MAXQUOTAS); /* Use our quota_off function to clear inode flags etc. */ - for (type = 0; type < EXT4_MAXQUOTAS; type++) + for (type--; type >= 0; type--) ext4_quota_off(sb, type); } @@ -1185,7 +1191,7 @@ static inline char *get_qf_name(struct super_block *sb, lockdep_is_held(&sb->s_umount)); } #else -static inline void ext4_quota_off_umount(struct super_block *sb) +static inline void ext4_quotas_off(struct super_block *sb, int type) { } #endif @@ -1285,7 +1291,7 @@ static void ext4_put_super(struct super_block *sb) &sb->s_uuid); ext4_unregister_li_request(sb); - ext4_quota_off_umount(sb); + ext4_quotas_off(sb, EXT4_MAXQUOTAS); flush_work(&sbi->s_error_work); destroy_workqueue(sbi->rsv_conversion_wq); @@ -1332,14 +1338,8 @@ static void ext4_put_super(struct super_block *sb) sync_blockdev(sb->s_bdev); invalidate_bdev(sb->s_bdev); - if (sbi->s_journal_bdev && sbi->s_journal_bdev != sb->s_bdev) { - /* - * Invalidate the journal device's buffers. We don't want them - * floating about in memory - the physical journal device may - * hotswapped, and it breaks the `ro-after' testing code. - */ + if (sbi->s_journal_bdev) { sync_blockdev(sbi->s_journal_bdev); - invalidate_bdev(sbi->s_journal_bdev); ext4_blkdev_remove(sbi); } @@ -3703,16 +3703,13 @@ static int ext4_run_li_request(struct ext4_li_request *elr) ext4_group_t group = elr->lr_next_group; unsigned int prefetch_ios = 0; int ret = 0; + int nr = EXT4_SB(sb)->s_mb_prefetch; u64 start_time; if (elr->lr_mode == EXT4_LI_MODE_PREFETCH_BBITMAP) { - elr->lr_next_group = ext4_mb_prefetch(sb, group, - EXT4_SB(sb)->s_mb_prefetch, &prefetch_ios); - if (prefetch_ios) - ext4_mb_prefetch_fini(sb, elr->lr_next_group, - prefetch_ios); - trace_ext4_prefetch_bitmaps(sb, group, elr->lr_next_group, - prefetch_ios); + elr->lr_next_group = ext4_mb_prefetch(sb, group, nr, &prefetch_ios); + ext4_mb_prefetch_fini(sb, elr->lr_next_group, nr); + trace_ext4_prefetch_bitmaps(sb, group, elr->lr_next_group, nr); if (group >= elr->lr_next_group) { ret = 1; if (elr->lr_first_not_zeroed != ngroups && @@ -5308,6 +5305,19 @@ static int __ext4_fill_super(struct fs_context *fc, struct super_block *sb) goto failed_mount3; sbi->s_stripe = ext4_get_stripe_size(sbi); + /* + * It's hard to get stripe aligned blocks if stripe is not aligned with + * cluster, just disable stripe and alert user to simpfy code and avoid + * stripe aligned allocation which will rarely successes. + */ + if (sbi->s_stripe > 0 && sbi->s_cluster_ratio > 1 && + sbi->s_stripe % sbi->s_cluster_ratio != 0) { + ext4_msg(sb, KERN_WARNING, + "stripe (%lu) is not aligned with cluster size (%u), " + "stripe is disabled", + sbi->s_stripe, sbi->s_cluster_ratio); + sbi->s_stripe = 0; + } sbi->s_extent_max_zeroout_kb = 32; /* @@ -5578,7 +5588,7 @@ static int __ext4_fill_super(struct fs_context *fc, struct super_block *sb) ext4_msg(sb, KERN_INFO, "recovery complete"); err = ext4_mark_recovery_complete(sb, es); if (err) - goto failed_mount9; + goto failed_mount10; } if (test_opt(sb, DISCARD) && !bdev_max_discard_sectors(sb->s_bdev)) @@ -5597,7 +5607,9 @@ static int __ext4_fill_super(struct fs_context *fc, struct super_block *sb) return 0; -failed_mount9: +failed_mount10: + ext4_quotas_off(sb, EXT4_MAXQUOTAS); +failed_mount9: __maybe_unused ext4_release_orphan_info(sb); failed_mount8: ext4_unregister_sysfs(sb); @@ -5656,6 +5668,7 @@ failed_mount: brelse(sbi->s_sbh); ext4_blkdev_remove(sbi); out_fail: + invalidate_bdev(sb->s_bdev); sb->s_fs_info = NULL; return err; } @@ -5738,6 +5751,11 @@ static void ext4_init_journal_params(struct super_block *sb, journal_t *journal) journal->j_flags |= JBD2_ABORT_ON_SYNCDATA_ERR; else journal->j_flags &= ~JBD2_ABORT_ON_SYNCDATA_ERR; + /* + * Always enable journal cycle record option, letting the journal + * records log transactions continuously between each mount. + */ + journal->j_flags |= JBD2_CYCLE_RECORD; write_unlock(&journal->j_state_lock); } @@ -5990,19 +6008,27 @@ static int ext4_load_journal(struct super_block *sb, err = jbd2_journal_wipe(journal, !really_read_only); if (!err) { char *save = kmalloc(EXT4_S_ERR_LEN, GFP_KERNEL); + __le16 orig_state; + bool changed = false; if (save) memcpy(save, ((char *) es) + EXT4_S_ERR_START, EXT4_S_ERR_LEN); err = jbd2_journal_load(journal); - if (save) + if (save && memcmp(((char *) es) + EXT4_S_ERR_START, + save, EXT4_S_ERR_LEN)) { memcpy(((char *) es) + EXT4_S_ERR_START, save, EXT4_S_ERR_LEN); + changed = true; + } kfree(save); + orig_state = es->s_state; es->s_state |= cpu_to_le16(EXT4_SB(sb)->s_mount_state & EXT4_ERROR_FS); + if (orig_state != es->s_state) + changed = true; /* Write out restored error information to the superblock */ - if (!bdev_read_only(sb->s_bdev)) { + if (changed && !really_read_only) { int err2; err2 = ext4_commit_super(sb); err = err ? : err2; @@ -7037,20 +7063,8 @@ int ext4_enable_quotas(struct super_block *sb) "(type=%d, err=%d, ino=%lu). " "Please run e2fsck to fix.", type, err, qf_inums[type]); - for (type--; type >= 0; type--) { - struct inode *inode; - - inode = sb_dqopt(sb)->files[type]; - if (inode) - inode = igrab(inode); - dquot_quota_off(sb, type); - if (inode) { - lockdep_set_quota_inode(inode, - I_DATA_SEM_NORMAL); - iput(inode); - } - } + ext4_quotas_off(sb, type); return err; } } diff --git a/fs/ext4/sysfs.c b/fs/ext4/sysfs.c index 3042bc605bbf..6d332dff79dd 100644 --- a/fs/ext4/sysfs.c +++ b/fs/ext4/sysfs.c @@ -223,6 +223,7 @@ EXT4_RW_ATTR_SBI_UI(warning_ratelimit_interval_ms, s_warning_ratelimit_state.int EXT4_RW_ATTR_SBI_UI(warning_ratelimit_burst, s_warning_ratelimit_state.burst); EXT4_RW_ATTR_SBI_UI(msg_ratelimit_interval_ms, s_msg_ratelimit_state.interval); EXT4_RW_ATTR_SBI_UI(msg_ratelimit_burst, s_msg_ratelimit_state.burst); +EXT4_RW_ATTR_SBI_UI(mb_best_avail_max_trim_order, s_mb_best_avail_max_trim_order); #ifdef CONFIG_EXT4_DEBUG EXT4_RW_ATTR_SBI_UL(simulate_fail, s_simulate_fail); #endif @@ -273,6 +274,7 @@ static struct attribute *ext4_attrs[] = { ATTR_LIST(warning_ratelimit_burst), ATTR_LIST(msg_ratelimit_interval_ms), ATTR_LIST(msg_ratelimit_burst), + ATTR_LIST(mb_best_avail_max_trim_order), ATTR_LIST(errors_count), ATTR_LIST(warning_count), ATTR_LIST(msg_count), diff --git a/fs/fhandle.c b/fs/fhandle.c index f2bc27d1975e..6ea8d35a9382 100644 --- a/fs/fhandle.c +++ b/fs/fhandle.c @@ -16,7 +16,7 @@ static long do_sys_name_to_handle(const struct path *path, struct file_handle __user *ufh, - int __user *mnt_id) + int __user *mnt_id, int fh_flags) { long retval; struct file_handle f_handle; @@ -24,11 +24,14 @@ static long do_sys_name_to_handle(const struct path *path, struct file_handle *handle = NULL; /* - * We need to make sure whether the file system - * support decoding of the file handle + * We need to make sure whether the file system support decoding of + * the file handle if decodeable file handle was requested. + * Otherwise, even empty export_operations are sufficient to opt-in + * to encoding FIDs. */ if (!path->dentry->d_sb->s_export_op || - !path->dentry->d_sb->s_export_op->fh_to_dentry) + (!(fh_flags & EXPORT_FH_FID) && + !path->dentry->d_sb->s_export_op->fh_to_dentry)) return -EOPNOTSUPP; if (copy_from_user(&f_handle, ufh, sizeof(struct file_handle))) @@ -45,27 +48,28 @@ static long do_sys_name_to_handle(const struct path *path, /* convert handle size to multiple of sizeof(u32) */ handle_dwords = f_handle.handle_bytes >> 2; - /* we ask for a non connected handle */ + /* we ask for a non connectable maybe decodeable file handle */ retval = exportfs_encode_fh(path->dentry, (struct fid *)handle->f_handle, - &handle_dwords, 0); + &handle_dwords, fh_flags); handle->handle_type = retval; /* convert handle size to bytes */ handle_bytes = handle_dwords * sizeof(u32); handle->handle_bytes = handle_bytes; if ((handle->handle_bytes > f_handle.handle_bytes) || - (retval == FILEID_INVALID) || (retval == -ENOSPC)) { + (retval == FILEID_INVALID) || (retval < 0)) { /* As per old exportfs_encode_fh documentation * we could return ENOSPC to indicate overflow * But file system returned 255 always. So handle * both the values */ + if (retval == FILEID_INVALID || retval == -ENOSPC) + retval = -EOVERFLOW; /* * set the handle size to zero so we copy only * non variable part of the file_handle */ handle_bytes = 0; - retval = -EOVERFLOW; } else retval = 0; /* copy the mount id */ @@ -84,6 +88,7 @@ static long do_sys_name_to_handle(const struct path *path, * @handle: resulting file handle * @mnt_id: mount id of the file system containing the file * @flag: flag value to indicate whether to follow symlink or not + * and whether a decodable file handle is required. * * @handle->handle_size indicate the space available to store the * variable part of the file handle in bytes. If there is not @@ -96,17 +101,19 @@ SYSCALL_DEFINE5(name_to_handle_at, int, dfd, const char __user *, name, { struct path path; int lookup_flags; + int fh_flags; int err; - if ((flag & ~(AT_SYMLINK_FOLLOW | AT_EMPTY_PATH)) != 0) + if (flag & ~(AT_SYMLINK_FOLLOW | AT_EMPTY_PATH | AT_HANDLE_FID)) return -EINVAL; lookup_flags = (flag & AT_SYMLINK_FOLLOW) ? LOOKUP_FOLLOW : 0; + fh_flags = (flag & AT_HANDLE_FID) ? EXPORT_FH_FID : 0; if (flag & AT_EMPTY_PATH) lookup_flags |= LOOKUP_EMPTY; err = user_path_at(dfd, name, lookup_flags, &path); if (!err) { - err = do_sys_name_to_handle(&path, handle, mnt_id); + err = do_sys_name_to_handle(&path, handle, mnt_id, fh_flags); path_put(&path); } return err; @@ -235,7 +242,6 @@ static long do_handle_open(int mountdirfd, struct file_handle __user *ufh, retval = PTR_ERR(file); } else { retval = fd; - fsnotify_open(file); fd_install(fd, file); } path_put(&path); diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c index 6e17f8f94dfd..fbce16fedaa4 100644 --- a/fs/jbd2/journal.c +++ b/fs/jbd2/journal.c @@ -1557,8 +1557,21 @@ static int journal_reset(journal_t *journal) journal->j_first = first; journal->j_last = last; - journal->j_head = journal->j_first; - journal->j_tail = journal->j_first; + if (journal->j_head != 0 && journal->j_flags & JBD2_CYCLE_RECORD) { + /* + * Disable the cycled recording mode if the journal head block + * number is not correct. + */ + if (journal->j_head < first || journal->j_head >= last) { + printk(KERN_WARNING "JBD2: Incorrect Journal head block %lu, " + "disable journal_cycle_record\n", + journal->j_head); + journal->j_head = journal->j_first; + } + } else { + journal->j_head = journal->j_first; + } + journal->j_tail = journal->j_head; journal->j_free = journal->j_last - journal->j_first; journal->j_tail_sequence = journal->j_transaction_sequence; @@ -1730,6 +1743,7 @@ static void jbd2_mark_journal_empty(journal_t *journal, blk_opf_t write_flags) sb->s_sequence = cpu_to_be32(journal->j_tail_sequence); sb->s_start = cpu_to_be32(0); + sb->s_head = cpu_to_be32(journal->j_head); if (jbd2_has_feature_fast_commit(journal)) { /* * When journal is clean, no need to commit fast commit flag and @@ -1903,6 +1917,9 @@ static int journal_get_superblock(journal_t *journal) bh = journal->j_sb_buffer; J_ASSERT(bh != NULL); + if (buffer_verified(bh)) + return 0; + err = bh_read(bh, 0); if (err < 0) { printk(KERN_ERR @@ -1910,9 +1927,6 @@ static int journal_get_superblock(journal_t *journal) goto out; } - if (buffer_verified(bh)) - return 0; - sb = journal->j_superblock; err = -EINVAL; @@ -1923,21 +1937,13 @@ static int journal_get_superblock(journal_t *journal) goto out; } - switch(be32_to_cpu(sb->s_header.h_blocktype)) { - case JBD2_SUPERBLOCK_V1: - journal->j_format_version = 1; - break; - case JBD2_SUPERBLOCK_V2: - journal->j_format_version = 2; - break; - default: + if (be32_to_cpu(sb->s_header.h_blocktype) != JBD2_SUPERBLOCK_V1 && + be32_to_cpu(sb->s_header.h_blocktype) != JBD2_SUPERBLOCK_V2) { printk(KERN_WARNING "JBD2: unrecognised superblock format ID\n"); goto out; } - if (be32_to_cpu(sb->s_maxlen) < journal->j_total_len) - journal->j_total_len = be32_to_cpu(sb->s_maxlen); - else if (be32_to_cpu(sb->s_maxlen) > journal->j_total_len) { + if (be32_to_cpu(sb->s_maxlen) > journal->j_total_len) { printk(KERN_WARNING "JBD2: journal file too short\n"); goto out; } @@ -1980,25 +1986,14 @@ static int journal_get_superblock(journal_t *journal) journal->j_chksum_driver = NULL; goto out; } - } - - if (jbd2_journal_has_csum_v2or3(journal)) { /* Check superblock checksum */ if (sb->s_checksum != jbd2_superblock_csum(journal, sb)) { printk(KERN_ERR "JBD2: journal checksum error\n"); err = -EFSBADCRC; goto out; } - - /* Precompute checksum seed for all metadata */ - journal->j_csum_seed = jbd2_chksum(journal, ~0, sb->s_uuid, - sizeof(sb->s_uuid)); } - - journal->j_revoke_records_per_block = - journal_revoke_records_per_block(journal); set_buffer_verified(bh); - return 0; out: @@ -2029,6 +2024,15 @@ static int load_superblock(journal_t *journal) journal->j_errno = be32_to_cpu(sb->s_errno); journal->j_last = be32_to_cpu(sb->s_maxlen); + if (be32_to_cpu(sb->s_maxlen) < journal->j_total_len) + journal->j_total_len = be32_to_cpu(sb->s_maxlen); + /* Precompute checksum seed for all metadata */ + if (jbd2_journal_has_csum_v2or3(journal)) + journal->j_csum_seed = jbd2_chksum(journal, ~0, sb->s_uuid, + sizeof(sb->s_uuid)); + journal->j_revoke_records_per_block = + journal_revoke_records_per_block(journal); + if (jbd2_has_feature_fast_commit(journal)) { journal->j_fc_last = be32_to_cpu(sb->s_maxlen); num_fc_blocks = jbd2_journal_get_num_fc_blks(sb); @@ -2060,10 +2064,12 @@ int jbd2_journal_load(journal_t *journal) return err; sb = journal->j_superblock; - /* If this is a V2 superblock, then we have to check the - * features flags on it. */ - if (journal->j_format_version >= 2) { + /* + * If this is a V2 superblock, then we have to check the + * features flags on it. + */ + if (jbd2_format_support_feature(journal)) { if ((sb->s_feature_ro_compat & ~cpu_to_be32(JBD2_KNOWN_ROCOMPAT_FEATURES)) || (sb->s_feature_incompat & @@ -2221,11 +2227,9 @@ int jbd2_journal_check_used_features(journal_t *journal, unsigned long compat, if (!compat && !ro && !incompat) return 1; - /* Load journal superblock if it is not loaded yet. */ - if (journal->j_format_version == 0 && - journal_get_superblock(journal) != 0) + if (journal_get_superblock(journal)) return 0; - if (journal->j_format_version == 1) + if (!jbd2_format_support_feature(journal)) return 0; sb = journal->j_superblock; @@ -2255,11 +2259,7 @@ int jbd2_journal_check_available_features(journal_t *journal, unsigned long comp if (!compat && !ro && !incompat) return 1; - /* We can support any known requested features iff the - * superblock is in version 2. Otherwise we fail to support any - * extended sb features. */ - - if (journal->j_format_version != 2) + if (!jbd2_format_support_feature(journal)) return 0; if ((compat & JBD2_KNOWN_COMPAT_FEATURES) == compat && diff --git a/fs/jbd2/recovery.c b/fs/jbd2/recovery.c index 8286a9ec122f..0184931d47f7 100644 --- a/fs/jbd2/recovery.c +++ b/fs/jbd2/recovery.c @@ -29,6 +29,7 @@ struct recovery_info { tid_t start_transaction; tid_t end_transaction; + unsigned long head_block; int nr_replays; int nr_revokes; @@ -301,11 +302,11 @@ int jbd2_journal_recover(journal_t *journal) * is always zero if, and only if, the journal was cleanly * unmounted. */ - if (!sb->s_start) { - jbd2_debug(1, "No recovery required, last transaction %d\n", - be32_to_cpu(sb->s_sequence)); + jbd2_debug(1, "No recovery required, last transaction %d, head block %u\n", + be32_to_cpu(sb->s_sequence), be32_to_cpu(sb->s_head)); journal->j_transaction_sequence = be32_to_cpu(sb->s_sequence) + 1; + journal->j_head = be32_to_cpu(sb->s_head); return 0; } @@ -324,6 +325,9 @@ int jbd2_journal_recover(journal_t *journal) /* Restart the log at the next transaction ID, thus invalidating * any existing commit records in the log. */ journal->j_transaction_sequence = ++info.end_transaction; + journal->j_head = info.head_block; + jbd2_debug(1, "JBD2: last transaction %d, head block %lu\n", + journal->j_transaction_sequence, journal->j_head); jbd2_journal_clear_revoke(journal); err2 = sync_blockdev(journal->j_fs_dev); @@ -364,6 +368,7 @@ int jbd2_journal_skip_recovery(journal_t *journal) if (err) { printk(KERN_ERR "JBD2: error %d scanning journal\n", err); ++journal->j_transaction_sequence; + journal->j_head = journal->j_first; } else { #ifdef CONFIG_JBD2_DEBUG int dropped = info.end_transaction - @@ -373,6 +378,7 @@ int jbd2_journal_skip_recovery(journal_t *journal) dropped, (dropped == 1) ? "" : "s"); #endif journal->j_transaction_sequence = ++info.end_transaction; + journal->j_head = info.head_block; } journal->j_tail = 0; @@ -462,7 +468,7 @@ static int do_one_pass(journal_t *journal, struct recovery_info *info, enum passtype pass) { unsigned int first_commit_ID, next_commit_ID; - unsigned long next_log_block; + unsigned long next_log_block, head_block; int err, success = 0; journal_superblock_t * sb; journal_header_t * tmp; @@ -485,6 +491,7 @@ static int do_one_pass(journal_t *journal, sb = journal->j_superblock; next_commit_ID = be32_to_cpu(sb->s_sequence); next_log_block = be32_to_cpu(sb->s_start); + head_block = next_log_block; first_commit_ID = next_commit_ID; if (pass == PASS_SCAN) @@ -809,6 +816,7 @@ static int do_one_pass(journal_t *journal, if (commit_time < last_trans_commit_time) goto ignore_crc_mismatch; info->end_transaction = next_commit_ID; + info->head_block = head_block; if (!jbd2_has_feature_async_commit(journal)) { journal->j_failed_commit = @@ -817,8 +825,10 @@ static int do_one_pass(journal_t *journal, break; } } - if (pass == PASS_SCAN) + if (pass == PASS_SCAN) { last_trans_commit_time = commit_time; + head_block = next_log_block; + } brelse(bh); next_commit_ID++; continue; @@ -868,6 +878,8 @@ static int do_one_pass(journal_t *journal, if (pass == PASS_SCAN) { if (!info->end_transaction) info->end_transaction = next_commit_ID; + if (!info->head_block) + info->head_block = head_block; } else { /* It's really bad news if different passes end up at * different places (but possible due to IO errors). */ diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index a3eb1e826947..a14a0f18a4c4 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -178,7 +178,13 @@ int dbMount(struct inode *ipbmap) dbmp_le = (struct dbmap_disk *) mp->data; bmp->db_mapsize = le64_to_cpu(dbmp_le->dn_mapsize); bmp->db_nfree = le64_to_cpu(dbmp_le->dn_nfree); + bmp->db_l2nbperpage = le32_to_cpu(dbmp_le->dn_l2nbperpage); + if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE) { + err = -EINVAL; + goto err_release_metapage; + } + bmp->db_numag = le32_to_cpu(dbmp_le->dn_numag); if (!bmp->db_numag) { err = -EINVAL; @@ -1953,6 +1959,9 @@ dbAllocDmapLev(struct bmap * bmp, if (dbFindLeaf((dmtree_t *) & dp->tree, l2nb, &leafidx)) return -ENOSPC; + if (leafidx < 0) + return -EIO; + /* determine the block number within the file system corresponding * to the leaf at which free space was found. */ @@ -3851,7 +3860,7 @@ static int dbInitTree(struct dmaptree * dtp) l2max = le32_to_cpu(dtp->l2nleafs) + dtp->budmin; /* - * configure the leaf levevl into binary buddy system + * configure the leaf level into binary buddy system * * Try to combine buddies starting with a buddy size of 1 * (i.e. two leaves). At a buddy size of 1 two buddy leaves diff --git a/fs/jfs/jfs_filsys.h b/fs/jfs/jfs_filsys.h index b5d702df7111..33ef13a0b110 100644 --- a/fs/jfs/jfs_filsys.h +++ b/fs/jfs/jfs_filsys.h @@ -122,7 +122,9 @@ #define NUM_INODE_PER_IAG INOSPERIAG #define MINBLOCKSIZE 512 +#define L2MINBLOCKSIZE 9 #define MAXBLOCKSIZE 4096 +#define L2MAXBLOCKSIZE 12 #define MAXFILESIZE ((s64)1 << 52) #define JFS_LINK_MAX 0xffffffff diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c index ffd4feece078..ce4b4760fcb1 100644 --- a/fs/jfs/jfs_txnmgr.c +++ b/fs/jfs/jfs_txnmgr.c @@ -354,6 +354,11 @@ tid_t txBegin(struct super_block *sb, int flag) jfs_info("txBegin: flag = 0x%x", flag); log = JFS_SBI(sb)->log; + if (!log) { + jfs_error(sb, "read-only filesystem\n"); + return 0; + } + TXN_LOCK(); INCREMENT(TxStat.txBegin); diff --git a/fs/jfs/namei.c b/fs/jfs/namei.c index 494b9f4043cf..9b030297aa64 100644 --- a/fs/jfs/namei.c +++ b/fs/jfs/namei.c @@ -799,6 +799,11 @@ static int jfs_link(struct dentry *old_dentry, if (rc) goto out; + if (isReadOnly(ip)) { + jfs_error(ip->i_sb, "read-only filesystem\n"); + return -EROFS; + } + tid = txBegin(ip->i_sb, 0); mutex_lock_nested(&JFS_IP(dir)->commit_mutex, COMMIT_MUTEX_PARENT); diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c index e8e13ae72e3c..c291389a1d71 100644 --- a/fs/nfsd/nfsfh.c +++ b/fs/nfsd/nfsfh.c @@ -414,10 +414,13 @@ static void _fh_update(struct svc_fh *fhp, struct svc_export *exp, struct fid *fid = (struct fid *) (fhp->fh_handle.fh_fsid + fhp->fh_handle.fh_size/4 - 1); int maxsize = (fhp->fh_maxsize - fhp->fh_handle.fh_size)/4; - int subtreecheck = !(exp->ex_flags & NFSEXP_NOSUBTREECHECK); + int fh_flags = (exp->ex_flags & NFSEXP_NOSUBTREECHECK) ? 0 : + EXPORT_FH_CONNECTABLE; + int fileid_type = + exportfs_encode_fh(dentry, fid, &maxsize, fh_flags); fhp->fh_handle.fh_fileid_type = - exportfs_encode_fh(dentry, fid, &maxsize, subtreecheck); + fileid_type > 0 ? fileid_type : FILEID_INVALID; fhp->fh_handle.fh_size += maxsize * 4; } else { fhp->fh_handle.fh_fileid_type = FILEID_ROOT; diff --git a/fs/notify/fanotify/fanotify.c b/fs/notify/fanotify/fanotify.c index 29bdd99b29fa..9dac7f6e72d2 100644 --- a/fs/notify/fanotify/fanotify.c +++ b/fs/notify/fanotify/fanotify.c @@ -380,7 +380,7 @@ static int fanotify_encode_fh_len(struct inode *inode) if (!inode) return 0; - exportfs_encode_inode_fh(inode, NULL, &dwords, NULL); + exportfs_encode_fid(inode, NULL, &dwords); fh_len = dwords << 2; /* @@ -443,9 +443,9 @@ static int fanotify_encode_fh(struct fanotify_fh *fh, struct inode *inode, } dwords = fh_len >> 2; - type = exportfs_encode_inode_fh(inode, buf, &dwords, NULL); + type = exportfs_encode_fid(inode, buf, &dwords); err = -EINVAL; - if (!type || type == FILEID_INVALID || fh_len != dwords << 2) + if (type <= 0 || type == FILEID_INVALID || fh_len != dwords << 2) goto out_err; fh->type = type; diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c index 22fb1cf7e1fc..95d7d8790bc3 100644 --- a/fs/notify/fanotify/fanotify_user.c +++ b/fs/notify/fanotify/fanotify_user.c @@ -1591,11 +1591,10 @@ static int fanotify_test_fid(struct dentry *dentry) * We need to make sure that the file system supports at least * encoding a file handle so user can use name_to_handle_at() to * compare fid returned with event to the file handle of watched - * objects. However, name_to_handle_at() requires that the - * filesystem also supports decoding file handles. + * objects. However, even the relaxed AT_HANDLE_FID flag requires + * at least empty export_operations for ecoding unique file ids. */ - if (!dentry->d_sb->s_export_op || - !dentry->d_sb->s_export_op->fh_to_dentry) + if (!dentry->d_sb->s_export_op) return -EOPNOTSUPP; return 0; diff --git a/fs/notify/fdinfo.c b/fs/notify/fdinfo.c index 55081ae3a6ec..5c430736ec12 100644 --- a/fs/notify/fdinfo.c +++ b/fs/notify/fdinfo.c @@ -50,7 +50,7 @@ static void show_mark_fhandle(struct seq_file *m, struct inode *inode) f.handle.handle_bytes = sizeof(f.pad); size = f.handle.handle_bytes >> 2; - ret = exportfs_encode_inode_fh(inode, (struct fid *)f.handle.f_handle, &size, NULL); + ret = exportfs_encode_fid(inode, (struct fid *)f.handle.f_handle, &size); if ((ret == FILEID_INVALID) || (ret < 0)) { WARN_ONCE(1, "Can't encode file handler for inotify: %d\n", ret); return; diff --git a/fs/open.c b/fs/open.c index f472e68b1f32..a21d09cae3e5 100644 --- a/fs/open.c +++ b/fs/open.c @@ -965,6 +965,11 @@ static int do_dentry_open(struct file *f, } } + /* + * Once we return a file with FMODE_OPENED, __fput() will call + * fsnotify_close(), so we need fsnotify_open() here for symmetry. + */ + fsnotify_open(f); return 0; cleanup_all: @@ -1406,7 +1411,6 @@ static long do_sys_openat2(int dfd, const char __user *filename, put_unused_fd(fd); fd = PTR_ERR(f); } else { - fsnotify_open(f); fd_install(fd, f); } } diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index ffd40dc3e4e9..e3e4f4047657 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -555,7 +555,7 @@ restart: continue; /* Wait for dquot users */ if (atomic_read(&dquot->dq_count)) { - dqgrab(dquot); + atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); /* * Once dqput() wakes us up, we know it's time to free @@ -2420,7 +2420,8 @@ int dquot_load_quota_sb(struct super_block *sb, int type, int format_id, error = add_dquot_ref(sb, type); if (error) - dquot_disable(sb, type, flags); + dquot_disable(sb, type, + DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED); return error; out_fmt: diff --git a/fs/quota/quota.c b/fs/quota/quota.c index 052f143e2e0e..0e41fb84060f 100644 --- a/fs/quota/quota.c +++ b/fs/quota/quota.c @@ -895,8 +895,9 @@ retry: up_write(&sb->s_umount); else up_read(&sb->s_umount); - wait_event(sb->s_writers.wait_unfrozen, - sb->s_writers.frozen == SB_UNFROZEN); + /* Wait for sb to unfreeze */ + sb_start_write(sb); + sb_end_write(sb); put_super(sb); goto retry; } diff --git a/fs/super.c b/fs/super.c index 05ff6abddd3c..e781226e2880 100644 --- a/fs/super.c +++ b/fs/super.c @@ -236,7 +236,6 @@ static struct super_block *alloc_super(struct file_system_type *type, int flags, &type->s_writers_key[i])) goto fail; } - init_waitqueue_head(&s->s_writers.wait_unfrozen); s->s_bdi = &noop_backing_dev_info; s->s_flags = flags; if (s->s_user_ns != &init_user_ns) @@ -1716,7 +1715,6 @@ int freeze_super(struct super_block *sb) if (ret) { sb->s_writers.frozen = SB_UNFROZEN; sb_freeze_unlock(sb, SB_FREEZE_PAGEFAULT); - wake_up(&sb->s_writers.wait_unfrozen); deactivate_locked_super(sb); return ret; } @@ -1732,7 +1730,6 @@ int freeze_super(struct super_block *sb) "VFS:Filesystem freeze failed\n"); sb->s_writers.frozen = SB_UNFROZEN; sb_freeze_unlock(sb, SB_FREEZE_FS); - wake_up(&sb->s_writers.wait_unfrozen); deactivate_locked_super(sb); return ret; } @@ -1778,7 +1775,6 @@ static int thaw_super_locked(struct super_block *sb) sb->s_writers.frozen = SB_UNFROZEN; sb_freeze_unlock(sb, SB_FREEZE_FS); out: - wake_up(&sb->s_writers.wait_unfrozen); deactivate_locked_super(sb); return 0; } diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c index 14b9db4c80f0..ab3ffc355949 100644 --- a/fs/udf/balloc.c +++ b/fs/udf/balloc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * balloc.c * @@ -5,11 +6,6 @@ * Block allocation handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1999-2001 Ben Fennema * (C) 1999 Stelias Computing Inc * diff --git a/fs/udf/dir.c b/fs/udf/dir.c index 212393b12c22..f6533f93851b 100644 --- a/fs/udf/dir.c +++ b/fs/udf/dir.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * dir.c * @@ -5,11 +6,6 @@ * Directory handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-2004 Ben Fennema * * HISTORY diff --git a/fs/udf/directory.c b/fs/udf/directory.c index 654536d2b609..1c775e072b2f 100644 --- a/fs/udf/directory.c +++ b/fs/udf/directory.c @@ -1,14 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * directory.c * * PURPOSE * Directory related functions * - * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. */ #include "udfdecl.h" diff --git a/fs/udf/file.c b/fs/udf/file.c index 29daf5d5cb67..243840dc83ad 100644 --- a/fs/udf/file.c +++ b/fs/udf/file.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * file.c * @@ -5,11 +6,6 @@ * File handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-1999 Dave Boynton * (C) 1998-2004 Ben Fennema * (C) 1999-2000 Stelias Computing Inc diff --git a/fs/udf/ialloc.c b/fs/udf/ialloc.c index 8d50121778a5..5f7ac8c84798 100644 --- a/fs/udf/ialloc.c +++ b/fs/udf/ialloc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * ialloc.c * @@ -5,11 +6,6 @@ * Inode allocation handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-2001 Ben Fennema * * HISTORY diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 1e71e04ae8f6..28cdfc57d946 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * inode.c * @@ -5,11 +6,6 @@ * Inode handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998 Dave Boynton * (C) 1998-2004 Ben Fennema * (C) 1999-2000 Stelias Computing Inc diff --git a/fs/udf/lowlevel.c b/fs/udf/lowlevel.c index c87ed942d076..9d847a7a0905 100644 --- a/fs/udf/lowlevel.c +++ b/fs/udf/lowlevel.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * lowlevel.c * @@ -5,11 +6,6 @@ * Low Level Device Routines for the UDF filesystem * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1999-2001 Ben Fennema * * HISTORY diff --git a/fs/udf/misc.c b/fs/udf/misc.c index 3777468d06ce..0788593b6a1d 100644 --- a/fs/udf/misc.c +++ b/fs/udf/misc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * misc.c * @@ -5,11 +6,6 @@ * Miscellaneous routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998 Dave Boynton * (C) 1998-2004 Ben Fennema * (C) 1999-2000 Stelias Computing Inc diff --git a/fs/udf/namei.c b/fs/udf/namei.c index fd29a66e7241..a95579b043ab 100644 --- a/fs/udf/namei.c +++ b/fs/udf/namei.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * namei.c * @@ -5,11 +6,6 @@ * Inode name handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-2004 Ben Fennema * (C) 1999-2000 Stelias Computing Inc * diff --git a/fs/udf/partition.c b/fs/udf/partition.c index 5bcfe78d5cab..af877991edc1 100644 --- a/fs/udf/partition.c +++ b/fs/udf/partition.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * partition.c * @@ -5,11 +6,6 @@ * Partition handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-2001 Ben Fennema * * HISTORY diff --git a/fs/udf/super.c b/fs/udf/super.c index 6304e3c5c3d9..928a04d9d9e0 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * super.c * @@ -15,11 +16,6 @@ * https://www.iso.org/ * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998 Dave Boynton * (C) 1998-2004 Ben Fennema * (C) 2000 Stelias Computing Inc diff --git a/fs/udf/symlink.c b/fs/udf/symlink.c index a34c8c4e6d21..779b5c2c75f6 100644 --- a/fs/udf/symlink.c +++ b/fs/udf/symlink.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * symlink.c * @@ -5,11 +6,6 @@ * Symlink handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1998-2001 Ben Fennema * (C) 1999 Stelias Computing Inc * diff --git a/fs/udf/truncate.c b/fs/udf/truncate.c index 2e7ba234bab8..a686c10fd709 100644 --- a/fs/udf/truncate.c +++ b/fs/udf/truncate.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * truncate.c * @@ -5,11 +6,6 @@ * Truncate handling routines for the OSTA-UDF(tm) filesystem. * * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. - * * (C) 1999-2004 Ben Fennema * (C) 1999 Stelias Computing Inc * diff --git a/fs/udf/udftime.c b/fs/udf/udftime.c index fce4ad976c8c..758163af39c2 100644 --- a/fs/udf/udftime.c +++ b/fs/udf/udftime.c @@ -1,21 +1,7 @@ +// SPDX-License-Identifier: LGPL-2.0+ /* Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. This file is part of the GNU C Library. - Contributed by Paul Eggert (eggert@twinsun.com). - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Library General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Library General Public License for more details. - - You should have received a copy of the GNU Library General Public - License along with the GNU C Library; see the file COPYING.LIB. If not, - write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ + Contributed by Paul Eggert (eggert@twinsun.com). */ /* * dgb 10/02/98: ripped this from glibc source to help convert timestamps diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c index 622569007b53..32c7f3d27f74 100644 --- a/fs/udf/unicode.c +++ b/fs/udf/unicode.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * unicode.c * @@ -11,11 +12,6 @@ * UTF-8 is explained in the IETF RFC XXXX. * ftp://ftp.internic.net/rfc/rfcxxxx.txt * - * COPYRIGHT - * This file is distributed under the terms of the GNU General Public - * License (GPL). Copies of the GPL can be obtained from: - * ftp://prep.ai.mit.edu/pub/gnu/GPL - * Each contributing author retains all rights to their own work. */ #include "udfdecl.h" @@ -247,7 +243,7 @@ static int udf_name_from_CS0(struct super_block *sb, } if (translate) { - if (str_o_len <= 2 && str_o[0] == '.' && + if (str_o_len > 0 && str_o_len <= 2 && str_o[0] == '.' && (str_o_len == 1 || str_o[1] == '.')) needsCRC = 1; if (needsCRC) { diff --git a/fs/xfs/libxfs/xfs_fs.h b/fs/xfs/libxfs/xfs_fs.h index 1cfd5bc6520a..9c60ebb328b4 100644 --- a/fs/xfs/libxfs/xfs_fs.h +++ b/fs/xfs/libxfs/xfs_fs.h @@ -257,6 +257,8 @@ typedef struct xfs_fsop_resblks { #define XFS_MAX_AG_BLOCKS (XFS_MAX_AG_BYTES / XFS_MIN_BLOCKSIZE) #define XFS_MAX_CRC_AG_BLOCKS (XFS_MAX_AG_BYTES / XFS_MIN_CRC_BLOCKSIZE) +#define XFS_MAX_AGNUMBER ((xfs_agnumber_t)(NULLAGNUMBER - 1)) + /* keep the maximum size under 2^31 by a small amount */ #define XFS_MAX_LOG_BYTES \ ((2 * 1024 * 1024 * 1024ULL) - XFS_MIN_LOG_BYTES) diff --git a/fs/xfs/xfs_aops.c b/fs/xfs/xfs_aops.c index 2ef78aa1d3f6..451942fb38ec 100644 --- a/fs/xfs/xfs_aops.c +++ b/fs/xfs/xfs_aops.c @@ -582,7 +582,6 @@ const struct address_space_operations xfs_address_space_operations = { .release_folio = iomap_release_folio, .invalidate_folio = iomap_invalidate_folio, .bmap = xfs_vm_bmap, - .direct_IO = noop_direct_IO, .migrate_folio = filemap_migrate_folio, .is_partially_uptodate = iomap_is_partially_uptodate, .error_remove_page = generic_error_remove_page, @@ -591,7 +590,6 @@ const struct address_space_operations xfs_address_space_operations = { const struct address_space_operations xfs_dax_aops = { .writepages = xfs_dax_writepages, - .direct_IO = noop_direct_IO, .dirty_folio = noop_dirty_folio, .swap_activate = xfs_iomap_swapfile_activate, }; diff --git a/fs/xfs/xfs_file.c b/fs/xfs/xfs_file.c index 0c6671eb11d6..4f502219ae4f 100644 --- a/fs/xfs/xfs_file.c +++ b/fs/xfs/xfs_file.c @@ -1194,7 +1194,7 @@ xfs_file_open( if (xfs_is_shutdown(XFS_M(inode->i_sb))) return -EIO; file->f_mode |= FMODE_NOWAIT | FMODE_BUF_RASYNC | FMODE_BUF_WASYNC | - FMODE_DIO_PARALLEL_WRITE; + FMODE_DIO_PARALLEL_WRITE | FMODE_CAN_ODIRECT; return generic_file_open(inode, file); } diff --git a/fs/xfs/xfs_fsops.c b/fs/xfs/xfs_fsops.c index 9ebb8333a308..122b83488a05 100644 --- a/fs/xfs/xfs_fsops.c +++ b/fs/xfs/xfs_fsops.c @@ -115,11 +115,16 @@ xfs_growfs_data_private( nb_div = nb; nb_mod = do_div(nb_div, mp->m_sb.sb_agblocks); - nagcount = nb_div + (nb_mod != 0); - if (nb_mod && nb_mod < XFS_MIN_AG_BLOCKS) { - nagcount--; - nb = (xfs_rfsblock_t)nagcount * mp->m_sb.sb_agblocks; + if (nb_mod && nb_mod >= XFS_MIN_AG_BLOCKS) + nb_div++; + else if (nb_mod) + nb = nb_div * mp->m_sb.sb_agblocks; + + if (nb_div > XFS_MAX_AGNUMBER + 1) { + nb_div = XFS_MAX_AGNUMBER + 1; + nb = nb_div * mp->m_sb.sb_agblocks; } + nagcount = nb_div; delta = nb - mp->m_sb.sb_dblocks; /* * Reject filesystems with a single AG because they are not @@ -140,9 +145,13 @@ xfs_growfs_data_private( return -EINVAL; } - error = xfs_trans_alloc(mp, &M_RES(mp)->tr_growdata, - (delta > 0 ? XFS_GROWFS_SPACE_RES(mp) : -delta), 0, - XFS_TRANS_RESERVE, &tp); + if (delta > 0) + error = xfs_trans_alloc(mp, &M_RES(mp)->tr_growdata, + XFS_GROWFS_SPACE_RES(mp), 0, XFS_TRANS_RESERVE, + &tp); + else + error = xfs_trans_alloc(mp, &M_RES(mp)->tr_growdata, -delta, 0, + 0, &tp); if (error) return error; diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c index d910b141d52e..818510243130 100644 --- a/fs/xfs/xfs_super.c +++ b/fs/xfs/xfs_super.c @@ -1707,10 +1707,6 @@ xfs_fs_fill_super( goto out_filestream_unmount; } - if (xfs_has_large_extent_counts(mp)) - xfs_warn(mp, - "EXPERIMENTAL Large extent counts feature in use. Use at your own risk!"); - error = xfs_mountfs(mp); if (error) goto out_filestream_unmount; diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 802495b20276..bcbe9ee2cdaf 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -216,6 +216,9 @@ #define QCOM_ID_SM8350 439 #define QCOM_ID_QCM2290 441 #define QCOM_ID_SM6115 444 +#define QCOM_ID_IPQ5010 446 +#define QCOM_ID_IPQ5018 447 +#define QCOM_ID_IPQ5028 448 #define QCOM_ID_SC8280XP 449 #define QCOM_ID_IPQ6005 453 #define QCOM_ID_QRB5165 455 @@ -229,6 +232,9 @@ #define QCOM_ID_SM8450_3 482 #define QCOM_ID_SC7280 487 #define QCOM_ID_SC7180P 495 +#define QCOM_ID_IPQ5000 503 +#define QCOM_ID_IPQ0509 504 +#define QCOM_ID_IPQ0518 505 #define QCOM_ID_SM6375 507 #define QCOM_ID_IPQ9514 510 #define QCOM_ID_IPQ9550 511 @@ -236,6 +242,7 @@ #define QCOM_ID_IPQ9570 513 #define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 +#define QCOM_ID_IPQ5016 520 #define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 @@ -243,11 +250,15 @@ #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 #define QCOM_ID_QDU1010 587 +#define QCOM_ID_IPQ5019 569 #define QCOM_ID_QRU1032 588 #define QCOM_ID_QRU1052 589 #define QCOM_ID_QRU1062 590 #define QCOM_ID_IPQ5332 592 #define QCOM_ID_IPQ5322 593 +#define QCOM_ID_IPQ5312 594 +#define QCOM_ID_IPQ5302 595 +#define QCOM_ID_IPQ5300 624 /* * The board type and revision information, used by Qualcomm bootloaders and diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h new file mode 100644 index 000000000000..ba2d70f776a6 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + */ + +#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H +#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H + +/* external and internal oscillator clocks */ +#define HXT 0 +#define HXT_GATE 1 +#define LXT 2 +#define LXT_GATE 3 +#define HIRC 4 +#define HIRC_GATE 5 +#define LIRC 6 +#define LIRC_GATE 7 +/* PLLs */ +#define CAPLL 8 +#define SYSPLL 9 +#define DDRPLL 10 +#define APLL 11 +#define EPLL 12 +#define VPLL 13 +/* EPLL divider */ +#define EPLL_DIV2 14 +#define EPLL_DIV4 15 +#define EPLL_DIV8 16 +/* CPU clock, system clock, AXI, HCLK and PCLK */ +#define CA35CLK_MUX 17 +#define AXICLK_DIV2 18 +#define AXICLK_DIV4 19 +#define AXICLK_MUX 20 +#define SYSCLK0_MUX 21 +#define SYSCLK1_MUX 22 +#define SYSCLK1_DIV2 23 +#define HCLK0 24 +#define HCLK1 25 +#define HCLK2 26 +#define PCLK0 27 +#define PCLK1 28 +#define PCLK2 29 +#define HCLK3 30 +#define PCLK3 31 +#define PCLK4 32 +/* AXI and AHB peripheral clocks */ +#define USBPHY0 33 +#define USBPHY1 34 +#define DDR0_GATE 35 +#define DDR6_GATE 36 +#define CAN0_MUX 37 +#define CAN0_DIV 38 +#define CAN0_GATE 39 +#define CAN1_MUX 40 +#define CAN1_DIV 41 +#define CAN1_GATE 42 +#define CAN2_MUX 43 +#define CAN2_DIV 44 +#define CAN2_GATE 45 +#define CAN3_MUX 46 +#define CAN3_DIV 47 +#define CAN3_GATE 48 +#define SDH0_MUX 49 +#define SDH0_GATE 50 +#define SDH1_MUX 51 +#define SDH1_GATE 52 +#define NAND_GATE 53 +#define USBD_GATE 54 +#define USBH_GATE 55 +#define HUSBH0_GATE 56 +#define HUSBH1_GATE 57 +#define GFX_MUX 58 +#define GFX_GATE 59 +#define VC8K_GATE 60 +#define DCU_MUX 61 +#define DCU_GATE 62 +#define DCUP_DIV 63 +#define EMAC0_GATE 64 +#define EMAC1_GATE 65 +#define CCAP0_MUX 66 +#define CCAP0_DIV 67 +#define CCAP0_GATE 68 +#define CCAP1_MUX 69 +#define CCAP1_DIV 70 +#define CCAP1_GATE 71 +#define PDMA0_GATE 72 +#define PDMA1_GATE 73 +#define PDMA2_GATE 74 +#define PDMA3_GATE 75 +#define WH0_GATE 76 +#define WH1_GATE 77 +#define HWS_GATE 78 +#define EBI_GATE 79 +#define SRAM0_GATE 80 +#define SRAM1_GATE 81 +#define ROM_GATE 82 +#define TRA_GATE 83 +#define DBG_MUX 84 +#define DBG_GATE 85 +#define CKO_MUX 86 +#define CKO_DIV 87 +#define CKO_GATE 88 +#define GTMR_GATE 89 +#define GPA_GATE 90 +#define GPB_GATE 91 +#define GPC_GATE 92 +#define GPD_GATE 93 +#define GPE_GATE 94 +#define GPF_GATE 95 +#define GPG_GATE 96 +#define GPH_GATE 97 +#define GPI_GATE 98 +#define GPJ_GATE 99 +#define GPK_GATE 100 +#define GPL_GATE 101 +#define GPM_GATE 102 +#define GPN_GATE 103 +/* APB peripheral clocks */ +#define TMR0_MUX 104 +#define TMR0_GATE 105 +#define TMR1_MUX 106 +#define TMR1_GATE 107 +#define TMR2_MUX 108 +#define TMR2_GATE 109 +#define TMR3_MUX 110 +#define TMR3_GATE 111 +#define TMR4_MUX 112 +#define TMR4_GATE 113 +#define TMR5_MUX 114 +#define TMR5_GATE 115 +#define TMR6_MUX 116 +#define TMR6_GATE 117 +#define TMR7_MUX 118 +#define TMR7_GATE 119 +#define TMR8_MUX 120 +#define TMR8_GATE 121 +#define TMR9_MUX 122 +#define TMR9_GATE 123 +#define TMR10_MUX 124 +#define TMR10_GATE 125 +#define TMR11_MUX 126 +#define TMR11_GATE 127 +#define UART0_MUX 128 +#define UART0_DIV 129 +#define UART0_GATE 130 +#define UART1_MUX 131 +#define UART1_DIV 132 +#define UART1_GATE 133 +#define UART2_MUX 134 +#define UART2_DIV 135 +#define UART2_GATE 136 +#define UART3_MUX 137 +#define UART3_DIV 138 +#define UART3_GATE 139 +#define UART4_MUX 140 +#define UART4_DIV 141 +#define UART4_GATE 142 +#define UART5_MUX 143 +#define UART5_DIV 144 +#define UART5_GATE 145 +#define UART6_MUX 146 +#define UART6_DIV 147 +#define UART6_GATE 148 +#define UART7_MUX 149 +#define UART7_DIV 150 +#define UART7_GATE 151 +#define UART8_MUX 152 +#define UART8_DIV 153 +#define UART8_GATE 154 +#define UART9_MUX 155 +#define UART9_DIV 156 +#define UART9_GATE 157 +#define UART10_MUX 158 +#define UART10_DIV 159 +#define UART10_GATE 160 +#define UART11_MUX 161 +#define UART11_DIV 162 +#define UART11_GATE 163 +#define UART12_MUX 164 +#define UART12_DIV 165 +#define UART12_GATE 166 +#define UART13_MUX 167 +#define UART13_DIV 168 +#define UART13_GATE 169 +#define UART14_MUX 170 +#define UART14_DIV 171 +#define UART14_GATE 172 +#define UART15_MUX 173 +#define UART15_DIV 174 +#define UART15_GATE 175 +#define UART16_MUX 176 +#define UART16_DIV 177 +#define UART16_GATE 178 +#define RTC_GATE 179 +#define DDR_GATE 180 +#define KPI_MUX 181 +#define KPI_DIV 182 +#define KPI_GATE 183 +#define I2C0_GATE 184 +#define I2C1_GATE 185 +#define I2C2_GATE 186 +#define I2C3_GATE 187 +#define I2C4_GATE 188 +#define I2C5_GATE 189 +#define QSPI0_MUX 190 +#define QSPI0_GATE 191 +#define QSPI1_MUX 192 +#define QSPI1_GATE 193 +#define SMC0_MUX 194 +#define SMC0_DIV 195 +#define SMC0_GATE 196 +#define SMC1_MUX 197 +#define SMC1_DIV 198 +#define SMC1_GATE 199 +#define WDT0_MUX 200 +#define WDT0_GATE 201 +#define WDT1_MUX 202 +#define WDT1_GATE 203 +#define WDT2_MUX 204 +#define WDT2_GATE 205 +#define WWDT0_MUX 206 +#define WWDT1_MUX 207 +#define WWDT2_MUX 208 +#define EPWM0_GATE 209 +#define EPWM1_GATE 210 +#define EPWM2_GATE 211 +#define I2S0_MUX 212 +#define I2S0_GATE 213 +#define I2S1_MUX 214 +#define I2S1_GATE 215 +#define SSMCC_GATE 216 +#define SSPCC_GATE 217 +#define SPI0_MUX 218 +#define SPI0_GATE 219 +#define SPI1_MUX 220 +#define SPI1_GATE 221 +#define SPI2_MUX 222 +#define SPI2_GATE 223 +#define SPI3_MUX 224 +#define SPI3_GATE 225 +#define ECAP0_GATE 226 +#define ECAP1_GATE 227 +#define ECAP2_GATE 228 +#define QEI0_GATE 229 +#define QEI1_GATE 230 +#define QEI2_GATE 231 +#define ADC_DIV 232 +#define ADC_GATE 233 +#define EADC_DIV 234 +#define EADC_GATE 235 +#define CLK_MAX_IDX 236 + +#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 5a2961bfe893..b32a7aa65349 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -210,4 +210,8 @@ #define GCC_SNOC_PCIE1_1LANE_S_CLK 201 #define GCC_SNOC_PCIE2_2LANE_S_CLK 202 #define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#define GCC_CRYPTO_CLK_SRC 204 +#define GCC_CRYPTO_CLK 205 +#define GCC_CRYPTO_AXI_CLK 206 +#define GCC_CRYPTO_AHB_CLK 207 #endif diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h new file mode 100644 index 000000000000..d190d57fc81a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,sdx75-gcc.h b/include/dt-bindings/clock/qcom,sdx75-gcc.h new file mode 100644 index 000000000000..a470e8c4fd41 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sdx75-gcc.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL5 3 +#define GPLL6 4 +#define GPLL8 5 +#define GCC_AHB_PCIE_LINK_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_EEE_EMAC0_CLK 8 +#define GCC_EEE_EMAC0_CLK_SRC 9 +#define GCC_EEE_EMAC1_CLK 10 +#define GCC_EEE_EMAC1_CLK_SRC 11 +#define GCC_EMAC0_AXI_CLK 12 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16 +#define GCC_EMAC0_PHY_AUX_CLK 17 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 18 +#define GCC_EMAC0_PTP_CLK 19 +#define GCC_EMAC0_PTP_CLK_SRC 20 +#define GCC_EMAC0_RGMII_CLK 21 +#define GCC_EMAC0_RGMII_CLK_SRC 22 +#define GCC_EMAC0_RPCS_RX_CLK 23 +#define GCC_EMAC0_RPCS_TX_CLK 24 +#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25 +#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26 +#define GCC_EMAC0_SLV_AHB_CLK 27 +#define GCC_EMAC0_XGXS_RX_CLK 28 +#define GCC_EMAC0_XGXS_TX_CLK 29 +#define GCC_EMAC1_AXI_CLK 30 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34 +#define GCC_EMAC1_PHY_AUX_CLK 35 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 36 +#define GCC_EMAC1_PTP_CLK 37 +#define GCC_EMAC1_PTP_CLK_SRC 38 +#define GCC_EMAC1_RGMII_CLK 39 +#define GCC_EMAC1_RGMII_CLK_SRC 40 +#define GCC_EMAC1_RPCS_RX_CLK 41 +#define GCC_EMAC1_RPCS_TX_CLK 42 +#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43 +#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44 +#define GCC_EMAC1_SLV_AHB_CLK 45 +#define GCC_EMAC1_XGXS_RX_CLK 46 +#define GCC_EMAC1_XGXS_TX_CLK 47 +#define GCC_EMAC_0_CLKREF_EN 48 +#define GCC_EMAC_1_CLKREF_EN 49 +#define GCC_GP1_CLK 50 +#define GCC_GP1_CLK_SRC 51 +#define GCC_GP2_CLK 52 +#define GCC_GP2_CLK_SRC 53 +#define GCC_GP3_CLK 54 +#define GCC_GP3_CLK_SRC 55 +#define GCC_PCIE_0_CLKREF_EN 56 +#define GCC_PCIE_1_AUX_CLK 57 +#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58 +#define GCC_PCIE_1_CFG_AHB_CLK 59 +#define GCC_PCIE_1_CLKREF_EN 60 +#define GCC_PCIE_1_MSTR_AXI_CLK 61 +#define GCC_PCIE_1_PHY_RCHNG_CLK 62 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_1_PIPE_CLK 64 +#define GCC_PCIE_1_PIPE_CLK_SRC 65 +#define GCC_PCIE_1_PIPE_DIV2_CLK 66 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67 +#define GCC_PCIE_1_SLV_AXI_CLK 68 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_2_AUX_CLK 70 +#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71 +#define GCC_PCIE_2_CFG_AHB_CLK 72 +#define GCC_PCIE_2_CLKREF_EN 73 +#define GCC_PCIE_2_MSTR_AXI_CLK 74 +#define GCC_PCIE_2_PHY_RCHNG_CLK 75 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76 +#define GCC_PCIE_2_PIPE_CLK 77 +#define GCC_PCIE_2_PIPE_CLK_SRC 78 +#define GCC_PCIE_2_PIPE_DIV2_CLK 79 +#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80 +#define GCC_PCIE_2_SLV_AXI_CLK 81 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82 +#define GCC_PCIE_AUX_CLK 83 +#define GCC_PCIE_AUX_CLK_SRC 84 +#define GCC_PCIE_AUX_PHY_CLK_SRC 85 +#define GCC_PCIE_CFG_AHB_CLK 86 +#define GCC_PCIE_MSTR_AXI_CLK 87 +#define GCC_PCIE_PIPE_CLK 88 +#define GCC_PCIE_PIPE_CLK_SRC 89 +#define GCC_PCIE_RCHNG_PHY_CLK 90 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91 +#define GCC_PCIE_SLEEP_CLK 92 +#define GCC_PCIE_SLV_AXI_CLK 93 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 94 +#define GCC_PDM2_CLK 95 +#define GCC_PDM2_CLK_SRC 96 +#define GCC_PDM_AHB_CLK 97 +#define GCC_PDM_XO4_CLK 98 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99 +#define GCC_QUPV3_WRAP0_CORE_CLK 100 +#define GCC_QUPV3_WRAP0_S0_CLK 101 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102 +#define GCC_QUPV3_WRAP0_S1_CLK 103 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104 +#define GCC_QUPV3_WRAP0_S2_CLK 105 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S3_CLK 107 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S4_CLK 109 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110 +#define GCC_QUPV3_WRAP0_S5_CLK 111 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S6_CLK 113 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S7_CLK 115 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S8_CLK 117 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120 +#define GCC_SDCC1_AHB_CLK 121 +#define GCC_SDCC1_APPS_CLK 122 +#define GCC_SDCC1_APPS_CLK_SRC 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_SDCC2_APPS_CLK_SRC 126 +#define GCC_USB2_CLKREF_EN 127 +#define GCC_USB30_MASTER_CLK 128 +#define GCC_USB30_MASTER_CLK_SRC 129 +#define GCC_USB30_MOCK_UTMI_CLK 130 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132 +#define GCC_USB30_MSTR_AXI_CLK 133 +#define GCC_USB30_SLEEP_CLK 134 +#define GCC_USB30_SLV_AHB_CLK 135 +#define GCC_USB3_PHY_AUX_CLK 136 +#define GCC_USB3_PHY_AUX_CLK_SRC 137 +#define GCC_USB3_PHY_PIPE_CLK 138 +#define GCC_USB3_PHY_PIPE_CLK_SRC 139 +#define GCC_USB3_PRIM_CLKREF_EN 140 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141 +#define GCC_XO_PCIE_LINK_CLK 142 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_EMAC1_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_PCIE_2_GDSC 4 +#define GCC_PCIE_2_PHY_GDSC 5 +#define GCC_PCIE_GDSC 6 +#define GCC_PCIE_PHY_GDSC 7 +#define GCC_USB30_GDSC 8 +#define GCC_USB3_PHY_GDSC 9 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_EMMC_BCR 2 +#define GCC_PCIE_1_BCR 3 +#define GCC_PCIE_1_LINK_DOWN_BCR 4 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_1_PHY_BCR 6 +#define GCC_PCIE_2_BCR 7 +#define GCC_PCIE_2_LINK_DOWN_BCR 8 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_2_PHY_BCR 10 +#define GCC_PCIE_BCR 11 +#define GCC_PCIE_LINK_DOWN_BCR 12 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_QUSB2PHY_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_EMAC0_RGMII_CLK_ARES 24 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-gpucc.h b/include/dt-bindings/clock/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..712b171503d6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H + +/* Clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_SNOC_DVM_CLK 5 +#define GPU_CC_CXO_AON_CLK 6 +#define GPU_CC_CXO_CLK 7 +#define GPU_CC_DEMET_CLK 8 +#define GPU_CC_DEMET_DIV_CLK_SRC 9 +#define GPU_CC_FF_CLK_SRC 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_FF_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_RDVM_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19 +#define GPU_CC_HUB_AON_CLK 20 +#define GPU_CC_HUB_CLK_SRC 21 +#define GPU_CC_HUB_CX_INT_CLK 22 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23 +#define GPU_CC_MEMNOC_GFX_CLK 24 +#define GPU_CC_MND1X_0_GFX3D_CLK 25 +#define GPU_CC_MND1X_1_GFX3D_CLK 26 +#define GPU_CC_PLL0 27 +#define GPU_CC_PLL1 28 +#define GPU_CC_SLEEP_CLK 29 +#define GPU_CC_XO_CLK_SRC 30 +#define GPU_CC_XO_DIV_CLK_SRC 31 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h new file mode 100644 index 000000000000..9d795adfe4eb --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK 0 +#define VIDEO_CC_MVS0_CLK_SRC 1 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS0C_CLK 3 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS1_CLK 5 +#define VIDEO_CC_MVS1_CLK_SRC 6 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS1C_CLK 8 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 +#define VIDEO_CC_PLL0 10 +#define VIDEO_CC_PLL1 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8550-gpucc.h b/include/dt-bindings/clock/qcom,sm8550-gpucc.h new file mode 100644 index 000000000000..a6760547a3ab --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DEMET_DIV_CLK_SRC 7 +#define GPU_CC_FF_CLK_SRC 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_MEMNOC_GFX_CLK 15 +#define GPU_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_CC_PLL0 18 +#define GPU_CC_PLL1 19 +#define GPU_CC_SLEEP_CLK 20 +#define GPU_CC_XO_CLK_SRC 21 +#define GPU_CC_XO_DIV_CLK_SRC 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif diff --git a/include/dt-bindings/gpio/tegra234-gpio.h b/include/dt-bindings/gpio/tegra234-gpio.h index d7a1f2e298e8..784673c2c752 100644 --- a/include/dt-bindings/gpio/tegra234-gpio.h +++ b/include/dt-bindings/gpio/tegra234-gpio.h @@ -33,18 +33,14 @@ #define TEGRA234_MAIN_GPIO_PORT_P 14 #define TEGRA234_MAIN_GPIO_PORT_Q 15 #define TEGRA234_MAIN_GPIO_PORT_R 16 -#define TEGRA234_MAIN_GPIO_PORT_S 17 -#define TEGRA234_MAIN_GPIO_PORT_T 18 -#define TEGRA234_MAIN_GPIO_PORT_U 19 -#define TEGRA234_MAIN_GPIO_PORT_V 20 -#define TEGRA234_MAIN_GPIO_PORT_X 21 -#define TEGRA234_MAIN_GPIO_PORT_Y 22 -#define TEGRA234_MAIN_GPIO_PORT_Z 23 -#define TEGRA234_MAIN_GPIO_PORT_AC 24 -#define TEGRA234_MAIN_GPIO_PORT_AD 25 -#define TEGRA234_MAIN_GPIO_PORT_AE 26 -#define TEGRA234_MAIN_GPIO_PORT_AF 27 -#define TEGRA234_MAIN_GPIO_PORT_AG 28 +#define TEGRA234_MAIN_GPIO_PORT_X 17 +#define TEGRA234_MAIN_GPIO_PORT_Y 18 +#define TEGRA234_MAIN_GPIO_PORT_Z 19 +#define TEGRA234_MAIN_GPIO_PORT_AC 20 +#define TEGRA234_MAIN_GPIO_PORT_AD 21 +#define TEGRA234_MAIN_GPIO_PORT_AE 22 +#define TEGRA234_MAIN_GPIO_PORT_AF 23 +#define TEGRA234_MAIN_GPIO_PORT_AG 24 #define TEGRA234_MAIN_GPIO(port, offset) \ ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 347e55e89a2a..6e60d55491b3 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -536,4 +536,9 @@ #define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 #define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 +/* ICC ID's for dummy MC clients used to represent CPU Clusters */ +#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 +#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 +#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 + #endif diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4d..28ad0235086a 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 867b18e041ea..83be996cb5eb 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -216,20 +216,30 @@ #define SC8280XP_XO 15 /* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 /* MDM9607 Power Domains */ #define MDM9607_VDDCX 0 diff --git a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h new file mode 100644 index 000000000000..2e99ee0d68c5 --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + * Author: Chi-Fen Li + * + * Device Tree binding constants for MA35D1 reset controller. + */ + +#ifndef __DT_BINDINGS_RESET_MA35D1_H +#define __DT_BINDINGS_RESET_MA35D1_H + +#define MA35D1_RESET_CHIP 0 +#define MA35D1_RESET_CA35CR0 1 +#define MA35D1_RESET_CA35CR1 2 +#define MA35D1_RESET_CM4 3 +#define MA35D1_RESET_PDMA0 4 +#define MA35D1_RESET_PDMA1 5 +#define MA35D1_RESET_PDMA2 6 +#define MA35D1_RESET_PDMA3 7 +#define MA35D1_RESET_DISP 8 +#define MA35D1_RESET_VCAP0 9 +#define MA35D1_RESET_VCAP1 10 +#define MA35D1_RESET_GFX 11 +#define MA35D1_RESET_VDEC 12 +#define MA35D1_RESET_WHC0 13 +#define MA35D1_RESET_WHC1 14 +#define MA35D1_RESET_GMAC0 15 +#define MA35D1_RESET_GMAC1 16 +#define MA35D1_RESET_HWSEM 17 +#define MA35D1_RESET_EBI 18 +#define MA35D1_RESET_HSUSBH0 19 +#define MA35D1_RESET_HSUSBH1 20 +#define MA35D1_RESET_HSUSBD 21 +#define MA35D1_RESET_USBHL 22 +#define MA35D1_RESET_SDH0 23 +#define MA35D1_RESET_SDH1 24 +#define MA35D1_RESET_NAND 25 +#define MA35D1_RESET_GPIO 26 +#define MA35D1_RESET_MCTLP 27 +#define MA35D1_RESET_MCTLC 28 +#define MA35D1_RESET_DDRPUB 29 +#define MA35D1_RESET_TMR0 30 +#define MA35D1_RESET_TMR1 31 +#define MA35D1_RESET_TMR2 32 +#define MA35D1_RESET_TMR3 33 +#define MA35D1_RESET_I2C0 34 +#define MA35D1_RESET_I2C1 35 +#define MA35D1_RESET_I2C2 36 +#define MA35D1_RESET_I2C3 37 +#define MA35D1_RESET_QSPI0 38 +#define MA35D1_RESET_SPI0 39 +#define MA35D1_RESET_SPI1 40 +#define MA35D1_RESET_SPI2 41 +#define MA35D1_RESET_UART0 42 +#define MA35D1_RESET_UART1 43 +#define MA35D1_RESET_UART2 44 +#define MA35D1_RESET_UART3 45 +#define MA35D1_RESET_UART4 46 +#define MA35D1_RESET_UART5 47 +#define MA35D1_RESET_UART6 48 +#define MA35D1_RESET_UART7 49 +#define MA35D1_RESET_CANFD0 50 +#define MA35D1_RESET_CANFD1 51 +#define MA35D1_RESET_EADC0 52 +#define MA35D1_RESET_I2S0 53 +#define MA35D1_RESET_SC0 54 +#define MA35D1_RESET_SC1 55 +#define MA35D1_RESET_QSPI1 56 +#define MA35D1_RESET_SPI3 57 +#define MA35D1_RESET_EPWM0 58 +#define MA35D1_RESET_EPWM1 59 +#define MA35D1_RESET_QEI0 60 +#define MA35D1_RESET_QEI1 61 +#define MA35D1_RESET_ECAP0 62 +#define MA35D1_RESET_ECAP1 63 +#define MA35D1_RESET_CANFD2 64 +#define MA35D1_RESET_ADC0 65 +#define MA35D1_RESET_TMR4 66 +#define MA35D1_RESET_TMR5 67 +#define MA35D1_RESET_TMR6 68 +#define MA35D1_RESET_TMR7 69 +#define MA35D1_RESET_TMR8 70 +#define MA35D1_RESET_TMR9 71 +#define MA35D1_RESET_TMR10 72 +#define MA35D1_RESET_TMR11 73 +#define MA35D1_RESET_UART8 74 +#define MA35D1_RESET_UART9 75 +#define MA35D1_RESET_UART10 76 +#define MA35D1_RESET_UART11 77 +#define MA35D1_RESET_UART12 78 +#define MA35D1_RESET_UART13 79 +#define MA35D1_RESET_UART14 80 +#define MA35D1_RESET_UART15 81 +#define MA35D1_RESET_UART16 82 +#define MA35D1_RESET_I2S1 83 +#define MA35D1_RESET_I2C4 84 +#define MA35D1_RESET_I2C5 85 +#define MA35D1_RESET_EPWM2 86 +#define MA35D1_RESET_ECAP2 87 +#define MA35D1_RESET_QEI2 88 +#define MA35D1_RESET_CANFD3 89 +#define MA35D1_RESET_KPI 90 +#define MA35D1_RESET_GIC 91 +#define MA35D1_RESET_SSMCC 92 +#define MA35D1_RESET_SSPCC 93 +#define MA35D1_RESET_COUNT 94 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h index d01dc6a24cf1..c709d103673d 100644 --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -160,5 +160,6 @@ #define GCC_WCSS_Q6_BCR 151 #define GCC_WCSS_Q6_TBU_BCR 152 #define GCC_TCSR_BCR 153 +#define GCC_CRYPTO_BCR 154 #endif diff --git a/include/dt-bindings/reset/qcom,sm8450-gpucc.h b/include/dt-bindings/reset/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..58ba8f987107 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8450-gpucc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 + +#endif diff --git a/include/dt-bindings/thermal/tegra234-bpmp-thermal.h b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h new file mode 100644 index 000000000000..934787950932 --- /dev/null +++ b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding nvidia,tegra234-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H + +#define TEGRA234_BPMP_THERMAL_ZONE_CPU 0 +#define TEGRA234_BPMP_THERMAL_ZONE_GPU 1 +#define TEGRA234_BPMP_THERMAL_ZONE_CV0 2 +#define TEGRA234_BPMP_THERMAL_ZONE_CV1 3 +#define TEGRA234_BPMP_THERMAL_ZONE_CV2 4 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC0 5 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC1 6 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC2 7 +#define TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX 8 + +#endif diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h index d0e44201d855..7f7a576267bc 100644 --- a/include/linux/arm-cci.h +++ b/include/linux/arm-cci.h @@ -43,6 +43,8 @@ static inline int __cci_control_port_by_index(u32 port, bool enable) } #endif +void cci_enable_port_for_self(void); + #define cci_disable_port_by_device(dev) \ __cci_control_port_by_device(dev, false) #define cci_enable_port_by_device(dev) \ diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h index c794ea7096ba..6cb3e9af78c9 100644 --- a/include/linux/buffer_head.h +++ b/include/linux/buffer_head.h @@ -217,6 +217,10 @@ int inode_has_buffers(struct inode *); void invalidate_inode_buffers(struct inode *); int remove_inode_buffers(struct inode *inode); int sync_mapping_buffers(struct address_space *mapping); +int generic_buffers_fsync_noflush(struct file *file, loff_t start, loff_t end, + bool datasync); +int generic_buffers_fsync(struct file *file, loff_t start, loff_t end, + bool datasync); void clean_bdev_aliases(struct block_device *bdev, sector_t block, sector_t len); static inline void clean_bdev_bh_alias(struct buffer_head *bh) diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h index 9edb29101ec8..11fbd0ee1370 100644 --- a/include/linux/exportfs.h +++ b/include/linux/exportfs.h @@ -135,6 +135,9 @@ struct fid { }; }; +#define EXPORT_FH_CONNECTABLE 0x1 /* Encode file handle with parent */ +#define EXPORT_FH_FID 0x2 /* File handle may be non-decodeable */ + /** * struct export_operations - for nfsd to communicate with file systems * @encode_fh: encode a file handle fragment from a dentry @@ -150,7 +153,7 @@ struct fid { * encode_fh: * @encode_fh should store in the file handle fragment @fh (using at most * @max_len bytes) information that can be used by @decode_fh to recover the - * file referred to by the &struct dentry @de. If the @connectable flag is + * file referred to by the &struct dentry @de. If @flag has CONNECTABLE bit * set, the encode_fh() should store sufficient information so that a good * attempt can be made to find not only the file but also it's place in the * filesystem. This typically means storing a reference to de->d_parent in @@ -225,9 +228,18 @@ struct export_operations { }; extern int exportfs_encode_inode_fh(struct inode *inode, struct fid *fid, - int *max_len, struct inode *parent); + int *max_len, struct inode *parent, + int flags); extern int exportfs_encode_fh(struct dentry *dentry, struct fid *fid, - int *max_len, int connectable); + int *max_len, int flags); + +static inline int exportfs_encode_fid(struct inode *inode, struct fid *fid, + int *max_len) +{ + return exportfs_encode_inode_fh(inode, fid, max_len, NULL, + EXPORT_FH_FID); +} + extern struct dentry *exportfs_decode_fh_raw(struct vfsmount *mnt, struct fid *fid, int fh_len, int fileid_type, diff --git a/include/linux/fs.h b/include/linux/fs.h index 776e367ac1bb..cd481cfa4e45 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1148,7 +1148,6 @@ enum { struct sb_writers { int frozen; /* Is sb frozen? */ - wait_queue_head_t wait_unfrozen; /* wait for thaw */ struct percpu_rw_semaphore rw_sem[SB_FREEZE_LEVELS]; }; diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index a86115bc799c..a1b3de87a3d1 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -48,7 +48,7 @@ struct fsl_mc_driver { struct device_driver driver; const struct fsl_mc_device_id *match_id_table; int (*probe)(struct fsl_mc_device *dev); - int (*remove)(struct fsl_mc_device *dev); + void (*remove)(struct fsl_mc_device *dev); void (*shutdown)(struct fsl_mc_device *dev); int (*suspend)(struct fsl_mc_device *dev, pm_message_t state); int (*resume)(struct fsl_mc_device *dev); diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h index f619bae1dcc5..d860499e15e4 100644 --- a/include/linux/jbd2.h +++ b/include/linux/jbd2.h @@ -265,8 +265,10 @@ typedef struct journal_superblock_s __u8 s_padding2[3]; /* 0x0054 */ __be32 s_num_fc_blks; /* Number of fast commit blocks */ -/* 0x0058 */ - __u32 s_padding[41]; + __be32 s_head; /* blocknr of head of log, only uptodate + * while the filesystem is clean */ +/* 0x005C */ + __u32 s_padding[40]; __be32 s_checksum; /* crc32c(superblock) */ /* 0x0100 */ @@ -274,17 +276,6 @@ typedef struct journal_superblock_s /* 0x0400 */ } journal_superblock_t; -/* Use the jbd2_{has,set,clear}_feature_* helpers; these will be removed */ -#define JBD2_HAS_COMPAT_FEATURE(j,mask) \ - ((j)->j_format_version >= 2 && \ - ((j)->j_superblock->s_feature_compat & cpu_to_be32((mask)))) -#define JBD2_HAS_RO_COMPAT_FEATURE(j,mask) \ - ((j)->j_format_version >= 2 && \ - ((j)->j_superblock->s_feature_ro_compat & cpu_to_be32((mask)))) -#define JBD2_HAS_INCOMPAT_FEATURE(j,mask) \ - ((j)->j_format_version >= 2 && \ - ((j)->j_superblock->s_feature_incompat & cpu_to_be32((mask)))) - #define JBD2_FEATURE_COMPAT_CHECKSUM 0x00000001 #define JBD2_FEATURE_INCOMPAT_REVOKE 0x00000001 @@ -803,11 +794,6 @@ struct journal_s */ journal_superblock_t *j_superblock; - /** - * @j_format_version: Version of the superblock format. - */ - int j_format_version; - /** * @j_state_lock: Protect the various scalars in the journal. */ @@ -1324,11 +1310,22 @@ struct journal_s rwsem_release(&j->j_trans_commit_map, _THIS_IP_); \ } while (0) +/* + * We can support any known requested features iff the + * superblock is not in version 1. Otherwise we fail to support any + * extended sb features. + */ +static inline bool jbd2_format_support_feature(journal_t *j) +{ + return j->j_superblock->s_header.h_blocktype != + cpu_to_be32(JBD2_SUPERBLOCK_V1); +} + /* journal feature predicate functions */ #define JBD2_FEATURE_COMPAT_FUNCS(name, flagname) \ static inline bool jbd2_has_feature_##name(journal_t *j) \ { \ - return ((j)->j_format_version >= 2 && \ + return (jbd2_format_support_feature(j) && \ ((j)->j_superblock->s_feature_compat & \ cpu_to_be32(JBD2_FEATURE_COMPAT_##flagname)) != 0); \ } \ @@ -1346,7 +1343,7 @@ static inline void jbd2_clear_feature_##name(journal_t *j) \ #define JBD2_FEATURE_RO_COMPAT_FUNCS(name, flagname) \ static inline bool jbd2_has_feature_##name(journal_t *j) \ { \ - return ((j)->j_format_version >= 2 && \ + return (jbd2_format_support_feature(j) && \ ((j)->j_superblock->s_feature_ro_compat & \ cpu_to_be32(JBD2_FEATURE_RO_COMPAT_##flagname)) != 0); \ } \ @@ -1364,7 +1361,7 @@ static inline void jbd2_clear_feature_##name(journal_t *j) \ #define JBD2_FEATURE_INCOMPAT_FUNCS(name, flagname) \ static inline bool jbd2_has_feature_##name(journal_t *j) \ { \ - return ((j)->j_format_version >= 2 && \ + return (jbd2_format_support_feature(j) && \ ((j)->j_superblock->s_feature_incompat & \ cpu_to_be32(JBD2_FEATURE_INCOMPAT_##flagname)) != 0); \ } \ @@ -1400,6 +1397,9 @@ JBD2_FEATURE_INCOMPAT_FUNCS(fast_commit, FAST_COMMIT) #define JBD2_ABORT_ON_SYNCDATA_ERR 0x040 /* Abort the journal on file * data write error in ordered * mode */ +#define JBD2_CYCLE_RECORD 0x080 /* Journal cycled record log on + * clean and empty filesystem + * logging area */ #define JBD2_FAST_COMMIT_ONGOING 0x100 /* Fast commit is ongoing */ #define JBD2_FULL_COMMIT_ONGOING 0x200 /* Full commit is ongoing */ #define JBD2_JOURNAL_FLUSH_DISCARD 0x0001 diff --git a/include/linux/platform_data/asoc-pxa.h b/include/linux/platform_data/asoc-pxa.h index 327454cd8246..7b5b9e20fbf5 100644 --- a/include/linux/platform_data/asoc-pxa.h +++ b/include/linux/platform_data/asoc-pxa.h @@ -27,5 +27,6 @@ typedef struct { } pxa2xx_audio_ops_t; extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); +extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio); #endif diff --git a/include/linux/platform_data/davinci-cpufreq.h b/include/linux/platform_data/davinci-cpufreq.h index bc208c64e3d7..1ef91c36f609 100644 --- a/include/linux/platform_data/davinci-cpufreq.h +++ b/include/linux/platform_data/davinci-cpufreq.h @@ -16,4 +16,10 @@ struct davinci_cpufreq_config { int (*init)(void); }; +#ifdef CONFIG_CPU_FREQ +int davinci_cpufreq_init(void); +#else +static inline int davinci_cpufreq_init(void) { return 0; } +#endif + #endif /* _MACH_DAVINCI_CPUFREQ_H */ diff --git a/include/linux/platform_data/pxa2xx_udc.h b/include/linux/platform_data/pxa2xx_udc.h index ff9c35dca59d..bc99cc6a3c5f 100644 --- a/include/linux/platform_data/pxa2xx_udc.h +++ b/include/linux/platform_data/pxa2xx_udc.h @@ -25,4 +25,10 @@ struct pxa2xx_udc_mach_info { int gpio_pullup; /* high == pullup activated */ }; +#ifdef CONFIG_PXA27x +extern void pxa27x_clear_otgph(void); +#else +#define pxa27x_clear_otgph() do {} while (0) +#endif + #endif diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index ecfded30ed05..c9a31c567e85 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -9,7 +9,55 @@ #ifndef _PRUSS_DRIVER_H_ #define _PRUSS_DRIVER_H_ +#include +#include #include +#include + +/* + * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the + * PRUSS_GPCFG0/1 registers + * + * NOTE: The below defines are the most common values, but there + * are some exceptions like on 66AK2G, where the RESERVED and MII2 + * values are interchanged. Also, this bit-field does not exist on + * AM335x SoCs + */ +enum pruss_gp_mux_sel { + PRUSS_GP_MUX_SEL_GP, + PRUSS_GP_MUX_SEL_ENDAT, + PRUSS_GP_MUX_SEL_RESERVED, + PRUSS_GP_MUX_SEL_SD, + PRUSS_GP_MUX_SEL_MII2, + PRUSS_GP_MUX_SEL_MAX, +}; + +/* + * enum pruss_gpi_mode - PRUSS GPI configuration modes, used + * to program the PRUSS_GPCFG0/1 registers + */ +enum pruss_gpi_mode { + PRUSS_GPI_MODE_DIRECT, + PRUSS_GPI_MODE_PARALLEL, + PRUSS_GPI_MODE_28BIT_SHIFT, + PRUSS_GPI_MODE_MII, + PRUSS_GPI_MODE_MAX, +}; + +/** + * enum pru_type - PRU core type identifier + * + * @PRU_TYPE_PRU: Programmable Real-time Unit + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit + * @PRU_TYPE_MAX: just keep this one at the end + */ +enum pru_type { + PRU_TYPE_PRU, + PRU_TYPE_RTU, + PRU_TYPE_TX_PRU, + PRU_TYPE_MAX, +}; /* * enum pruss_mem - PRUSS memory range identifiers @@ -39,6 +87,8 @@ struct pruss_mem_region { * @cfg_base: base iomap for CFG region * @cfg_regmap: regmap for config region * @mem_regions: data for each of the PRUSS memory regions + * @mem_in_use: to indicate if memory resource is in use + * @lock: mutex to serialize access to resources * @core_clk_mux: clk handle for PRUSS CORE_CLK_MUX * @iep_clk_mux: clk handle for PRUSS IEP_CLK_MUX */ @@ -47,8 +97,81 @@ struct pruss { void __iomem *cfg_base; struct regmap *cfg_regmap; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; + struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX]; + struct mutex lock; /* PRU resource lock */ struct clk *core_clk_mux; struct clk *iep_clk_mux; }; +#if IS_ENABLED(CONFIG_TI_PRUSS) + +struct pruss *pruss_get(struct rproc *rproc); +void pruss_put(struct pruss *pruss); +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region); +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region); +int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux); +int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux); +int pruss_cfg_gpimode(struct pruss *pruss, enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode); +int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable); +int pruss_cfg_xfr_enable(struct pruss *pruss, enum pru_type pru_type, + bool enable); + +#else + +static inline struct pruss *pruss_get(struct rproc *rproc) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void pruss_put(struct pruss *pruss) { } + +static inline int pruss_request_mem_region(struct pruss *pruss, + enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + return -EOPNOTSUPP; +} + +static inline int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + return -EOPNOTSUPP; +} + +static inline int pruss_cfg_get_gpmux(struct pruss *pruss, + enum pruss_pru_id pru_id, u8 *mux) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_set_gpmux(struct pruss *pruss, + enum pruss_pru_id pru_id, u8 mux) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_gpimode(struct pruss *pruss, + enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_xfr_enable(struct pruss *pruss, + enum pru_type pru_type, + bool enable); +{ + return ERR_PTR(-EOPNOTSUPP); +} + +#endif /* CONFIG_TI_PRUSS */ + #endif /* _PRUSS_DRIVER_H_ */ diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 0ce5746a4470..e6fe4f73ffe6 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -629,11 +629,25 @@ struct scmi_powercap_info { * @num_domains_get: get the count of powercap domains provided by SCMI. * @info_get: get the information for the specified domain. * @cap_get: get the current CAP value for the specified domain. + * On SCMI platforms supporting powercap zone disabling, this could + * report a zero value for a zone where powercapping is disabled. * @cap_set: set the CAP value for the specified domain to the provided value; * if the domain supports setting the CAP with an asynchronous command * this request will finally trigger an asynchronous transfer, but, if * @ignore_dresp here is set to true, this call will anyway return * immediately without waiting for the related delayed response. + * Note that the powercap requested value must NOT be zero, even if + * the platform supports disabling a powercap by setting its cap to + * zero (since SCMI v3.2): there are dedicated operations that should + * be used for that. (@cap_enable_set/get) + * @cap_enable_set: enable or disable the powercapping on the specified domain, + * if supported by the SCMI platform implementation. + * Note that, by the SCMI specification, the platform can + * silently ignore our disable request and decide to enforce + * anyway some other powercap value requested by another agent + * on the system: for this reason @cap_get and @cap_enable_get + * will always report the final platform view of the powercaps. + * @cap_enable_get: get the current CAP enable status for the specified domain. * @pai_get: get the current PAI value for the specified domain. * @pai_set: set the PAI value for the specified domain to the provided value. * @measurements_get: retrieve the current average power measurements for the @@ -662,6 +676,10 @@ struct scmi_powercap_proto_ops { u32 *power_cap); int (*cap_set)(const struct scmi_protocol_handle *ph, u32 domain_id, u32 power_cap, bool ignore_dresp); + int (*cap_enable_set)(const struct scmi_protocol_handle *ph, + u32 domain_id, bool enable); + int (*cap_enable_get)(const struct scmi_protocol_handle *ph, + u32 domain_id, bool *enable); int (*pai_get)(const struct scmi_protocol_handle *ph, u32 domain_id, u32 *pai); int (*pai_set)(const struct scmi_protocol_handle *ph, u32 domain_id, diff --git a/include/linux/slab.h b/include/linux/slab.h index ca7329a962d5..faf88c99498d 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -54,16 +54,18 @@ * stays valid, the trick to using this is relying on an independent * object validation pass. Something like: * - * rcu_read_lock() - * again: + * begin: + * rcu_read_lock(); * obj = lockless_lookup(key); * if (obj) { * if (!try_get_ref(obj)) // might fail for free objects - * goto again; + * rcu_read_unlock(); + * goto begin; * * if (obj->key != key) { // not the object we expected * put_ref(obj); - * goto again; + * rcu_read_unlock(); + * goto begin; * } * } * rcu_read_unlock(); @@ -107,6 +109,18 @@ /* Avoid kmemleak tracing */ #define SLAB_NOLEAKTRACE ((slab_flags_t __force)0x00800000U) +/* + * Prevent merging with compatible kmem caches. This flag should be used + * cautiously. Valid use cases: + * + * - caches created for self-tests (e.g. kunit) + * - general caches created and used by a subsystem, only when a + * (subsystem-specific) debug option is enabled + * - performance critical caches, should be very rare and consulted with slab + * maintainers, and not used together with CONFIG_SLUB_TINY + */ +#define SLAB_NO_MERGE ((slab_flags_t __force)0x01000000U) + /* Fault injection mark */ #ifdef CONFIG_FAILSLAB # define SLAB_FAILSLAB ((slab_flags_t __force)0x02000000U) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 37544ea6286d..2475ef914746 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -27,8 +27,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_CCORR, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DP_INTF1, diff --git a/include/linux/soc/pxa/smemc.h b/include/linux/soc/pxa/smemc.h index f1ffea236c15..4feb1dded3ec 100644 --- a/include/linux/soc/pxa/smemc.h +++ b/include/linux/soc/pxa/smemc.h @@ -10,4 +10,20 @@ int pxa2xx_smemc_get_sdram_rows(void); unsigned int pxa3xx_smemc_get_memclkdiv(void); void __iomem *pxa_smemc_get_mdrefr(void); +/* + * Once fully converted to the clock framework, all these functions should be + * removed, and replaced with a clk_get(NULL, "core"). + */ +#ifdef CONFIG_PXA25x +extern unsigned pxa25x_get_clk_frequency_khz(int); +#else +#define pxa25x_get_clk_frequency_khz(x) (0) +#endif + +#ifdef CONFIG_PXA27x +extern unsigned pxa27x_get_clk_frequency_khz(int); +#else +#define pxa27x_get_clk_frequency_khz(x) (0) +#endif + #endif diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index 86e1b358688a..223db6a9c733 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -11,4 +11,6 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); +int qcom_smem_get_soc_id(u32 *id); + #endif diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h new file mode 100644 index 000000000000..e78777bb0f4a --- /dev/null +++ b/include/linux/soc/qcom/socinfo.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __QCOM_SOCINFO_H__ +#define __QCOM_SOCINFO_H__ + +/* + * SMEM item id, used to acquire handles to respective + * SMEM region. + */ +#define SMEM_HW_SW_BUILD_ID 137 + +#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 +#define SMEM_SOCINFO_CHIP_ID_LENGTH 32 + +/* Socinfo SMEM item structure */ +struct socinfo { + __le32 fmt; + __le32 id; + __le32 ver; + char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; + /* Version 2 */ + __le32 raw_id; + __le32 raw_ver; + /* Version 3 */ + __le32 hw_plat; + /* Version 4 */ + __le32 plat_ver; + /* Version 5 */ + __le32 accessory_chip; + /* Version 6 */ + __le32 hw_plat_subtype; + /* Version 7 */ + __le32 pmic_model; + __le32 pmic_die_rev; + /* Version 8 */ + __le32 pmic_model_1; + __le32 pmic_die_rev_1; + __le32 pmic_model_2; + __le32 pmic_die_rev_2; + /* Version 9 */ + __le32 foundry_id; + /* Version 10 */ + __le32 serial_num; + /* Version 11 */ + __le32 num_pmics; + __le32 pmic_array_offset; + /* Version 12 */ + __le32 chip_family; + __le32 raw_device_family; + __le32 raw_device_num; + /* Version 13 */ + __le32 nproduct_id; + char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; + /* Version 14 */ + __le32 num_clusters; + __le32 ncluster_array_offset; + __le32 num_subset_parts; + __le32 nsubset_parts_array_offset; + /* Version 15 */ + __le32 nmodem_supported; + /* Version 16 */ + __le32 feature_code; + __le32 pcode; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; + /* Version 17 */ + __le32 oem_variant; + /* Version 18 */ + __le32 num_kvps; + __le32 kvps_offset; + /* Version 19 */ + __le32 num_func_clusters; + __le32 boot_cluster; + __le32 boot_core; +}; + +#endif diff --git a/include/linux/tegra-icc.h b/include/linux/tegra-icc.h new file mode 100644 index 000000000000..4b4d4bee290c --- /dev/null +++ b/include/linux/tegra-icc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022-2023 NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef LINUX_TEGRA_ICC_H +#define LINUX_TEGRA_ICC_H + +enum tegra_icc_client_type { + TEGRA_ICC_NONE, + TEGRA_ICC_NISO, + TEGRA_ICC_ISO_DISPLAY, + TEGRA_ICC_ISO_VI, + TEGRA_ICC_ISO_AUDIO, + TEGRA_ICC_ISO_VIFAL, +}; + +/* ICC ID's for MC client's used in BPMP */ +#define TEGRA_ICC_BPMP_DEBUG 1 +#define TEGRA_ICC_BPMP_CPU_CLUSTER0 2 +#define TEGRA_ICC_BPMP_CPU_CLUSTER1 3 +#define TEGRA_ICC_BPMP_CPU_CLUSTER2 4 +#define TEGRA_ICC_BPMP_GPU 5 +#define TEGRA_ICC_BPMP_CACTMON 6 +#define TEGRA_ICC_BPMP_DISPLAY 7 +#define TEGRA_ICC_BPMP_VI 8 +#define TEGRA_ICC_BPMP_EQOS 9 +#define TEGRA_ICC_BPMP_PCIE_0 10 +#define TEGRA_ICC_BPMP_PCIE_1 11 +#define TEGRA_ICC_BPMP_PCIE_2 12 +#define TEGRA_ICC_BPMP_PCIE_3 13 +#define TEGRA_ICC_BPMP_PCIE_4 14 +#define TEGRA_ICC_BPMP_PCIE_5 15 +#define TEGRA_ICC_BPMP_PCIE_6 16 +#define TEGRA_ICC_BPMP_PCIE_7 17 +#define TEGRA_ICC_BPMP_PCIE_8 18 +#define TEGRA_ICC_BPMP_PCIE_9 19 +#define TEGRA_ICC_BPMP_PCIE_10 20 +#define TEGRA_ICC_BPMP_DLA_0 21 +#define TEGRA_ICC_BPMP_DLA_1 22 +#define TEGRA_ICC_BPMP_SDMMC_1 23 +#define TEGRA_ICC_BPMP_SDMMC_2 24 +#define TEGRA_ICC_BPMP_SDMMC_3 25 +#define TEGRA_ICC_BPMP_SDMMC_4 26 +#define TEGRA_ICC_BPMP_NVDEC 27 +#define TEGRA_ICC_BPMP_NVENC 28 +#define TEGRA_ICC_BPMP_NVJPG_0 29 +#define TEGRA_ICC_BPMP_NVJPG_1 30 +#define TEGRA_ICC_BPMP_OFAA 31 +#define TEGRA_ICC_BPMP_XUSB_HOST 32 +#define TEGRA_ICC_BPMP_XUSB_DEV 33 +#define TEGRA_ICC_BPMP_TSEC 34 +#define TEGRA_ICC_BPMP_VIC 35 +#define TEGRA_ICC_BPMP_APE 36 +#define TEGRA_ICC_BPMP_APEDMA 37 +#define TEGRA_ICC_BPMP_SE 38 +#define TEGRA_ICC_BPMP_ISP 39 +#define TEGRA_ICC_BPMP_HDA 40 +#define TEGRA_ICC_BPMP_VIFAL 41 +#define TEGRA_ICC_BPMP_VI2FAL 42 +#define TEGRA_ICC_BPMP_VI2 43 +#define TEGRA_ICC_BPMP_RCE 44 +#define TEGRA_ICC_BPMP_PVA 45 + +#endif /* LINUX_TEGRA_ICC_H */ diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index a63de5da8124..3a513be50243 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved. */ #ifndef __SOC_TEGRA_FUSE_H__ @@ -17,6 +17,7 @@ #define TEGRA186 0x18 #define TEGRA194 0x19 #define TEGRA234 0x23 +#define TEGRA264 0x26 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 #define TEGRA30_FUSE_SATA_CALIB 0x124 diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 51a2263e1bc5..fc3001483e62 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -13,6 +13,7 @@ #include #include #include +#include struct clk; struct device; @@ -26,6 +27,8 @@ struct tegra_mc_timing { struct tegra_mc_client { unsigned int id; + unsigned int bpmp_id; + enum tegra_icc_client_type type; const char *name; /* * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the @@ -166,8 +169,10 @@ struct tegra_mc_icc_ops { int (*set)(struct icc_node *src, struct icc_node *dst); int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data); struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, void *data); + int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak); }; struct tegra_mc_ops { @@ -214,6 +219,7 @@ struct tegra_mc_soc { }; struct tegra_mc { + struct tegra_bpmp *bpmp; struct device *dev; struct tegra_smmu *smmu; struct gart_device *gart; @@ -228,7 +234,9 @@ struct tegra_mc { struct tegra_mc_timing *timings; unsigned int num_timings; + unsigned int num_channels; + bool bwmgr_mrq_supported; struct reset_controller_dev reset; struct icc_provider provider; diff --git a/include/trace/events/ext4.h b/include/trace/events/ext4.h index ebccf6a6aa1b..65029dfb92fb 100644 --- a/include/trace/events/ext4.h +++ b/include/trace/events/ext4.h @@ -120,6 +120,20 @@ TRACE_DEFINE_ENUM(EXT4_FC_REASON_MAX); { EXT4_FC_REASON_INODE_JOURNAL_DATA, "INODE_JOURNAL_DATA"}, \ { EXT4_FC_REASON_ENCRYPTED_FILENAME, "ENCRYPTED_FILENAME"}) +TRACE_DEFINE_ENUM(CR_POWER2_ALIGNED); +TRACE_DEFINE_ENUM(CR_GOAL_LEN_FAST); +TRACE_DEFINE_ENUM(CR_BEST_AVAIL_LEN); +TRACE_DEFINE_ENUM(CR_GOAL_LEN_SLOW); +TRACE_DEFINE_ENUM(CR_ANY_FREE); + +#define show_criteria(cr) \ + __print_symbolic(cr, \ + { CR_POWER2_ALIGNED, "CR_POWER2_ALIGNED" }, \ + { CR_GOAL_LEN_FAST, "CR_GOAL_LEN_FAST" }, \ + { CR_BEST_AVAIL_LEN, "CR_BEST_AVAIL_LEN" }, \ + { CR_GOAL_LEN_SLOW, "CR_GOAL_LEN_SLOW" }, \ + { CR_ANY_FREE, "CR_ANY_FREE" }) + TRACE_EVENT(ext4_other_inode_update_time, TP_PROTO(struct inode *inode, ino_t orig_ino), @@ -560,10 +574,10 @@ TRACE_EVENT(ext4_writepages_result, (unsigned long) __entry->writeback_index) ); -DECLARE_EVENT_CLASS(ext4__page_op, - TP_PROTO(struct page *page), +DECLARE_EVENT_CLASS(ext4__folio_op, + TP_PROTO(struct inode *inode, struct folio *folio), - TP_ARGS(page), + TP_ARGS(inode, folio), TP_STRUCT__entry( __field( dev_t, dev ) @@ -573,29 +587,29 @@ DECLARE_EVENT_CLASS(ext4__page_op, ), TP_fast_assign( - __entry->dev = page->mapping->host->i_sb->s_dev; - __entry->ino = page->mapping->host->i_ino; - __entry->index = page->index; + __entry->dev = inode->i_sb->s_dev; + __entry->ino = inode->i_ino; + __entry->index = folio->index; ), - TP_printk("dev %d,%d ino %lu page_index %lu", + TP_printk("dev %d,%d ino %lu folio_index %lu", MAJOR(__entry->dev), MINOR(__entry->dev), (unsigned long) __entry->ino, (unsigned long) __entry->index) ); -DEFINE_EVENT(ext4__page_op, ext4_readpage, +DEFINE_EVENT(ext4__folio_op, ext4_read_folio, - TP_PROTO(struct page *page), + TP_PROTO(struct inode *inode, struct folio *folio), - TP_ARGS(page) + TP_ARGS(inode, folio) ); -DEFINE_EVENT(ext4__page_op, ext4_releasepage, +DEFINE_EVENT(ext4__folio_op, ext4_release_folio, - TP_PROTO(struct page *page), + TP_PROTO(struct inode *inode, struct folio *folio), - TP_ARGS(page) + TP_ARGS(inode, folio) ); DECLARE_EVENT_CLASS(ext4_invalidate_folio_op, @@ -1063,7 +1077,7 @@ TRACE_EVENT(ext4_mballoc_alloc, ), TP_printk("dev %d,%d inode %lu orig %u/%d/%u@%u goal %u/%d/%u@%u " - "result %u/%d/%u@%u blks %u grps %u cr %u flags %s " + "result %u/%d/%u@%u blks %u grps %u cr %s flags %s " "tail %u broken %u", MAJOR(__entry->dev), MINOR(__entry->dev), (unsigned long) __entry->ino, @@ -1073,7 +1087,7 @@ TRACE_EVENT(ext4_mballoc_alloc, __entry->goal_len, __entry->goal_logical, __entry->result_group, __entry->result_start, __entry->result_len, __entry->result_logical, - __entry->found, __entry->groups, __entry->cr, + __entry->found, __entry->groups, show_criteria(__entry->cr), show_mballoc_flags(__entry->flags), __entry->tail, __entry->buddy ? 1 << __entry->buddy : 0) ); diff --git a/include/uapi/linux/fcntl.h b/include/uapi/linux/fcntl.h index e8c07da58c9f..6c80f96049bd 100644 --- a/include/uapi/linux/fcntl.h +++ b/include/uapi/linux/fcntl.h @@ -112,4 +112,9 @@ #define AT_RECURSIVE 0x8000 /* Apply to the entire subtree */ +/* Flags for name_to_handle_at(2). We reuse AT_ flag space to save bits... */ +#define AT_HANDLE_FID AT_REMOVEDIR /* file handle is needed to + compare object identity and may not + be usable to open_by_handle_at(2) */ + #endif /* _UAPI_LINUX_FCNTL_H */ diff --git a/io_uring/openclose.c b/io_uring/openclose.c index a1b98c81a52d..10ca57f5bd24 100644 --- a/io_uring/openclose.c +++ b/io_uring/openclose.c @@ -150,7 +150,6 @@ int io_openat2(struct io_kiocb *req, unsigned int issue_flags) if ((issue_flags & IO_URING_F_NONBLOCK) && !nonblock_set) file->f_flags &= ~O_NONBLOCK; - fsnotify_open(file); if (!fixed) fd_install(ret, file); diff --git a/kernel/configs/tiny.config b/kernel/configs/tiny.config index 144b2bd86b14..00009f7d0835 100644 --- a/kernel/configs/tiny.config +++ b/kernel/configs/tiny.config @@ -6,6 +6,5 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KERNEL_XZ=y # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set -# CONFIG_SLAB is not set CONFIG_SLUB=y CONFIG_SLUB_TINY=y diff --git a/kernel/trace/trace_events_user.c b/kernel/trace/trace_events_user.c index 0536db7fef61..4f5e74bbdab2 100644 --- a/kernel/trace/trace_events_user.c +++ b/kernel/trace/trace_events_user.c @@ -2096,7 +2096,8 @@ static ssize_t user_events_write_core(struct file *file, struct iov_iter *i) if (unlikely(faulted)) return -EFAULT; - } + } else + return -EBADF; return ret; } diff --git a/kernel/umh.c b/kernel/umh.c index 41088c5c39fd..1b13c5d34624 100644 --- a/kernel/umh.c +++ b/kernel/umh.c @@ -494,6 +494,7 @@ int call_usermodehelper(const char *path, char **argv, char **envp, int wait) } EXPORT_SYMBOL(call_usermodehelper); +#if defined(CONFIG_SYSCTL) static int proc_cap_handler(struct ctl_table *table, int write, void *buffer, size_t *lenp, loff_t *ppos) { @@ -544,7 +545,6 @@ static int proc_cap_handler(struct ctl_table *table, int write, return 0; } -#if defined(CONFIG_SYSCTL) static struct ctl_table usermodehelper_table[] = { { .procname = "bset", diff --git a/mm/Kconfig b/mm/Kconfig index e00df648c91d..09130434e30d 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -234,18 +234,23 @@ choice help This option allows to select a slab allocator. -config SLAB - bool "SLAB" +config SLAB_DEPRECATED + bool "SLAB (DEPRECATED)" depends on !PREEMPT_RT - select HAVE_HARDENED_USERCOPY_ALLOCATOR help + Deprecated and scheduled for removal in a few cycles. Replaced by + SLUB. + + If you cannot migrate to SLUB, please contact linux-mm@kvack.org + and the people listed in the SLAB ALLOCATOR section of MAINTAINERS + file, explaining why. + The regular slab allocator that is established and known to work well in all environments. It organizes cache hot objects in per cpu and per node queues. config SLUB bool "SLUB (Unqueued Allocator)" - select HAVE_HARDENED_USERCOPY_ALLOCATOR help SLUB is a slab allocator that minimizes cache line usage instead of managing queues of cached objects (SLAB approach). @@ -256,6 +261,11 @@ config SLUB endchoice +config SLAB + bool + default y + depends on SLAB_DEPRECATED + config SLUB_TINY bool "Configure SLUB for minimal memory footprint" depends on SLUB && EXPERT diff --git a/mm/kfence/kfence_test.c b/mm/kfence/kfence_test.c index 6aee19a79236..9e008a336d9f 100644 --- a/mm/kfence/kfence_test.c +++ b/mm/kfence/kfence_test.c @@ -191,11 +191,10 @@ static size_t setup_test_cache(struct kunit *test, size_t size, slab_flags_t fla kunit_info(test, "%s: size=%zu, ctor=%ps\n", __func__, size, ctor); /* - * Use SLAB_NOLEAKTRACE to prevent merging with existing caches. Any - * other flag in SLAB_NEVER_MERGE also works. Use SLAB_ACCOUNT to - * allocate via memcg, if enabled. + * Use SLAB_NO_MERGE to prevent merging with existing caches. + * Use SLAB_ACCOUNT to allocate via memcg, if enabled. */ - flags |= SLAB_NOLEAKTRACE | SLAB_ACCOUNT; + flags |= SLAB_NO_MERGE | SLAB_ACCOUNT; test_cache = kmem_cache_create("test", size, 1, flags, ctor); KUNIT_ASSERT_TRUE_MSG(test, test_cache, "could not create cache"); diff --git a/mm/mmap.c b/mm/mmap.c index 7bad6757e0ac..3eadf5ee4060 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -2490,7 +2490,8 @@ do_vmi_align_munmap(struct vma_iterator *vmi, struct vm_area_struct *vma, } vma_start_write(next); mas_set_range(&mas_detach, next->vm_start, next->vm_end - 1); - if (mas_store_gfp(&mas_detach, next, GFP_KERNEL)) + error = mas_store_gfp(&mas_detach, next, GFP_KERNEL); + if (error) goto munmap_gather_failed; vma_mark_detached(next, true); if (next->vm_flags & VM_LOCKED) @@ -2543,12 +2544,12 @@ do_vmi_align_munmap(struct vma_iterator *vmi, struct vm_area_struct *vma, BUG_ON(count != test_count); } #endif - /* Point of no return */ - error = -ENOMEM; vma_iter_set(vmi, start); - if (vma_iter_clear_gfp(vmi, start, end, GFP_KERNEL)) + error = vma_iter_clear_gfp(vmi, start, end, GFP_KERNEL); + if (error) goto clear_tree_failed; + /* Point of no return */ mm->locked_vm -= locked_vm; mm->map_count -= count; /* diff --git a/mm/slab.c b/mm/slab.c index b7817dcba63e..88194391d553 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -1883,14 +1883,12 @@ static bool set_on_slab_cache(struct kmem_cache *cachep, return true; } -/** +/* * __kmem_cache_create - Create a cache. * @cachep: cache management descriptor * @flags: SLAB flags * - * Returns a ptr to the cache on success, NULL on failure. - * Cannot be called within an int, but can be interrupted. - * The @ctor is run when new pages are allocated by the cache. + * Returns zero on success, nonzero on failure. * * The flags are * @@ -1903,8 +1901,6 @@ static bool set_on_slab_cache(struct kmem_cache *cachep, * %SLAB_HWCACHE_ALIGN - Align the objects in this cache to a hardware * cacheline. This can be beneficial if you're counting cycles as closely * as davem. - * - * Return: a pointer to the created cache or %NULL in case of error */ int __kmem_cache_create(struct kmem_cache *cachep, slab_flags_t flags) { @@ -2355,44 +2351,34 @@ static void cache_init_objs_debug(struct kmem_cache *cachep, struct slab *slab) #ifdef CONFIG_SLAB_FREELIST_RANDOM /* Hold information during a freelist initialization */ -union freelist_init_state { - struct { - unsigned int pos; - unsigned int *list; - unsigned int count; - }; - struct rnd_state rnd_state; +struct freelist_init_state { + unsigned int pos; + unsigned int *list; + unsigned int count; }; /* * Initialize the state based on the randomization method available. * return true if the pre-computed list is available, false otherwise. */ -static bool freelist_state_initialize(union freelist_init_state *state, +static bool freelist_state_initialize(struct freelist_init_state *state, struct kmem_cache *cachep, unsigned int count) { bool ret; - unsigned int rand; - - /* Use best entropy available to define a random shift */ - rand = get_random_u32(); - - /* Use a random state if the pre-computed list is not available */ if (!cachep->random_seq) { - prandom_seed_state(&state->rnd_state, rand); ret = false; } else { state->list = cachep->random_seq; state->count = count; - state->pos = rand % count; + state->pos = get_random_u32_below(count); ret = true; } return ret; } /* Get the next entry on the list and randomize it using a random shift */ -static freelist_idx_t next_random_slot(union freelist_init_state *state) +static freelist_idx_t next_random_slot(struct freelist_init_state *state) { if (state->pos >= state->count) state->pos = 0; @@ -2413,7 +2399,7 @@ static void swap_free_obj(struct slab *slab, unsigned int a, unsigned int b) static bool shuffle_freelist(struct kmem_cache *cachep, struct slab *slab) { unsigned int objfreelist = 0, i, rand, count = cachep->num; - union freelist_init_state state; + struct freelist_init_state state; bool precomputed; if (count < 2) @@ -2442,8 +2428,7 @@ static bool shuffle_freelist(struct kmem_cache *cachep, struct slab *slab) /* Fisher-Yates shuffle */ for (i = count - 1; i > 0; i--) { - rand = prandom_u32_state(&state.rnd_state); - rand %= (i + 1); + rand = get_random_u32_below(i + 1); swap_free_obj(slab, i, rand); } } else { diff --git a/mm/slab.h b/mm/slab.h index a59c8e5d2441..6a5633b25eb5 100644 --- a/mm/slab.h +++ b/mm/slab.h @@ -332,11 +332,11 @@ static inline bool is_kmalloc_cache(struct kmem_cache *s) #if defined(CONFIG_SLAB) #define SLAB_CACHE_FLAGS (SLAB_MEM_SPREAD | SLAB_NOLEAKTRACE | \ SLAB_RECLAIM_ACCOUNT | SLAB_TEMPORARY | \ - SLAB_ACCOUNT) + SLAB_ACCOUNT | SLAB_NO_MERGE) #elif defined(CONFIG_SLUB) #define SLAB_CACHE_FLAGS (SLAB_NOLEAKTRACE | SLAB_RECLAIM_ACCOUNT | \ SLAB_TEMPORARY | SLAB_ACCOUNT | \ - SLAB_NO_USER_FLAGS | SLAB_KMALLOC) + SLAB_NO_USER_FLAGS | SLAB_KMALLOC | SLAB_NO_MERGE) #else #define SLAB_CACHE_FLAGS (SLAB_NOLEAKTRACE) #endif @@ -357,6 +357,7 @@ static inline bool is_kmalloc_cache(struct kmem_cache *s) SLAB_TEMPORARY | \ SLAB_ACCOUNT | \ SLAB_KMALLOC | \ + SLAB_NO_MERGE | \ SLAB_NO_USER_FLAGS) bool __kmem_cache_empty(struct kmem_cache *); @@ -870,16 +871,8 @@ struct kmem_obj_info { void __kmem_obj_info(struct kmem_obj_info *kpp, void *object, struct slab *slab); #endif -#ifdef CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR void __check_heap_object(const void *ptr, unsigned long n, const struct slab *slab, bool to_user); -#else -static inline -void __check_heap_object(const void *ptr, unsigned long n, - const struct slab *slab, bool to_user) -{ -} -#endif #ifdef CONFIG_SLUB_DEBUG void skip_orig_size_check(struct kmem_cache *s, const void *object); diff --git a/mm/slab_common.c b/mm/slab_common.c index 43c008165f56..d1555ea2981a 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -49,7 +49,7 @@ static DECLARE_WORK(slab_caches_to_rcu_destroy_work, */ #define SLAB_NEVER_MERGE (SLAB_RED_ZONE | SLAB_POISON | SLAB_STORE_USER | \ SLAB_TRACE | SLAB_TYPESAFE_BY_RCU | SLAB_NOLEAKTRACE | \ - SLAB_FAILSLAB | kasan_never_merge()) + SLAB_FAILSLAB | SLAB_NO_MERGE | kasan_never_merge()) #define SLAB_MERGE_SAME (SLAB_RECLAIM_ACCOUNT | SLAB_CACHE_DMA | \ SLAB_CACHE_DMA32 | SLAB_ACCOUNT) @@ -238,14 +238,12 @@ static struct kmem_cache *create_cache(const char *name, s->refcount = 1; list_add(&s->list, &slab_caches); -out: - if (err) - return ERR_PTR(err); return s; out_free_cache: kmem_cache_free(kmem_cache, s); - goto out; +out: + return ERR_PTR(err); } /** @@ -892,6 +890,13 @@ new_kmalloc_cache(int idx, enum kmalloc_cache_type type, slab_flags_t flags) flags |= SLAB_CACHE_DMA; } + /* + * If CONFIG_MEMCG_KMEM is enabled, disable cache merging for + * KMALLOC_NORMAL caches. + */ + if (IS_ENABLED(CONFIG_MEMCG_KMEM) && (type == KMALLOC_NORMAL)) + flags |= SLAB_NO_MERGE; + if (minalign > ARCH_KMALLOC_MINALIGN) { aligned_size = ALIGN(aligned_size, minalign); aligned_idx = __kmalloc_index(aligned_size, false); @@ -903,13 +908,6 @@ new_kmalloc_cache(int idx, enum kmalloc_cache_type type, slab_flags_t flags) aligned_size, flags); if (idx != aligned_idx) kmalloc_caches[type][idx] = kmalloc_caches[type][aligned_idx]; - - /* - * If CONFIG_MEMCG_KMEM is enabled, disable cache merging for - * KMALLOC_NORMAL caches. - */ - if (IS_ENABLED(CONFIG_MEMCG_KMEM) && (type == KMALLOC_NORMAL)) - kmalloc_caches[type][idx]->refcount = -1; } /* @@ -1162,7 +1160,7 @@ EXPORT_SYMBOL(kmalloc_large_node); #ifdef CONFIG_SLAB_FREELIST_RANDOM /* Randomize a generic freelist */ -static void freelist_randomize(struct rnd_state *state, unsigned int *list, +static void freelist_randomize(unsigned int *list, unsigned int count) { unsigned int rand; @@ -1173,8 +1171,7 @@ static void freelist_randomize(struct rnd_state *state, unsigned int *list, /* Fisher-Yates shuffle */ for (i = count - 1; i > 0; i--) { - rand = prandom_u32_state(state); - rand %= (i + 1); + rand = get_random_u32_below(i + 1); swap(list[i], list[rand]); } } @@ -1183,7 +1180,6 @@ static void freelist_randomize(struct rnd_state *state, unsigned int *list, int cache_random_seq_create(struct kmem_cache *cachep, unsigned int count, gfp_t gfp) { - struct rnd_state state; if (count < 2 || cachep->random_seq) return 0; @@ -1192,10 +1188,7 @@ int cache_random_seq_create(struct kmem_cache *cachep, unsigned int count, if (!cachep->random_seq) return -ENOMEM; - /* Get best entropy at this stage of boot */ - prandom_seed_state(&state, get_random_long()); - - freelist_randomize(&state, cachep->random_seq, count); + freelist_randomize(cachep->random_seq, count); return 0; } diff --git a/mm/slub.c b/mm/slub.c index 7529626bbec2..e3b5d5c0eb3a 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -1365,14 +1365,6 @@ static void remove_full(struct kmem_cache *s, struct kmem_cache_node *n, struct list_del(&slab->slab_list); } -/* Tracking of the number of slabs for debugging purposes */ -static inline unsigned long slabs_node(struct kmem_cache *s, int node) -{ - struct kmem_cache_node *n = get_node(s, node); - - return atomic_long_read(&n->nr_slabs); -} - static inline unsigned long node_nr_slabs(struct kmem_cache_node *n) { return atomic_long_read(&n->nr_slabs); @@ -1743,8 +1735,6 @@ slab_flags_t kmem_cache_flags(unsigned int object_size, #define disable_higher_order_debug 0 -static inline unsigned long slabs_node(struct kmem_cache *s, int node) - { return 0; } static inline unsigned long node_nr_slabs(struct kmem_cache_node *n) { return 0; } static inline void inc_slabs_node(struct kmem_cache *s, int node, @@ -4623,7 +4613,7 @@ bool __kmem_cache_empty(struct kmem_cache *s) struct kmem_cache_node *n; for_each_kmem_cache_node(s, node, n) - if (n->nr_partial || slabs_node(s, node)) + if (n->nr_partial || node_nr_slabs(n)) return false; return true; } @@ -4640,7 +4630,7 @@ int __kmem_cache_shutdown(struct kmem_cache *s) /* Attempt to free all objects */ for_each_kmem_cache_node(s, node, n) { free_partial(s, n); - if (n->nr_partial || slabs_node(s, node)) + if (n->nr_partial || node_nr_slabs(n)) return 1; } return 0; @@ -4853,7 +4843,7 @@ static int __kmem_cache_do_shrink(struct kmem_cache *s) list_for_each_entry_safe(slab, t, &discard, slab_list) free_slab(s, slab); - if (slabs_node(s, node)) + if (node_nr_slabs(n)) ret = 1; } @@ -5191,9 +5181,9 @@ static int validate_slab_node(struct kmem_cache *s, validate_slab(s, slab, obj_map); count++; } - if (count != atomic_long_read(&n->nr_slabs)) { + if (count != node_nr_slabs(n)) { pr_err("SLUB: %s %ld slabs counted but counter=%ld\n", - s->name, count, atomic_long_read(&n->nr_slabs)); + s->name, count, node_nr_slabs(n)); slab_add_kunit_errors(); } @@ -5477,12 +5467,11 @@ static ssize_t show_slab_objects(struct kmem_cache *s, for_each_kmem_cache_node(s, node, n) { if (flags & SO_TOTAL) - x = atomic_long_read(&n->total_objects); + x = node_nr_objs(n); else if (flags & SO_OBJECTS) - x = atomic_long_read(&n->total_objects) - - count_partial(n, count_free); + x = node_nr_objs(n) - count_partial(n, count_free); else - x = atomic_long_read(&n->nr_slabs); + x = node_nr_slabs(n); total += x; nodes[node] += x; } @@ -5637,12 +5626,6 @@ static ssize_t cpu_slabs_show(struct kmem_cache *s, char *buf) } SLAB_ATTR_RO(cpu_slabs); -static ssize_t objects_show(struct kmem_cache *s, char *buf) -{ - return show_slab_objects(s, buf, SO_ALL|SO_OBJECTS); -} -SLAB_ATTR_RO(objects); - static ssize_t objects_partial_show(struct kmem_cache *s, char *buf) { return show_slab_objects(s, buf, SO_PARTIAL|SO_OBJECTS); @@ -5671,7 +5654,7 @@ static ssize_t slabs_cpu_partial_show(struct kmem_cache *s, char *buf) objects = (slabs * oo_objects(s->oo)) / 2; len += sysfs_emit_at(buf, len, "%d(%d)", objects, slabs); -#if defined(CONFIG_SLUB_CPU_PARTIAL) && defined(CONFIG_SMP) +#ifdef CONFIG_SLUB_CPU_PARTIAL for_each_online_cpu(cpu) { struct slab *slab; @@ -5737,6 +5720,12 @@ static ssize_t total_objects_show(struct kmem_cache *s, char *buf) } SLAB_ATTR_RO(total_objects); +static ssize_t objects_show(struct kmem_cache *s, char *buf) +{ + return show_slab_objects(s, buf, SO_ALL|SO_OBJECTS); +} +SLAB_ATTR_RO(objects); + static ssize_t sanity_checks_show(struct kmem_cache *s, char *buf) { return sysfs_emit(buf, "%d\n", !!(s->flags & SLAB_CONSISTENCY_CHECKS)); @@ -5968,7 +5957,6 @@ static struct attribute *slab_attrs[] = { &order_attr.attr, &min_partial_attr.attr, &cpu_partial_attr.attr, - &objects_attr.attr, &objects_partial_attr.attr, &partial_attr.attr, &cpu_slabs_attr.attr, @@ -5982,6 +5970,7 @@ static struct attribute *slab_attrs[] = { &slabs_cpu_partial_attr.attr, #ifdef CONFIG_SLUB_DEBUG &total_objects_attr.attr, + &objects_attr.attr, &slabs_attr.attr, &sanity_checks_attr.attr, &trace_attr.attr, @@ -6249,7 +6238,7 @@ static int __init slab_sysfs_init(void) if (!slab_kset) { mutex_unlock(&slab_mutex); pr_err("Cannot register slab subsystem.\n"); - return -ENOSYS; + return -ENOMEM; } slab_state = FULL; @@ -6421,7 +6410,7 @@ static int slab_debug_trace_open(struct inode *inode, struct file *filep) unsigned long flags; struct slab *slab; - if (!atomic_long_read(&n->nr_slabs)) + if (!node_nr_slabs(n)) continue; spin_lock_irqsave(&n->list_lock, flags); diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 2ab936e4179d..4405d5b67578 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -34,6 +34,6 @@ $(dst)/%.dtbo: $(obj)/%.dtbo PHONY += $(subdirs) $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) .PHONY: $(PHONY) diff --git a/security/Kconfig b/security/Kconfig index 97abeb9b9a19..52c9af08ad35 100644 --- a/security/Kconfig +++ b/security/Kconfig @@ -127,16 +127,8 @@ config LSM_MMAP_MIN_ADDR this low address space will need the permission specific to the systems running LSM. -config HAVE_HARDENED_USERCOPY_ALLOCATOR - bool - help - The heap allocator implements __check_heap_object() for - validating memory ranges against heap object sizes in - support of CONFIG_HARDENED_USERCOPY. - config HARDENED_USERCOPY bool "Harden memory copies between kernel and userspace" - depends on HAVE_HARDENED_USERCOPY_ALLOCATOR imply STRICT_DEVMEM help This option checks for obviously wrong memory regions when diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 2ca33fd5a575..a03a3291de84 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c @@ -33,8 +33,6 @@ static struct clk *ac97conf_clk; static int reset_gpio; static void __iomem *ac97_reg_base; -extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio); - /* * Beware PXA27x bugs: * diff --git a/tools/objtool/noreturns.h b/tools/objtool/noreturns.h index 1514e84d5cc4..e45c7cb1d5bc 100644 --- a/tools/objtool/noreturns.h +++ b/tools/objtool/noreturns.h @@ -14,7 +14,6 @@ NORETURN(__stack_chk_fail) NORETURN(__ubsan_handle_builtin_unreachable) NORETURN(arch_call_rest_init) NORETURN(arch_cpu_idle_dead) -NORETURN(btrfs_assertfail) NORETURN(cpu_bringup_and_idle) NORETURN(cpu_startup_entry) NORETURN(do_exit) diff --git a/tools/testing/selftests/user_events/ftrace_test.c b/tools/testing/selftests/user_events/ftrace_test.c index eb6904d89f14..5beb0aef1d81 100644 --- a/tools/testing/selftests/user_events/ftrace_test.c +++ b/tools/testing/selftests/user_events/ftrace_test.c @@ -324,6 +324,10 @@ TEST_F(user, write_events) { io[0].iov_base = ®.write_index; io[0].iov_len = sizeof(reg.write_index); + /* Write should return -EBADF when event is not enabled */ + ASSERT_EQ(-1, writev(self->data_fd, (const struct iovec *)io, 3)); + ASSERT_EQ(EBADF, errno); + /* Enable event */ self->enable_fd = open(enable_file, O_RDWR); ASSERT_NE(-1, write(self->enable_fd, "1", sizeof("1"))) @@ -400,6 +404,10 @@ TEST_F(user, write_fault) { ASSERT_EQ(0, ioctl(self->data_fd, DIAG_IOCSREG, ®)); ASSERT_EQ(0, reg.write_index); + /* Enable event */ + self->enable_fd = open(enable_file, O_RDWR); + ASSERT_NE(-1, write(self->enable_fd, "1", sizeof("1"))) + /* Write should work normally */ ASSERT_NE(-1, writev(self->data_fd, (const struct iovec *)io, 2));