d31e2e846b
Add the device tree entries and bindings needed to support the Altera L2
cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to
declare and setup On-chip RAM properly:
8b907c8b62 ("arm: dts: socfpga: Add OCRAM node")
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: ijc+devicetree@hellion.org.uk
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: m.chehab@samsung.com
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
50 lines
1.4 KiB
Plaintext
50 lines
1.4 KiB
Plaintext
Altera SoCFPGA ECC Manager
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This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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On Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-ocram-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- iram : phandle to On-Chip RAM definition.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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Example:
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eccmgr: eccmgr@ffd08140 {
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compatible = "altr,socfpga-ecc-manager";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l2-ecc@ffd08140 {
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compatible = "altr,socfpga-l2-ecc";
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reg = <0xffd08140 0x4>;
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interrupts = <0 36 1>, <0 37 1>;
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};
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ocram-ecc@ffd08144 {
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compatible = "altr,socfpga-ocram-ecc";
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reg = <0xffd08144 0x4>;
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iram = <&ocram>;
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interrupts = <0 178 1>, <0 179 1>;
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};
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};
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