Ketan Patil
4ef740cae9
Add support for mc-err logging for T264 in upstream mc driver. - Add mc-error handling flow for MCF, HUB, HUBC, SBS and MC Channel. - Each of these components have different interrupt lines for mc-err. - Register interrupt handlers for interrupts from these different MSS components. - Introduce new SOC specific fields in tegra_mc_soc. http://nvbugs/4655916 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
280 lines
8.3 KiB
C
280 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-2024 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef MEMORY_TEGRA_MC_H
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#define MEMORY_TEGRA_MC_H
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#include <linux/bits.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <soc/tegra/mc.h>
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#define MC_INTSTATUS 0x00
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#define MC_INT_INVALID_GART_PAGE BIT(7)
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#define MC_INT_INVALID_SMMU_PAGE BIT(10)
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#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11)
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#define MC_ERR_ROUTE_SANITY_SEC BIT(13)
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#define MC_INTMASK 0x04
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#define MC_GART_ERROR_REQ 0x30
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
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#define MC_SECURITY_VIOLATION_STATUS 0x74
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
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#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9c
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#define MC_EMEM_ARB_TIMING_RC 0xa0
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#define MC_EMEM_ARB_TIMING_RAS 0xa4
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#define MC_EMEM_ARB_TIMING_FAW 0xa8
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#define MC_EMEM_ARB_TIMING_RRD 0xac
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
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#define MC_EMEM_ARB_TIMING_R2R 0xb8
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#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
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#define MC_EMEM_ARB_MISC2 0xc8
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#define MC_EMEM_ARB_DA_TURNS 0xd0
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#define MC_EMEM_ARB_DA_COVERS 0xd4
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ARB_MISC1 0xdc
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#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
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#define MC_EMEM_ARB_OVERRIDE 0xe8
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#define MC_TIMING_CONTROL_DBG 0xf8
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#define MC_TIMING_CONTROL 0xfc
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#define MC_TIMING_UPDATE BIT(0)
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#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8
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#define MC_GLOBAL_INTSTATUS 0xf24
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/* Registers for MSS HUB */
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#define MSS_HUB_GLOBAL_INTSTATUS_0 0x6000
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#define MSS_HUBC_INTR BIT(0)
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#define MSS_HUB_HUBC_INTSTATUS_0 0x6008
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#define MSS_HUB_INTRSTATUS_0 0x600c
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#define MSS_HUB_HUBC_INTMASK_0 0x6010
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#define MSS_HUB_HUBC_SCRUB_DONE_INTMASK BIT(0)
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#define MSS_HUB_HUBC_INTPRIORITY_0 0x6014
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#define MSS_HUB_INTRMASK_0 0x6018
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#define MSS_HUB_COALESCER_ERR_INTMASK BIT(0)
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#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK BIT(1)
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#define MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK BIT(2)
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#define MSS_HUB_MSI_ERR_INTMASK BIT(3)
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#define MSS_HUB_POISON_RSP_INTMASK BIT(4)
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#define MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK BIT(5)
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#define MSS_HUB_RESERVED_PA_ERR_INTMASK BIT(6)
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#define MSS_HUB_INTRPRIORITY_0 0x601c
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#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0 0x6020
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#define MSS_HUB_MSI_ERR_STATUS_0 0x6024
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#define MSS_HUB_POISON_RSP_STATUS_0 0x6028
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#define MSS_HUB_COALESCE_ERR_STATUS_0 0x60e0
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#define MSS_HUB_COALESCE_ERR_ADR_HI_0 0x60e4
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#define MSS_HUB_COALESCE_ERR_ADR_0 0x60e8
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#define MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0 0x638c
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#define MSS_HUB_RESERVED_PA_ERR_STATUS_0 0x6390
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#define MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0 0x63b0
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/* Registers for MC Channel */
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#define MC_CH_INTSTATUS_0 0x82d4
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#define MC_CH_INTMASK_0 0x82d8
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#define WCAM_ERR_INTMASK BIT(19)
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#define T264_MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0x8870
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#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0 0xbc74
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/* Registers for MCF */
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#define MCF_COMMON_INTSTATUS0_0_0 0xce04
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#define MCF_INTSTATUS_0 0xce2c
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#define MC_INT_DECERR_EMEM BIT(6)
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#define MC_INT_SECURITY_VIOLATION BIT(8)
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#define MC_INT_DECERR_VPR BIT(12)
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#define MC_INT_SECERR_SEC BIT(13)
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#define MC_INT_DECERR_MTS BIT(16)
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#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)
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#define MC_INT_DECERR_ROUTE_SANITY BIT(20)
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#define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI BIT(21)
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#define MCF_INTMASK_0 0xce30
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#define MCF_INTPRIORITY_0 0xce34
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/* Registers for SBS */
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#define MSS_SBS_INTSTATUS_0 0xec08
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#define MSS_SBS_INTMASK_0 0xec0c
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#define MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK BIT(0)
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#define MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK BIT(1)
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#define MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK BIT(2)
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/*Bit field of MC_ERR_ROUTE_SANITY_STATUS_0 register */
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#define MC_ERR_ROUTE_SANITY_RW BIT(12)
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/*Bit field of MC_ERR_STATUS_0 register */
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#define MC_ERR_STATUS_RW BIT(16)
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#define MC_ERR_STATUS_SECURITY BIT(17)
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#define MC_ERR_STATUS_NONSECURE BIT(25)
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#define MC_ERR_STATUS_WRITABLE BIT(26)
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#define MC_ERR_STATUS_READABLE BIT(27)
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#define MC_ERR_STATUS_ADR_HI_MASK_GSC 0xffff
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#define MC_ERR_STATUS_ADR_HI_SHIFT_GSC 16
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#define MC_ERR_STATUS_ADR_HI_SHIFT_RT 15
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#define MC_ERR_STATUS_TYPE_SHIFT 28
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#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
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#define MC_ERR_STATUS_TYPE_MASK_RT (0xf << 28)
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#define MC_ERR_STATUS_TYPE_SHIFT_RT 28
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#define MC_ERR_STATUS_ADR_HI_SHIFT 20
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#define ERR_GENERALIZED_APERTURE_ID_SHIFT 0
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#define ERR_GENERALIZED_APERTURE_ID_MASK 0x1F
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#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT 5
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#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK 0x1F
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
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#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
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#define MC_BROADCAST_CHANNEL ~0
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static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents)
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{
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val = val * percents;
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do_div(val, 100);
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return min_t(u64, val, U32_MAX);
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}
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static inline struct tegra_mc *
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icc_provider_to_tegra_mc(struct icc_provider *provider)
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{
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return container_of(provider, struct tegra_mc, provider);
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}
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static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
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unsigned long offset)
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{
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if (!mc->bcast_ch_regs)
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return 0;
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if (ch == MC_BROADCAST_CHANNEL)
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return readl_relaxed(mc->bcast_ch_regs + offset);
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return readl_relaxed(mc->ch_regs[ch] + offset);
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}
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static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
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u32 value, unsigned long offset)
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{
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if (!mc->bcast_ch_regs)
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return;
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if (ch == MC_BROADCAST_CHANNEL)
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writel_relaxed(value, mc->bcast_ch_regs + offset);
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else
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writel_relaxed(value, mc->ch_regs[ch] + offset);
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}
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static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
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{
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return readl_relaxed(mc->regs + offset);
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}
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static inline void mc_writel(const struct tegra_mc *mc, u32 value,
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unsigned long offset)
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{
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writel_relaxed(value, mc->regs + offset);
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}
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extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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extern const struct tegra_mc_soc tegra20_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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extern const struct tegra_mc_soc tegra30_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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extern const struct tegra_mc_soc tegra114_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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extern const struct tegra_mc_soc tegra124_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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extern const struct tegra_mc_soc tegra132_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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extern const struct tegra_mc_soc tegra210_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_186_SOC
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extern const struct tegra_mc_soc tegra186_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_194_SOC
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extern const struct tegra_mc_soc tegra194_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_234_SOC
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extern const struct tegra_mc_soc tegra234_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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extern const struct tegra_mc_soc tegra264_mc_soc;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
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defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC)
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int tegra30_mc_probe(struct tegra_mc *mc);
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extern const struct tegra_mc_ops tegra30_mc_ops;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
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defined(CONFIG_ARCH_TEGRA_194_SOC) || \
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defined(CONFIG_ARCH_TEGRA_234_SOC)
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extern const struct tegra_mc_ops tegra186_mc_ops;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_264_SOC)
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extern const struct tegra_mc_ops tegra264_mc_ops;
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#endif
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irqreturn_t tegra30_mc_handle_irq(int irq, void *data);
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extern const char * const tegra20_mc_status_names[32];
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extern const char * const tegra20_mc_error_names[8];
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int tegra186_mc_probe(struct tegra_mc *mc);
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int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev);
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int tegra186_mc_resume(struct tegra_mc *mc);
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void tegra186_mc_remove(struct tegra_mc *mc);
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/*
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* These IDs are for internal use of Tegra ICC drivers. The ID numbers are
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* chosen such that they don't conflict with the device-tree ICC node IDs.
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*/
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#define TEGRA_ICC_MC 1000
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#define TEGRA_ICC_EMC 1001
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#define TEGRA_ICC_EMEM 1002
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#endif /* MEMORY_TEGRA_MC_H */
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