platform/x86: intel/pmc: Relocate Sunrise Point PCH support
Create spt.c for Sunrise Point PCH specific structures and init(). This file supports Sky Lake and Kaby Lake platforms. There are no functional changes involved. Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-4-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Rajvi Jingar
committed by
Hans de Goede
Hans de Goede
parent
03c58a1e94
commit
f23e21a345
@@ -3,7 +3,7 @@
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# Intel x86 Platform-Specific Drivers
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#
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intel_pmc_core-y := core.o
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intel_pmc_core-y := core.o spt.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
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intel_pmc_core_pltdrv-y := pltdrv.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
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@@ -60,130 +60,6 @@ const struct pmc_bit_map msr_map[] = {
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{}
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};
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static const struct pmc_bit_map spt_pll_map[] = {
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{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
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{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
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{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
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{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
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{}
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};
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static const struct pmc_bit_map spt_mphy_map[] = {
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{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
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{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
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{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
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{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
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{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
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{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
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{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
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{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
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{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
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{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
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{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
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{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
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{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
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{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
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{}
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};
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static const struct pmc_bit_map spt_pfear_map[] = {
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{"PMC", SPT_PMC_BIT_PMC},
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{"OPI-DMI", SPT_PMC_BIT_OPI},
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{"SPI / eSPI", SPT_PMC_BIT_SPI},
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{"XHCI", SPT_PMC_BIT_XHCI},
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{"SPA", SPT_PMC_BIT_SPA},
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{"SPB", SPT_PMC_BIT_SPB},
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{"SPC", SPT_PMC_BIT_SPC},
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{"GBE", SPT_PMC_BIT_GBE},
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{"SATA", SPT_PMC_BIT_SATA},
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{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
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{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
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{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
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{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
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{"RSVD", SPT_PMC_BIT_RSVD_0B},
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{"LPSS", SPT_PMC_BIT_LPSS},
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{"LPC", SPT_PMC_BIT_LPC},
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{"SMB", SPT_PMC_BIT_SMB},
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{"ISH", SPT_PMC_BIT_ISH},
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{"P2SB", SPT_PMC_BIT_P2SB},
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{"DFX", SPT_PMC_BIT_DFX},
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{"SCC", SPT_PMC_BIT_SCC},
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{"RSVD", SPT_PMC_BIT_RSVD_0C},
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{"FUSE", SPT_PMC_BIT_FUSE},
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{"CAMERA", SPT_PMC_BIT_CAMREA},
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{"RSVD", SPT_PMC_BIT_RSVD_0D},
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{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
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{"EXI", SPT_PMC_BIT_EXI},
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{"CSE", SPT_PMC_BIT_CSE},
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{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
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{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
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{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
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{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
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{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
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{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
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{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
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{"RSVD", SPT_PMC_BIT_RSVD_1A},
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{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
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{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
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{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
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{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
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{}
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};
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static const struct pmc_bit_map *ext_spt_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of spt_reg_map for
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* a list of core SoCs using this.
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*/
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spt_pfear_map,
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NULL
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};
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static const struct pmc_bit_map spt_ltr_show_map[] = {
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{"SOUTHPORT_A", SPT_PMC_LTR_SPA},
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{"SOUTHPORT_B", SPT_PMC_LTR_SPB},
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{"SATA", SPT_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
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{"XHCI", SPT_PMC_LTR_XHCI},
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{"Reserved", SPT_PMC_LTR_RESERVED},
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{"ME", SPT_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", SPT_PMC_LTR_EVA},
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{"SOUTHPORT_C", SPT_PMC_LTR_SPC},
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{"HD_AUDIO", SPT_PMC_LTR_AZ},
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{"LPSS", SPT_PMC_LTR_LPSS},
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{"SOUTHPORT_D", SPT_PMC_LTR_SPD},
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{"SOUTHPORT_E", SPT_PMC_LTR_SPE},
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{"CAMERA", SPT_PMC_LTR_CAM},
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{"ESPI", SPT_PMC_LTR_ESPI},
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{"SCC", SPT_PMC_LTR_SCC},
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{"ISH", SPT_PMC_LTR_ISH},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
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{}
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};
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static const struct pmc_reg_map spt_reg_map = {
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.pfear_sts = ext_spt_pfear_map,
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.mphy_sts = spt_mphy_map,
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.pll_sts = spt_pll_map,
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.ltr_show_sts = spt_ltr_show_map,
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.msr_sts = msr_map,
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.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = SPT_PMC_MMIO_REG_LEN,
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.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
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.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
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.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
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};
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/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
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static const struct pmc_bit_map cnp_pfear_map[] = {
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{"PMC", BIT(0)},
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@@ -1907,11 +1783,6 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
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}
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}
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void spt_core_init(struct pmc_dev *pmcdev)
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{
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pmcdev->map = &spt_reg_map;
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}
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void cnp_core_init(struct pmc_dev *pmcdev)
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{
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pmcdev->map = &cnp_reg_map;
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@@ -337,6 +337,13 @@ struct pmc_dev {
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};
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extern const struct pmc_bit_map msr_map[];
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extern const struct pmc_bit_map spt_pll_map[];
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extern const struct pmc_bit_map spt_mphy_map[];
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extern const struct pmc_bit_map spt_pfear_map[];
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extern const struct pmc_bit_map *ext_spt_pfear_map[];
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extern const struct pmc_bit_map spt_ltr_show_map[];
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extern const struct pmc_reg_map spt_reg_map;
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void spt_core_init(struct pmc_dev *pmcdev);
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void cnp_core_init(struct pmc_dev *pmcdev);
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void icl_core_init(struct pmc_dev *pmcdev);
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@@ -0,0 +1,140 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains platform specific structure definitions
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* and init function used by Sunrise Point PCH.
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*
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* Copyright (c) 2022, Intel Corporation.
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* All Rights Reserved.
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*
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*/
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#include "core.h"
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const struct pmc_bit_map spt_pll_map[] = {
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{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
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{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
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{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
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{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
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{}
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};
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const struct pmc_bit_map spt_mphy_map[] = {
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{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
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{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
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{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
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{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
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{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
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{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
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{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
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{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
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{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
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{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
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{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
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{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
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{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
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{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
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{}
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};
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const struct pmc_bit_map spt_pfear_map[] = {
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{"PMC", SPT_PMC_BIT_PMC},
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{"OPI-DMI", SPT_PMC_BIT_OPI},
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{"SPI / eSPI", SPT_PMC_BIT_SPI},
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{"XHCI", SPT_PMC_BIT_XHCI},
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{"SPA", SPT_PMC_BIT_SPA},
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{"SPB", SPT_PMC_BIT_SPB},
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{"SPC", SPT_PMC_BIT_SPC},
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{"GBE", SPT_PMC_BIT_GBE},
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{"SATA", SPT_PMC_BIT_SATA},
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{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
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{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
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{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
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{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
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{"RSVD", SPT_PMC_BIT_RSVD_0B},
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{"LPSS", SPT_PMC_BIT_LPSS},
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{"LPC", SPT_PMC_BIT_LPC},
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{"SMB", SPT_PMC_BIT_SMB},
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{"ISH", SPT_PMC_BIT_ISH},
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{"P2SB", SPT_PMC_BIT_P2SB},
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{"DFX", SPT_PMC_BIT_DFX},
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{"SCC", SPT_PMC_BIT_SCC},
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{"RSVD", SPT_PMC_BIT_RSVD_0C},
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{"FUSE", SPT_PMC_BIT_FUSE},
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{"CAMERA", SPT_PMC_BIT_CAMREA},
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{"RSVD", SPT_PMC_BIT_RSVD_0D},
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{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
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{"EXI", SPT_PMC_BIT_EXI},
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{"CSE", SPT_PMC_BIT_CSE},
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{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
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{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
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{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
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{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
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{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
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{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
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{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
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{"RSVD", SPT_PMC_BIT_RSVD_1A},
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{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
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{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
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{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
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{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
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{}
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};
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const struct pmc_bit_map *ext_spt_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of spt_reg_map for
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* a list of core SoCs using this.
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*/
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spt_pfear_map,
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NULL
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};
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const struct pmc_bit_map spt_ltr_show_map[] = {
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{"SOUTHPORT_A", SPT_PMC_LTR_SPA},
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{"SOUTHPORT_B", SPT_PMC_LTR_SPB},
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{"SATA", SPT_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
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{"XHCI", SPT_PMC_LTR_XHCI},
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{"Reserved", SPT_PMC_LTR_RESERVED},
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{"ME", SPT_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", SPT_PMC_LTR_EVA},
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{"SOUTHPORT_C", SPT_PMC_LTR_SPC},
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{"HD_AUDIO", SPT_PMC_LTR_AZ},
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{"LPSS", SPT_PMC_LTR_LPSS},
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{"SOUTHPORT_D", SPT_PMC_LTR_SPD},
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{"SOUTHPORT_E", SPT_PMC_LTR_SPE},
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{"CAMERA", SPT_PMC_LTR_CAM},
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{"ESPI", SPT_PMC_LTR_ESPI},
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{"SCC", SPT_PMC_LTR_SCC},
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{"ISH", SPT_PMC_LTR_ISH},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
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{}
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};
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const struct pmc_reg_map spt_reg_map = {
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.pfear_sts = ext_spt_pfear_map,
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.mphy_sts = spt_mphy_map,
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.pll_sts = spt_pll_map,
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.ltr_show_sts = spt_ltr_show_map,
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.msr_sts = msr_map,
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.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = SPT_PMC_MMIO_REG_LEN,
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.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
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.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
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.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
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};
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void spt_core_init(struct pmc_dev *pmcdev)
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{
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pmcdev->map = &spt_reg_map;
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}
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