clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags

BugLink: https://bugs.launchpad.net/bugs/2100292

commit e7f37a7d16310d3c9474825de26a67f00983ebea upstream.

Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
configuration on machine suspend. Currently, the QMP combo PHY driver
doesn't reinitialise the HW on resume. Under such conditions, the USB
SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
RET_ON. This has been already done for USB 0 and 1 SS PHY GDSCs,
Do this also for the USB MP SS1 PHY GDSC config. The USB MP SS0 PHY GDSC
already has it.

Fixes: 161b7c401f ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241021-x1e80100-clk-gcc-fix-usb-mp-phy-gdsc-pwrsts-flags-v2-1-0bfd64556238@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Koichiro Den <koichiro.den@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

This commit is contained in:

Abel Vesa

2025-02-26 22:49:14 +09:00

committed by

Stefan Bader

parent 0bd85999f0

commit e1b59aae2c

1 changed files with 1 additions and 1 deletions

									
										drivers/clk/qcom/gcc-x1e80100.c
									
		+1
		-1
	
												View File
												
				@@ -6155,7 +6155,7 @@ static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {

					.pd = {

						.name = "gcc_usb3_mp_ss1_phy_gdsc",

					},

					.pwrsts = PWRSTS_OFF_ON,

					.pwrsts = PWRSTS_RET_ON,

					.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,

				};