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NVIDIA: SAUCE: net: phy: tegra: p2u: update power on sequence

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BugLink: https://bugs.launchpad.net/bugs/2072591

During P2U power on P2U_CONTROL_GEN1 register needs to be
configured to enable RXIDLE_ENTRY_ON_LINK_STATUS and disable
ENABLE_RXIDLE_ENTRY_ON_EIOS bit for tegra194.

http://nvbugs/3624069

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Nagarjuna Kristam
2022-11-17 15:16:59 +05:30
committed by Noah Wager
parent 6d5e95ac1d
commit cd94ad3fb3
1 changed files with 15 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/phy/tegra/phy-tegra194-p2u.c
+15
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@@ -21,6 +21,10 @@
#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13)
#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)
#define P2U_CONTROL_GEN1 0x78U
#define P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_LINK_STATUS BIT(2)
#define P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_EIOS BIT(3)
#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
@@ -78,6 +82,7 @@
struct tegra_p2u_of_data {
bool one_dir_search;
bool lane_margin;
bool eios_override;
};
struct tegra_p2u {
@@ -122,6 +127,14 @@ static int tegra_p2u_power_on(struct phy *x)
p2u_writel(phy, val, P2U_CONTROL_CMN);
}
val = p2u_readl(phy, P2U_CONTROL_GEN1);
if (phy->of_data->eios_override)
val &= ~P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_EIOS;
val |= (P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_LINK_STATUS);
p2u_writel(phy, val, P2U_CONTROL_GEN1);
val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
@@ -451,11 +464,13 @@ static int tegra_p2u_remove(struct platform_device *pdev)
static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
.one_dir_search = false,
.lane_margin = false,
.eios_override = true,
};
static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
.one_dir_search = true,
.lane_margin = true,
.eios_override = false,
};
static const struct of_device_id tegra_p2u_id_table[] = {