NVIDIA: SAUCE: perf: arm_cspmu: nvidia: add T264 support
Adds PMU support for the following IPs in NVIDIA Tegra T264 SOC: - Unified Coherency Fabric (UCF) - Vision - Display - High-speed IO - UCF GPU Bug 5524939 Change-Id: I595dc746e3b45b9f40c5f4343212c37f42f0faa1 Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/canonical/linux-noble/+/3459617 Tested-by: Ryan Bissell <rbissell@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
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Besar Wicaksono
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@@ -10,6 +10,11 @@ metrics like memory bandwidth, latency, and utilization:
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* NVLink-C2C1
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* CNVLink
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* PCIE
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* Unified Coherency Fabric (UCF)
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* Vision
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* Display
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* High-speed IO
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* UCF-GPU
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PMU Driver
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----------
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@@ -183,6 +188,159 @@ Example usage:
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perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
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UCF PMU
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-------
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The UCF PMU monitors system level cache events and DRAM traffic that flows
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through UCF.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_ucf_pmu_<socket-id>.
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User can configure the PMU to capture events from specific source and destination.
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The source/destination filter is described in
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/sys/bus/event_sources/devices/nvidia_ucf_pmu_<socket-id>/format/. By default
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traffic from all sources and destinations will be captured if no source/destination
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is specified.
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Example usage:
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* Count event id 0x0 from any source/destination of socket 0::
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perf stat -a -e nvidia_ucf_pmu_0/event=0x0/
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* Count event id 0x1 from socket 0's CPUs to socket 0's DRAM::
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perf stat -a -e nvidia_ucf_pmu_0/event=0x1,src_loc_cpu=0x1,dst_loc=0x1/
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* Count event id 0x1 from remote source of socket 0 to local and remote DRAM::
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perf stat -a -e nvidia_ucf_pmu_0/event=0x1,src_rem=0x1,dst_loc=0x1,dst_rem=0x1/
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* Count event id 0x2 from any source/destination of socket 1::
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perf stat -a -e nvidia_ucf_pmu_1/event=0x2/
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* Count event id 0x3 from socket 1's CPUs to socket 1's DRAM::
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perf stat -a -e nvidia_ucf_pmu_1/event=0x3,src_loc_cpu=0x1,dst_loc=0x1/
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Vision PMU
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------------
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The vision PMU monitors memory traffic from the multimedia IPs in the SOC.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_vision_pmu_<socket-id>.
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User can configure the PMU to capture events from specific IPs.
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/sys/bus/event_sources/devices/nvidia_vision_pmu_<socket-id>/format/ contains
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the filter attribute name of each multimedia IP. This filter attribute is a
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bitmask to select the AXI/hub interface of the IP to monitor. By default traffic
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from all interfaces of all IPs will be captured if no IPs are specified.
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Example usage:
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* Count event id 0x0 from all multimedia IPs in socket 0::
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perf stat -a -e nvidia_vision_pmu_0/event=0x0/
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* Count event id 0x1 from AXI/hub interface 0 in VI-0 of socket 0::
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perf stat -a -e nvidia_vision_pmu_0/event=0x1,vi_0=0x1/
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* Count event id 0x1 from AXI/hub interface 0 and 1 in VI-0 of socket 0::
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perf stat -a -e nvidia_vision_pmu_0/event=0x1,vi_0=0x3/
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* Count event id 0x2 from all multimedia IPs in socket 1::
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perf stat -a -e nvidia_vision_pmu_1/event=0x2/
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* Count event id 0x3 from AXI/hub interface 0 in VI-0 and PVA of socket 1::
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perf stat -a -e nvidia_vision_pmu_1/event=0x3,vi_0=0x1,pva=0x1/
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Display PMU
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------------
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The display PMU monitors memory traffic from the display IP in the SOC.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_display_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 in socket 0::
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perf stat -a -e nvidia_display_pmu_0/event=0x0/
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* Count event id 0x0 in socket 1::
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perf stat -a -e nvidia_display_pmu_1/event=0x0/
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High-speed I/O PMU
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-------------------
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The high-speed I/O PMU monitors memory traffic from the high speed I/O devices
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in the SOC.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_uphy_pmu_<socket-id>.
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User can configure the PMU to capture events from specific I/Os.
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/sys/bus/event_sources/devices/nvidia_uphy_pmu_<socket-id>/format/ contains
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the filter attribute name of each I/O. This filter attribute is a
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bitmask to select the AXI/hub interface of the I/O to monitor. By default
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traffic from all interfaces of all I/Os will be captured if no I/Os are
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specified.
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Example usage:
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* Count event id 0x0 from all I/Os in socket 0::
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perf stat -a -e nvidia_uphy_pmu_0/event=0x0/
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* Count event id 0x1 from PCIE Root Port 1 of socket 0::
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perf stat -a -e nvidia_uphy_pmu_0/event=0x1,pcie_rp_1=0x1/
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* Count event id 0x1 from PCIE Root Port 1 and Root Port 2 of socket 0::
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perf stat -a -e nvidia_uphy_pmu_0/event=0x1,pcie_rp_1=0x1,pcie_rp_2=0x1/
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* Count event id 0x2 from all IPs in socket 1::
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perf stat -a -e nvidia_uphy_pmu_1/event=0x2/
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* Count event id 0x3 from PCIE Root Port 3 and UFS of socket 1::
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perf stat -a -e nvidia_uphy_pmu_1/event=0x1,pcie_rp_3=0x1,ufs=0x1/
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UCF-GPU PMU
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------------
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The UCF-GPU PMU monitors integrated GPU physical address traffic flowing through
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UCF.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_ucf_gpu_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 in socket 0::
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perf stat -a -e nvidia_ucf_gpu_pmu_0/event=0x0/
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* Count event id 0x0 in socket 1::
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perf stat -a -e nvidia_ucf_gpu_pmu_1/event=0x0/
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.. _NVIDIA_Uncore_PMU_Traffic_Coverage_Section:
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Traffic Coverage
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@@ -20,6 +20,16 @@
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#define NV_CNVL_PORT_COUNT 4ULL
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#define NV_CNVL_FILTER_ID_MASK GENMASK_ULL(NV_CNVL_PORT_COUNT - 1, 0)
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#define NV_UCF_FILTER_ID_MASK GENMASK_ULL(4, 0)
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#define NV_UPHY_FILTER_ID_MASK GENMASK_ULL(16, 0)
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#define NV_VISION_FILTER_ID_MASK GENMASK_ULL(19, 0)
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#define NV_DISPLAY_FILTER_ID_MASK BIT(0)
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#define NV_UCF_GPU_FILTER_ID_MASK BIT(0)
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#define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0)
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#define NV_PRODID_MASK (ARM_CSPMU_PMIIDR_PRODUCTID | \
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@@ -178,6 +188,72 @@ static struct attribute *mcf_pmu_event_attrs[] = {
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NULL,
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};
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static struct attribute *ucf_pmu_event_attrs[] = {
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ARM_CSPMU_EVENT_ATTR(slc_allocate, 0xf0),
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ARM_CSPMU_EVENT_ATTR(slc_refill, 0xf1),
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ARM_CSPMU_EVENT_ATTR(slc_access, 0xf2),
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ARM_CSPMU_EVENT_ATTR(slc_wb, 0xf3),
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ARM_CSPMU_EVENT_ATTR(slc_hit, 0x118),
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ARM_CSPMU_EVENT_ATTR(slc_access_wr, 0x112),
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ARM_CSPMU_EVENT_ATTR(slc_access_rd, 0x111),
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ARM_CSPMU_EVENT_ATTR(slc_refill_wr, 0x10a),
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ARM_CSPMU_EVENT_ATTR(slc_refill_rd, 0x109),
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ARM_CSPMU_EVENT_ATTR(slc_hit_wr, 0x11a),
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ARM_CSPMU_EVENT_ATTR(slc_hit_rd, 0x119),
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ARM_CSPMU_EVENT_ATTR(slc_access_dataless, 0x183),
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ARM_CSPMU_EVENT_ATTR(slc_access_atomic, 0x184),
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ARM_CSPMU_EVENT_ATTR(local_snoop, 0x180),
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ARM_CSPMU_EVENT_ATTR(ext_snp_access, 0x181),
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ARM_CSPMU_EVENT_ATTR(ext_snp_evict, 0x182),
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ARM_CSPMU_EVENT_ATTR(ucf_bus_cycles, 0x1d),
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ARM_CSPMU_EVENT_ATTR(any_access_wr, 0x112),
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ARM_CSPMU_EVENT_ATTR(any_access_rd, 0x111),
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ARM_CSPMU_EVENT_ATTR(any_byte_wr, 0x114),
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ARM_CSPMU_EVENT_ATTR(any_byte_rd, 0x113),
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ARM_CSPMU_EVENT_ATTR(any_outstanding_rd, 0x115),
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ARM_CSPMU_EVENT_ATTR(local_dram_access_wr, 0x122),
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ARM_CSPMU_EVENT_ATTR(local_dram_access_rd, 0x121),
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ARM_CSPMU_EVENT_ATTR(local_dram_byte_wr, 0x124),
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ARM_CSPMU_EVENT_ATTR(local_dram_byte_rd, 0x123),
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ARM_CSPMU_EVENT_ATTR(mmio_access_wr, 0x132),
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ARM_CSPMU_EVENT_ATTR(mmio_access_rd, 0x131),
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ARM_CSPMU_EVENT_ATTR(mmio_byte_wr, 0x134),
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ARM_CSPMU_EVENT_ATTR(mmio_byte_rd, 0x133),
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ARM_CSPMU_EVENT_ATTR(mmio_outstanding_rd, 0x135),
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ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
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NULL,
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};
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static struct attribute *display_pmu_event_attrs[] = {
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ARM_CSPMU_EVENT_ATTR(rd_bytes_loc, 0x0),
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ARM_CSPMU_EVENT_ATTR(rd_req_loc, 0x6),
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ARM_CSPMU_EVENT_ATTR(rd_cum_outs_loc, 0xc),
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ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
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NULL,
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};
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static struct attribute *ucf_gpu_pmu_event_attrs[] = {
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ARM_CSPMU_EVENT_ATTR(rd_bytes_loc_rem, 0x0),
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ARM_CSPMU_EVENT_ATTR(wr_bytes_loc, 0x2),
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ARM_CSPMU_EVENT_ATTR(wr_bytes_rem, 0x3),
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ARM_CSPMU_EVENT_ATTR(rd_req_loc_rem, 0x6),
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ARM_CSPMU_EVENT_ATTR(wr_req_loc, 0x8),
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ARM_CSPMU_EVENT_ATTR(wr_req_rem, 0x9),
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ARM_CSPMU_EVENT_ATTR(rd_cum_outs_loc_rem, 0xc),
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ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
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NULL,
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};
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static struct attribute *generic_pmu_event_attrs[] = {
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ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
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NULL,
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@@ -205,6 +281,54 @@ static struct attribute *cnvlink_pmu_format_attrs[] = {
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NULL,
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};
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static struct attribute *ucf_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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ARM_CSPMU_FORMAT_ATTR(src_loc_noncpu, "config1:0"),
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ARM_CSPMU_FORMAT_ATTR(src_loc_cpu, "config1:1"),
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ARM_CSPMU_FORMAT_ATTR(src_rem, "config1:2"),
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ARM_CSPMU_FORMAT_ATTR(dst_loc, "config1:3"),
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ARM_CSPMU_FORMAT_ATTR(dst_rem, "config1:4"),
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NULL,
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};
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static struct attribute *display_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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NULL,
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};
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static struct attribute *ucf_gpu_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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NULL,
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};
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static struct attribute *uphy_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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ARM_CSPMU_FORMAT_ATTR(pcie_rp_1, "config1:0"),
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ARM_CSPMU_FORMAT_ATTR(pcie_rp_2, "config1:1"),
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ARM_CSPMU_FORMAT_ATTR(pcie_rp_3, "config1:2"),
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ARM_CSPMU_FORMAT_ATTR(pcie_rp_4, "config1:3"),
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ARM_CSPMU_FORMAT_ATTR(pcie_rp_5, "config1:4"),
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ARM_CSPMU_FORMAT_ATTR(xusb, "config1:5-10"),
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ARM_CSPMU_FORMAT_ATTR(mgbe_0, "config1:11"),
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ARM_CSPMU_FORMAT_ATTR(mgbe_1, "config1:12"),
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ARM_CSPMU_FORMAT_ATTR(mgbe_2, "config1:13"),
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ARM_CSPMU_FORMAT_ATTR(mgbe_3, "config1:14"),
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ARM_CSPMU_FORMAT_ATTR(eqos, "config1:15"),
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ARM_CSPMU_FORMAT_ATTR(ufs, "config1:16"),
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NULL,
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};
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static struct attribute *vision_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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ARM_CSPMU_FORMAT_ATTR(vi_0, "config1:0-1"),
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ARM_CSPMU_FORMAT_ATTR(vi_1, "config1:2-3"),
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ARM_CSPMU_FORMAT_ATTR(isp_0, "config1:4-7"),
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ARM_CSPMU_FORMAT_ATTR(isp_1, "config1:8-11"),
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ARM_CSPMU_FORMAT_ATTR(vic, "config1:12-13"),
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ARM_CSPMU_FORMAT_ATTR(pva, "config1:14-19"),
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NULL,
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};
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static struct attribute *generic_pmu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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ARM_CSPMU_FORMAT_FILTER_ATTR,
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@@ -313,6 +437,56 @@ static const struct nv_cspmu_match nv_cspmu_match[] = {
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.event_attr = scf_pmu_event_attrs,
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.format_attr = scf_pmu_format_attrs
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},
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{
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.prodid = 0x2CF10000,
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.prodid_mask = NV_PRODID_MASK,
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.filter_mask = NV_UCF_FILTER_ID_MASK,
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.filter_default_val = NV_UCF_FILTER_ID_MASK,
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.name_pattern = "nvidia_ucf_pmu_%u",
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.name_fmt = NAME_FMT_SOCKET,
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.event_attr = ucf_pmu_event_attrs,
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.format_attr = ucf_pmu_format_attrs
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},
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{
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.prodid = 0x10800000,
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.prodid_mask = NV_PRODID_MASK,
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.filter_mask = NV_UPHY_FILTER_ID_MASK,
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.filter_default_val = NV_UPHY_FILTER_ID_MASK,
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.name_pattern = "nvidia_uphy_pmu_%u",
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.name_fmt = NAME_FMT_SOCKET,
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.event_attr = mcf_pmu_event_attrs,
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.format_attr = uphy_pmu_format_attrs
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},
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{
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.prodid = 0x10a00000,
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.prodid_mask = NV_PRODID_MASK,
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.filter_mask = 0,
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.filter_default_val = NV_UCF_GPU_FILTER_ID_MASK,
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.name_pattern = "nvidia_ucf_gpu_pmu_%u",
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.name_fmt = NAME_FMT_SOCKET,
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.event_attr = ucf_gpu_pmu_event_attrs,
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.format_attr = ucf_gpu_pmu_format_attrs
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},
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{
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.prodid = 0x10d00000,
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.prodid_mask = NV_PRODID_MASK,
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.filter_mask = 0,
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.filter_default_val = NV_DISPLAY_FILTER_ID_MASK,
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.name_pattern = "nvidia_display_pmu_%u",
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.name_fmt = NAME_FMT_SOCKET,
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.event_attr = display_pmu_event_attrs,
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.format_attr = display_pmu_format_attrs
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},
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{
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.prodid = 0x10e00000,
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.prodid_mask = NV_PRODID_MASK,
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.filter_mask = NV_VISION_FILTER_ID_MASK,
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.filter_default_val = NV_VISION_FILTER_ID_MASK,
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.name_pattern = "nvidia_vision_pmu_%u",
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.name_fmt = NAME_FMT_SOCKET,
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.event_attr = mcf_pmu_event_attrs,
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.format_attr = vision_pmu_format_attrs
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},
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{
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.prodid = 0,
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.prodid_mask = 0,
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