MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a
BugLink: https://bugs.launchpad.net/bugs/2102118 [ Upstream commit 4fbd66d8254cedfd1218393f39d83b6c07a01917 ] Fix the dtc warnings: arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider' And a runtime warning introduced in commit 045b14ca5c36 ("of: WARN on deprecated #address-cells/#size-cells handling"): WARNING: CPU: 0 PID: 1 at drivers/of/base.c:106 of_bus_n_addr_cells+0x9c/0xe0 Missing '#address-cells' in /bus@10000000/pci@1a000000/pci_bridge@9,0 The fix is similar to commit d89a415ff8d5 ("MIPS: Loongson64: DTS: Fix PCIe port nodes for ls7a"), which has fixed the issue for ls2k (despite its subject mentions ls7a). Signed-off-by: Xi Ruoyao <xry111@xry111.site> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sasha Levin <sashal@kernel.org> CVE-2024-56785 Signed-off-by: Koichiro Den <koichiro.den@canonical.com> Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
Xi Ruoyao
Stefan Bader
@@ -70,7 +70,6 @@
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <2>;
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msi-parent = <&msi>;
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reg = <0 0x1a000000 0 0x02000000>,
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@@ -234,7 +233,7 @@
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};
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};
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pci_bridge@9,0 {
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pcie@9,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@@ -244,12 +243,16 @@
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@a,0 {
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pcie@a,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@@ -259,12 +262,16 @@
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interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@b,0 {
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pcie@b,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@@ -274,12 +281,16 @@
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interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@c,0 {
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pcie@c,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@@ -289,12 +300,16 @@
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interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@d,0 {
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pcie@d,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@@ -304,12 +319,16 @@
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@e,0 {
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pcie@e,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@@ -319,12 +338,16 @@
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@f,0 {
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pcie@f,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@@ -334,12 +357,16 @@
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@10,0 {
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pcie@10,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@@ -349,12 +376,16 @@
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@11,0 {
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pcie@11,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@@ -364,12 +395,16 @@
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@12,0 {
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pcie@12,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@@ -379,12 +414,16 @@
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interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@13,0 {
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pcie@13,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@@ -394,12 +433,16 @@
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@14,0 {
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pcie@14,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@@ -409,9 +452,13 @@
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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};
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