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drm/msm/dpu: add division of drm_display_mode's hskew parameter

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BugLink: https://bugs.launchpad.net/bugs/2060097

[ Upstream commit 551ee0f210991d25f336bc27262353bfe99d3eed ]

Setting up the timing engine when the physical encoder has a split role
neglects dividing the drm_display_mode's hskew parameter. Let's fix this
since this must also be done in preparation for implementing YUV420 over
DP.

Fixes: 25fdd5933e ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579605/
Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit 0b492855578b6dc35c7f93b8083ccc57a363f979)
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
This commit is contained in:
Paloma Arellano
2024-02-22 11:39:47 -08:00
committed by Roxana Nicolescu
parent 038de900c3
commit a59adea938
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+4 -2
View File
@@ -260,12 +260,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
mode.htotal >>= 1;
mode.hsync_start >>= 1;
mode.hsync_end >>= 1;
mode.hskew >>= 1;
DPU_DEBUG_VIDENC(phys_enc,
"split_role %d, halve horizontal %d %d %d %d\n",
"split_role %d, halve horizontal %d %d %d %d %d\n",
phys_enc->split_role,
mode.hdisplay, mode.htotal,
mode.hsync_start, mode.hsync_end);
mode.hsync_start, mode.hsync_end,
mode.hskew);
}
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);