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NVIDIA: SAUCE: PCI: tegra194: Add ASPM L1 entrance latency config

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BugLink: https://bugs.launchpad.net/bugs/2072591

ASPM L1 latency configuration is needed for T234 EP mode. Add generic
support for this configuration keeping POR values for non T234 EP mode
and expected config value for T234 EP.

http://nvbugs/3920798

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Nagarjuna Kristam
2023-02-09 15:54:47 +05:30
committed by Noah Wager
parent 2d8d4374cb
commit a2a6caf497
1 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/pci/controller/dwc/pcie-tegra194.c
+8
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@@ -364,6 +364,8 @@ struct tegra_pcie_dw_of_data {
u32 cdm_chk_int_en_bit;
u32 gen4_preset_vec;
u8 n_fts[2];
/* L2 Latency entrance values(Rest/Prod) */
u32 aspm_l1_enter_lat;
};
struct tegra_pcie_dw {
@@ -1123,6 +1125,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
val |= (pcie->of_data->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
val |= PORT_AFR_ENTER_ASPM;
dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
@@ -3124,6 +3128,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {
/* Gen4 - 5, 6, 8 and 9 presets enabled */
.gen4_preset_vec = 0x360,
.n_fts = { 52, 52 },
.aspm_l1_enter_lat = 3,
};
static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
@@ -3133,6 +3138,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
/* Gen4 - 5, 6, 8 and 9 presets enabled */
.gen4_preset_vec = 0x360,
.n_fts = { 52, 52 },
.aspm_l1_enter_lat = 3,
};
static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
@@ -3145,6 +3151,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
/* Gen4 - 6, 8 and 9 presets enabled */
.gen4_preset_vec = 0x340,
.n_fts = { 52, 80 },
.aspm_l1_enter_lat = 4,
};
static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
@@ -3157,6 +3164,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
/* Gen4 - 6, 8 and 9 presets enabled */
.gen4_preset_vec = 0x340,
.n_fts = { 52, 80 },
.aspm_l1_enter_lat = 5,
};
static const struct of_device_id tegra_pcie_dw_of_match[] = {