NVIDIA: SAUCE: nvmem: Add Tegra efuse driver
Add Tegra efuse driver. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Kartik
Noah Wager
@@ -83,3 +83,5 @@ obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o
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nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o
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obj-$(CONFIG_NVMEM_QORIQ_EFUSE) += nvmem-qoriq-efuse.o
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nvmem-qoriq-efuse-y := qoriq-efuse.o
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obj-y += nvmem-tegra-efuse.o
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nvmem-tegra-efuse-y := tegra-efuse.o
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@@ -0,0 +1,334 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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struct tegra_efuse_soc {
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int size;
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const struct nvmem_cell_lookup *lookups;
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unsigned int num_lookups;
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const struct nvmem_cell_info *cells;
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unsigned int num_cells;
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const struct nvmem_keepout *keepouts;
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unsigned int num_keepouts;
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};
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struct tegra_efuse {
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void __iomem *base;
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struct nvmem_device *nvmem;
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const struct tegra_efuse_soc *soc;
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};
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static int tegra_efuse_readl(struct tegra_efuse *efuse, unsigned int offset)
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{
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return readl_relaxed(efuse->base + offset);
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}
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static int tegra_efuse_read(void *priv, unsigned int offset, void *value, size_t bytes)
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{
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unsigned int count = bytes / 4, i;
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struct tegra_efuse *efuse = priv;
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u32 *buffer = value;
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for (i = 0; i < count; i++)
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buffer[i] = tegra_efuse_readl(efuse, offset + i * 4);
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return 0;
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}
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static int tegra_efuse_probe(struct platform_device *pdev)
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{
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struct tegra_efuse *efuse;
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struct nvmem_config nvmem;
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struct resource *res;
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int id;
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id = of_alias_get_id(pdev->dev.of_node, "efuse");
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if (id < 0)
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return dev_err_probe(&pdev->dev, id, "failed to get alias id\n");
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efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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efuse->soc = device_get_match_data(&pdev->dev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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efuse->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(efuse->base))
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return PTR_ERR(efuse->base);
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platform_set_drvdata(pdev, efuse);
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memset(&nvmem, 0, sizeof(nvmem));
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nvmem.name = "efuse";
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nvmem.dev = &pdev->dev;
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nvmem.id = id;
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nvmem.owner = THIS_MODULE;
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nvmem.cells = efuse->soc->cells;
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nvmem.ncells = efuse->soc->num_cells;
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nvmem.keepout = efuse->soc->keepouts;
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nvmem.nkeepout = efuse->soc->num_keepouts;
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nvmem.type = NVMEM_TYPE_OTP;
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nvmem.read_only = true;
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nvmem.root_only = false;
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nvmem.reg_read = tegra_efuse_read;
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nvmem.size = efuse->soc->size;
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nvmem.word_size = 4;
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nvmem.stride = 4;
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nvmem.priv = efuse;
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efuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
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if (IS_ERR(efuse->nvmem))
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return dev_err_probe(&pdev->dev, PTR_ERR(efuse->nvmem),
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"failed to register NVMEM device\n");
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return 0;
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}
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static int tegra_efuse_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct nvmem_cell_info tegra264_efuse_cells[] = {
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{
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.name = "tsensor-cpu1",
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.offset = 0x084,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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},
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};
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static const struct nvmem_cell_lookup tegra264_efuse_lookups[] = {
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/* Sample Node */
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{
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.nvmem_name = "efuse0",
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.cell_name = "tensor-cpu1",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "cpu1",
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},
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};
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static const struct nvmem_keepout tegra264_efuse_keepouts[] = {
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{ .start = 0x00038, .end = 0x00050 },
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|
||||
{ .start = 0x1f04c, .end = 0x1f050 },
|
||||
};
|
||||
|
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static const struct tegra_efuse_soc tegra264_efuse_soc = {
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.cells = tegra264_efuse_cells,
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.num_cells = ARRAY_SIZE(tegra264_efuse_cells),
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.lookups = tegra264_efuse_lookups,
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.num_lookups = ARRAY_SIZE(tegra264_efuse_lookups),
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.keepouts = tegra264_efuse_keepouts,
|
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.num_keepouts = ARRAY_SIZE(tegra264_efuse_keepouts),
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||||
.size = 0x1f094,
|
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};
|
||||
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static const struct of_device_id tegra_efuse_of_match[] = {
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{ .compatible = "nvidia,tegra264-efuse", .data = &tegra264_efuse_soc },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, tegra_efuse_of_match);
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static struct platform_driver tegra_efuse_driver = {
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.driver = {
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.name = "tegra-efuse",
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.of_match_table = tegra_efuse_of_match,
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},
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.probe = tegra_efuse_probe,
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||||
.remove = tegra_efuse_remove,
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};
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module_platform_driver(tegra_efuse_driver);
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||||
|
||||
MODULE_LICENSE("GPL v2");
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@@ -3,6 +3,7 @@ obj-y += fuse/
|
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obj-y += cbb/
|
||||
|
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obj-y += common.o
|
||||
obj-y += tegra-soc.o
|
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obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
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obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
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obj-$(CONFIG_SOC_TEGRA_PMC) += tegra264-pmc.o
|
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|
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@@ -22,6 +22,8 @@ static const struct of_device_id tegra_machine_match[] = {
|
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{ .compatible = "nvidia,tegra124", },
|
||||
{ .compatible = "nvidia,tegra132", },
|
||||
{ .compatible = "nvidia,tegra210", },
|
||||
{ .compatible = "nvidia,tegra234", },
|
||||
{ .compatible = "nvidia,tegra264", },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
obj-y += fuse-tegra.o
|
||||
obj-y += fuse-tegra30.o
|
||||
obj-y += tegra-apbmisc.o
|
||||
obj-y += tegra-efuse-nvmem-helper.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += fuse-tegra20.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += speedo-tegra20.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += speedo-tegra30.o
|
||||
|
||||
@@ -35,19 +35,6 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
|
||||
[TEGRA_REVISION_A04] = "A04",
|
||||
};
|
||||
|
||||
static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
|
||||
[TEGRA_PLATFORM_SILICON] = "Silicon",
|
||||
[TEGRA_PLATFORM_QT] = "QT",
|
||||
[TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA",
|
||||
[TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA",
|
||||
[TEGRA_PLATFORM_ASIM_QT] = "Asim QT",
|
||||
[TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim",
|
||||
[TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",
|
||||
[TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",
|
||||
[TEGRA_PLATFORM_VDK] = "VDK",
|
||||
[TEGRA_PLATFORM_VSP] = "VSP",
|
||||
};
|
||||
|
||||
static const struct of_device_id car_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-car", },
|
||||
{ .compatible = "nvidia,tegra30-car", },
|
||||
@@ -278,6 +265,9 @@ u32 __init tegra_fuse_read_early(unsigned int offset)
|
||||
|
||||
int tegra_fuse_readl(unsigned long offset, u32 *value)
|
||||
{
|
||||
if (tegra_get_chip_id() == TEGRA264)
|
||||
return tegra_efuse_nvmem_readl(offset + 0x100, value);
|
||||
|
||||
if (!fuse->read || !fuse->clk)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
@@ -307,92 +297,6 @@ static void tegra_enable_fuse_clk(void __iomem *base)
|
||||
writel(reg, base + 0x14);
|
||||
}
|
||||
|
||||
static ssize_t major_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sprintf(buf, "%d\n", tegra_get_major_rev());
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(major);
|
||||
|
||||
static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sprintf(buf, "%d\n", tegra_get_minor_rev());
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(minor);
|
||||
|
||||
static struct attribute *tegra_soc_attr[] = {
|
||||
&dev_attr_major.attr,
|
||||
&dev_attr_minor.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
const struct attribute_group tegra_soc_attr_group = {
|
||||
.attrs = tegra_soc_attr,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
|
||||
IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
|
||||
static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
/*
|
||||
* Displays the value in the 'pre_si_platform' field of the HIDREV
|
||||
* register for Tegra194 devices. A value of 0 indicates that the
|
||||
* platform type is silicon and all other non-zero values indicate
|
||||
* the type of simulation platform is being used.
|
||||
*/
|
||||
return sprintf(buf, "%d\n", tegra_get_platform());
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(platform);
|
||||
|
||||
static struct attribute *tegra194_soc_attr[] = {
|
||||
&dev_attr_major.attr,
|
||||
&dev_attr_minor.attr,
|
||||
&dev_attr_platform.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
const struct attribute_group tegra194_soc_attr_group = {
|
||||
.attrs = tegra194_soc_attr,
|
||||
};
|
||||
#endif
|
||||
|
||||
struct device * __init tegra_soc_device_register(void)
|
||||
{
|
||||
struct soc_device_attribute *attr;
|
||||
struct soc_device *dev;
|
||||
|
||||
attr = kzalloc(sizeof(*attr), GFP_KERNEL);
|
||||
if (!attr)
|
||||
return NULL;
|
||||
|
||||
attr->family = kasprintf(GFP_KERNEL, "Tegra");
|
||||
if (tegra_is_silicon())
|
||||
attr->revision = kasprintf(GFP_KERNEL, "%s %s",
|
||||
tegra_platform_name[tegra_sku_info.platform],
|
||||
tegra_revision_name[tegra_sku_info.revision]);
|
||||
else
|
||||
attr->revision = kasprintf(GFP_KERNEL, "%s",
|
||||
tegra_platform_name[tegra_sku_info.platform]);
|
||||
attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
|
||||
attr->custom_attr_group = fuse->soc->soc_attr_group;
|
||||
|
||||
dev = soc_device_register(attr);
|
||||
if (IS_ERR(dev)) {
|
||||
kfree(attr->soc_id);
|
||||
kfree(attr->revision);
|
||||
kfree(attr->family);
|
||||
kfree(attr);
|
||||
return ERR_CAST(dev);
|
||||
}
|
||||
|
||||
return soc_device_to_device(dev);
|
||||
}
|
||||
|
||||
static int __init tegra_init_fuse(void)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
@@ -506,27 +410,3 @@ static int __init tegra_init_fuse(void)
|
||||
return 0;
|
||||
}
|
||||
early_initcall(tegra_init_fuse);
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
static int __init tegra_init_soc(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device *soc;
|
||||
|
||||
/* make sure we're running on Tegra */
|
||||
np = of_find_matching_node(NULL, tegra_fuse_match);
|
||||
if (!np)
|
||||
return 0;
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
soc = tegra_soc_device_register();
|
||||
if (IS_ERR(soc)) {
|
||||
pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
|
||||
return PTR_ERR(soc);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(tegra_init_soc);
|
||||
#endif
|
||||
|
||||
@@ -110,7 +110,6 @@ const struct tegra_fuse_soc tegra30_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra30_init_speedo_data,
|
||||
.info = &tegra30_fuse_info,
|
||||
.soc_attr_group = &tegra_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
@@ -126,7 +125,6 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra114_init_speedo_data,
|
||||
.info = &tegra114_fuse_info,
|
||||
.soc_attr_group = &tegra_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
@@ -286,7 +284,6 @@ const struct tegra_fuse_soc tegra124_fuse_soc = {
|
||||
.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
|
||||
.cells = tegra124_fuse_cells,
|
||||
.num_cells = ARRAY_SIZE(tegra124_fuse_cells),
|
||||
.soc_attr_group = &tegra_soc_attr_group,
|
||||
.clk_suspend_on = true,
|
||||
};
|
||||
#endif
|
||||
@@ -457,7 +454,6 @@ const struct tegra_fuse_soc tegra210_fuse_soc = {
|
||||
.cells = tegra210_fuse_cells,
|
||||
.num_cells = ARRAY_SIZE(tegra210_fuse_cells),
|
||||
.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
|
||||
.soc_attr_group = &tegra_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
@@ -516,7 +512,6 @@ const struct tegra_fuse_soc tegra186_fuse_soc = {
|
||||
.num_cells = ARRAY_SIZE(tegra186_fuse_cells),
|
||||
.keepouts = tegra186_fuse_keepouts,
|
||||
.num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts),
|
||||
.soc_attr_group = &tegra_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
@@ -609,7 +604,6 @@ const struct tegra_fuse_soc tegra194_fuse_soc = {
|
||||
.num_cells = ARRAY_SIZE(tegra194_fuse_cells),
|
||||
.keepouts = tegra194_fuse_keepouts,
|
||||
.num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts),
|
||||
.soc_attr_group = &tegra194_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
@@ -674,7 +668,6 @@ const struct tegra_fuse_soc tegra234_fuse_soc = {
|
||||
.num_cells = ARRAY_SIZE(tegra234_fuse_cells),
|
||||
.keepouts = tegra234_fuse_keepouts,
|
||||
.num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts),
|
||||
.soc_attr_group = &tegra194_soc_attr_group,
|
||||
.clk_suspend_on = false,
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -37,8 +37,6 @@ struct tegra_fuse_soc {
|
||||
const struct nvmem_keepout *keepouts;
|
||||
unsigned int num_keepouts;
|
||||
|
||||
const struct attribute_group *soc_attr_group;
|
||||
|
||||
bool clk_suspend_on;
|
||||
};
|
||||
|
||||
@@ -72,6 +70,7 @@ void tegra_init_apbmisc(void);
|
||||
|
||||
u32 __init tegra_fuse_read_spare(unsigned int spare);
|
||||
u32 __init tegra_fuse_read_early(unsigned int offset);
|
||||
int tegra_efuse_nvmem_readl(unsigned long offset, u32 *value);
|
||||
|
||||
u8 tegra_get_major_rev(void);
|
||||
u8 tegra_get_minor_rev(void);
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/nvmem-consumer.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
struct tegra_efuse_nvmem_helper {
|
||||
struct device *dev;
|
||||
struct nvmem_device *ndev;
|
||||
} efuse_helper;
|
||||
|
||||
int tegra_efuse_nvmem_readl(unsigned long offset, u32 *value)
|
||||
{
|
||||
int num_bytes_read;
|
||||
|
||||
if (IS_ERR_OR_NULL(efuse_helper.ndev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
num_bytes_read = nvmem_device_read(efuse_helper.ndev, offset, 4, value);
|
||||
if (num_bytes_read < 0)
|
||||
return num_bytes_read;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_efuse_nvmem_helper_probe(struct platform_device *pdev)
|
||||
{
|
||||
efuse_helper.dev = &pdev->dev;
|
||||
|
||||
efuse_helper.ndev = devm_nvmem_device_get(&pdev->dev, "efuse");
|
||||
if (IS_ERR(efuse_helper.ndev))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(efuse_helper.ndev),
|
||||
"failed to get alias id\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_efuse_nvmem_helper_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra_efuse_nvmem_helper_match[] = {
|
||||
{ .compatible = "nvidia,efuse-nvmem-helper", },
|
||||
{ /* Sentinel. */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_efuse_nvmem_helper_match);
|
||||
|
||||
static struct platform_driver tegra_efuse_nvmem_helper_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-efuse-nvmem-helper",
|
||||
.of_match_table = tegra_efuse_nvmem_helper_match,
|
||||
},
|
||||
.probe = tegra_efuse_nvmem_helper_probe,
|
||||
.remove = tegra_efuse_nvmem_helper_remove,
|
||||
};
|
||||
module_platform_driver(tegra_efuse_nvmem_helper_driver);
|
||||
@@ -0,0 +1,202 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include <soc/tegra/common.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#define TEGRA_SOC_MAJOR_REV_SHIFT 4
|
||||
#define TEGRA_SOC_MAJOR_REV_MASK 0xf
|
||||
#define TEGRA_SOC_ID_SHIFT 8
|
||||
#define TEGRA_SOC_ID_MASK 0xff
|
||||
#define TEGRA_SOC_MINOR_REV_SHIFT 16
|
||||
#define TEGRA_SOC_MINOR_REV_MASK 0xf
|
||||
#define TEGRA_SOC_PLATFORM_SHIFT 20
|
||||
#define TEGRA_SOC_PLATFORM_MASK 0xf
|
||||
|
||||
enum tegra_soc_revision {
|
||||
TEGRA_SOC_REVISION_0 = 0,
|
||||
TEGRA_SOC_REVISION_1,
|
||||
TEGRA_SOC_REVISION_2,
|
||||
TEGRA_SOC_REVISION_3,
|
||||
TEGRA_SOC_REVISION_4,
|
||||
TEGRA_SOC_REVISION_5,
|
||||
TEGRA_SOC_REVISION_6,
|
||||
TEGRA_SOC_REVISION_7,
|
||||
TEGRA_SOC_REVISION_8,
|
||||
TEGRA_SOC_REVISION_9,
|
||||
TEGRA_SOC_REVISION_10,
|
||||
TEGRA_SOC_REVISION_11,
|
||||
TEGRA_SOC_REVISION_12,
|
||||
TEGRA_SOC_REVISION_13,
|
||||
TEGRA_SOC_REVISION_14,
|
||||
TEGRA_SOC_REVISION_15,
|
||||
TEGRA_SOC_REVISION_MAX,
|
||||
};
|
||||
|
||||
enum tegra_soc_platform {
|
||||
TEGRA_SOC_PLATFORM_SILICON = 0,
|
||||
TEGRA_SOC_PLATFORM_QT,
|
||||
TEGRA_SOC_PLATFORM_SYSTEM_FPGA,
|
||||
TEGRA_SOC_PLATFORM_UNIT_FPGA,
|
||||
TEGRA_SOC_PLATFORM_ASIM_QT,
|
||||
TEGRA_SOC_PLATFORM_ASIM_LINSIM,
|
||||
TEGRA_SOC_PLATFORM_DSIM_ASIM_LINSIM,
|
||||
TEGRA_SOC_PLATFORM_VERIFICATION_SIMULATION,
|
||||
TEGRA_SOC_PLATFORM_VDK,
|
||||
TEGRA_SOC_PLATFORM_VSP,
|
||||
TEGRA_SOC_PLATFORM_MAX,
|
||||
};
|
||||
|
||||
static const char *tegra_soc_revision_name[TEGRA_SOC_REVISION_MAX] = {
|
||||
[TEGRA_SOC_REVISION_0] = "unknown",
|
||||
[TEGRA_SOC_REVISION_1] = "A01",
|
||||
[TEGRA_SOC_REVISION_2] = "A02",
|
||||
[TEGRA_SOC_REVISION_3] = "A03",
|
||||
[TEGRA_SOC_REVISION_4] = "unknown",
|
||||
[TEGRA_SOC_REVISION_5] = "B01",
|
||||
[TEGRA_SOC_REVISION_6] = "B02",
|
||||
[TEGRA_SOC_REVISION_7] = "B03",
|
||||
[TEGRA_SOC_REVISION_8] = "unknown",
|
||||
[TEGRA_SOC_REVISION_9] = "C01",
|
||||
[TEGRA_SOC_REVISION_10] = "C02",
|
||||
[TEGRA_SOC_REVISION_11] = "C03",
|
||||
[TEGRA_SOC_REVISION_12] = "unknown",
|
||||
[TEGRA_SOC_REVISION_13] = "D01",
|
||||
[TEGRA_SOC_REVISION_14] = "D02",
|
||||
[TEGRA_SOC_REVISION_15] = "D03",
|
||||
};
|
||||
|
||||
static const char *tegra_soc_platform_name[TEGRA_SOC_PLATFORM_MAX] = {
|
||||
[TEGRA_SOC_PLATFORM_SILICON] = "Silicon",
|
||||
[TEGRA_SOC_PLATFORM_QT] = "QT",
|
||||
[TEGRA_SOC_PLATFORM_SYSTEM_FPGA] = "System FPGA",
|
||||
[TEGRA_SOC_PLATFORM_UNIT_FPGA] = "Unit FPGA",
|
||||
[TEGRA_SOC_PLATFORM_ASIM_QT] = "Asim QT",
|
||||
[TEGRA_SOC_PLATFORM_ASIM_LINSIM] = "Asim Linsim",
|
||||
[TEGRA_SOC_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",
|
||||
[TEGRA_SOC_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",
|
||||
[TEGRA_SOC_PLATFORM_VDK] = "VDK",
|
||||
[TEGRA_SOC_PLATFORM_VSP] = "VSP",
|
||||
};
|
||||
|
||||
static ssize_t major_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
int major_rev;
|
||||
|
||||
major_rev = (tegra_read_chipid() >> TEGRA_SOC_MAJOR_REV_SHIFT) & TEGRA_SOC_MAJOR_REV_MASK;
|
||||
return sprintf(buf, "%d\n", major_rev);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(major);
|
||||
|
||||
static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
int minor_rev;
|
||||
|
||||
minor_rev = (tegra_read_chipid() >> TEGRA_SOC_MINOR_REV_SHIFT) & TEGRA_SOC_MINOR_REV_SHIFT;
|
||||
return sprintf(buf, "%d\n", minor_rev);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(minor);
|
||||
|
||||
static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
return sprintf(buf, "%d\n", tegra_get_platform());
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(platform);
|
||||
|
||||
static struct attribute *tegra_soc_custom_attr[] = {
|
||||
&dev_attr_major.attr,
|
||||
&dev_attr_minor.attr,
|
||||
&dev_attr_platform.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
const struct attribute_group tegra_soc_custom_attr_group = {
|
||||
.attrs = tegra_soc_custom_attr,
|
||||
};
|
||||
|
||||
static struct soc_device_attribute *tegra_soc_attr;
|
||||
static struct soc_device *tegra_soc_dev;
|
||||
|
||||
static int __init tegra_soc_init(void)
|
||||
{
|
||||
u32 miscreg = 0;
|
||||
u8 platform;
|
||||
u8 revision;
|
||||
u32 soc_id;
|
||||
|
||||
/* Return if not running on Tegra. */
|
||||
if (!soc_is_tegra())
|
||||
return 0;
|
||||
|
||||
miscreg = tegra_read_chipid();
|
||||
if (!miscreg)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
platform = (miscreg >> TEGRA_SOC_PLATFORM_SHIFT) & TEGRA_SOC_PLATFORM_MASK;
|
||||
revision = (miscreg >> TEGRA_SOC_MINOR_REV_SHIFT) & TEGRA_SOC_MINOR_REV_MASK;
|
||||
|
||||
/*
|
||||
* FIXME: From Tegra234 onwards the SOC_ID consists of CHIP_ID + Major revision.
|
||||
* So, soc_id should be (miscreg >> 4) & 0xfff, but most of the userspace
|
||||
* applications and tests are written with an assumption that SOC_ID = CHIP_ID.
|
||||
* This causes failures while identifying platforms from those userspace
|
||||
* applications.
|
||||
*
|
||||
* For now, keep soc_id as (miscreg >> 8) & 0xff, until the userspace
|
||||
* applications are patched.
|
||||
*/
|
||||
soc_id = (miscreg >> TEGRA_SOC_ID_SHIFT) & TEGRA_SOC_ID_MASK;
|
||||
|
||||
tegra_soc_attr = kzalloc(sizeof(*tegra_soc_attr), GFP_KERNEL);
|
||||
if (!tegra_soc_attr)
|
||||
return -EINVAL;
|
||||
|
||||
tegra_soc_attr->family = kasprintf(GFP_KERNEL, "Tegra");
|
||||
if (tegra_is_silicon())
|
||||
tegra_soc_attr->revision = kasprintf(GFP_KERNEL, "%s %s",
|
||||
tegra_soc_platform_name[platform],
|
||||
tegra_soc_revision_name[revision]);
|
||||
else
|
||||
tegra_soc_attr->revision = kasprintf(GFP_KERNEL, "%s",
|
||||
tegra_soc_platform_name[platform]);
|
||||
|
||||
/*
|
||||
* FIXME: Use hex value for SOC_ID as it is the most widely used notation
|
||||
* for identifying chips.
|
||||
*
|
||||
* Fixing this would require patching all the userspace applications
|
||||
* relying on SOC_ID.
|
||||
*/
|
||||
tegra_soc_attr->soc_id = kasprintf(GFP_KERNEL, "%u", soc_id);
|
||||
tegra_soc_attr->custom_attr_group = &tegra_soc_custom_attr_group;
|
||||
|
||||
tegra_soc_dev = soc_device_register(tegra_soc_attr);
|
||||
if (IS_ERR(tegra_soc_dev)) {
|
||||
kfree(tegra_soc_attr->soc_id);
|
||||
kfree(tegra_soc_attr->revision);
|
||||
kfree(tegra_soc_attr->family);
|
||||
kfree(tegra_soc_attr);
|
||||
|
||||
return PTR_ERR(tegra_soc_dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(tegra_soc_init);
|
||||
|
||||
static void __exit tegra_soc_exit(void)
|
||||
{
|
||||
soc_device_unregister(tegra_soc_dev);
|
||||
|
||||
kfree(tegra_soc_attr->soc_id);
|
||||
kfree(tegra_soc_attr->revision);
|
||||
kfree(tegra_soc_attr->family);
|
||||
kfree(tegra_soc_attr);
|
||||
}
|
||||
module_exit(tegra_soc_exit);
|
||||
Reference in New Issue
Block a user