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Merge tag 'keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt

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Pull "Keystone dts updates for 3.19" from Santosh Shilimkar:

	- PCIE controller related updates
	- 1GBe phy related upates

* tag 'keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1
  ARM: dts: keystone: add DT bindings for PCI controller for port 0
  ARM: dts: k2l-evm: add 1g ethernet phys nodes
  ARM: dts: k2e-evm: add 1g ethernet phys nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2014-11-20 13:20:37 +01:00
parent 0924a4254e fc89a57600
commit 9e64b2a421
4 changed files with 114 additions and 0 deletions
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arch/arm/boot/dts/k2e-evm.dts
+12
View File
@@ -139,3 +139,15 @@
};
};
};
&mdio {
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
arch/arm/boot/dts/k2e.dtsi
+45
View File
@@ -85,6 +85,51 @@
#gpio-cells = <2>;
gpio,syscon-dev = <&devctrl 0x240>;
};
pcie@21020000 {
compatible = "ti,keystone-pcie","snps,dw-pcie";
clocks = <&clkpcie1>;
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
device_type = "pci";
num-lanes = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
<0 0 0 2 &pcie_intc1 1>, /* INT B */
<0 0 0 3 &pcie_intc1 2>, /* INT C */
<0 0 0 4 &pcie_intc1 3>; /* INT D */
pcie_msi_intc1: msi-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
};
pcie_intc1: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
};
};
};
};
arch/arm/boot/dts/k2l-evm.dts
+12
View File
@@ -116,3 +116,15 @@
};
};
};
&mdio {
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
arch/arm/boot/dts/keystone.dtsi
+45
View File
@@ -285,5 +285,50 @@
#interrupt-cells = <1>;
ti,syscon-dev = <&devctrl 0x2a0>;
};
pcie@21800000 {
compatible = "ti,keystone-pcie", "snps,dw-pcie";
clocks = <&clkpcie>;
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
ranges = <0x81000000 0 0 0x23250000 0 0x4000
0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
device_type = "pci";
num-lanes = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
<0 0 0 2 &pcie_intc0 1>, /* INT B */
<0 0 0 3 &pcie_intc0 2>, /* INT C */
<0 0 0 4 &pcie_intc0 3>; /* INT D */
pcie_msi_intc0: msi-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
};
pcie_intc0: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
};
};
};
};