NVIDIA: SAUCE: scsi:ufs: Change the power sequence to LSx1->LSx2->HSx2

BugLink: https://bugs.launchpad.net/bugs/2080908

Change the power sequence to LSx1->LSx2->HSx2

http://nvbugs/4763966

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
[nwager: The parent upstream stable commit
195118ada3 ("scsi: ufs: core: Add missing post notify for power mode change")
removes a ufshcd_vops_pwr_change_notify() call which caused a conflict
with the original SAUCE patch. As per the original SAUCE author, the
affected if-else block can still be overwritten as if that line wasn't
there, thus resolving the conflict.]
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Mallikarjun Kasoju
2024-08-16 09:22:55 +00:00
committed by Noah Wager
parent aa5d160643
commit 8ba5e88683
2 changed files with 43 additions and 14 deletions
+38 -14
View File
@@ -4601,7 +4601,27 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
* - PA_HSSERIES
*/
if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE)) {
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
pwr_mode->lane_rx);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
pwr_mode->lane_tx);
/* Lane change is triggered */
ret = ufshcd_uic_change_pwr_mode(hba, (SLOWAUTO_MODE << 4
| SLOWAUTO_MODE));
if (ret) {
dev_err(hba->dev,
"%s: lane change failed %d\n", __func__, ret);
goto out;
}
ufshcd_dme_configure_adapt(hba, pwr_mode->gear_rx, PA_INITIAL_ADAPT);
}
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE))
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
pwr_mode->lane_tx);
if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
pwr_mode->pwr_rx == FAST_MODE)
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
@@ -4653,23 +4673,27 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
return ret;
}
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
pwr_mode->lane_rx);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
pwr_mode->lane_tx);
if (hba->quirks & UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE) {
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
pwr_mode->lane_rx);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
pwr_mode->lane_tx);
ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
| pwr_mode->pwr_tx);
ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
| pwr_mode->pwr_tx);
if (ret) {
dev_err(hba->dev,
"%s: Lane change failed %d\n", __func__, ret);
} else {
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
if (ret)
dev_err(hba->dev,
"%s: Lane change failed %d\n", __func__, ret);
}
return ret;
out:
if (!ret) {
ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
pwr_mode);
memcpy(&hba->pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
return ret;
}
/**
+5
View File
@@ -640,6 +640,11 @@ enum ufshcd_quirks {
* thus need this quirk to skip related flow.
*/
UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
/*
* Enable this quirk to enable gear shift first
*/
UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE = 1 << 22,
};
enum ufshcd_caps {