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drm/bridge: it6505: update usleep_range for RC circuit charge time

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BugLink: https://bugs.launchpad.net/bugs/2102118

[ Upstream commit 8814444e62b8a8b573fba2cbbb327d5817b74eb0 ]

The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
circuit need at least 25ms for rising time, update for match spec

Signed-off-by: Kuro Chung <kuro.chung@ite.com.tw>
Signed-off-by: Hermes Wu <hermes.wu@ite.com.tw>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240604024405.1122488-1-kuro.chung@ite.com.tw
Stable-dep-of: c5f3f21728b0 ("drm/bridge: it6505: Fix inverted reset polarity")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Koichiro Den <koichiro.den@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
Kuro Chung
2025-03-12 22:51:00 +09:00
committed by Stefan Bader
parent b71f8593fa
commit 8910b73278
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/bridge/ite-it6505.c
+1 -1
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@@ -2614,7 +2614,7 @@ static int it6505_poweron(struct it6505 *it6505)
gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
usleep_range(1000, 2000);
gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
usleep_range(10000, 20000);
usleep_range(25000, 35000);
}
it6505->powered = true;