NVIDIA: SAUCE: ASoC: tegra: Tegra264 support in isomgr_bw
Tegra264 support max 32 channels, hence calculating the max bandwidth using the channel info from soc_data. http://nvbugs/4453712 Signed-off-by: Sheetal <sheetal@nvidia.com> Reviewed-by: Mohan kumar <mkumard@nvidia.com> Reviewed-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Vishwaroop A <va@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
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@@ -11,8 +11,8 @@
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#include "tegra_isomgr_bw.h"
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#include "tegra210_admaif.h"
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/* Max possible rate is 192KHz x 16channel x 4bytes */
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#define MAX_BW_PER_DEV 12288
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#define MAX_SAMPLE_RATE 192 /* KHz*/
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#define MAX_BYTES_PER_SAMPLE 4
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int tegra_isomgr_adma_setbw(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai, bool is_running)
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@@ -98,7 +98,8 @@ int tegra_isomgr_adma_register(struct device *dev)
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}
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adma_isomgr->max_pcm_device = admaif->soc_data->num_ch;
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adma_isomgr->max_bw = STREAM_TYPE * MAX_BW_PER_DEV * adma_isomgr->max_pcm_device;
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adma_isomgr->max_bw = STREAM_TYPE * MAX_SAMPLE_RATE * MAX_BYTES_PER_SAMPLE *
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admaif->soc_data->max_ch * adma_isomgr->max_pcm_device;
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for (i = 0; i < STREAM_TYPE; i++) {
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adma_isomgr->bw_per_dev[i] = devm_kzalloc(dev, adma_isomgr->max_pcm_device *
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