drm/xe: Set mask bits for CCS_MODE register
BugLink: https://bugs.launchpad.net/bugs/2100292 commit 7fd3fa006fa56c0ec299c61ecf5c572c723adad5 upstream. CCS_MODE register requires setting mask bits from Xe2+ platforms. Set the mask bits unconditionally, as those bits are unused for older platforms. Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Cc: stable@vger.kernel.org # v6.11+ Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241008073628.377433-2-balasubramani.vivekanandan@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> (cherry picked from commit 23ea2c7572d4735ef66beb1e4feb8ae510b78247) [ Fix conflict with mmio refactors ] Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Koichiro Den <koichiro.den@canonical.com> Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
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Stefan Bader
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116e1efd81
commit
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@@ -394,7 +394,7 @@
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* [4-6] RSVD
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* [7] Disabled
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*/
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#define CCS_MODE XE_REG(0x14804)
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#define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED)
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#define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */
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#define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */
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#define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1)
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@@ -66,6 +66,12 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
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}
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}
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/*
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* Mask bits need to be set for the register. Though only Xe2+
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* platforms require setting of mask bits, it won't harm for older
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* platforms as these bits are unused there.
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*/
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mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
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xe_mmio_write32(gt, CCS_MODE, mode);
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xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
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