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arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes

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BugLink: https://bugs.launchpad.net/bugs/2089340

[ Upstream commit ec9532628eb9d82282b8e52fd9c4a3800d87feec ]

The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.

Despite the RZ/G3S SoC being single-core, it has two instances of GICR.

Fixes: e20396d65b ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Portia Stephens <portia.stephens@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
Lad Prabhakar
2024-07-30 13:24:33 +01:00
committed by Mehmet Basaran
parent 3684efdefe
commit 6db2938036
1 changed files with 2 additions and 2 deletions
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arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+2 -2
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@@ -264,8 +264,8 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x12400000 0 0x40000>,
<0x0 0x12440000 0 0x60000>;
reg = <0x0 0x12400000 0 0x20000>,
<0x0 0x12440000 0 0x40000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};