RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation
BugLink: https://bugs.launchpad.net/bugs/2101915 [ Upstream commit 60821fb4dd7345e5662094accf0a52845306de8c ] In the section "4.7 Precise effects on interrupt-pending bits" of the RISC-V AIA specification defines that: "If the source mode is Level1 or Level0 and the interrupt domain is configured in MSI delivery mode (domaincfg.DM = 1): The pending bit is cleared whenever the rectified input value is low, when the interrupt is forwarded by MSI, or by a relevant write to an in_clrip register or to clripnum." Update the aplic_write_pending() to match the spec. Fixes: d8dd9f113e16 ("RISC-V: KVM: Fix APLIC setipnum_le/be write emulation") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20241029085542.30541-1-yongxuan.wang@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Koichiro Den <koichiro.den@canonical.com> Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
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Stefan Bader
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@@ -143,7 +143,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
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if (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH ||
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sm == APLIC_SOURCECFG_SM_LEVEL_LOW) {
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if (!pending)
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goto skip_write_pending;
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goto noskip_write_pending;
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if ((irqd->state & APLIC_IRQ_STATE_INPUT) &&
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sm == APLIC_SOURCECFG_SM_LEVEL_LOW)
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goto skip_write_pending;
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@@ -152,6 +152,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
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goto skip_write_pending;
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}
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noskip_write_pending:
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if (pending)
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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else
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