NVIDIA: SAUCE: aquantia: issue PHY reset during phy init

BugLink: https://bugs.launchpad.net/bugs/2072591

issue: The AQR113C is not able to pick up 50MHz Xtal as clock
source at the time of power on reset which inturn failing
to initialize the PHY and hence the link is not coming up

As a SW WAR reset the PHY during initialization so that
PHY reinitialized and link gets detected.

http://nvbugs/4267033
http://nvbugs/4283052

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Signed-off-by: Satish Seelamsetti <sseelamsetti@nvidia.com>
Reviewed-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>

drivers/net/phy/aquantia/aquantia_main.c

@@ -5,7 +5,7 @@
  * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
  *
  * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2021-2024, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -176,6 +176,9 @@
 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
 
+#define VEND1_GLOBAL_CMN_POR_CTRL	0x2681U
+#define PHY_RESET			BIT(0)
+
 /* Sleep and timeout for checking if the Processor-Intensive
  * MDIO operation is finished
  */
@@ -795,6 +798,11 @@ static int aqr107_config_init(struct phy_device *phydev)
 	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
 	     "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
 
+	/* SW WAR to reset PHY again to overcome link issues caused during boot */
+	err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CMN_POR_CTRL, PHY_RESET);
+	if (err < 0)
+		return err;
+
 	ret = aqr107_wait_reset_complete(phydev);
 	if (!ret)
 		aqr107_chip_info(phydev);