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NVIDIA: SAUCE: usb: gadget: tegra-xudc: Increase tPortConfiguration timeout

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The default tPortConfiguration timeout is too small.
Enlarge the timeout configuration to ensure better reliability.

http://nvbugs/4786323

Signed-off-by: Wayne Chang <waynec@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: HaoTien Hsu <haotienh@nvidia.com>
Signed-off-by: Vishwaroop A <va@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Wayne Chang
2024-09-03 09:04:19 +00:00
committed by Noah Wager
parent 32f8cbb802
commit 5094618371
1 changed files with 20 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/usb/gadget/udc/tegra-xudc.c
+20 -4
View File
@@ -146,10 +146,6 @@
#define SSPX_CORE_CNT0 0x610
#define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0)
#define SSPX_CORE_CNT0_PING_TBURST(x) ((x) & SSPX_CORE_CNT0_PING_TBURST_MASK)
#define SSPX_CORE_CNT30 0x688
#define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0)
#define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \
SSPX_CORE_CNT30_LMPITP_TIMER_MASK)
#define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0)
#define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \
SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK)
@@ -3492,11 +3488,18 @@ static void tegra186_xudc_device_params_init(struct tegra_xudc *xudc)
val |= SSPX_CORE_CNT0_PING_TBURST(0xa);
xudc_writel(xudc, val, SSPX_CORE_CNT0);
#define SSPX_CORE_CNT30 0x688
#define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0)
#define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \
SSPX_CORE_CNT30_LMPITP_TIMER_MASK)
/* Default tPortConfiguration timeout is too small. */
val = xudc_readl(xudc, SSPX_CORE_CNT30);
val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK);
val |= SSPX_CORE_CNT30_LMPITP_TIMER(0x978);
xudc_writel(xudc, val, SSPX_CORE_CNT30);
#undef SSPX_CORE_CNT30
#undef SSPX_CORE_CNT30_LMPITP_TIMER_MASK
#undef SSPX_CORE_CNT30_LMPITP_TIMER
/*
* Compliance suite appears to be violating polling
@@ -3528,6 +3531,19 @@ static void tegra264_xudc_device_params_init(struct tegra_xudc *xudc)
val |= SSPX_CORE_CNT13_CRDTHP_TIMER(0x33);
xudc_writel(xudc, val, SSPX_CORE_CNT13);
#define SSPX_CORE_CNT30 0x4088
#define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(11, 0)
#define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \
SSPX_CORE_CNT30_LMPITP_TIMER_MASK)
/* Default tPortConfiguration timeout is too small. */
val = xudc_readl(xudc, SSPX_CORE_CNT30);
val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK);
val |= SSPX_CORE_CNT30_LMPITP_TIMER(0xc9);;
xudc_writel(xudc, val, SSPX_CORE_CNT30);
#undef SSPX_CORE_CNT30
#undef SSPX_CORE_CNT30_LMPITP_TIMER_MASK
#undef SSPX_CORE_CNT30_LMPITP_TIMER
#define SSPX_CORE_CNT32 0x4090
/*
* Compliance suite appears to be violating polling