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clk: renesas: r8a779g0: Fix PCIe clock name

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BugLink: https://bugs.launchpad.net/bugs/2060097

[ Upstream commit 096311157d2a6bb8f06e28e1143e2a5de6a0183b ]

Fix a typo in the name of the module clock for the second PCIe channel.

Fixes: 5ab16198b4 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit 57ba901242123cbb0966aa842ce712e1d4072f9e)
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
This commit is contained in:
Geert Uytterhoeven
2024-01-30 10:47:49 +01:00
committed by Roxana Nicolescu
parent 7adead5d2a
commit 3bf07e2a43
1 changed files with 1 additions and 1 deletions
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drivers/clk/renesas/r8a779g0-cpg-mssr.c
+1 -1
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@@ -193,7 +193,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pscie1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pciec1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),