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NVIDIA: SAUCE: spi: spi-tegra114: retain the spi mode

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BugLink: https://bugs.launchpad.net/bugs/2080908

Retain the spi mode in def_command1 register
after transfer completion.

http://nvbugs/4204673

Signed-off-by: Vishwaroop A <va@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Vishwaroop A
2023-08-14 20:33:31 +00:00
committed by Noah Wager
parent 54fdbc8a4c
commit 2ca6c5cd4a
1 changed files with 11 additions and 1 deletions
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drivers/spi/spi-tegra114.c
+11 -1
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@@ -57,6 +57,7 @@
#define SPI_CONTROL_MODE_3 (3 << 28)
#define SPI_CONTROL_MODE_MASK (3 << 28)
#define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
#define SPI_MODE_VAL(x) (((x) >> 28) & 0x3)
#define SPI_M_S (1 << 30)
#define SPI_PIO (1 << 31)
@@ -205,6 +206,7 @@ struct tegra_spi_data {
u32 spi_cs_timing1;
u32 spi_cs_timing2;
u8 last_used_cs;
u8 def_chip_select;
struct completion xfer_completion;
struct spi_transfer *curr_xfer;
@@ -827,7 +829,9 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
tspi->cs_control = NULL;
} else
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
if (SPI_MODE_VAL(command1) !=
SPI_MODE_VAL(tspi->def_command1_reg))
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
/* GPIO based chip select control */
if (spi_get_csgpiod(spi, 0))
@@ -987,6 +991,8 @@ static int tegra_spi_setup(struct spi_device *spi)
val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
else
val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
if (tspi->def_chip_select == spi_get_chipselect(spi, 0))
val |= SPI_MODE_SEL(spi->mode & 0x3);
tspi->def_command1_reg = val;
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
spin_unlock_irqrestore(&tspi->lock, flags);
@@ -1341,6 +1347,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
goto exit_free_host;
}
tspi->def_chip_select = 0;
tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(tspi->base)) {
ret = PTR_ERR(tspi->base);
@@ -1400,6 +1408,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
reset_control_assert(tspi->rst);
udelay(2);
reset_control_deassert(tspi->rst);
tspi->def_command1_reg = tegra_spi_readl(tspi, SPI_COMMAND1);
tspi->def_command1_reg |= SPI_CS_SEL(tspi->def_chip_select);
tspi->def_command1_reg = SPI_M_S;
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);