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drm/amd/pm: print pp_dpm_mclk in ascending order on SMU v14.0.0

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BugLink: https://bugs.launchpad.net/bugs/2101042

commit df0279e2a1c0735e8ca80c5df8d9f8f9fc120b4a upstream.

Currently, the pp_dpm_mclk values are reported in descending order
on SMU IP v14.0.0/1/4. Adjust to ascending order for consistency
with other clock interfaces.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit d4be16ccfd5bf822176740a51ff2306679a2247e)
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Manuel Diewald <manuel.diewald@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
Tim Huang
2024-10-28 13:51:50 +08:00
committed by Stefan Bader
parent 10ee6c6e88
commit 1cd1e12164
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+3 -2
View File
@@ -836,7 +836,7 @@ static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu,
static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
int i, size = 0, ret = 0;
int i, idx, ret = 0, size = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min, max;
@@ -870,7 +870,8 @@ static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
break;
for (i = 0; i < count; i++) {
ret = smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
ret = smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, idx, &value);
if (ret)
break;