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@@ -8,6 +8,7 @@
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#include "ps.h"
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#include "debug.h"
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#include "reg.h"
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#include "phy.h"
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static u8 rtw_coex_next_rssi_state(struct rtw_dev *rtwdev, u8 pre_state,
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u8 rssi, u8 rssi_thresh)
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@@ -349,6 +350,10 @@ static void rtw_coex_check_rfk(struct rtw_dev *rtwdev)
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if (!btk && !wlk)
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break;
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rtw_dbg(rtwdev, RTW_DBG_COEX,
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"[BTCoex], (Before Ant Setup) wlk = %d, btk = %d\n",
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wlk, btk);
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mdelay(COEX_MIN_DELAY);
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} while (++cnt < wait_cnt);
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@@ -1054,7 +1059,8 @@ static void rtw_coex_tdma(struct rtw_dev *rtwdev, bool force, u32 tcase)
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coex_dm->cur_ps_tdma_on = turn_on;
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coex_dm->cur_ps_tdma = type;
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rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], coex tdma type (%d)\n", type);
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rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], coex tdma type(%s, %d)\n",
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turn_on ? "on" : "off", type);
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}
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static void rtw_coex_set_ant_path(struct rtw_dev *rtwdev, bool force, u8 phase)
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@@ -3016,6 +3022,81 @@ static const char *rtw_coex_get_reason_string(u8 reason)
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}
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}
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static u8 rtw_coex_get_table_index(struct rtw_dev *rtwdev, u32 wl_reg_6c0,
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u32 wl_reg_6c4)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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struct rtw_efuse *efuse = &rtwdev->efuse;
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u8 ans = 0xFF;
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u8 n, i;
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u32 load_bt_val;
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u32 load_wl_val;
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bool share_ant = efuse->share_ant;
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if (share_ant)
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n = chip->table_sant_num;
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else
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n = chip->table_nsant_num;
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for (i = 0; i < n; i++) {
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if (share_ant) {
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load_bt_val = chip->table_sant[i].bt;
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load_wl_val = chip->table_sant[i].wl;
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} else {
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load_bt_val = chip->table_nsant[i].bt;
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load_wl_val = chip->table_nsant[i].wl;
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}
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if (wl_reg_6c0 == load_bt_val &&
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wl_reg_6c4 == load_wl_val) {
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ans = i;
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if (!share_ant)
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ans += 100;
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break;
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}
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}
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return ans;
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}
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static u8 rtw_coex_get_tdma_index(struct rtw_dev *rtwdev, u8 *tdma_para)
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{
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struct rtw_efuse *efuse = &rtwdev->efuse;
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struct rtw_chip_info *chip = rtwdev->chip;
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u8 ans = 0xFF;
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u8 n, i, j;
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u8 load_cur_tab_val;
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bool valid = false;
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bool share_ant = efuse->share_ant;
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if (share_ant)
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n = chip->tdma_sant_num;
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else
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n = chip->tdma_nsant_num;
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for (i = 0; i < n; i++) {
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valid = false;
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for (j = 0; j < 5; j++) {
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if (share_ant)
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load_cur_tab_val = chip->tdma_sant[i].para[j];
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else
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load_cur_tab_val = chip->tdma_nsant[i].para[j];
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if (*(tdma_para + j) != load_cur_tab_val)
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break;
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if (j == 4)
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valid = true;
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}
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if (valid) {
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ans = i;
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break;
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}
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}
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return ans;
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}
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static int rtw_coex_addr_info(struct rtw_dev *rtwdev,
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const struct rtw_reg_domain *reg,
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char addr_info[], int n)
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@@ -3305,6 +3386,13 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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bt_lo_pri = rtw_read32(rtwdev, REG_BT_ACT_STATISTICS_1);
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rtw_write8(rtwdev, REG_BT_COEX_ENH_INTR_CTRL,
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BIT_R_GRANTALL_WLMASK | BIT_STATIS_BT_EN);
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coex_stat->hi_pri_tx = FIELD_GET(MASKLWORD, bt_hi_pri);
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coex_stat->hi_pri_rx = FIELD_GET(MASKHWORD, bt_hi_pri);
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coex_stat->lo_pri_tx = FIELD_GET(MASKLWORD, bt_lo_pri);
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coex_stat->lo_pri_rx = FIELD_GET(MASKHWORD, bt_lo_pri);
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sys_lte = rtw_read8(rtwdev, 0x73);
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lte_coex = rtw_coex_read_indirect_reg(rtwdev, 0x38);
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bt_coex = rtw_coex_read_indirect_reg(rtwdev, 0x54);
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@@ -3356,15 +3444,17 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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coex_stat->bt_slave ? "Slave" : "Master",
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coex_stat->cnt_bt[COEX_CNT_BT_ROLESWITCH],
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coex_dm->ignore_wl_act);
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seq_printf(m, "%-40s = %u.%u/ 0x%x/ %c\n",
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"WL FW/ BT FW/ KT",
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seq_printf(m, "%-40s = %u.%u/ 0x%x/ 0x%x/ %c\n",
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"WL FW/ BT FW/ BT FW Desired/ KT",
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fw->version, fw->sub_version,
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coex_stat->patch_ver, coex_stat->kt_ver + 65);
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coex_stat->patch_ver,
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chip->wl_fw_desired_ver, coex_stat->kt_ver + 65);
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seq_printf(m, "%-40s = %u/ %u/ %u/ ch-(%u)\n",
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"AFH Map",
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coex_dm->wl_ch_info[0], coex_dm->wl_ch_info[1],
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coex_dm->wl_ch_info[2], hal->current_channel);
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rtw_debugfs_get_simple_phy_info(m);
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seq_printf(m, "**********************************************\n");
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seq_printf(m, "\t\tBT Status\n");
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seq_printf(m, "**********************************************\n");
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@@ -3408,8 +3498,8 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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score_board_WB, score_board_BW);
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seq_printf(m, "%-40s = %u/%u, %u/%u\n",
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"Hi-Pri TX/RX, Lo-Pri TX/RX",
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bt_hi_pri & 0xffff, bt_hi_pri >> 16,
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bt_lo_pri & 0xffff, bt_lo_pri >> 16);
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coex_stat->hi_pri_tx, coex_stat->hi_pri_rx,
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coex_stat->lo_pri_tx, coex_stat->lo_pri_rx);
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for (i = 0; i < COEX_BTINFO_SRC_BT_IQK; i++)
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seq_printf(m, "%-40s = %7ph\n",
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rtw_coex_get_bt_info_src_string(i),
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@@ -3438,9 +3528,11 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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seq_printf(m, "**********************************************\n");
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seq_printf(m, "\t\tMechanism (Under Manual)\n");
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seq_printf(m, "**********************************************\n");
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seq_printf(m, "%-40s = %5ph\n",
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seq_printf(m, "%-40s = %5ph (%d)\n",
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"TDMA Now",
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coex_dm->fw_tdma_para);
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coex_dm->fw_tdma_para,
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rtw_coex_get_tdma_index(rtwdev,
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&coex_dm->fw_tdma_para[0]));
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} else {
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seq_printf(m, "**********************************************\n");
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seq_printf(m, "\t\tMechanism\n");
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@@ -3454,9 +3546,11 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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rtw_coex_get_wl_coex_mode(coex_stat->wl_coex_mode),
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coex->freerun ? "Yes" : "No",
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coex_stat->tdma_timer_base);
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seq_printf(m, "%-40s = %d/ 0x%08x/ 0x%08x/ 0x%08x\n",
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seq_printf(m, "%-40s = %d(%d)/ 0x%08x/ 0x%08x/ 0x%08x\n",
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"Table/ 0x6c0/ 0x6c4/ 0x6c8",
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coex_dm->cur_table, wl_reg_6c0, wl_reg_6c4, wl_reg_6c8);
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coex_dm->cur_table,
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rtw_coex_get_table_index(rtwdev, wl_reg_6c0, wl_reg_6c4),
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wl_reg_6c0, wl_reg_6c4, wl_reg_6c8);
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seq_printf(m, "%-40s = 0x%08x/ 0x%08x/ %d/ reason (%s)\n",
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"0x778/ 0x6cc/ Run Count/ Reason",
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wl_reg_778, wl_reg_6cc,
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@@ -3520,5 +3614,22 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
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coex_stat->wl_noisy_level);
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rtw_coex_set_coexinfo_hw(rtwdev, m);
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seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
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"EVM A/ EVM B/ SNR A/ SNR B",
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-dm_info->rx_evm_dbm[RF_PATH_A],
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-dm_info->rx_evm_dbm[RF_PATH_B],
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-dm_info->rx_snr[RF_PATH_A],
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-dm_info->rx_snr[RF_PATH_B]);
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seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
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"CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
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dm_info->cck_cca_cnt, dm_info->cck_fa_cnt,
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dm_info->ofdm_cca_cnt, dm_info->ofdm_fa_cnt);
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seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC OK CCK/11g/11n/11ac",
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dm_info->cck_ok_cnt, dm_info->ofdm_ok_cnt,
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dm_info->ht_ok_cnt, dm_info->vht_ok_cnt);
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seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC Err CCK/11g/11n/11ac",
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dm_info->cck_err_cnt, dm_info->ofdm_err_cnt,
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dm_info->ht_err_cnt, dm_info->vht_err_cnt);
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}
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#endif /* CONFIG_RTW88_DEBUGFS */
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