NVIDIA: SAUCE: tty/serial: tegra-utc: Add support for earlycon
Add support for earlycon in Tegra UTC driver. http://nvbugs/4593743 Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
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@@ -406,6 +406,47 @@ static void tegra_utc_setup_port(struct device *dev, struct tegra_utc_port *tup,
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}
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#if IS_ENABLED(CONFIG_SERIAL_TEGRA_UTC_CONSOLE)
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static void tegra_utc_putc(struct uart_port *port, unsigned char c)
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{
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writel(c, port->membase + TEGRA_UTC_DATA);
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}
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static void tegra_utc_early_write(struct console *con, const char *s, unsigned int n)
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{
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struct earlycon_device *dev = con->data;
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while (n) {
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unsigned int burst_size = TEGRA_UTC_CLIENT_FIFO_SIZE;
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burst_size -= readl(dev->port.membase + TEGRA_UTC_FIFO_OCCUPANCY);
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if (n < burst_size)
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burst_size = n;
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uart_console_write(&dev->port, s, burst_size, tegra_utc_putc);
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n -= burst_size;
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s += burst_size;
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}
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}
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static int __init tegra_utc_early_console_setup(struct earlycon_device *device, const char *opt)
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{
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if (!device->port.membase)
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return -ENODEV;
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writel(0x11, device->port.membase + TEGRA_UTC_COMMAND);
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writel(0x4, device->port.membase + TEGRA_UTC_FIFO_THRESHOLD);
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writel(0xf, device->port.membase + TEGRA_UTC_INTR_CLEAR);
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writel(0x0, device->port.membase + TEGRA_UTC_INTR_MASK);
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writel(0x0, device->port.membase + TEGRA_UTC_INTR_SET);
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writel(0x1, device->port.membase + TEGRA_UTC_ENABLE);
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device->con->write = tegra_utc_early_write;
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return 0;
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}
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OF_EARLYCON_DECLARE(tegra_utc, "nvidia,tegra-utc", tegra_utc_early_console_setup);
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static void tegra_utc_console_putchar(struct uart_port *port, unsigned char ch)
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{
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struct tegra_utc_port *tup = container_of(port, struct tegra_utc_port, port);
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