Alex Frid
7a7ebd4523
Added DFLL tune high margin voltage entry in CVB table. This allows to
replace current fixed margin defined as number of DFLL voltage steps
with per-table/per-chip margin in millivolts, and convert it to steps
during DFLL initialization.
Bug 1967884
Change-Id: I56268ae2faf9cc633b9f988cacbfd0ea3ba77ff3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576307
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
63 lines
1.2 KiB
C
63 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Utility functions for parsing Tegra CVB voltage tables
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*/
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#ifndef __DRIVERS_CLK_TEGRA_CVB_H
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#define __DRIVERS_CLK_TEGRA_CVB_H
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#include <linux/types.h>
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struct device;
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#define MAX_DVFS_FREQS 40
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struct rail_alignment {
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int offset_uv;
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int step_uv;
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};
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struct cvb_coefficients {
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int c0;
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int c1;
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int c2;
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};
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struct cvb_table_freq_entry {
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unsigned long freq;
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struct cvb_coefficients coefficients;
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};
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struct cvb_cpu_dfll_data {
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u32 tune0_low;
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u32 tune0_high;
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u32 tune1_low;
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u32 tune1_high;
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unsigned int tune_high_min_millivolts;
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unsigned int tune_high_margin_millivolts;
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};
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struct cvb_table {
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int speedo_id;
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int process_id;
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int min_millivolts;
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int max_millivolts;
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int speedo_scale;
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int voltage_scale;
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struct cvb_table_freq_entry entries[MAX_DVFS_FREQS];
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struct cvb_cpu_dfll_data cpu_dfll_data;
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};
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const struct cvb_table *
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tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
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size_t count, struct rail_alignment *align,
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int process_id, int speedo_id, int speedo_value,
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unsigned long max_freq);
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void tegra_cvb_remove_opp_table(struct device *dev,
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const struct cvb_table *table,
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unsigned long max_freq);
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#endif
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